AN82526

AN82526 INTEL | Alldatasheet

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int | PRELIMINARY Automotive @ On-Board “MOTEL” @ Global Interrupt Disable @ Multimaster Architecture m@ Non-Destructive Bitwise Arbitration @ Bus Access Priority by Message @ Two 8-Bit I/O Ports @ 2032 Different Message Objects @ NRZ Coding/Decoding with Bit Stuffing m Guaranteed Latency Time for High m Programmable Transfer Rate to Priority Messages 1 MBit/Sec m@ Powerful Error Handling m Programmable Output Driver m Data Length to 8 Bytes Configuration m Message Configuration Flexibility m Programmable Clock Output m Broadcast Message Transfer m 44-PinPLCC m Ready Output @ Three Additional CS Outputs The 82526 Communication Controller is a highly integrated VLSI device which implements the CAN (Controller Area Network) Protocol. Included on the chip are an Interface Management Processor (IMP), Bit Stream Processor (BSP), Bus Timing Logic (BTL), Transceiver Control Logic (TCL), Processor Interface Unit (PIU), Error Management Logic (EML), Clock Generator and a pseudo Dual Port RAM (DPRAM). These hardware modules implement all necessary features of a high performance serial communication protocol. When con- nected to a microprocessor, the 82526 performs the principal functions of the physical and data link layer. Figure 1 shows a block diagram of the 82526. The 82526 uses an 8-bit multiplexed address and data bus optimized for operating with Intel’s microcontrollers and microprocessors. Other architectures may also be used with the direct connect on board “MOTEL” circuitry. As shown in Figure 1, the BSP, TCL, BTL and EML are related with Bus Line Logic. The IMP, RAM and PIU are related to the CPU Interface Logic. The logic blocks BSP, BTL, TCL and EML are referred to as the “Serial Interface Unit”. The CPU communicates with the 82526 through the on-chip pseudo dual port RAM which includes global status and control registers. The on-chip memory serves as the communication buffer interface between the CPU and the IMP. The CPU initializes the global status and control registers and creates a data structure (Communication Objects) within the communication buffer for reception and transmission of defined mes- sages. Commands, data and status transfers take place over the 8-bit parallel bus. The CPU writes data to the 82526 using CS, ALE and WR signals and reads the 82526 received data and status information using the CS, ALE and RD signals. The 82526 uses the interrupt line to alert the CPU of errors or data received. February 1992 3-40 Order Number: 270573-005

intel. 2528 PRELIMINARY ABSOLUTE MAXIMUM RATINGS Ambient Temperature

ELECTRICAL CHARACTERISTICS

DC CHARACTERISTICS Vcc = 4.5V to +5.5V; Ta = —40°C to + 125°C Vit Input Low Voltage Vss—0.5V 0.8V {All except XTAL1) Vin Input High Voltage 2.0V Voc + 0.5 {All except XTAL1, RST, ALE, CS) VoL Output Low Voltage 0.4V lo. = 1.6 mA (All Outputs except ADO-7, INT, RDY, CLKOUT, TXO, TX1) Vou1 Output Low Voltage 0.4 lo. = 3.2 mA (ADO-7) VoL2 Output Low Voltage 0.4V lo. = mA (RDY, INT) Vou Output High Voltage 2.5V lon = —80 pA (All Outputs except ADO-7, CSO, CS1, CS2, TXO, TX1, CLKOUT) tuk Input Leakage Current +10 pA Vss < Vin < Voc (Except Port0/Port1) lit Low Level Input Current —50 pA Vin = 0.4V (PortO/Port1) Re Logical 1 to 0 Transition —750 pA Vin = 2V . Current (Port0/Port1) Sleep Mode Supply Current 1.2mA 2.2mA Fytat = 1 MHz 5.5 mA 8.5 mA FxtaL = 16 MHz 3-42

intel. 92526 PRELIMINARY AC CHARACTERISTICS Conditions: Ta = —40°C to + 125°C, Vcc = 5V +10%, Vgg = OV, Port 2 outputs: CL = 150 pF, All other outputs: CL = 80 pF | symbot | ___—Parameter Tin Typ | Max | Titov ALE or TS(1) Low to 5 Txtat + 80 ns(8) Valid Data Out TRLbv Valid Data Out Delay from Read Control TavwH Input Data Setup to WR 20 ns High TwHax Input Data Hold after WR 18ns High Twuov WR High to Output Data 4TxtaL + 70 ns Valid on Port 0 or Port 1 TWHLL WR High to Next ALE or 2TxtaL + Sns CS Low(1, 2) TLLWH ALE or CS(1) Low to WR 4TxtaL + 10ns High TALAL Time between ALE 8 TxtaL + 5ns Falling Edges (or CS)(1) TLLYH End of ALE to RDY High(4) 4TytaL + 65 ns 6 TxtaL + 65 ns (with 1k External Pull-Up) Tics ALE or CS Low to CS0-1-2 Low(t. 5) THCSH CS0-1-2 High after ALE 70ns or CS High(3. 5) Tavcs Address Valid to CS0-1-2 Lowi) NOTES: 1. Whichever falling edge is last. 2. Some pipe-lining of the write accesses is possible. This spec is important mainly when processor speed is higher than 82526 speed (use of the RDY output... ). 3. Whichever rising edge comes first. 4. RDY is an open drain output (so is INT). 5. Timings valid on ALE falling or rising edges only if ALE is used to strobe the CS0-1-2 outputs (default mode). If the other mode is programmed by writing 1 to bit 7 of address 253, the new state starts propagating to the CS0-1-2 outputs as soon as a stable address has been decoded (providing that CS is also valid). 6. Timing valid only when ALE is not used to strobe the CS0-1-2 outputs. In this mode, THcsH also applies on CS rising edge and Ticst on CS falling edge. _ 7. must be active low with or WR rising edge for proper completion of the read or write access. 8. If tLLpy is too slow for the host microcontroller, a double read mechanism can be implemented. For details, contact an Intel representative. 3-43

intel. 32526 PRELIMINARY Physical Layer Specifications Load Condition: 80 pF Input Voltage Vss — 0.5V Voc + 0.5V [ss Common Mode Range Vsg + 1.0V Veo- tov fm) Sink Current 10omA | sd Vu = 0.4V Maximum Permitted Source —8.0mA Current (TXO, TX1 Together) Maximum Permitted Sink 22.0mA Current (TX0, TX1 Together) a CLKOUT Specifications CL = 50 PF [| min] Max | Conditions CLKOUT frequency (1/T) #XTAL/3008) 16 MHz | Rise Timet® pots Output Duty Cycle is 50% if OFH Clock Divider Register Not Equal Output Duty Cycle Equal XTAL OFH If Clock Divider Register Equal Minimum Differential Common Mode (2, 6) Internal Delay Time? ®) mn | oe Input Threshold tant) 187 ns 50 mV Vgg + 1.0V to Voc ~— 1.0V tan2) 137 ns 100 mV Vss + 1.0V to Voc — 1.0V tana) 127 ns 100 mv Veg + 1.5V to Voc — 1.0V NOTES: 1. See Internal Delay Times. 2. The Internal Delay Time is given by the sum: tiinternal logic) + Yinternal output driver) + tyinternal comparator): 4, Measured between 0.2 Voc — 0.1 and 0.7 Vcc. ~ 5. Push-pull mode. 6. The total delay time from transmit to sample point = titotal delay) = Ninternal delay) + trexternal logic) + (propagation delay) 3-44

0.7 Veo

Figure 1. External Clock Drive Configuration

27087312 For timing purposes a port pin is no longer floating when a

and 0.1V for a Logic “0”. Timing measurements are made at Vii when a 100 mV change trom the loaded VoH/Voy, level occurs. min for a Logic “1” and Vo. max for a Logic “0”. lov/lon 2 +20 mA.

intel. 42526 PRELIMINARY a READ ACCESS (TO DPRAM OR PORTO/PORT1) Tuy Tosun ts wT TLLov . cs aa 270573-3 WRITE ACCESS (TO DPRAM OR PORTO/PORT1) TALAL, = foe “ TwHox TAVEL TwHDV porto OLD DATA NEW DATA OUT 270573-4 3-46

intel. 92508 PRELIMINARY READY (RDY) OUTPUT TIMING TULyH ALE RDY muy 270573-5 €S0-1-2 OUTPUTS TIMING Mode programmed: outputs change on ALE or CS falling edge (whichever comes last). Test TucsH Test. Tics ALE cs Cs0-1-2 270573-6 CS0-1-2 OUTPUTS TIMING Mode programmed: outputs change when ALE is high. ° _ | 1 . KYYYV' VVVVYY @SO-1-2 NOOQ®s KY nae { Taves Tacs Test. Tacs 270573-7 : 3-47

intel. 52526 PRELIMINARY FREQUENCY TRANSITION TIME FOR CLOCKOUT LOGIC “0” | | | CLKOUT \\ J l J l J l J l J l J l PLT | NOTE 1 | |wore 2| 270573-8 NOTES: 1. Fout = Fxrat/Divider Register > Four = Fxtat max Logic “0” = 2 TxraL 2. Fout = Fxtat — Four = Fxtat/Divider Register max Logic “0” = 1,5 Tyrai If Divider Register = 2 max Logic “0” = (Divider Register — 1) XTAL if Divider Register > 2 RESET TIMING NOTE 1 READY RST |NoTe 2 [Nore 2 270573-9 Minimum 10 Oscillator Cycles NOTES: 1. Ready must not be pulled low during reset 2. Reset timing measure from rising edge to rising edge of OSC. DATA SHEET REVISION SUMMARY The following are the differences between the previous 82526 data sheet and this new data sheet (rev. -003): 1. loc and Ipc added to page 3-42. 3-48 ‘