LXT9863 INTEL | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1.0 Block Diagram
- 2.0 Pin Assignments and Signal Descriptions
- 3.0 Functional Description
- 3.1 Introduction
- 3.2 Port Configuration
- 3.2.1 Auto-Negotiation
- 3.2.2 Link Establishment and Port Connection
- 3.3 Interface Descriptions
- 3.3.1 Twisted-Pair Interface
- 3.3.2 Media Independent Interface
- 3.4 Repeater Operation
- 3.5 Requirements
- 3.5.1 Power
- 3.5.2 Clock
- 3.5.3 Bias Resistor
- 3.5.4 Reset
- 3.5.5 IRB Bus Pull-ups
- 3.6 LED Operation
- 3.6.1 LEDs at Start-up
- 3.6.2 LED Event Stretching
- 3.6.3 Serial LED Interface
- 3.6.4 Serial Shifting
- 3.6.4.1 Serial LED Signals
- 3.6.4.2 Activity Graph LEDs
- 3.6.5 Direct Drive LEDs
- 3.6.6 LED Modes
- 3.6.6.1 LED Mode
- 3.6.6.2 LED Mode
- 3.6.6.3 LED Mode
- 3.6.6.4 LED Mode
- 3.7 IRB Operation
- 3.7.1 IRB Signal Types
- 3.7.2.1 MAC IRB Access
- 3.7.3 LXT98x/91x/98xx Compatibility
- 3.8 MII Port Operation
- 3.8.1 Preamble Handling
- 4.0 Application Information
- 4.1 General Design Guidelines
- 4.2 Power and Ground
- 4.2.1 Supply Filtering
- 4.2.2 Ground Noise
Datasheet sections
- 4 Datasheet
- 4.2.3 Power and Ground Plane Layout Considerations
- 4.2.4 Chassis Ground
- 4.2.5 The RBIAS Pin
- 4.2.6 MII Terminations
- 4.2.7 Twisted-Pair Interface
- 4.2.7.1 Magnetics Information
- 4.2.8 Clock
- 4.2.9 LED Circuits
- 4.2.9.1 Direct Drive LEDs
- 4.2.9.2 LED Pins Multiplexed with Configuration Inputs
- 4.2.9.3 Serial LEDs
- 4.3 Inter-Repeater Backplane Compatibility
- 4.3.2.2 For 5V Backwards Stackability
- 5.0 Test Specifications
- 6.0 Mechanical Specifications
- 1 LXT98x3 Block Diagram
- 2 LXT9883 Pin Assignments
- 3 Typical LXT9883 Repeater Architecture
- 4 MII Interface
- 5 Serial LED Shift Loading
- 6 Serial LED Port Signaling
- 8 IRB Block Diagram
- 9 LXT9883 MII Operation
- 10 Power and Ground Connections
- 11 Typical Twisted-Pair Port Interface and Power Supply Filtering
- 12 Typical Reset Circuit
- 13 LED Circuits - Direct Drive & Multiplexed Configuration Inputs
- 14 Serial LED Circuit
- 16 Typical 100 Mbps IRB Implementation
- 17 Typical 10 Mbps IRB Implementation
- 26 LXT98x3 Package Specifications
Datasheet sections
- 1 MII #1 Signal Descriptions
- 2 MII #2 Signal Descriptions
- 3 Inter-Repeater Backplane Signal Descriptions
- 4 Twisted-Pair Port Signal Descriptions
- 5 LED Signal Descriptions
- 6 Power Supply and Indication Signal Descriptions
- 7 Miscellaneous Signal Descriptions
- 8 Serial LED Port Bit Stream
- 10 LED Terms
- 11 LED Mode 1 Indications
- 12 LED Mode 2 Indications
- 13 LED Mode 3 Indications
- 14 LED Mode 4 Indications
- 15 Cascading and Stacking Connections
- 16 IRB Signal Details
- 17 LXT98x3 Magnetics Specifications
- 18 Oscillator Manufacturers
- 19 Absolute Maximum Ratings
- 20 Operating Conditions
- 21 Input System Clock1 Requirements
- 22 I/O Electrical Characteristics
Datasheet sections
- 6 Datasheet
- 33 Replaced TBDs in fourth para under Supply Filtering to 1000 mA and
- 36 Replaced TBDs in fourth bullet under Twisted-Pair Interface to
- 37 Modified Oscillator Manufacturers table
- 43 Typical 100 Mbps IRB Implementation table:
- 43 Typical 10 Mbps IRB Implementation table:
1.0 Block Diagram
Figure 1. LXT98x3 Block Diagram
100 Mbps
8 Datasheet
2.0 Pin Assignments and Signal Descriptions
Figure 2. LXT9883 Pin Assignments Part # LXT9883 is the unique identifier for this product family. FPO # Identifies the Finish Process Order.
Table 1. MII #1 Signal Descriptions
9 MII1_SPD I
software reset. Selects operating speed of the respective MII (MAC) interface. High = 100 Mbps. Low = 10 Mbps. outputs. Data is driven on the falling edge of MII1_RXCLK. indicates valid data on MII1_RXD<3:0>. clock derived from the CLK25 input (refer to Table 7 on page 16). invalid data on MII1_RXD<3:0>. by sending ‘Invalid Code Symbols’ on the line. (refer to Table 7 on page 16). transmitted on the MII1_TXD<3:0> pins. Ground this input if unused.
- I = Input, O = Output, I/O = Input/Output, D = Digital, A = Analog, AI = Analog Input, A I/O = Analog Input/Output, OD = Open
OS = Open Source, PD = Pull Down, PU = Pull Up. NC = No Clamp. Pad does not clamp input in the absence of power.
- Pins are 5V tolerant, unless indicated.
10 Datasheet
Table 2. MII #2 Signal Descriptions
18 MII2_SPD
software reset. Selects operating speed of the respective MII (MAC) interface. High = 100 Mbps. Low = 10 Mbps. outputs. Data is driven on the falling edge of MII2_RXCLK. indicates valid data on MII2_RXD<3:0>. clock derived from the CLK25 input (refer to Table 7 on page 16). invalid data on MII2_RXD<3:0>. (refer to Table 7 on page 16). transmitted on the MII2_TXD<3:0> pins. Ground this input if unused.
- I = Input, O = Output, I/O = Input/Output, D = Digital, A = Analog, AI = Analog Input, A I/O = Analog Input/Output, OD = Open
OS = Open Source, PD = Pull Down, PU = Pull Up. NC = No Clamp. Pad does not clamp input in the absence of power.
- Pins are 5V tolerant, unless indicated.
Table 3. Inter-Repeater Backplane Signal Descriptions
39 COMP_SEL AI
operate in 5V backwards compatibility mode with LXT98x devices.
100 Mbps IRB Signals
36 IR100CFS 3 A I/O
connects between ICs on the same board.
37 IR100CFSBP
can be set in either 5V or 3.3V modes by the COMP_SEL pin.
38 IR100SNGL I/O
40 IR100COL I/O
connect this signal between boards.
41 IR100DEN
42 IR100DV
signal requires a 300Ω pull-up resistor. 100 Mbps IRB Data. These bidirectional signals carry 5-bit data on the 100 Mbps IRB. these signals between boards.
50 IR100CLK
74LVT245 buffer is recommended.
- I = Input, O = Output, I/O = Input/Output, D = Digital, AI = Analog Input, A I/O = Analog Input/Output, OD = Open Drain,
NC = No Clamp. Pad does not clamp input in the absence of power.
- Pins are 5V tolerant, unless indicated.
- IR10CFS is not 5V tolerant.
12 Datasheet
10 Mbps IRB Signals
11 IR10DAT
pulled High by a 330Ω resistor. Buffer this signal between boards.
12 IR10CLK
triggering is used to increase noise immunity.
6 IR10DEN
bidirectional transceiver (74LVT245) used to buffer the IRBs in multi-board applications. of the 74LVT245, and connect the off-board signals to the “A” side of the 74LVT245.
10 IR10ENA
330Ω pull-up resistor is required to pull the IR10ENA output High when the IRB is idle.
3 IR10COL
when there is no collision. Do not connect between boards and do not buffer.
4 IR10COLBP
one 330Ω resistor per stack.
2 IR10CFS 4
connect this signal between boards and do not buffer.
5 IR10CFSBP
3.3V modes by the COMP_SEL pin.
80 MACACTIVE
drives the three-level IR10CFS pin.
81 HOLDCOL
Table 3. Inter-Repeater Backplane Signal Descriptions (Continued)
- I = Input, O = Output, I/O = Input/Output, D = Digital, AI = Analog Input, A I/O = Analog Input/Output, OD = Open Drain,
NC = No Clamp. Pad does not clamp input in the absence of power.
- Pins are 5V tolerant, unless indicated.
- IR10CFS is not 5V tolerant.
Table 4. Twisted-Pair Port Signal Descriptions ports, these pins can be left open. negative inputs to the respective ports’ twisted-pair receivers. For unused ports, tie together with 100Ω resistors and float.
- I = Input, O = Output, I/O = Input/Output, D = Digital, A = Analog, AI = Analog Input, AO = Analog Output, A I/O = Analog
OS = Open Source, PD = Pull Down, PU = Pull Up. NC = No Clamp. Pad does not clamp input in the absence of power.
14 Datasheet
Table 5. LED Signal Descriptions LED Mode Select - Input. See Note 3 in footer below. These pins are shared with the LEDACT100, LEDCOL10 outputs.
175 LEDABGSEL I
LED Activity Bar Graph Mode Select - Input. See Note 2 in footer below. Refer to "Activity Graph LEDs” on page 23. This pin is shared with the Port8_LED2 output.
183 AUTOBLINK
LED Blink Mode Select - Input. See Note 3 in footer below. This pin is shared with the LEDACT100, LEDCOL10 outputs.
83 LEDDAT O
LED drivers. See"Serial LED Interface” on page 22..
84 LEDLAT O
LED Latch. Parallel load clock for external Serial-to-Parallel LED drivers. See "Serial LED Interface” on page 22..
82 LEDCLK
drivers. See "Serial LED Interface” on page 22.. LED Driver 1 - Ports 1 through 8. Programmable LED driver. Active Low. See "Direct Drive LEDs” on page 24.. LED Driver 2 - Ports 1 through 8. Programmable LED driver. Active Low. See "Direct Drive LEDs” on page 24.. The Port8_LED2 pin is shared with the LEDABGSEL configuration input. LED Driver 3 - Ports 1 through 8. Programmable LED driver. Active Low. See "Direct Drive LEDs” on page 24..
185 COL10_LED
segment. This pin is shared with the LEDSEL1 configuration input.
- I = Input, O = Output, I/O = Input/Output, D = Digital, A = Analog, AI = Analog Input, A I/O = Analog Input/Output, OD = Open
NC = No Clamp. Pad does not clamp input in the absence of power.
- Pins are 5V tolerant, unless indicated.
- Input must be static; Refer to "LED Pins Multiplexed with Configuration Inputs” on page 39. for information on pin use.
186 COL100_LED I
183 ACT10_LED
10M Activity LED Driver. Active output indicates activity on 10M segment.
184 ACT100_LED
Table 6. Power Supply and Indication Signal Descriptions supplied for every one of these pins. GND - Ground. Connect each of these pins to system ground plane.
- I = Input, O = Output, I/O = Input/Output, D = Digital, A = Analog, AI = Analog Input, A I/O = Analog Input/Output, OD = Open
OS = Open Source, PD = Pull Down, PU = Pull Up. NC = No Clamp. Pad does not clamp input in the absence of power.
- Pins are 5V tolerant, unless indicated.
Table 5. LED Signal Descriptions (Continued)
- I = Input, O = Output, I/O = Input/Output, D = Digital, A = Analog, AI = Analog Input, A I/O = Analog Input/Output, OD = Open
NC = No Clamp. Pad does not clamp input in the absence of power.
- Pins are 5V tolerant, unless indicated.
- Input must be static; Refer to "LED Pins Multiplexed with Configuration Inputs” on page 39. for information on pin use.
16 Datasheet
3.0 Functional Description
3.1 Introduction
current is provided through an external 22.1 kΩ, 1% resistor to GND.
79 RPS_PRES
redundant power supply. Tie Low if not used.
78 RPS_FAULT
LED section). Tie High if not used. Table 7. Miscellaneous Signal Descriptions
53 RESET
a common reset driven by an ‘LS14 or similar device.
54 CLK25 I
Schmitt 25 MHz system clock. Refer to Table 21 on page 44.
72 FPS
collisions to other devices on the board. Set Low for first device on the PCB. Set High for all other devices on the PCB. N/C - No Connects. Leave these pins unconnected.
- I = Input, O = Output, I/O = Input/Output, D = Digital, A = Analog, AI = Analog Input, A I/O = Analog Input/Output, OD = Open
OS = Open Source, PD = Pull Down, PU = Pull Up. NC = No Clamp. Pad does not clamp input in the absence of power.
- Pins are 5V tolerant, unless indicated.
Table 6. Power Supply and Indication Signal Descriptions (Continued)
- I = Input, O = Output, I/O = Input/Output, D = Digital, A = Analog, AI = Analog Input, A I/O = Analog Input/Output, OD = Open
OS = Open Source, PD = Pull Down, PU = Pull Up. NC = No Clamp. Pad does not clamp input in the absence of power.
- Pins are 5V tolerant, unless indicated.
ports that may be connected to 10/100 MACs. communicate with connected nodes and configure itself accordingly. ports) can be supported in a single stack.
3.2 Port Configuration
The LXT98x3 powers up in auto-negotiation mode for all twisted-pair ports.
3.2.1 Auto-Negotiation
Mbps link pulses. If it detects either of these signals, it configures the port accordingly. Figure 3. Typical LXT9883 Repeater Architecture
10 Mbps
LXT9883/9863 — Advanced 10/100 Unmanaged Repeater
18 Datasheet
Document #: 249115 Revision #: 003 Rev. Date: 08/07/01
3.2.2 Link Establishment and Port Connection
Once a port establishes link, the LXT98x3 automatically connects it to the appropriate repeater state machine. If link loss is detected and auto-negotiation is enabled, the port returns to the auto- negotiation state.
3.3 Interface Descriptions
The LXT9883 and LXT9863 provide eight and six network interface ports, respectively. Each port is a twisted-pair interface that directly supports 100BASE-TX (100TX) and 10BASE-T (10T) Ethernet applications and fully complies with IEEE 802.3 standards. A common termination circuit is used.
3.3.1 Twisted-Pair Interface
The LXT98x3 pinout is optimized for dual-height RJ-45 connectors. The twisted-pair interface for each port consists of two differential signal pairs — one for transmit and one for receive. The transmit signal pair is TPOP/TPON, the receive signal pair is TPIP/TPIN. The transmitter requires magnetics with 1:1 turns ratio. The center tap of the primary side of the transmit winding must be tied to a quiet VCC for proper operation. The receiver requires magnetics with a 1:1 turns ratio, and a load of 100Ω . When the twisted-pair port is enabled, the receiver actively biases its inputs to approximately 2.8V . A 4 kΩ load is always present across the TPIP/TPIN pair. When used in 100TX applications, the LXT98x3 sends and receives a continuous, scrambled 125 Mbps MLT-3 waveform on this interface. In the absence of data, IDLE symbols are sent and received in order to maintain the link. When used in 10T applications, the LXT98x3 sends and receives a non-continuous, 10 Mbps Manchester-encoded waveform. To maintain link during idle periods, the LXT98x3 sends link pulses every 16 ms, and expects to receive them every 10 to 20 ms. Each 10T port automatically detects and sends link pulses, and disables its transmitter if link pulses are not detected. Each 10BASE-T port can detect and automatically correct for polarity reversal on the TPIP/N inputs. The 10BASE-T interface provides integrated filters using Intel’s patented filter technology. These filters facilitate low-cost stack designs to meet EMI requirements.
3.3.2 Media Independent Interface
The LXT98x3 has two identical MII interfaces. The MII has been designed to allow expansion to a Media Access Controller (MAC) as shown in Figure 4. This interface is not MDIO/MDC capable. These MII ports can be set via hardware tie ups/downs to be either 10 Mbps or 100 Mbps. These ports are not the full MII drive strength and are intended only for point-to-point links.
3.4 Repeater Operation
repeaters perform the standard jabber and partition functions. Signal amplification, wave-shape restoration, and data-frame forwarding. SOP, SOJ, EOP , EOJ delay < 46BT; class II compliant. Figure 4. MII Interface
LXT9883/9863 — Advanced 10/100 Unmanaged Repeater
20 Datasheet
Document #: 249115 Revision #: 003 Rev. Date: 08/07/01 Un-partition. The un-partition algorithm, which complies with IEEE specification 802.3aa, un- partitions a port on either transmit or receive of at least 450-560 bits without collision. Isolate. The LXT98x3 isolates any port receiving more than two successive false carrier events. A false carrier event is a packet that does not start with a /J/K symbol pair. Un-isolate. The LXT98x3 un-isolates a port that remains in the IDLE state for 33000 +/- 25% BT or that receives a valid frame at least 450-500 BT in length. Jabber. The LXT98x3 ignores any receiver remaining active for more than 57,500 bit times. The LXT98x3 exits this state when either one of the following conditions is met: — On power-up reset — When carrier is no longer detected 3.4.2 10 Mbps Repeater Operation The LXT98x3 contains a complete 10 Mbps Repeater State Machine (10RSM) that is fully IEEE 802.3 compliant. Any port configured for 10 Mbps operation is automatically connected to the 10 Mbps Repeater. This includes any of the media and MII ports configured for 10 Mbps operation. The 10RSM has its own Inter-Repeater Backplane (10IRB). Multiple LXT98x3s can be cascaded on the 10IRB and operate as one repeater segment. Data from any port is forwarded to all other ports in the cascade. The LXT98x3 performs the following 10 Mbps repeater functions: Signal amplification, wave-shape restoration, and data-frame forwarding. Preamble regeneration. All outgoing packets have a minimum 56-bit preamble and 8-bit SFD. Collision Enforcement. During a 10 Mbps collision, the LXT98x3 drives a jam signal (“1010”) to all ports for a minimum of 96 bit times until the collision ends. Partition. The LXT98x3 partitions any port in excess of 31 consecutive collisions. Once partitioned, the LXT98x3 continues monitoring and transmitting to the port, but does not repeat data received from the port until it properly un-partitions. (Also partitions for excessive collision length.) Un-partition. The algorithm, which complies with the IEEE 802.3 specification, un-partitions a port when data can be either received or transmitted from the port for 450-560 bit times without a collision on that port. Jabber. The LXT98x3 asserts a minimum-IFG idle period when a port transmits for longer than 40,000 to 75,000 bit times.
3.5 Requirements
3.5.1 Power
The LXT98x3 has four types of +3.3V power supply input pins: two digital (VCC, GND) and two analog (VCCR, VCCT). These inputs may be supplied from a single source. Ferrite beads should be used to separate the analog and digital planes. These supplies should be clean.
Advanced 10/100 Unmanaged Repeater — LXT9883/9863 Datasheet 21 Document #: 249115 Revision #: 003 Rev. Date: 08/07/01 Each supply input should be decoupled to ground. Refer to Table 6 on page 15 for power and ground pin assignments, and to the "General Design Guidelines” on page 32..
3.5.2 Clock
A stable, external 25MHz reference clock source (TTL) is required to the CLK25 pin. The reference clock is used to generate transmit signals and recover receive signals. A crystal-based clock is recommended over a derived clock (i.e., PLL-based) to minimize transmit jitter. Refer to Table 18 on page 37 for a list of recommended oscillators and to Table 21 on page 44 for clock timing requirements.
3.5.3 Bias Resistor
The RBIAS input requires a 22.1 kΩ , 1% resistor connected to ground.
3.5.4 Reset
At power-up, the reset input must be held Low until VCC reaches at least 3.15V . A buffer should be used to drive reset if there are multiple LXT98x3 devices. The clock must be active.
3.5.5 IRB Bus Pull-ups
Even when the LXT98x3 is used in a stand-alone configuration, pull-up resistors are required on the IRB signals. See Figure 16 and Figure 17 on page 43.
3.6 LED Operation
The LXT98x3 drives the most commonly used LEDs directly (see "Direct Drive LEDs” on page 24.). The less frequently used LEDs are optionally driven via a serial bus to inexpensive Serial-to-Parallel devices (see “Serial LEDs” on this page).
3.6.1 LEDs at Start-up
For approximately 2 seconds after the LXT98x3 is reset, all LEDs are driven to the ON state. This start-up routine is an LED check.
100 Mbps IRB 10 Mbps IRB
22 Datasheet
3.6.2 LED Event Stretching
LED1, 2, 3 Modes section for stretching specifics.
3.6.3 Serial LED Interface
duplicated on the Serial Port (see "LED Pins Multiplexed with Configuration Inputs” on page 39.).
3.6.4 Serial Shifting
Figure 5 shows the Serial LED shift loading. Figure 5. Serial LED Shift Loading
30 LEDs
3.6.4.1 Serial LED Signals
and Table 8 for details on the LED serial bit stream.
3.6.4.2 Activity Graph LEDs
smoothing out the activity. LEDs are provided for both the 10 Mbps and 100 Mbps segments. Figure 6. Serial LED Port Signaling Table 8. Serial LED Port Bit Stream
7 MII Port 1 - LED1 Collision - 10M 1 ACTG8 ACTG8
6 MII Port 1 - LED2 Collision - 100M 1 ACTG7 ACTG7
5 MII Port 1 - LED3 Not Used ACTG6 ACTG6
4 MII Port 2 - LED1 Activity - 10M
1 ACTG5 ACTG5
3 MII Port 2 - LED2 Activity - 100M 1 ACTG4 ACTG4
2 MII Port 2 - LED3 Global Fault ACTG3 ACTG3
1 Not Used Not Used ACTG2 ACTG2
0 Not Used RPS Fault ACTG1 ACTG1
- These LEDs are multiplexed with Configuration Inputs.
24 Datasheet
lit when the percent activity value associated with that step is met or exceeded.
3.6.5 Direct Drive LEDs
port LEDs are updated simultaneously to illustrate clear, non-overlapping status. The drive level is determined by the particular input configuration function of the respective pin.
3.6.6 LED Modes
10 defines terms used to describe LED operation. Table 9. ACTGLED Display Modes Table 10. LED Terms Port_Enabled True if port is enabled. Link_OK True if link is enabled and link is detected. Always true for MII port. Port_Partitioned True if port has been auto partitioned (10Mb mode). True if port has been auto partitioned or isolated (100Mb mode). Port_Is_TP True if port is a twisted-pair port. RPS_Present True if redundant power supply is switched in. RPS_Fault True if redundant power supply has a fault. Rcv_Activity True if twisted-pair port on this device is receiving a packet.
3.6.6.1 LED Mode 1
Mode 1 operations are described in Table 11.
3.6.6.2 LED Mode 2
Mode 2 operations are described in Table 12. Table 11. LED Mode 1 Indications
10 Mbps operation Link_OK, not
100 Mbps operation
10 Mbps operation Link_OK,
on any additional activity is ignored by the activity LED logic.
- Refer to Table 11: LED Terms, which defines all key terms used in this section.
26 Datasheet
3.6.6.3 LED Mode 3
Mode 3 operations are described in Table 13. Table 12. LED Mode 2 Indications
2 N/A Any other state
any additional collisions are ignored by the collision LED logic. any additional activity is ignored by the activity LED logic.
- Refer to Table 10: LED Terms, which defines all key terms used in this section.
- Receive activity is stretched to a 20 ms wide pulse. For every on-cycle of the stretched LEDs, an off-cycle, with the same
period as the on-cycle, always follows.
Table 13. LED Mode 3 Indications any additional collisions is ignored by the collision LED logic. any additional activity is ignored by the activity LED logic.
- Refer to Table 10: LED Terms, which defines all key terms used in this section.
- Receive activity is stretched to a 20 ms wide pulse. For every on-cycle of the stretched LEDs, an off-cycle, with the same
period as the on-cycle, always follows.
28 Datasheet
3.6.6.4 LED Mode 4
Mode 4 operations are described in Table 14.
3.7 IRB Operation
shown in Figure 8 on page 30.
3.7.1 IRB Signal Types
Full— connected between devices in the same board and between boards. Table 14. LED Mode 4 Indications
10 Mbps operation
100 Mbps operation Any other state
additional collisions are ignored by the collision LED logic. any additional activity is ignored by the activity LED logic.
- Refer to Table 10: LED Terms, which defines all key terms used in this section.
- Receive activity is stretched to a 20 ms wide pulse. For every on-cycle of the stretched LEDs, an off-cycle, with the same
period as the on-cycle, always follows.
3.7.2.1 MAC IRB Access
3.7.3 LXT98x/91x/98xx Compatibility
however, are backwards stackable with LXT98x and LXT91x repeaters. Refer to "Inter-Repeater Backplane Compatibility” on page 41.. Figure 7. 100M IRB Connection
30 Datasheet
Figure 8. IRB Block Diagram Table 15. Cascading and Stacking Connections Local Connect all. Do not connect. Connect devices with FPS = 0 between boards. Use one pull-up resistor per stack. Full Connect all. Connect using buffers. Digital IRB signals include IRnDAT, IRnCOL, IR10COLBP, IRnENA and IRnCLK. Local Analog IRB signal: IRnCFS. Inter-Board Analog IRB signal: IRnCFSBP. This diagram shows a single IRB. The LXT98x3 actually has two independent IRBs, one per speed/segment. HOLDCOL is used on the 10Mbps IRB Only.
3.8 MII Port Operation
MIIn_SPD = 1. For 10 Mbps operation, set MIIn_SPD = 0.
3.8.1 Preamble Handling
with the 8-bit SFD (no preamble bits). Table 16. IRB Signal Details
- Driver Enable signals are provided to control an external bidirectional transceiver.
32 Datasheet
4.0 Application Information
4.1 General Design Guidelines
ground plane that is not located adjacent to the signal layer. recommended for decoupling caps). Provide ample power and ground planes. Provide termination on all high-speed switching signals and clock lines. Provide impedance matching on long traces to prevent reflections. Route high-speed signals next to a continuous, unbroken ground plane. Filter and shield DC-DC converters, oscillators, etc. edge of the board. Use this area for chassis ground, or leave it void. Figure 9. LXT9883 MII Operation
Advanced 10/100 Unmanaged Repeater — LXT9883/9863 Datasheet 33 Document #: 249115 Revision #: 003 Rev. Date: 08/07/01
4.2 Power and Ground
4.2.1 Supply Filtering
Power supply ripple and digital switching noise on the VCC plane causes EMI and degrades line performance. Predicting a design’s performance is difficult, although certain factors greatly increase the risks: Poorly-regulated or over-burdened power supplies. Wide data busses (>32-bits) running at a high clock rate. DC-to-DC converters. Many of these issues can be improved by following good general design guidelines. In addition, Intel recommends filtering between the power supply and the analog VCC pins of the LXT98x3. Filtering has two benefits. First, it keeps digital switching noise out of the analog circuitry inside the LXT98x3, which helps line performance. Second, if the VCC planes are laid out correctly, it keeps digital switching noise away from external connectors, reducing EMI. The VCC plane should be divided into two sections. The digital section supplies power to the digital VCC pins and to the external components. The analog section supplies power to VCCR and VCCT pins of the LXT98x3. The break between the two planes should run under the device. In designs with more than one LXT98x3, use a single continuous analog VCC plane to supply them all. The digital and analog VCC planes should be joined at one or more points by ferrite beads. The beads should produce at least a 100 Ω impedance at 100 MHz. The beads should be placed so current flows evenly. The maximum current rating of the beads should be at least 150% of the current that is actually expected to flow through them. Each LXT98x3 draws a maximum of 1000 mA from the analog supply so beads rated at 1500 mA should be used. A bulk cap (2.2 -10 µF) should be placed on each side of each ferrite bead to ground to stop switching noise from traveling through the ferrite. In addition, a high-frequency bypass cap (.01µf) should be placed near each analog VCC pin to ground.
4.2.2 Ground Noise
The best approach to minimize ground noise is strict use of good general design guidelines and by filtering the VCC plane.
4.2.3 Power and Ground Plane Layout Considerations
The power and ground planes should be laid out carefully. The following guidelines are recommended: Follow the guidelines in the Application Note 113 (LXT98x3 Design and Layout Guide) for locating the split between the digital and analog VCC planes. Keep the digital VCC plane away from the TPOP/N and TPIP/N signals, magnetics, and RJ-45 connectors. Place the layers so the TPOP/N and TPIP/N signals are routed near or next to the ground plane. For EMI, it is more important to shield TPOP/N than TPIP/N.
LXT9883/9863 — Advanced 10/100 Unmanaged Repeater
34 Datasheet
Document #: 249115 Revision #: 003 Rev. Date: 08/07/01
4.2.4 Chassis Ground
For ESD protection, create a separate chassis ground. For isolation, encircle the board and place a “moat” around the signal ground plane to separate signal ground from chassis ground. Chassis ground should extend from the RJ-45 connectors to the magnetics, and can be used to terminate unused signal pairs (‘Bob Smith’ termination). In single-point grounding applications, provide a single connection between chassis and circuit grounds with a 2kV isolation capacitor. In multi- point grounding schemes (chassis and circuit grounds joined at multiple points), provide 2kV isolation to the Bob Smith termination.
4.2.5 The RBIAS Pin
The LXT98x3 requires a 22.1 kΩ, 1% resistor directly connected between the RBIAS pin and ground. Place the RBIAS resistor as close to the RBIAS pin as possible. Run an etch directly from the pin to the resistor, sink the other side of the resistor, and surround the RBIAS trace with a filtered ground. Do not run high-speed signals next to RBIAS.
4.2.6 MII Terminations
Figure 10. Power and Ground Connections
36 Datasheet
4.2.7 Twisted-Pair Interface
Place magnetics as close as possible to the LXT98x3. Keep transmit pair traces short. traces completely. Otherwise, keep planes 3-4 layers away. the bead should be rated at > 1500 mA. Route the signal pairs differentially, close together. Allow nothing to come between them. Keep distances as short as possible; both traces should have the same length. Avoid vias and layer changes. Keep the transmit and receive pairs apart to avoid cross-talk. transmit on the other side of the PCB. Keep termination circuits grouped closely together and on the same side of the board. Always put termination circuits close to the source end of any circuit.
4.2.7.1 Magnetics Information
static voltages across the connectors and cables. Refer to Table 17 for magnetics specifications. Table 17. LXT98x3 Magnetics Specifications
4.2.8 Clock
Table 18. Oscillator Manufacturers
38 Datasheet
Figure 11. Typical Twisted-Pair Port Interface and Power Supply Filtering Figure 12. Typical Reset Circuit
4.2.9 LED Circuits
4.2.9.1 Direct Drive LEDs
limiting resistor, to a positive voltage rail. The LEDs are turned on when the output pin drives Low. LED component selection by allowing more common, high forward voltage LEDs to be used. Refer to Figure 13 for a circuit illustration.
4.2.9.2 LED Pins Multiplexed with Configuration Inputs
Some static configuration inputs are multiplexed with LED pins to reduce the LXT98x3 pin count. with a single resistor to set them all to the same value. Refer to Figure 13 for a circuit illustration. selection as with Direct Drive LEDs). achieved (see "Serial LEDs” on page 40.). Figure 13. LED Circuits - Direct Drive &
40 Datasheet
4.2.9.3 Serial LEDs
status indications are provided on multiplexed configuration pins and duplicated on the serial port. implementation. Refer to Figure 14 for an illustration of the LED serial interface circuit. the last serial output to serial input of next serial interface device. port signalling and Table 8 on page 23 which documents the Serial LED Stream. Figure 14. Serial LED Circuit
Advanced 10/100 Unmanaged Repeater — LXT9883/9863 Datasheet 41 Document #: 249115 Revision #: 003 Rev. Date: 08/07/01
4.3 Inter-Repeater Backplane Compatibility
The Inter-repeater Backplane (IRB) comprises two parts: Local— the backplane between cascaded devices on the same board. Stack— the backplane between multiple boards. Each of these backplanes consists of both analog and digital signals. 4.3.1 Local Backplane— 3.3V Only The LXT98x3 local backplane operates at 3.3V only. LXT98x and LXT91x devices operate at 5V . LXT98x3 devices are, therefore, not cascadable with LXT98x and LXT91x devices. Note: Do not mix LXT98x3 with either LXT98x or LXT91x devices on the local backplanes. 4.3.2 Stack Backplane — 3.3V or 5V The LXT98x3 stack backplanes can be configured to be either 3.3V or 5V . COMP_SEL (Pin 39), a special input pin, selects between the two voltage modes, depending on whether 3.3V or 5V is applied. 4.3.2.1 3.3V-Only Stacks Apply 3.3V to COMP_SEL, IR100CFSBP, IR10CFSBP, and IR10COLBP for LXT98x3 backplane operation
4.3.2.2 For 5V Backwards Stackability
Apply 5V to COMP_SEL, IR100CFSBP , IR10CFSBP, and IR10COLBP for LXT98x and LXT91x backplane operation. Note: With either mode (3.3V or 5V), COMP_SEL draws less than 3 mA. 1. The external pull-up resistor values remain the same, regardless of 3.3V or 5V backplane operation. 2. The recommended digital signal external buffer has been changed to 74LVT245 for the LXT98x3. Boards designed for 3.3V backplane operation should only be stacked with other 3.3V boards. Existing LXT98x or LXT91x based designs cannot operate in 3.3V .
4.3.2.3.2 Incompatible Stacking Configurations
The following stacking configurations are incompatible:
42 Datasheet
board configured for 5V backplane operation. operation causes network errors. LXT98x or LXT91x-based designs. LXT98x3 designs configured for 5V backplane operation. operation causes network errors. Figure 15. 100M Backplane Connection between LXT98x and LXT98x3
- The LXT98x and LXT9883 devices can share the same Inter-Repeater Backplane so long as the proper backplane
buffers are used. Configuration is set to 5V.
- For LXT98x, LXT91x: The buffer should be the 74ABT245.
- Layout follows the same pattern for 10M operation.
44 Datasheet
5.0 Test Specifications
guaranteed over the recommended operating conditions specified in Table 20. Table 19. Absolute Maximum Ratings Caution:Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 20. Operating Conditions
- Typical values are at 25° C and are for design aid only; they are not guaranteed and not subject to production testing.
Table 21. Input System Clock1 Requirements
- The system clock is CLK25 (Pin 54).
- These requirements apply to the external clock supplied to the LXT98x3, not to LXT98x3 test specifications.
- Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
Table 22. I/O Electrical Characteristics
- Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
- Does not apply to IRB pins. Refer to Table 23 and Table 24 for IRB I/O characteristics.
- Applies to RESET, CLK25, IR100SNGL, IR100COL, IR100DV, IR100DATn, IR100CLK, and IR10CLK pins.
Table 23. 100 Mbps IRB Electrical Characteristics
- Typical values are at 25° C and are for design aid only; they are not guaranteed and not subject to production testing.
- 91Ω resistors provide greater noise immunity. Systems using 91Ω resistors are backwards stackable with systems using
46 Datasheet
Table 24. 10 Mbps IRB Electrical Characteristics
- Typical values are at 25° C and are for design aid only; they are not guaranteed and not subject to production testing.
Table 23. 100 Mbps IRB Electrical Characteristics (Continued)
- Typical values are at 25° C and are for design aid only; they are not guaranteed and not subject to production testing.
- 91Ω resistors provide greater noise immunity. Systems using 91Ω resistors are backwards stackable with systems using
Table 25. 100BASE-TX Transceiver Electrical Characteristics
- Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
- Measured at line side of transformer, line replaced by 100Ω (±1%) resistor.
Table 26. 10BASE-T Transceiver Electrical Characteristics
- Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
- Parameter is guaranteed by design; not subject to production testing.
48 Datasheet
Figure 18. 100 Mbps TP Port-to-Port Delay Timing Table 27. 100 Mbps TP Port-to-Port Delay Timing Parameters
- Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
- Bit Time (BT) is the duration of one bit as transferred to/from the MAC and is the reciprocal of bit rate. BT for
Figure 19. 100BASE-TX MII-to-TP Port Timing Table 28. 100BASE-TX MII-to-TP Port Timing Parameters
- Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
- Bit Time (BT) is the duration of one bit as transferred to/from the MAC and is the reciprocal of bit rate. BT for
50 Datasheet
Figure 20. 100BASE-TX TP-to-MII Timing Table 29. 100BASE-TX TP-to-MII Timing Parameters
- Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
- Bit Time (BT) is the duration of one bit as transferred to/from the MAC and is the reciprocal of bit rate. BT for
Figure 21. 10BASE-T MII-to-TP Timing Table 30. 10BASE-T MII-to-TP Timing Parameters
- Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
- Bit Time (BT) is the duration of one bit as transferred to/from the MAC and is the reciprocal of bit rate. BT for
52 Datasheet
Figure 22. 10BASE-T TP-to-MII Port Timing Table 31. 10BASE-T TP-to-MII Port Timing Parameters
- Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
- Bit Time (BT) is the duration of one bit as transferred to/from the MAC and is the reciprocal of bit rate. BT for
Figure 23. 100 Mbps TP-to-IRB Timing Table 32. 100 Mbps TP-to-IRB Timing Parameters1
- This table contains propagation delays from the TP ports to the IRB for normal repeater operation. All values in this table are
- Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing.
- Bit Time (BT) is the duration of one bit as transferred to/from the MAC and is the reciprocal of bit rate. BT for
54 Datasheet
Figure 24. 10 Mbps TP-to-IRB Timing Table 33. 10 Mbps TP-to-IRB Timing Parameters1 330 Ω pull-up, 150pF load on IR10DAT.
- This table contains propagation delays from the TP ports to the IRB for normal repeater operation. All values in this table are
- There is a delay of approximately 13 to 16 bit times between the assertion of IR10ENA and the assertion of IR10CLK and
- Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
- Bit Time (BT) is the duration of one bit as transferred to/from the MAC and is the reciprocal of bit rate. BT for
Figure 25. 10 Mbps IRB-to-TP Port Timing Table 34. 10 Mbps IRB-to TP Port Timing Parameters
- Typical values are at 25° C and are for design aid only; they are not guaranteed and not subject to production testing.
- Bit Time (BT) is the duration of one bit as transferred to/from the MAC and is the reciprocal of bit rate. BT for
- External devices should allow at least one 10 MHz clock cycle (10 ns) between assertion of MACACTIVE and IR10ENA.
56 Datasheet
6.0 Mechanical Specifications
Figure 26. LXT98x3 Package Specifications