9880

LXT9860 INTEL | Alldatasheet

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Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management — LXT9860/9880

Contents

LXT9860/9880 — Advanced 10/100 Repeater with Integrated Management

4 Datasheet

Document #: 248987 Revision#: 003 Rev Date: 08/07/01

Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management — LXT9860/9880

LXT9860/9880 — Advanced 10/100 Repeater with Integrated Management

6 Datasheet

Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Figures

Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management — LXT9860/9880 Tables 40 100 Mbps TP-to-IRB Timing Parameters

LXT9860/9880 — Advanced 10/100 Repeater with Integrated Management

8 Datasheet

Document #: 248987 Revision#: 003 Rev Date: 08/07/01

Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management — LXT9860/9880

Revision History

Date Revision Page Description August 2001 003 75 Changed Absolute Maximum Ratings Supply Voltage value to 4.0V. January 2001 002 Title Page Added extended temperature range to title page.

13 Modified LXT98x0 Pins, Numeric Order table (Pins 10, 11, 17, 19, 20,

1. 38 Modified clock requirements language. 38 Replaced TBD with 3.15V under Reset.

65 Under Twisted Pair Interface, 4th bullet: Replaced text containingT-

BDs with: A ferrite bead with a total maximum current rating of 1.5Amp is recommended. 67 Modified Oscillator Manufacturers table. 75 Modified Absolute Maximum Ratings table. 75 Modified Operating Conditions table. 117, 118 Mechanical Specifications: Add part number LXT98x0AHC to LXT98x0 Package Specifications Commercial Temperature figure; Add page for LXT98x0 Package Specifications Extended Tempera- ture figure.

1.0 Other Related Documents …

design and layout of Intel’s Inter-Repeater Backplane (IRB). registers of the LXT98x and more recent LXT98x0 devices. connect an SCC to Intel devices and how to implement management across a network system. Figure 1. LXT98x0 Block Diagram

10 Mbps

100 Mbps

12 Datasheet

2.0 Pin Assignments and Signal Descriptions

Figure 2. LXT98x0 Pin Assignments

• Indicates LXT9880-only pins. TP Ports 7 and 8 are not available on LXT9860 devices.

Table 1. Signal Types I Input Standard input-only signal. O Output Standard output-only signal. I/O Bidirectional Input and output signal. A Analog Current source signal. OD Open Drain Output that will only drive the signal Low. OS Open Source Output that will only drive the signal High. PD Pull Down Internal, weak pull down signal. PU Pull Up Internal, weak pull up signal. NC No Clamp Pad does not clamp input in the absence of power. Table 2. LXT98x0 Pins, Numeric Order

1. IR10CFS A, I/O, OD Table 5 on page 22
2. IR10COL I/O, OD, PU Table 5 on page 22
3. IR10COLBP I/O, OD Table 5 on page 22
4. IR10CFSBP A I/O, OD Table 5 on page 22
5. IR10DEN O, OD Table 5 on page 22
6. MII1_SPD I, PU Table 3 on page 20
7. IR10ENA O, Table 3 on page 20
8. IR10DAT O Table 3 on page 20
9. IR10CLK I/O Table 5 on page 22
10. MII1_CRS O Table 3 on page 20
11. MII1_COL O Table 3 on page 20
12. GND - Table 9 on page 28
13. VCC - Table 9 on page 28
14. MII1_TXD3 I Table 3 on page 20
15. MII2_SPD I Table 3 on page 20
16. MII1_TXD2 I Table 3 on page 20
17. MII1_TXD1 I Table 3 on page 20
18. MII1_TXD0 I Table 3 on page 20
19. Refer to Table 1 for Signal Type definitions.
20. Pins are 5V tolerant, unless indicated.
21. Input must be static; Refer to “LED Pins Multiplexed with

Configuration Inputs” on page 69 for information on pin use.

14 Datasheet

1. MII1_TXEN I Table 3 on page 20
2. MII1_TXCLK I Table 3 on page 20
3. MII1_TXER I Table 3 on page 20
4. CONFIG1/CF I/O Table 11 on page 30
5. MII1RXER I Table 3 on page 20
6. GND - Table 9 on page 28
7. VCC - Table 9 on page 28
8. MII1_RXCLK O Table 3 on page 20
9. MII1_RXDV O Table 3 on page 20
10. MII1_RXD0 O Table 3 on page 20
11. MII1_RXD1 O Table 3 on page 20
12. CONFIG/CFG_DT I Table 12 on page 41
13. MII1_RXD2 O Table 3 on page 20
14. MII1_RXD3 O Table 3 on page 20
15. IR100CFS A I/O Table 5 on page 22
16. IR100CFSBP A I/O Table 5 on page 22
17. IR100SNGL I/O Table 5 on page 22
18. COMP_SEL AI Table 5 on page 22
19. IR100COL O Table 5 on page 22
20. IR100DEN O Table 5 on page 22
21. IR100DV I/O Table 5 on page 22
22. IR100DAT0 I/O Table 5 on page 22
23. IR100DAT1 I/O Table 5 on page 22
24. IR100DAT2 I/O Table 5 on page 22
25. GND - Table 9 on page 28
26. VCC - Table 9 on page 28
27. IR100DAT3 I/O Table 5 on page 22
28. IR100DAT4 I/O Table 5 on page 22
29. IR100CLK I/O Table 5 on page 22
30. NC - Table 11 on page 30
31. NC - Table 11 on page 30
32. RESET I Table 11 on page 30
33. CLK25 I Table 11 on page 30
34. IR10ISO O Table 5 on page 22
35. Refer to Table 1 for Signal Type definitions.
36. Pins are 5V tolerant, unless indicated.
37. Input must be static; Refer to “LED Pins Multiplexed with

Configuration Inputs” on page 69 for information on pin use.

1. IR100ISO O Table 5 on page 22
2. RECONFIG I, PD Table 7 on page 26
3. SRX I, PD Table 7 on page 26
4. STX O, OD Table 7 on page 26
5. VCC - Table 9 on page 28
6. SER_MATCH O Table 7 on page 26
7. MMSTROUT O Table 5 on page 22
8. ARBOUT O Table 7 on page 26
9. NC - Table 11 on page 30
10. PROM_CS O, Tri-State Table 10 on page 29
11. PROM_DTOUT O, Tri-State Table 10 on page 29
12. PROM_DTIN I, PD Table 10 on page 29
13. VCC - Table 9 on page 28
14. GND - Table 9 on page 28
15. VCC - Table 9 on page 28
16. VCC - Table 9 on page 28
17. RPS_FAULT I, PU Table 9 on page 28
18. RPS_PRES I, PU Table 9 on page 28
19. MACACTIVE I, PD Table 5 on page 22
20. HOLDCOL I/O, PD Table 5 on page 22
21. LEDDAT O Table 8 on page 27
22. LEDLAT O Table 8 on page 27
23. VCC - Table 9 on page 28
24. Refer to Table 1 for Signal Type definitions.
25. Pins are 5V tolerant, unless indicated.
26. Input must be static; Refer to “LED Pins Multiplexed with

Configuration Inputs” on page 69 for information on pin use.

16 Datasheet

1. GND - Table 9 on page 28
2. PORT1_LED3 O, OD Table 8 on page 27
3. PORT1_LED2 O, OD Table 8 on page 27
4. PORT1_LED1 O, OD Table 8 on page 27
5. GND - Table 9 on page 28
6. PORT2_LED3 O, OD Table 8 on page 27
7. PORT2_LED2 O, OD Table 8 on page 27
8. PORT2_LED1 O, OD Table 8 on page 27
9. GND - Table 9 on page 28
10. PORT3_LED3 O, OD Table 8 on page 27
11. PORT3_LED2 O, OD Table 8 on page 27
12. PORT3_LED1 O, OD Table 8 on page 27
13. GND - Table 9 on page 28
14. PORT4_LED3 O, OD Table 8 on page 27
15. PORT4_LED2 O, OD Table 8 on page 27
16. PORT4_LED1 O, OD Table 8 on page 27
17. RBIAS A Table 9 on page 28
18. GND - Table 9 on page 28
19. TPIP1 AI Table 6 on page 25
20. TPIN1 AI Table 6 on page 25
21. VCCR - Table 9 on page 28
22. TPOP1 AO Table 6 on page 25
23. TPON1 AO Table 6 on page 25
24. GND - Table 9 on page 28
25. TPON2 AO Table 6 on page 25
26. TPOP2 AO Table 6 on page 25
27. VCCT - Table 9 on page 28
28. VCCR - Table 9 on page 28
29. TPIN2 AI Table 6 on page 25
30. TPIP2 AI Table 6 on page 25
31. GND - Table 9 on page 28
32. GND - Table 9 on page 28
33. TPIP3 AI Table 6 on page 25
34. TPIN3 AI Table 6 on page 25
35. Refer to Table 1 for Signal Type definitions.
36. Pins are 5V tolerant, unless indicated.
37. Input must be static; Refer to “LED Pins Multiplexed with

Configuration Inputs” on page 69 for information on pin use.

1. VCCR - Table 9 on page 28
2. TPOP3 AO Table 6 on page 25
3. TPON3 AO Table 6 on page 25
4. GND - Table 9 on page 28
5. TPON4 AO Table 6 on page 25
6. TPOP4 AO Table 6 on page 25
7. VCCT - Table 9 on page 28
8. VCCR - Table 9 on page 28
9. TPIN4 AI Table 6 on page 25
10. TPIP4 AI Table 6 on page 25
11. GND - Table 9 on page 28
12. GND - Table 9 on page 28
13. TPIP5 AI Table 6 on page 25
14. TPIN5 AI Table 6 on page 25
15. VCCR - Table 9 on page 28
16. VCCT - Table 9 on page 28
17. TPOP5 AO Table 6 on page 25
18. TPON5 AO Table 6 on page 25
19. GND - Table 9 on page 28
20. TPON6 AO Table 6 on page 25
21. TPOP6 AO Table 6 on page 25
22. VCCR - Table 9 on page 28
23. TPIN6 AI Table 6 on page 25
24. TPIP6 AI Table 6 on page 25
25. GND - Table 9 on page 28
26. GND - Table 9 on page 28
27. TPIP7 AI Table 6 on page 25
28. TPIN7 AI Table 6 on page 25
29. VCCR - Table 9 on page 28
30. VCCT - Table 9 on page 28
31. TPOP7 AO Table 6 on page 25
32. TPON7 AO Table 6 on page 25
33. GND - Table 9 on page 28
34. TPON8 AO Table 6 on page 25
35. Refer to Table 1 for Signal Type definitions.
36. Pins are 5V tolerant, unless indicated.
37. Input must be static; Refer to “LED Pins Multiplexed with

Configuration Inputs” on page 69 for information on pin use.

18 Datasheet

1. TPOP8 AO Table 6 on page 25
2. VCCR - Table 9 on page 28
3. TPIN8 AI Table 6 on page 25
4. TPIP8 AI Table 6 on page 25
5. GND - Table 9 on page 28
6. TxSLEW_0 I, PD Table 6 on page 25
7. TxSLEW_1 I, PD Table 6 on page 25
8. PORT5_LED3 O, OD Table 8 on page 27
9. PORT5_LED2 O, OD Table 8 on page 27
10. PORT5_LED1 O, OD Table 8 on page 27
11. GND - Table 9 on page 28
12. PORT6_LED3 O, OD Table 8 on page 27
13. PORT6_LED2 O, OD Table 8 on page 27
14. PORT6_LED1 O, OD Table 8 on page 27
15. GND - Table 9 on page 28
16. PORT7_LED3 O, OD Table 8 on page 27
17. PORT7_LED2 O, OD Table 8 on page 27
18. PORT7_LED1 O, OD Table 8 on page 27
19. GND - Table 9 on page 28
20. VCC - Table 9 on page 28
21. PORT8_LED3 O, OD Table 8 on page 27
22. PORT8_LED2 O, OD Table 8 on page 27
23. PORT8_LED1 O, OD Table 8 on page 27
24. VCC - Table 9 on page 28
25. GND - Table 9 on page 28
26. VCC - Table 9 on page 28
27. GND - Table 9 on page 28
28. IRQ O, OD Table 11 on page 30
29. AUTOBLINK/ I 3, O-OD/OS Table 8 on page 27
30. LEDSEL0 I 3, O-OD/OS Table 8 on page 27
31. Refer to Table 1 for Signal Type definitions.
32. Pins are 5V tolerant, unless indicated.
33. Input must be static; Refer to “LED Pins Multiplexed with

Configuration Inputs” on page 69 for information on pin use.

1. LEDSEL1 I 3, O-OD/OS Table 8 on page 27
2. ARBSELECT I 3, O-OD/OS Table 7 on page 26
3. MII2_CRS O Table 4 on page 21
4. MII2_COL O Table 4 on page 21
5. GND - Table 9 on page 28
6. VCC - Table 9 on page 28
7. MII2_TXD3 I Table 4 on page 21
8. MII2_TXD2 I Table 4 on page 21
9. MII2_TXD1 I Table 4 on page 21
10. MII2_TXD0 I Table 4 on page 21
11. MII2_TXEN I Table 4 on page 21
12. MII2_TXCLK O Table 4 on page 21
13. MII2_TXER I Table 4 on page 21
14. ARBIN I, PD Table 7 on page 26
15. GND - Table 9 on page 28
16. VCC - Table 9 on page 28
17. MMSTRIN I, PD Table 5 on page 22
18. MII2_RXER O Table 4 on page 21
19. MII2_RXCLK O Table 4 on page 21
20. MII2_RXDV O Table 4 on page 21
21. MII2_RXD0 O Table 4 on page 21
22. MII2_RXD1 O Table 4 on page 21
23. MII2_RXD2 O Table 4 on page 21
24. MII2_RXD3 O Table 4 on page 21
25. Refer to Table 1 for Signal Type definitions.
26. Pins are 5V tolerant, unless indicated.
27. Input must be static; Refer to “LED Pins Multiplexed with

Configuration Inputs” on page 69 for information on pin use.

20 Datasheet

Table 3. MII #1 Signal Descriptions

9 MII1_SPD I

the respective MII (MAC) interface. High = 100 Mbps. Low = 10 Mbps. MII1_RXCLK, indicates valid data on MII1_RXD<3:0>. MII1_RXCLK, indicates invalid data on MII1_RXD<3:0>. Transmit Error - MII 1. MII1_TXER is a 100 Mbps-only signal. from the CLK25 input (refer to Table 11 on page 30). to indicate data is transmitted on the MII1_TXD<3:0> pins. Ground this input if unused.

1. I = Input, O = Output, I/O = Input/Output, D = Digital, A = Analog, AI = Analog Input,

A I/O = Analog Input/Output, OD = Open Drain, OS = Open Source, PD = Pull Down, PU = Pull Up. NC = No Clamp. Pad does not clamp input in the absence of power.

1. Pins are 5V tolerant, unless indicated.

Table 4. MII #2 Signal Descriptions

18 MII2_SPD

the respective MII (MAC) interface. High = 100 Mbps. Low = 10 Mbps. MII2_RXCLK, indicates valid data on MII2_RXD<3:0>. MII2_RXCLK, indicates invalid data on MII2_RXD<3:0>.

197 MII2_TXER I

Transmit Error - MII 2. MII2_TXER is a 100 Mbps-only signal. from the CLK25 input (refer to Table 11 on page 30). to indicate data is transmitted on the MII2_TXD<3:0> pins. Ground this input if unused.

188 MII2_COL

187 MII2_CRS

1. I = Input, O = Output, I/O = Input/Output, D = Digital, A = Analog, AI = Analog Input,

A I/O = Analog Input/Output, OD = Open Drain, OS = Open Source, PD = Pull Down, PU = Pull Up. NC = No Clamp. Pad does not clamp input in the absence of power.

1. Pins are 5V tolerant, unless indicated.

22 Datasheet

Table 5. Inter-Repeater Backplane Signal Descriptions

39 COMP_SEL AI

100 Mbps IRB Signals

36 IR100CFS 3

pull-up resistor, and connects between ICs on the same board.

37 IR100CFSBP

connects between ICs with Chip ID = 00, on different boards. IR100CFSBP requires a single 91Ω pull-up resistor in each stack.

38 IR100SNGL

one or more ports. Do not connect this signal between boards.

40 IR100COL

41 IR100DEN

42 IR100DV

1. I = Input, O = Output, I/O = Input/Output, D = Digital, AI = Analog Input, A I/O = Analog Input/Output,

pull-up resistors must be installed as listed above. NC = No Clamp. Pad does not clamp input in the absence of power.

1. Pins are 5V tolerant, unless indicated.
2. IR10CFS is not 5V tolerant.

50 IR100CLK

74LVT245 buffer is recommended.

56 IR100ISO

to isolate the 100 Mbps IRB.

10 Mbps IRB Signals

11 IR10DAT

330Ω resistor. Buffer this signal between boards.

12 IR10CLK

used to increase noise immunity.

6 IR10DEN

10 IR10ENA

3 IR10COL

collision. Do not connect between boards and do not buffer. Table 5. Inter-Repeater Backplane Signal Descriptions (Continued)

1. I = Input, O = Output, I/O = Input/Output, D = Digital, AI = Analog Input, A I/O = Analog Input/Output,

pull-up resistors must be installed as listed above. NC = No Clamp. Pad does not clamp input in the absence of power.

1. Pins are 5V tolerant, unless indicated.
2. IR10CFS is not 5V tolerant.

24 Datasheet

4 IR10COLBP

the same function as IR10COL, but is used between boards. pulled up by one 330Ω resistor per stack.

2 IR10CFS 4

between boards and do not buffer.

5 IR10CFSBP

80 MACACTIVE

drives the three-level IR10CFS pin.

55 IR10ISO

74LVT245. Driven High (disable) to isolate the 10 Mbps IRB.

81 HOLDCOL

attach the HOLDCOL signals from different boards together.

201 MMSTRIN I

64 MMSTROUT

pass between MMSTRIN and MMSTROUT.

1. I = Input, O = Output, I/O = Input/Output, D = Digital, AI = Analog Input, A I/O = Analog Input/Output,

pull-up resistors must be installed as listed above. NC = No Clamp. Pad does not clamp input in the absence of power.

1. Pins are 5V tolerant, unless indicated.
2. IR10CFS is not 5V tolerant.

Table 6. Twisted-Pair Port Signal Descriptions For unused ports, tie together with 100Ω resistors and float.

1. I = Input, O = Output, I/O = Input/Output, D = Digital, A = Analog, AI = Analog Input, AO = Analog Output,

A I/O = Analog Input/Output, OD = Open Drain, OS = Open Source, PD = Pull Down, PU = Pull Up. NC = No Clamp. Pad does not clamp input in the absence of power.

26 Datasheet

Table 7. Serial Management Interface Signal Descriptions

57 RECONFIG

Flag with all 0s) on the bus.

63 SER_MATCH

58 SRX

externally. SRX is sampled on the rising edge of SERCLK.

59 STX

impedance state. STX is driven on the falling edge of SERCLK.

60 SERCLK

is either a 625 kHz output or a 0 to 2 MHz input.

198 ARBIN

186 ARBSELECT

Arbitration Mode Select - Input. 0 = PROM based, 1 = chain based. (refer to Note 3 below and to Table 8).

67 MGR_PRES

1. I = Input, O = Output, I/O = Input/Output, D = Digital, A = Analog, AI = Analog Input,

A I/O = Analog Input/Output, OD = Open Drain, OS = Open Source, PD = Pull Down, PU = Pull Up. NC = No Clamp. Pad does not clamp input in the absence of power.

1. Pins are 5V tolerant, unless indicated.
2. Input must be static. Refer to “LED Pins Multiplexed with Configuration Inputs” on page 69 for information

Table 8. LED Signal Descriptions LED Mode Select - Input. See Note 3 in footer below. These pins are shared with the LEDACT100, LEDCOL10 outputs.

175 LEDABGSEL I

Refer to “Activity Graph LEDs” on page 59. This pin is shared with the Port8_LED2 output.

183 AUTOBLINK

LED Blink Mode Select - Input. See Note 3 in footer below. This pin is shared with the LEDACT10 output.

83 LEDDAT O

to-Parallel LED drivers. See “Serial LED Interface” on page 40.

84 LEDLAT O

LED drivers. See “Serial LED Interface” on page 40.

82 LEDCLK

Parallel LED drivers. See “Serial LED Interface” on page 40. Configuration Interface” on page 60. LED Driver 1 - Ports 1 through 8. Programmable LED driver. Active Low. See “Direct Drive LEDs” on page 42. LED Driver 2 - Ports 1 through 8. Programmable LED driver. Active Low. See “Direct Drive LEDs” on page 42. LED Driver 3 - Ports 1 through 8. Programmable LED driver. Active Low. See “Direct Drive LEDs” on page 42.

1. I = Input, O = Output, I/O = Input/Output, D = Digital, A = Analog, AI = Analog Input,

the IRB is not used, required pull-up resistors must be installed as listed above. NC = No Clamp. Pad does not clamp input in the absence of power.

1. Pins are 5V tolerant, unless indicated.
2. Input must be static; Refer to “LED Pins Multiplexed with Configuration Inputs” on page 69 for information

28 Datasheet

185 COL10_LED

186 COL100_LED

183 ACT10_LED

configuration input (refer to Note 3 below).

184 ACT100_LED

configuration input (refer to Note 3 below). Table 9. Power Supply and Indication Signal Descriptions digital ground should be supplied for every one of these pins. capacitor to GND should be supplied for every one of these pins. Use ferrite beads to create a separate analog VCC plane. capacitor to GND should be supplied for every one of these pins. Use ferrite beads to create a separate analog VCC plane.

1. I = Input, O = Output, I/O = Input/Output, D = Digital, A = Analog, AI = Analog Input,

A I/O = Analog Input/Output, OD = Open Drain, OS = Open Source, PD = Pull Down, PU = Pull Up. NC = No Clamp. Pad does not clamp input in the absence of power.

1. Pins are 5V tolerant, unless indicated.

Table 8. LED Signal Descriptions (Continued)

1. I = Input, O = Output, I/O = Input/Output, D = Digital, A = Analog, AI = Analog Input,

the IRB is not used, required pull-up resistors must be installed as listed above. NC = No Clamp. Pad does not clamp input in the absence of power.

1. Pins are 5V tolerant, unless indicated.
2. Input must be static; Refer to “LED Pins Multiplexed with Configuration Inputs” on page 69 for information

GND - Ground. Connect each of these pins to system ground plane.

102 RBIAS A

79 RPS_PRES

presence of redundant power supply. Tie Low if not used.

78 RPS_FAULT

the RPS_LED output (refer to LED section). Tie High if not used. Table 9. Power Supply and Indication Signal Descriptions (Continued)

1. I = Input, O = Output, I/O = Input/Output, D = Digital, A = Analog, AI = Analog Input,

A I/O = Analog Input/Output, OD = Open Drain, OS = Open Source, PD = Pull Down, PU = Pull Up. NC = No Clamp. Pad does not clamp input in the absence of power.

1. Pins are 5V tolerant, unless indicated.

Table 10. PROM Interface Signal Descriptions

68 PROM_CLK

If a PROM is not used, this pin must be tied Low.

69 PROM_CS

70 PROM_DTOUT

High signal driven only when ChipID = 00.

71 PROM_DTIN

1. I = Input, O = Output, I/O = Input/Output, D = Digital, A = Analog, AI = Analog Input,

A I/O = Analog Input/Output, OD = Open Drain, OS = Open Source, PD = Pull Down, PU = Pull Up. NC = No Clamp. Pad does not clamp input in the absence of power.

1. Pins are 5V tolerant, unless indicated.

30 Datasheet

Table 11. Miscellaneous Signal Descriptions

53 RESET

driven by an ‘LS14 or similar device.

54 CLK25

assigned ChipID = 00. See “Serial Management I/F” on page 52.

33 CONFIG(0) /

Serial Management Interface (SMI).

25 CONFIG(1) /

cards, status, etc.) in the Repeater Serial Configuration register. brought to the SMI for user access.

1. I = Input, O = Output, I/O = Input/Output, D = Digital, A = Analog, AI = Analog Input,

A I/O = Analog Input/Output, OD = Open Drain, OS = Open Source, PD = Pull Down, PU = Pull Up. NC = No Clamp. Pad does not clamp input in the absence of power.

1. Pins are 5V tolerant, unless indicated.

3.0 Functional Description

3.1 Introduction

ports that may be connected to 10/100 MACs. configure itself accordingly. TP ports and 48 MII ports) can be supported in a single stack. Parallel LED drivers. Refer to Table 8 for details.

182 IRQ

for criteria and clearing options. Requires an external pull-up resistor. NC - No Connects. Leave these pins unconnected. Table 11. Miscellaneous Signal Descriptions (Continued)

1. I = Input, O = Output, I/O = Input/Output, D = Digital, A = Analog, AI = Analog Input,

A I/O = Analog Input/Output, OD = Open Drain, OS = Open Source, PD = Pull Down, PU = Pull Up. NC = No Clamp. Pad does not clamp input in the absence of power.

1. Pins are 5V tolerant, unless indicated.

32 Datasheet

3.2 Port Configuration

or change the configuration through the PHY Port Control Register.

3.2.1 Auto-Negotiation

status registers, and control register. 100 Mbps half-duplex and/or 10 Mbps half-duplex; it never advertises full duplex. configures the port and updates the status registers appropriately. Figure 3. Typical LXT988x Managed Repeater Architectures

Advanced 10/100 Repeater with Integrated Management — LXT9860/9880 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 33

3.2.2 Forced Operation

A port can be directly configured to operate in either 100BASE-TX or 10BASE-T. When a port is configured for forced operation, it immediately operates in the selected mode. All links are established as half-duplex only. As a repeater, the LXT98x0 cannot support full-duplex operation.

3.2.3 Changing Port Speed - Forced

To force a port speed change while operating, the following sequence is required:  Disable the port(s) to be changed.  Set PHY Port Control Register to desired speed.  Perform a Repeater Reset (at Register 144; see Table 83 on page 113. The LXT98x0 does not read hardware configuration pins).  Re-enable the port(s). Note: Forcing a speed change on any port requires a Repeater Reset.

3.2.4 Link Establishment and Port Connection

Once a port establishes link, the LXT98x0 automatically connects it to the appropriate repeater state machine. If link loss is detected, the port returns to the auto-negotiation state.

3.2.5 MII Port Configuration

These ports can be set via hardware tie ups/downs to be either 10 Mbps or 100 Mbps. The statistics for these ports are the same as for the other 10/100 ports, except Isolation, Partition, and Symbol Error.

3.3 Interface Descriptions

The LXT9880 and LXT9860 devices provide eight and six network interface ports, respectively. Each port provides a twisted-pair interface. The twisted-pair interface directly supports 100BASE- TX and 10BASE-T. Ethernet applications and fully complies with IEEE 802.3 standards. A common termination circuit is used.

3.3.1 Twisted-Pair Interface

The LXT98x0 pinout is optimized for dual-height RJ-45 connectors. The twisted-pair interface for each port consists of two differential signal pairs — one for transmit and one for receive. The transmit signal pair is TPOP/TPON, the receive signal pair is TPIP/TPIN. The transmitter requires magnetics with 1:1 turns ratio. The center tap of the primary side of the transmit winding must be tied to a quiet VCC for proper operation. When the twisted-pair interface is disabled, the transmitter outputs are tri-stated. The receiver requires magnetics with a 1:1 turns ratio, and a load of 100Ω . When the twisted-pair port is enabled, the receiver actively biases its inputs to approximately 2.8V . When the twisted-pair interface is disabled, no biasing is provided. A 4 kΩ load is always present across the TPIP/TPIN pair.

34 Datasheet

sent and received in order to maintain the link. stack designs to meet EMI requirements.

3.3.2 Media Independent Interface

Media Access Controller (MAC) as shown in Figure 4. This interface is not MDIO/MDC capable.

3.3.3 Serial Management Interface

common line, and uses the minimum number of signals (2) for ease of stack design. with a start/stop flag, header and CRC field for error checking. Zero-bit insertion/removal is used. Figure 4. MII Interface

Advanced 10/100 Repeater with Integrated Management — LXT9860/9880 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 35 Address assignment is provided via one of two arbitration mechanisms which are activated whenever the device is powered up or reset/reconfigured. Refer to “Serial Management I/F” on page 52.

3.3.4 Serial PROM Interface

The serial PROM interface allows the loading of optional information unique to each board. Items such as serial number or date of manufacture can be placed in the serial PROM, which is also used in the address arbitration process. See “Serial PROM Interface” on page 59.

3.4 Repeater Operation

The LXT98x0 contains two internal repeater state machines— one operating at 10 Mbps and the other at 100 Mbps. The LXT98x0 automatically switches each port to the correct repeater, once the operational state of that port has been determined. Each repeater connects all ports configured to the same speed (including the MII), and the corresponding Inter-Repeater Backplane. Both repeaters perform the standard jabber and partition functions. 3.4.1 100 Mbps Repeater Operation The LXT98x0 contains a complete 100 Mbps Repeater State Machine (100RSM) that is fully IEEE 802.3 Class II compliant. Any port configured for 100 Mbps operation is automatically connected to the 100 Mbps Repeater. This includes any of the eight media and two MII ports configured for 100 Mbps operation. The 100 Mbps RSM has its own Inter-Repeater Backplane (100IRB). Multiple LXT98x0s can be cascaded on the 100IRB and operate as one repeater segment. Data from any port is forwarded to all other ports in the cascade. The 100IRB is a 5-bit symbol-mode interface. It is designed to be stackable. The LXT98x0 maintains a complete set of statistics for its local 100 Mbps repeater segment. These are accessible through the high-speed serial management interface. The LXT98x0 performs the following 100 Mbps repeater functions:  Signal amplification, wave-shape restoration, and data-frame forwarding.  SOP, SOJ, EOP , EOJ delay < 46BT; class II compliant.  Collision Enforcement. During a 100 Mbps collision, the LXT98x0 drives a 0101 jam signal (encoded as Data 5 on TX links) to all ports until the collision ends. There is no minimum enforcement time.  Partition. The LXT98x0 partitions any port that participates in excess of 60 consecutive collisions or one long collision approximately 575.2 µs long. Once partitioned, the LXT98x0 monitors and transmits to the port, but does not repeat data received from the port until it un- partitions.  Un-partition. The LXT98x0 supports two un-partition algorithms: — The alternative un-partition algorithm (default), which complies with IEEE specification 802.3aa un-partitions a port on either transmit or receive of at least 450-560 bits without collision.

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36 Datasheet

Document #: 248987 Revision#: 003 Rev Date: 08/07/01 — The normal algorithm, which complies with the IEEE specification 802.3u, is available through the management interface. This algorithm un-partitions a port only when data is transmitted to the port for 450-560 bit times without a collision.  Isolate. The LXT98x0 isolates any port receiving more than two successive false carrier events. A false carrier event is a packet that does not start with a /J/K symbol pair. Note: this is not the same function as the 100IRB isolate function, which involves isolating the backplane.  Un-isolate. The LXT98x0 un-isolates a port that remains in the IDLE state for 33000 +/- 25% BT or that receives a valid frame at least 450-500 BT in length.  /T/R generation. The LXT98x0 can insert a /T/R symbol pair (End-of-Stream Delimiter) on any incoming packet that does not include one. This feature is optional, and is enabled through the management interface.  Jabber. The LXT98x0 ignores any receiver remaining active for more than 57,500 bit times. The LXT98x0 exits this state when either one of the following conditions is met: — On power-up reset — When carrier is no longer detected Note: The Isolate, Partition, and Symbol Error functions do not apply to MII ports. 3.4.2 10 Mbps Repeater Operation The LXT98x0 contains a complete 10 Mbps Repeater State Machine (10RSM) that is fully IEEE 802.3 compliant. Any port configured for 10 Mbps operation is automatically connected to the 10 Mbps Repeater. This includes any of the media and MII ports configured for 10 Mbps operation. The 10RSM has its own Inter-Repeater Backplane (10IRB). Multiple LXT98x0s can be cascaded on the 10IRB and operate as one repeater segment. Data from any port is forwarded to all other ports in the cascade. The LXT98x0 maintains a complete set of statistics on its 10 Mbps repeater segment. These are accessible through the high-speed serial management interface. The LXT98x0 performs the following 10 Mbps repeater functions:  Signal amplification, wave-shape restoration, and data-frame forwarding.  Preamble regeneration. All outgoing packets have a minimum 56-bit preamble and 8-bit SFD.  Collision Enforcement. During a 10 Mbps collision, the LXT98x0 drives a jam signal (“1010”) to all ports for a minimum of 96 bit times until the collision ends.  Partition. The LXT98x0 partitions any port in excess of 31 consecutive collisions. Once partitioned, the LXT98x0 continues monitoring and transmitting to the port, but does not repeat data received from the port until it properly un-partitions. (Also partitions for excessive length of a collision.)  Un-partition. The algorithm, which complies with the IEEE 802.3 specification, un-partitions a port when data can be either received or transmitted from the port for 450-560 bit times without a collision on that port.  Jabber. The LXT98x0 asserts a minimum-IFG idle period when a port transmits for longer than 40,000 to 75,000 bit times.

Advanced 10/100 Repeater with Integrated Management — LXT9860/9880 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 37

3.5 Management Support

3.5.1 Configuration and Status

The LXT98x0 provides management control and visibility of the following functions:  Counter Reset and Zeroing  Auto-negotiation (Control, Status, Advertisement, Link Partner, and Expansion)  Device and Board Configuration  LED Functions  Source Address Tracking (per port)  Source Address Matching (per chip)  Device/Revision ID

3.5.2 SNMP and RMON Support

The LXT98x0 provides SNMP and RMON support through its statistics gathering function. Statistics are gathered on all packets flowing through the device for each of the ports, including the MII. The LXT98x0 maintains statistics for both the entire 10 Mbps and 100 Mbps repeaters, independent of the speed setting of the MII ports. All statistics are stored in 32- or 64-bit registers. Per-port counters include:

3.5.3 Source Address Management

The LXT98x0 provides two source address management functions per port: source address tracking and source address matching. These functions allow a network manager to track source addresses at each port, or to identify any port sourcing a particular address.

3.6 Requirements

3.6.1 Power

The LXT98x0 has four types of +3.3V power supply input pins: two digital (VCC, GND) and two analog (VCCR, VCCT). These inputs may be supplied from a single source. Ferrite beads should be used to separate the analog and digital planes. These supplies should be as clean as possible. Each supply input should be decoupled to ground. Refer to Table 9 on page 28 for power and ground pin assignments, and to the “General Design Guidelines” on page 61. Readable Frames Readable Octets FCS Errors Alignment Errors FramesTooLong ShortEvents Runts Collisions LateEvents VeryLongEvents DataRateMismatch AutoPartitions Broadcast Multicast SA Changes Isolates Symbol Errors

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3.6.2 Clock

A stable, external 25 MHz reference clock source (TTL) is required to the CLK25 pin. The reference clock is used to generate transmit signals and recover receive signals. A crystal-based clock is recommended over a derived clock (i.e., PLL-based) to minimize transmit jitter. Refer to Table 26 on page 67 for a list of recommended oscillators and to Table 29 on page 75 for clock timing requirements.

3.6.3 Bias Resistor

The RBIAS input requires a 22.1 kΩ , 1% resistor connected to ground.

3.6.4 Reset

At power-up, the reset input must be held Low until VCC reaches at least 3.15V . A buffer should be used to drive reset if there are multiple LXT98x0 devices. The clock must be active. Software and hardware resets are identical. Refer to Table 74 on page 108 and Table 84 on page 113 for Software Reset details.

3.6.5 PROM

Although not required, an external, auto-incrementing 48-bit PROM can be used for two purposes:  Support the PROM-based address arbitration scheme on the Serial Management Interface (See “PROM Arbitration Mechanism” on page 58.)  Assign a unique ID and upload configuration data to all LXT98x0s on a board Multiple devices on the same board can share a single common PROM. The LXT98x0 with ChipID = 00 actively reads the PROM at power-up; all other LXT98x0s “listen in”. If PROM arbitration is not used, the PROM data input signal must be tied either High or Low. (See “Serial PROM Interface” on page 59.)

3.6.6 Chip ID

Each cascaded LXT98x0 requires a unique 2-bit Chip ID value. The Serial Management Interface (SMI) identifies each IC by ChipID. One LXT98x0 on each board must be assigned ChipID = 00. In the Header Field, the Chip Address is defined by three bits. The Most Significant Bit (MSB) = 0; the value of the other two bits is set by pins. Refer to “Serial Management I/F” on page 52.

3.6.7 Management Master I/O Link

In multiple device applications, the Management Master daisy chain (MMSTRIN/MMSTROUT) ensures that collisions are counted correctly. Connect the MMSTRIN input to the MMSTROUT output of the previous device when cascading and stacking. Ground the MMSTRIN input of the first or only device. In hot-swap applications, resistive bypassing can be used with a 1 - 3 kΩ value.

3.6.8 IRB Bus Pull-ups

Even when the LXT98x0 is used in a stand-alone configuration, pull-up resistors are required on the IRB signals listed. See Figure 30 on page 74 and Figure 31 on page 74 for sample circuits.

3.7 LED Operation

Serial-to-Parallel devices (see “Serial LEDs” on this page).

3.7.1 LEDs at Start-up

start-up routine is an LED check.

3.7.2 LED Event Stretching

LED1, 2, 3 Modes section for stretching specifics.

3.7.3 LED Blink Rates

100 Mbps IRB 10 Mbps IRB

Figure 5. LED Blink Rates

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3.7.4 Serial LED Interface

3.7.4.1 Serial Shifting

Figure 6 shows the Serial LED shift loading.

3.7.4.2 Serial LED Signals

and Table 12 for details on the LED serial bit stream. Figure 6. Serial LED Shift Loading

100 Mbps Shift Order

30 LEDs

3.7.4.3 Activity Graph LEDs

smoothing out the activity. LEDs are provided for both the 10 Mbps and 100 Mbps segments. lit when the percent activity value associated with that step is met or exceeded. Figure 7. Serial LED Port Signaling Table 12. Serial LED Port Bit Stream

7 MII Port 1 - LED1 Collision - 10M1 ACTG8 ACTG8

6 MII Port 1 - LED2 Collision - 100M1 ACTG7 ACTG7

5 MII Port 1 - LED3 Manager Present ACTG6 ACTG6

4 MII Port 2 - LED1 Activity - 10M

1 ACTG5 ACTG5

3 MII Port 2 - LED2 Activity - 100M1 ACTG4 ACTG4

2 MII Port 2 - LED3 Global Fault ACTG3 ACTG3

1 Not Used Not Used ACTG2 ACTG2

0 Not Used RPS Fault ACTG1 ACTG1

1. These LEDs are multiplexed with Configuration Inputs.

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3.7.5 Direct Drive LEDs

port LEDs are updated simultaneously to illustrate clear, non-overlapping status. segments are available in both serial and direct drive.

3.7.6 LED Modes

LED mode control. Refer to Table 8 on page 27 for pin assignments and signal descriptions. are similarly controlled. Table 14 defines terms used to describe LED operation. Table 13. ACTGLED Display Modes

Table 14. LED Terms Port_Enabled True if port is enabled. (see Table 60 on page 102). Port_PartitionedTrue if port has been auto partitioned (10Mb mode). True if port has been auto partitioned or isolated (100Mb mode). Port_Is_TP True if port is a twisted-pair port. RPS_Present True if redundant power supply is switched in. RPS_Fault True if redundant power supply has a fault. Port_Ctl_HW True if configuration bits are set to hardware control. Port_Ctl_Off True if configuration bits are set to turn off the LED. Port_Ctl_On True if configuration bits are set to turn on the LED solid. Port_Ctl_Fast True if configuration bits are set to fast blink the LED. Rcv_Activity True if twisted-pair port on this device is receiving a packet.

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3.7.6.1 LED Mode 1

Mode 1 operations are described in Table 15. Table 15. LED Mode 1 Indications

10 Mbps operation Link_OK, not

100 Mbps operation

10 Mbps operation Link_OK,

100 Mbps mode

10 Mbps mode

the on-cycle, always follows. additional activity is ignored by the activity LED logic.

1. Refer to Table 13: LED Terms, which defines all key terms used in this section.

3.7.6.2 LED Mode 2

Mode 2 operations are described in Table 16. Table 16. LED Mode 2 Indications

10 Mbps:

100 Mbps:

2 N/A Any other state N/A

additional activity is ignored by the activity LED logic.

1. Refer to Table 14: LED Terms, which defines all key terms used in this section.
2. Receive activity is stretched to a 20 ms wide pulse. For every on-cycle of the stretched LEDs, an off-cycle,

with the same period as the on-cycle, always follows.

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3.7.6.3 LED Mode 3

Mode 3 operations are described in Table 17. Table 17. LED Mode 3 Indications as the on-cycle, always follows. additional activity is ignored by the activity LED logic.

1. Refer to Table Table 14: LED Terms, which defines all key terms used in this section.
2. Receive activity is stretched to a 20 ms wide pulse. For every on-cycle of the stretched LEDs, an off-cycle,

3.7.6.4 LED Mode 4

Mode 4 operations are described in Table 18.

3.8 IRB Operation

shown in Figure 9 on page 50. Table 18. LED Mode 4 Indications

100 Mbps operation Any other state

100 Mbps Link_OK

additional activity is ignored by the activity LED logic.

1. Refer to Table 14: LED Terms, which defines all key terms used in this section.
2. Receive activity is stretched to a 20 ms wide pulse. For every on-cycle of the stretched LEDs, an off-cycle,

with the same period as the on-cycle, always follows.

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3.8.1 IRB Signal Types

IRB signals can be characterized by the following connection types (For Stacking and Cascading connections, see Table 19 on page 50):  Local— connected between devices on the same board  Stack— connected between boards  Full— connected between devices in the same board and between boards.

3.8.2 IRB Isolation

The ISOLATE outputs (IR10ISO and IR100ISO) are provided to control the enable pins of external bidirectional transceivers. In stacking applications, they can be used to isolate one board from the rest of the stack. Only one device can control these signals. The output states of these pins are controlled by the Isolate bits in the Repeater Configuration Register. 3.8.3 10 Mbps-Only Operation

3.8.3.1 MAC IRB Access

The MACACTIVE pin allows an external MAC or other digital ASIC to interface directly to the 10 Mbps IRB. When the MACACTIVE pin is asserted, the LXT98x0 drives the IR10CFS and IR10CFSBP signals on behalf of the external device, allowing it to participate in collision detection functions.

3.8.3.2 Management Master Chain Arbitration

This daisy chain is provided for correct statistics gathering in 10 Mbps cascaded configurations. In stacked applications, this daisy chain must be maintained through cascades. In stand-alone applications, or for the first device in a chain, the MMSTRIN input must be pulled Low for the management counters to work correctly.

3.8.4 LXT98x/91x/98x0 Compatibility

The LXT98x0 devices feature low-power 3.3V design. The LXT98x and LXT91x devices operate at 5V and are incompatible with the LXT98x0 devices in cascades. The LXT98x0 devices, however, are backwards stackable with LXT98x and LXT91x repeaters. Note: Refer to “Inter-Repeater Backplane Compatibility” on page 71.

Figure 8. 100 Mbps IRB Connection

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Figure 9. IRB Block Diagram Table 19. Cascading and Stacking Connections Local Connect all. Do not connect. device and do not interconnect. boards. Use one pull-up resistor per stack. Full Connect all. Connect using buffers. For devices with ChipID ≠ 00, leave open. Digital IRB signals include IRnDAT, IRnCOL, IR10COLBP, IRnENA and IRnCLK. Local Analog IRB signal: IRnCFS. Inter-Board Analog IRB signal: IRnCFSBP. This diagram shows a single IRB. The LXT98xx actually has two independent IRBs, one per speed/segment. HOLDCOL, MMSTRIN, and MMSTROUT are used on the 10M IRB Only.

3.9 MII Port Operation

MIIn_SPD = 1. For 10 Mbps operation, set MIIn_SPD = 0. this is provided via the Serial Management Interface (SMI).

3.9.1 Preamble Handling

with the 8-bit SFD (no preamble bits). Note: MII Ports do not count partition, isolation, or symbol errors. Table 20. IRB Signal Details

1. Isolate and Driver Enable signals are provided to control an external bidirectional transceiver.

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3.10 Serial Management I/F

multiple LXT98x0 devices to be managed from one common bus.

3.10.1 SMI Signals

The interface consists of a data input line (SRX), data output line (STX), and a clock (SERCLK). management interface architecture. Refer to Figure 23 on page 68 for circuit details. Figure 10. LXT9880 MII Operation Figure 11. Typical SMI Bus Architecture

Advanced 10/100 Repeater with Integrated Management — LXT9860/9880 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 53

3.10.1.1 Serial Clock

SERCLK is a bidirectional pin; direction control is provided by the RECONFIG input. If RECONFIG is High, the LXT98x0 drives SERCLK at 625 kHz. If RECONFIG is Low, SERCLK is an input, between 0 and 2 MHz. The clock can be stopped after each operation, as long as an idle (at least 12 ones in a row) is transmitted first.

3.10.1.2 Serial Data I/O

The serial data pins, SRX and STX, should be “logically” tied together using open-collector buffers. See Figure 23 on page 68. The SRX input is compared with the STX output. If a mismatch occurs, STX goes to a high impedance. STX is driven on the falling edge of SERCLK. SRX is sampled on the rising edge.

3.10.2 Read and Write Operations

Data can be read or written in blocks. The LXT98x0 can read the full length field of consecutive counters with a single access. Block writes are limited to 2 long words. Normally the network manager directs read and write operations to a specific LXT98x0 device using a two-part address consisting of HubID and Chip Address. Note: In the Header Field, the Chip Address is defined by three bits. The Most Significant Bit (MSB) = 0; the value of the other two bits is set by pins. The LXT98x0 responds to an operation within 12 serial controller bit times. In the case of an error during a transfer, the LXT98x0 does not implement the requested command.

3.10.2.1 SMI Collision Handling

Upon colliding with another packet, the LXT98x0 ceases transmission, based on the bit pattern of the colliding packets as shown in Figure 12. In the case of a collision, the driver who is sourcing a 0 wins. The LXT98x0 does not retry a response, unless it was an address arbitration packet. In addition, if an address arbitration packet jumps in during a request/response sequence, before the addressed LXT98x0 has responded, the addressed LXT98x0 aborts the requested operation. Note: The minimum time between packets must be at least 12 bit times with the data set to all ones.

3.10.2.2 SMI Address Match Indication

The LXT98x0 SER_MATCH pin (see Figure 13) indicates detection of a serial command matching the device Hub ID. Broadcast commands also trigger the SER_MATCH output. Note that the initial HubID upon power-up or reset is the Broadcast (all ones) address.

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3.10.2.3 SMI Frame Format

The SMI uses a simple frame format, shown in Figure 14. Table 21 describes the individual fields. provides a variety of typical packets. must be preceded with an idle. Figure 12. SMI Collision Handling Figure 13. SMI Address Match Indication

1. Simultaneous Transmissions, Pkt 1 completes

Transmit om falling CLK edge, sample on rising CLK edge.

1. SER_MATCH can also occur at the end of a packet if a Start Flag is not seen but a Stop Flag is.

This can occur only during unit installation or removal.

Table 21. SMI Message Fields Chip ID Identifies one of eight devices on a system. Assigned by 2 external pins on each device. The Most Significant Bit (MSB) = 0; the value of the other two bits is set by pins. Address Specifies address of register or register block to be transferred. Figure 14. Serial Management Frame Format Table 22. SMI Header Storage

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Table 23. SMI Command Set address in one serial packet. instruction is the actual returned data. ID. Once assigned, the command is discontinued. 00 (Hex) ConfigChg Arbitration LXT98x0 Notifies system of configuration change (hot swap). Requests new arbitration phase. 10 (Hex) Re-arbitrate Arbitration Network Mgr Re-starts arbitration. Assigns all new addresses. for this type of packet is the actual returned data.

3.10.3 Address Assignment Methods

HubID is assigned through one of two arbitration mechanisms as shown in Figure 15. Table 24. Typical Serial Management Packets

1. Other than checking that the top 3 bits of the address equals 000, the LXT98x0 does not check if the user
2. If the user performs a write operation of length 1 or 2 and does not send a data field, the LXT98x0 writes

junk into the specified registers. This constitutes an invalid command.

1. If the user reads past the highest location of the LXT98x0, all those locations reads back 0s.
2. If a read operation is performed with a length of 0, the LXT98x0 does not respond.
3. ChipID is defined by 3 bits, with the MSB = 0; value of the other two bits is set by pins.

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3.10.3.1 Chain Arbitration Mechanism

assigns Hub IDs using the Assign Hub ID (Arb Method 2) and Set ARBOUT to ZERO commands. until all chips have been assigned a unique address. Note: It is recommended that HubIDs match in any given hub. ARBOUT to 1, and then re-perform the address assignment process. new board has been encountered.

3.10.3.2 PROM Arbitration Mechanism

1. At power-up, the device with ChipID = 00 reads a 48-bit ID from the PROM. All other devices

Figure 15. Address Arbitration Mechanisms

Advanced 10/100 Repeater with Integrated Management — LXT9860/9880 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 59 on the board listen in and record the ID. The device with ChipID = 00 then transmits Arbitration Request messages on the SMI every 2-3 ms. The request messages from two boards may collide. If this happens, a resolution scheme ensures that only one message is transmitted. The network manager must respond to each request with a message that includes the 48-bit ID and the HubID. All devices hear this message, but only those matching the 48-bit ID receive the HubID as their own. Once a HubID is assigned to a hub, that hub ceases requesting a HubID. This process continues until all hubs are assigned an ID. Should a hub power off and back on, the hub re- requests an ID, which the manager provides. An address arbitration packet is selected over normal requests.

3.10.3.3 Address Re-Arbitration

There are two mechanisms for address re-arbitration following a configuration change, such as a hot-swap of a board:  Manual Re-arbitration. If the LXT98x0 detects a Low-to-High transition on RECONFIG, or if RECONFIG is High at power-up, it sends out a “Configuration Change” message (Start Flag with all 0s) on the bus. The network manager can use this message to detect that re-arbitration is required.  Network Manager. The network manager can detect or re-start arbitration at any time by sending the “Re-arbitrate” command.

3.10.4 Interrupt Functions

The LXT98x0 provides a single open-collector pin for external interrupt signalling. Several different interrupt conditions may be reported. The Interrupt Status Register (see Table 86) identifies the specific interrupt condition. The Interrupt Mask Register (see Table 87 on page 115) allows specific interrupts to be masked. Interrupts may be cleared in two ways, depending on the status of bit 11 in the repeater configuration register.

3.11 Serial PROM Interface

The serial PROM interface allows the vendor to load in optional information unique to each board. Items such as serial number or manufacture date can be placed in the serial PROM which can also be used in the address arbitration process. Each board must contain a unique set of information. Additionally, only 1 serial PROM is required per board, they are not required per chip. The LXT98x0 reads in the first 48 bits (three 16-bit words) from the PROM and stores them in a register. This read occurs only on power-up. Only the LXT98x0 with a ChipID of 00 drives the serial PROM control lines; all other LXT98x0s “listen” to the data and clock lines. The first bit into the LXT98x0 from this interface corresponds to bit 47. The serial PROM shifts out the most significant bit (15) of the word first (the PROM must be auto-incrementing).

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3.12 Serial Configuration Interface

plug-in cards, status, etc.) into the Repeater Configuration Register (see Table 75 on page 109). positions versus the ‘165 parallel input positions. Figure 16. Optional R/W Serial PROM Interface The LXT98x0 drives outgoing data on the falling clock edge. The LXT98x0 samples incoming data on the rising clock edge.

4.0 Application Information

4.1 General Design Guidelines

ground plane that is not located adjacent to the signal layer. recommended for decoupling caps).  Provide ample power and ground planes.  Provide termination on all high-speed switching signals and clock lines.  Provide impedance matching on long traces to prevent reflections.  Route high-speed signals next to a continuous, unbroken ground plane.  Filter and shield DC-DC converters, oscillators, etc. Figure 17. Serial Configuration Interface Figure 18. Serial Configuration Interface Signaling

62 Datasheet

edge of the board. Use this area for chassis ground, or leave it void.

4.2 Typical Applications

through Figure 26 show application circuitry details. Figure 19. 8-Port Managed 10/100 Stackable Repeater Figure 20. 32-Port Managed 10/100 Repeater

Advanced 10/100 Repeater with Integrated Management — LXT9860/9880 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 63

4.3 Application Circuitry

4.3.1 Power and Ground

4.3.1.1 Supply Filtering

Power supply ripple and digital switching noise on the VCC plane causes EMI and degrades line performance. Predicting a design’s performance is difficult, although certain factors greatly increase the risks:  Poorly-regulated or over-burdened power supplies.  Wide data busses (>32-bits) running at a high clock rate.  DC-to-DC converters. Many of these issues can be improved by following good general design guidelines. In addition, Intel recommends filtering between the power supply and the analog VCC pins of the LXT98x0. Filtering has two benefits. First, it keeps digital switching noise out of the analog circuitry inside the LXT98x0, which helps line performance. Second, if the VCC planes are laid out correctly, it keeps digital switching noise away from external connectors, reducing EMI. The VCC plane should be divided into two sections. The digital section supplies power to the digital VCC pins and to the external components. The analog section supplies power to VCCR and VCCT pins of the LXT98x0. The break between the two planes should run under the device. In designs with more than one LXT98x0, use a single continuous analog VCC plane to supply them all. The digital and analog VCC planes should be joined at one or more points by ferrite beads. The beads should produce at least a 100Ω impedance at 100 MHz. The beads should be placed so current flows evenly. The maximum current rating of the beads should be at least 150% of the current that is actually expected to flow through them. Each LXT98x0 draws a maximum of 1000mA from the analog supply so beads rated at 1500mA maximum should be used. A bulk cap (2.2 -10 µF) should be placed on each side of each ferrite bead to ground to stop switching noise from traveling through the ferrite. In addition, a high-frequency bypass cap (.01µf) should be placed near each analog VCC pin to ground.

4.3.1.2 Ground Noise

The best approach to minimize ground noise is strict use of good general design guidelines and by filtering the VCC plane.

4.3.1.3 Power and Ground Plane Layout Considerations

The power and ground planes should be laid out carefully. The following guidelines are recommended:  Follow the guidelines in the Application Note 113 (LXT98x0 Design and Layout Guide) for locating the split between the digital and analog VCC planes.  Keep the digital VCC plane away from the TPOP/N and TPIP/N signals, magnetics, and RJ-45 connectors.

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Document #: 248987 Revision#: 003 Rev Date: 08/07/01  Place the layers so the TPOP/N and TPIP/N signals are routed near or next to the ground plane. For EMI, it is more important to shield TPOP/N than TPIP/N.

4.3.1.4 Chassis Ground

For ESD protection, create a separate chassis ground. For isolation, encircle the board and place a “moat” around the signal ground plane to separate signal ground from chassis ground. Chassis ground should extend from the RJ-45 connectors to the magnetics, and can be used to terminate unused signal pairs (‘Bob Smith’ termination). In single-point grounding applications, provide a single connection between chassis and circuit grounds with a 2kV isolation capacitor. In multi- point grounding schemes (chassis and circuit grounds joined at multiple points), provide 2kV isolation to the Bob Smith termination.

4.3.1.5 The RBIAS Pin

The LXT98x0 requires a 22.1 kΩ, 1% resistor directly connected between the RBIAS pin and ground. Place the RBIAS resistor as close to the RBIAS pin as possible. Run an etch directly from the pin to the resistor, sink the other side of the resistor, and surround the RBIAS trace with a filtered ground. Do not run high-speed signals next to RBIAS.

4.3.2 MII Terminations

4.3.3 Twisted-Pair Interface

Figure 21. Power and Ground Connections

66 Datasheet

 Place magnetics as close as possible to the LXT98x0.  Keep transmit pair traces short. traces completely. Otherwise, keep planes 3-4 layers away. receiver, especially for long line lengths.  Route the signal pairs differentially, close together. Allow nothing to come between them.  Keep distances as short as possible; both traces should have the same length.  Avoid vias and layer changes.  Keep the transmit and receive pairs apart to avoid cross-talk. transmit on the other side of the PCB.  Keep termination circuits grouped closely together and on the same side of the board.  Always put termination circuits close to the source end of any circuit.

4.3.3.1 Magnetics Information

static voltages across the connectors and cables. Refer to Table 25 for magnetics specifications.

4.3.4 Clock

A stable, external 25 MHz system clock source (CMOS) is required. See Table 26. Table 25. LXT98x0 Magnetics Specifications

Table 26. Oscillator Manufacturers Figure 22. Typical Twisted-Pair Port Interface and Power Supply Filtering

68 Datasheet

4.3.5 SMI and PROM Circuits

Figure 23. Typical Serial Management Interface Connections Figure 24. Serial Controller Connection Showing PAL

1. When not transmitting STX goes to 1, hence

open collector and no drive.

1. PAL is used to detect collisions and gate (cease) transmission.

the CTS bit, which is then cleared by the RTS bit.

4.3.6 LED Circuits

4.3.6.1 Direct Drive LEDs

limiting resistor, to a positive voltage rail. The LEDs are turned on when the output pin drives Low. LED component selection by allowing more common, high forward voltage LEDs to be used. Refer to Figure 27 for a circuit illustration.

4.3.6.2 LED Pins Multiplexed with Configuration Inputs

Some static configuration inputs are multiplexed with LED pins to reduce the LXT98x0 pin count. Figure 25. Serial PROM Interface Figure 26. Typical Reset Circuit

1. t(CR1 > Power Supply Ramp Up Time. R2 discharges C when supply

goes away. The ‘14 is needed for multiple LXT98x0 devices.

70 Datasheet

with a single resistor to set them all to the same value. Refer to Figure 27 for a circuit illustration. selection as with Direct Drive LEDs). used for the LED serial interface, 5V LED driving is achieved (see “Serial LEDs” on page 70).

4.3.6.3 Serial LEDs

status indications are provided on multiplexed configuration pins and duplicated on the serial port. implementation. Refer to Figure 28 for an illustration of the LED serial interface circuit. the last serial output to serial input of next serial interface device. Figure 27. LED Circuits - Direct Drive & Multiplexed Configuration Inputs

port signalling and Table 12 on page 41 which documents the Serial LED Stream. design so that it is not noticeable to the eye. The LED outputs may change momentarily.

4.4 Inter-Repeater Backplane Compatibility

 Local— the backplane between cascaded devices on the same board.  Stack— the backplane between multiple boards. Each of these backplanes consists of both analog and digital signals. Figure 28. Serial LED Circuit

LXT9860/9880 — Advanced 10/100 Repeater with Integrated Management

72 Datasheet

Document #: 248987 Revision#: 003 Rev Date: 08/07/01 4.4.1 Local Backplane — 3.3V Only The LXT98x0 local backplane operates at 3.3V only. LXT98x and LXT91x devices operate at 5V . LXT98x0 devices are, therefore, not cascadable with LXT98x and LXT91x devices. Note: Do not mix LXT98x0 with either LXT98x or LXT91x devices on the local backplanes. 4.4.2 Stack Backplane — 3.3V or 5V The LXT98x0 stack backplanes can be configured to be either 3.3V or 5V . COMP_SEL (Pin 39), a special input pin, selects between the two voltage modes, depending on whether 3.3V or 5V is applied. 3.3V-Only Stacks Apply 3.3V to COMP_SEL, IR100CFSBP , IR10CFSBP, and IR10COLBP for LXT98x0 backplane operation For 5V Backwards Stackability Apply 5V to COMP_SEL, IR100CFSBP, IR10CFSBP, and IR10COLBP for LXT98x and LXT91x backplane operation. With either mode (3.3V or 5V), COMP_SEL draws less than 3 mA. Note: 1. The external pull-up resistor values remain the same, regardless of 3.3V or 5V backplane operation. 2. The recommended digital signal external buffer has been changed to 74LVT245 for the LXT98x0. 3.3V Operation Boards designed for 3.3V backplane operation should only be stacked with other 3.3V boards. Existing LXT98x or LXT91x based designs cannot operate in 3.3V . Incompatible Stacking Configurations The following stacking configurations are incompatible:  A LXT98x0-based board configured for 3.3V backplane operation and LXT98x or LXT91x based boards (5V only).  A LXT98x0-based board configured for 3.3V backplane operation and a LXT98x0-based board configured for 5V backplane operation. Note: Stacking boards designed for 3.3V backplane operation with boards designed for 5V backplane operation causes network errors. 5V Operation Boards designed for 5V backplane operation should only be stacked with other 5V boards:  LXT98x or LXT91x-based designs.  LXT98x0 designs configured for 5V backplane operation.

operation causes network errors. Figure 29. 100 Mbps Backplane Connection between LXT98x and LXT98x0

1. The LXT98x and LXT98x0 devices can share the same Inter-Repeater Backplane so long as the proper backplane

buffers are used. Configuration is set to 5V.

1. For LXT98x, LXT91x: The buffer should be the 74ABT245.
2. Layout follows the same pattern for 10 Mbps operation.

74 Datasheet

Figure 30. Typical 100 Mbps IRB Implementation Figure 31. Typical 10 Mbps IRB Implementation

1. In stacked configurations, all devices with ChipID = 00 are tied together at IR100CFSBP. The entire stack
2. All devices with ChipID ¹ 00 require individual pull-up resistors at IR100CFSBP .
3. In stacked configurations, all devices with ChipID = 00 are tied together at IR100CFSBP . The entire stack must be
4. All devices with ChipID ¹ 00 require individual pull-up resistors at IR100CFSBP .

5.0 Test Specifications

guaranteed over the recommended operating conditions specified in Table 28. Table 27. Absolute Maximum Ratings Table 28. Operating Conditions

1. Typical values are at 25° C and are for design aid only; they are not guaranteed and not subject to

Table 29. Input System Clock1 Requirements

1. The system clock is CLK25 (Pin 54).
2. These requirements apply to the external clock supplied to the LXT98x0, not to LXT98x0 test
3. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production

76 Datasheet

Table 30. I/O Electrical Characteristics

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
2. Does not apply to IRB pins. Refer to Table 31 and Table 32 for IRB I/O characteristics.
3. Applies to RESET, CLK25, IR100SNGL, IR100COL, IR100DATn, IR100CLK, and IR10CLK pins.

Table 31. 100 Mbps IRB Electrical Characteristics

1. Typical values are at 25° C and are for design aid only; they are not guaranteed and not subject to
2. 91Ω resistors provide greater noise immunity. Systems using 91Ω resistors are backwards stackable with

systems using 100Ω resistors.

Table 32. 10 Mbps IRB Electrical Characteristics

1. Typical values are at 25° C and are for design aid only; they are not guaranteed and not subject to

Table 31. 100 Mbps IRB Electrical Characteristics (Continued)

1. Typical values are at 25° C and are for design aid only; they are not guaranteed and not subject to
2. 91Ω resistors provide greater noise immunity. Systems using 91Ω resistors are backwards stackable with

systems using 100Ω resistors.

78 Datasheet

Table 33. 100BASE-TX Transceiver Electrical Characteristics

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
2. Measured at line side of transformer, line replaced by 100Ω (±1%) resistor.

Table 34. 10BASE-T Transceiver Electrical Characteristics

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
2. Parameter is guaranteed by design; not subject to production testing.
3. IEEE 802.3 specifies maximum jitter additions at 1.5 ns for the AUI cable, 0.5 ns from the encoder, and

Figure 32. 100 Mbps TP Port-to-Port Delay Timing Table 35. 100 Mbps TP Port-to-Port Delay Timing Parameters

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
2. Bit Time (BT) is the duration of one bit as transferred to/from the MAC and is the reciprocal of bit rate. BT

80 Datasheet

Figure 33. 100BASE-TX MII-to-TP Port Timing Table 36. 100BASE-TX MII-to-TP Port Timing Parameters

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
2. Bit Time (BT) is the duration of one bit as transferred to/from the MAC and is the reciprocal of bit rate. BT

Figure 34. 100BASE-TX TP-to-MII Timing Table 37. 100BASE-TX TP-to-MII Timing Parameters

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
2. Bit Time (BT) is the duration of one bit as transferred to/from the MAC and is the reciprocal of bit rate. BT

82 Datasheet

Figure 35. 10BASE-T MII-to-TP Timing Table 38. 10BASE-T MII-to-TP Timing Parameters

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
2. Bit Time (BT) is the duration of one bit as transferred to/from the MAC and is the reciprocal of bit rate. BT

Figure 36. 10BASE-T TP-to-MII Timing Table 39. 10BASE-T TP-to-MII Timing Parameters

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
2. Bit Time (BT) is the duration of one bit as transferred to/from the MAC and is the reciprocal of bit rate. BT

84 Datasheet

Figure 37. 100 Mbps TP-to-IRB Timing Table 40. 100 Mbps TP-to-IRB Timing Parameters1

1. This table contains propagation delays from the TP ports to the IRB for normal repeater operation. All

values in this table are output timings.

1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production
2. Bit Time (BT) is the duration of one bit as transferred to/from the MAC and is the reciprocal of bit rate. BT

Figure 38. 10 Mbps TP-to-IRB Timing

Table 41. 10 Mbps TP-to-IRB Timing Parameters1

1. This table contains propagation delays from the TP ports to the IRB for normal repeater operation. All

values in this table are output timings.

1. There is a delay of approximately 13 to 16 bit times between the assertion of IR10ENA and the assertion of

generating preamble as soon as IR10ENA is asserted.

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
2. Bit Time (BT) is the duration of one bit as transferred to/from the MAC and is the reciprocal of bit rate. BT

Figure 39. 10 Mbps IRB-to-TP Port Timing

86 Datasheet

Table 42. 10 Mbps IRB-to-TP Port Timing Parameters

1. Typical values are at 25° C and are for design aid only; they are not guaranteed and not subject to
2. Bit Time (BT) is the duration of one bit as transferred to/from the MAC and is the reciprocal of bit rate. BT
3. External devices should allow at least one 10 MHz clock cycle (10 ns) between assertion of MACACTIVE

Figure 40. Serial Management Interface Timing Table 43. Serial Management Interface Timing Characteristics

1. Typical values are at 25° C and are for design aid only; they are not guaranteed and not subject to

6.0 Register Definitions

6.1 Register Map

register addresses are hexadecimal. Figure 41. PROM Interface Timing Table 44. PROM Interface Timing Characteristics PROM_CLK –– 1.0 MHz PROM_CLK frequency.

1. Typical values are at 25° C and are for design aid only; they are not guaranteed and not subject to

88 Datasheet

Table 45. Register Map

1. R = Read only; W = Write only; R/W = Read/Write; LH = Latch High; LL = Latch Low; SC = Self Clearing.
2. If Register Clear bit is set to ‘1’, then clearing of the associated bit is done by writing ‘1’ to it, otherwise this

register self clears upon read. Register Clear (Bit 11) is set through the Repeater Configuration Register.

Table 45. Register Map (Continued)

1. R = Read only; W = Write only; R/W = Read/Write; LH = Latch High; LL = Latch Low; SC = Self Clearing.
2. If Register Clear bit is set to ‘1’, then clearing of the associated bit is done by writing ‘1’ to it, otherwise this

register self clears upon read. Register Clear (Bit 11) is set through the Repeater Configuration Register.

90 Datasheet

1. R = Read only; W = Write only; R/W = Read/Write; LH = Latch High; LL = Latch Low; SC = Self Clearing.
2. If Register Clear bit is set to ‘1’, then clearing of the associated bit is done by writing ‘1’ to it, otherwise this

register self clears upon read. Register Clear (Bit 11) is set through the Repeater Configuration Register.

1. R = Read only; W = Write only; R/W = Read/Write; LH = Latch High; LL = Latch Low; SC = Self Clearing.
2. If Register Clear bit is set to ‘1’, then clearing of the associated bit is done by writing ‘1’ to it, otherwise this

register self clears upon read. Register Clear (Bit 11) is set through the Repeater Configuration Register.

92 Datasheet

1. R = Read only; W = Write only; R/W = Read/Write; LH = Latch High; LL = Latch Low; SC = Self Clearing.
2. If Register Clear bit is set to ‘1’, then clearing of the associated bit is done by writing ‘1’ to it, otherwise this

register self clears upon read. Register Clear (Bit 11) is set through the Repeater Configuration Register.

1. R = Read only; W = Write only; R/W = Read/Write; LH = Latch High; LL = Latch Low; SC = Self Clearing.
2. If Register Clear bit is set to ‘1’, then clearing of the associated bit is done by writing ‘1’ to it, otherwise this

register self clears upon read. Register Clear (Bit 11) is set through the Repeater Configuration Register.

94 Datasheet

1. R = Read only; W = Write only; R/W = Read/Write; LH = Latch High; LL = Latch Low; SC = Self Clearing.
2. If Register Clear bit is set to ‘1’, then clearing of the associated bit is done by writing ‘1’ to it, otherwise this

register self clears upon read. Register Clear (Bit 11) is set through the Repeater Configuration Register.

6.2 Counter Registers

All counters power up to zero. off to write to the counters. A write operation of the counters is non-atomic for the 64 bit counters. For further definitions refer to RFC 1757 and clause 30 of IEEE 802.3. setting the Extended Frame bit (13) in the Repeater Configuration Register.

6.2.1 Port Counter Registers

items. All Port Counters are Read-Only. Table 46. Port Counter Registers Packets (UnicastFrameCount = 1). See Note 3. affected by the UnicastFrameCount bit. See Note 3.

1. All offset addresses are expressed in hex.
2. Replace “X” in address with specific port to be addressed (offsets 0 through 9 correspond to Ports 1
3. The ReadableFrame counter max size threshold can either be 1518 or 1522. All counters expecting a MTU

Repeater Configuration Register.

1. For 100 Mbps: the “Short Events” register counts events < 88 bit times; the “Port Runts” register counts
2. A 4-bit-time differential exists because 100 Mbps operates with nibble boundaries, so data

packets < 4 bits are counted as 4.

1. A0 - A7 corresponds to Port 1 - Port 8.
2. AA - B1 corresponds to Port 1 - Port 8.

96 Datasheet

6.2.2 RMON Counter Registers

bits (start of frame, end of frame, dribble bits, etc.). Counts events < ‘ShortEventMax’. rptrMonitorPortRunts 0X7 Counts events > ‘ShortEventMax’, but <512 bits. is counted here and also in the ‘collisions’ attribute. the local transmit frequency. partitioned from the network. the MII ports this counter is invalid. Table 46. Port Counter Registers (Continued)

1. All offset addresses are expressed in hex.
2. Replace “X” in address with specific port to be addressed (offsets 0 through 9 correspond to Ports 1
3. The ReadableFrame counter max size threshold can either be 1518 or 1522. All counters expecting a MTU

Repeater Configuration Register.

1. For 100 Mbps: the “Short Events” register counts events < 88 bit times; the “Port Runts” register counts

packets < 4 bits are counted as 4.

1. A0 - A7 corresponds to Port 1 - Port 8.
2. AA - B1 corresponds to Port 1 - Port 8.

Table 47. RMON Counter Registers - 10 Mbps etherStatsBroadcastPkts 0B6 Total number of good broadcast packets received. does not include broadcast packets. octets (excluding framing bits but including FCS octets). octets (excluding framing bits but including FCS octets). octets in length (excluding framing bits, but including FCS octets). Note: a packet without SFD or 0 length is counted here. framing bits but including FCS octets). framing bits but including FCS octets). framing bits but including FCS octets). framing bits but including FCS octets). framing bits but including FCS octets).

98 Datasheet

Table 48. RMON Counter Registers - 100 Mbps etherStatsBroadcastPkts 0C9 Total number of good broadcast packets received. does not include broadcast packets. octets (excluding framing bits but including FCS octets). octets (excluding framing bits but including FCS octets). octets in length (excluding framing bits, but including FCS octets). Note: A packet without SFD or 0 length is counted here. framing bits but including FCS octets). framing bits but including FCS octets). framing bits but including FCS octets). framing bits but including FCS octets). framing bits but including FCS octets).

6.3 Ethernet Address Registers

address. Address values are unknown on power up.

6.3.1 Port Address Registers

registers can be used for security functions.

6.3.2 Search Address Registers

Address Match register contains the port from the Search Address match function. Table 49. Ethernet Address Register Bit Assignments Upper Address Bits 31:16 Reserved. Bits 15:0 contain bits 47:32 of the Ethernet Address. Lower Address Bits 31:0 contain bits 31:0 of the Ethernet Address. Table 50. Port Address Tracking Registers act as NewLastSourceAddress via SW. register. X’s are currently defined as zeros. rptrAddrTrackNewLastSrcAddress register.

1. R = Read only; W = Write only; R/W = Read/Write; LH = Latch High; LL = Latch Low; SC = Self Clearing.
2. All offset addresses are expressed in hex.

100 Datasheet

assignments are provided in Table 53; Search Address Match bit definitions are given in Table 54. Table 51. Search Address/Search Address Match Register Table 52. Search Address Register Bit Assignments Upper Address Bits 31:16 Reserved. Bits 15:0 contain bits 47:32 of the Address. Lower Address Bits 31:0 contain bits 31:0 of the Address. Table 53. Search Match Address Bit Assignments Table 54. Search Match Address Bit Definitions Port 10 (MII 2) R/W 1 = Address in Search Address register matched on this port. Port 9 (MII 1) R/W 1 = Address in Search Address register matched on this port. Port 8 R/W 1 = Address in Search Address register matched on this port. Port 7 R/W 1 = Address in Search Address register matched on this port. Port 6 R/W 1 = Address in Search Address register matched on this port. Port 5 R/W 1 = Address in Search Address register matched on this port. Port 4 R/W 1 = Address in Search Address register matched on this port. Port 3 R/W 1 = Address in Search Address register matched on this port. Port 2 R/W 1 = Address in Search Address register matched on this port. Port 1 R/W 1 = Address in Search Address register matched on this port.

6.4 Repeater Port Control Registers

The Control Register set includes general port control as well as link and learn enable registers.

6.4.1 General Port Control Registers

the General Port Control Register descriptions.

6.4.2 Port Link Control Register

Port Link Control Register description. Table 55. Port Control Register Bit Assignments

1. Bits 8 and 9 (MII Ports) are not used by the Link Control Register.

Table 56. General Port Control Registers Provides per-port selection of partition algorithms. This register controls whether a port is enabled/disabled.

1. R = Read only; W = Write only; R/W = Read/Write; LH = Latch High; LL = Latch Low; SC = Self Clearing.
2. Alternate partition mode also causes port to partition after a single long collision.

Table 57. Port Link Control and Status Register Bit Assignments

102 Datasheet

6.4.3 Port Learn Enable Register

Port Learn Enable Register description.

6.5 Repeater Port Status Registers

Status Register descriptions. Table 58. Port Link Control Register disconnected due to Link Fail.

1. R = Read only; W = Write only; R/W = Read/Write; LH = Latch High; LL = Latch Low; SC = Self Clearing.

Table 59. Port Learn Enable Register Table 60. Port Learn Enable Register 0 0 Learn each new source addresses. 10 Lock. Hardware locked-down the address. Only software can write to this address.

Table 61. Port Status Register Bit Assignments

1. Not all Status Registers use bits 8 and 9.

Table 62. Port Status Registers Reflects the current link status of each twisted-pair port. Reflects the current polarity status of each twisted-pair port. Reflects the current partition status of each twisted-pair port. 0 = Port is Not Partitioned. Indicates the current speed status of each port. 1 = Port is connected at 100 Mbps. 0 = port is connected at 10 Mbps.

1. Register does not track MII port status. Bits 8 and 9 reserved.

Table 63. MII Speed Status Bit Assignments Table 64. MII Status Bit Definitions Individual MII port speed status registers.

1. R = Read only; W = Write only, R/W = Read/Write, LOR = Latch on Reset, LL = Latch Low,

104 Datasheet

6.6 PHY Port Status Registers

The port auto-negotiation registers are described in Table 65 through Table 71. Table 65. Auto-Negotiation Registers Table 66. Auto-Negotiate Link Partner Advertisement Bit Definitions 15 Next Page 1 = Link partner has ability to send multi pages. 13 Remote Fault 1 = Remote fault. 9 100BASE-T4 1 = Link partner is 100BASE-T4 compatible. 8 100BASE-TX FD 1 = Link partner is 100BASE-TX FD capable. 7 100BASE-TX 1 = Link partner is 100BASE-TX capable.

1. R = Read only; W = Write only, R/W = Read/Write, LH = Latch High, LL = Latch Low, SC = Self Clearing

6 10BASE-T FD 1 = Link partner is 10BASE-T FD capable. 5 10BASE-T 1 = Link partner is 10BASE-T capable. Table 67. Auto-Negotiate Expansion Bit Definitions

4 Parallel

1 = More than one of the PMAs detects a valid link.

3 Link Partner Next

1 = Link partner is next page able.

1 Page Received

1 = 3 identical and consecutive link code words are received.

0 Link Partner Auto

1 = Link partner is auto negotiate able.

1. R = Read only; W = Write only, R/W = Read/Write, LH = Latch High, LL = Latch Low, SC = Self Clearing

Table 68. PHY Port Status Register Summary Per port register indicating current status of operating conditions. Table 66. Auto-Negotiate Link Partner Advertisement Bit Definitions (Continued)

1. R = Read only; W = Write only, R/W = Read/Write, LH = Latch High, LL = Latch Low, SC = Self Clearing

106 Datasheet

Table 69. PHY Port Status Register Bit Definitions 15 100BASE-T4 1 = Port able to perform 100BASE-T4. 1 = Port able to perform full-duplex 100BASE-X. 1 = Port able to perform half-duplex 100BASE-X. 1 = Port able to operate at 10 Mbps in full-duplex mode. 1 = Port able to operate at 10 Mbps in half-duplex mode. 1 = Port able to perform full-duplex 100BASE-T2. 1 = Port able to perform half duplex 100BASE-T2.

6 MF Preamble

1 = Port accepts management frames with preamble suppressed.

5 Auto-Negotiation

1 = Auto-Negotiation process completed. 4 Remote Fault 1 = Remote fault condition detected.

3 Auto-Negotiation

1 = PHY is able to perform Auto-Negotiation. 2 Link Status 1 = Link is up.

1. R = Read only; W = Write only, R/W = Read/Write, LH = Latch High, LL = Latch Low, SC = Self Clearing

6.7 PHY Port Control Registers

Table 70. Auto-Negotiation Advertisement Registers Table 71. Auto Negotiate Advertisement Bit Definitions 15 Next Page 1 = Port has ability to send multi pages. 13 Remote Fault 1 = Remote fault. 9 100BASE-T4 1 = Port is 100BASE-T4 compatible. 8 100BASE-TX FD 1 = Port is 100BASE-TX Full-Duplex capable. 7 100BASE-TX 1 = Port is 100BASE-TX capable. 6 10BASE-T FD 1 = Port is 10BASE-T FD capable. 5 10BASE-T 1 = Port is 10BASE-T capable.

1. R = Read only; W = Write only, R/W = Read/Write., LH = Latch High, LL = Latch Low, SC = Self Clearing

Table 72. PHY Port Control Register Port Control Register R/W 132 - 139 Refer to Table 73 for bit assignments.

1. R = Read only; W = Write only; R/W = Read /Write.

108 Datasheet

6.8 Repeater Port Control/Status Registers

assignments are shown in Table 73 through Table 76. Table 73. PHY Port Control Bit Definitions 13 Speed Selection 1 = 100 Mbps. 12 Auto-Negotiation Enable 1 = Enable Auto-Negotiation Process.

9 Restart

1 = Restart Auto-Negotiation Process. 8 Duplex Mode 1 = Full-Duplex. 7 Collision Test 1 = Enable COL signal test.

1. R = Read only; W = Write only, R/W = Read/Write, LH = Latch High, LL = Latch Low, SC = Self Clearing

Table 74. Configuration Registers Repeater Configuration Register R/W 13A Refer to Table 75 for bit assignments. pins. Refer to Table 76 for bit assignments. This register follows the IEEE 1149.1 specification. Refer to Table 77 for bit assignments. the Product ID field is implementation dependent.

1. R = Read only; W = Write only; R/W = Read /Write.

Refer to Table 83 on page 113 for details. Table 84 on page 113 for details. ID to the contents of the PROM ID register listed below. Table 90, “Assign Addr 2” on page 116 for details. “PROM Addr 2 ” on page 116 for details. Table 75. Repeater Configuration Register

14 Configuration

13 Extended Frame

1. R = Read only; W = Write only, R/W = Read/Write., LH = Latch High, LL = Latch Low, SC = Self Clearing
2. While the zeroing operation is in progress, the CPU is locked out from accessing the statistics RAM until

the “zero counter” bit has been reset back to ‘0’. This time period is roughly 15 µs. Table 74. Configuration Registers (Continued)

1. R = Read only; W = Write only; R/W = Read /Write.

110 Datasheet

12 Enable Port

11 Register Clear

0 = clears appropriate registers upon serial read.

9 Send /T/R Send /T/R - Forces a good /T/R after each 100 Mbps

8 Isolate100 Isolate100 - Isolates the IR100CFS

7 Isolate10 Isolate10 - Same as for 100 except also isolates stack

6 Unicast Frame

1 = portReadableFrames count only Unicast Frames. 0 = portReadableFrames count all Frames.

5 Arbitration Value Arbitration Input Value-as read from input pin R 0

4 Zero Counters

cleared, this bit is reset to ‘0’.

3 Enable FIFO

Table 76. Repeater Serial Configuration

1. R = Read only; W = Write only, R/W = Read/Write., LH = Latch High, LL = Latch Low, SC = Self Clearing

Table 75. Repeater Configuration Register (Continued)

1. R = Read only; W = Write only, R/W = Read/Write., LH = Latch High, LL = Latch Low, SC = Self Clearing
2. While the zeroing operation is in progress, the CPU is locked out from accessing the statistics RAM until

the “zero counter” bit has been reset back to ‘0’. This time period is roughly 15 µs.

6.8.1 Device/Revision Register

6.8.2 LED Control Registers

The LED Control Registers and bit assignments are described in Table 78.

6.8.3 LED Global Control Register

bits are read-only because the LED mode is set only via pins. When writing this register, all other bits in this register are reserved and may have default = 1 or 0.

6.8.4 Port LED Control Register

LEDs. The LED control encodings are listed in Table 81. Table 77. Device/Revision Register Bit Assignment

1. The JEDEC ID is an 8-bit identifier. However, the MSB is for parity only and is ignored.

Intel’s JEDEC ID is FE (1111 1110) which becomes 111 1110.

1. First Chain Bit = 0 if ChipID ≠ 00.

First Chain Bit = 1 if ChipID = 00. Table 78. Global Fault LED Bit Assignments

112 Datasheet

6.8.5 LED Timer Control Register

128 Hz while the minimum frequency is 0.5 Hz. Table 80. LED Configuration See Table 81 for Bit Definitions.

1. R = Read only; W = Write only, R/W = Read/Write, LH = Latch High, LL = Latch Low, SC = Self Clearing
2. During reset, the state of this register is all 1s. If a manager is present within the system, this register stays

in the all 1s state following reset. Otherwise, they default to hardware control (10). Table 81. Port LED1, 2, 3 Control Encodings

3 Function Modes 1, 3, 4 Mode 2

00 LED off LED off

01 Reserved LED fast blink Reserved

11 LED off LED on LED off LED Off

Table 82. LED Timer Control Register Bit Assignments

6.8.6 Repeater Reset Register

6.8.7 Software Reset Register

6.8.8 Interrupt Registers

Table 83. Repeater Reset

0 RPTRRS

1. R = Read only; W = Write only, R/W = Read/Write., LH = Latch High, LL = Latch Low, SC = Self Clearing

Table 84. Software Reset

1. R = Read only; W = Write only, R/W = Read/Write., LH = Latch High, LL = Latch Low, SC = Self Clearing

Table 85. Interrupt Status/Mask Register Interrupt Mask Register R/W 147 This register allows masking of individual interrupts.

114 Datasheet

Table 86. Interrupt Status Register Bit Definitions

5 JABINT R/W

A ‘1’ indicates that a port is in jabber state. exits this state when all receivers return to the idle condition. actively transmitting for longer than 40,000 to 75,000 bit times. A ‘1’ indicates that a port has been isolated (100 Mbps only). as a packet not starting with a /J/K symbol pair.

3 PARTINT R/W

A ‘1’ indicates a port has been partitioned. participating in excess of 60 consecutive collisions. participating in excess of 31 consecutive collisions. the port until it properly un-partitions.

2 FCCINT R/W False Carrier Count Interrupt

the last Source Address register.

0 SPDCHNGINT R/W Speed Change Interrupt

1. R = Read only; W = Write only, R/W = Read/Write., LH = Latch High, LL = Latch Low, SC = Self Clearing
2. If Register Clear bit is set to ‘1’, then clearing of the associated bit is done by writing ‘1’ to it, otherwise this

register self clears upon read. Register Clear (Bit 11) is set through the Repeater Configuration Register.

6.9 Serial Controller Registers

Table 87. Interrupt Mask Bit Definitions

5 JABMSK R/W

3 PARTMSK R/W

1 SACHNGMSK R/W

0 SPDCHNGMSK R/W

1. R = Read only; W = Write only, R/W = Read/Write., LH = Latch High, LL = Latch Low, SC = Self Clearing.

Table 88. Configuration Registers

1. R = Read only; W = Write only; R/W = Read /Write.

Table 89. Assign Addr 1

31.0 ASSIGN4716 Bits (47:16) of the PROM serial number W 0

1. R = Read only; W = Write only, R/W = Read/Write., LH = Latch High, LL = Latch Low, SC = Self Clearing.

116 Datasheet

Table 90. Assign Addr 2

31.21 Reserved Reserved W 0

1. R = Read only; W = Write only, R/W = Read/Write., LH = Latch High, LL = Latch Low, SC = Self Clearing.

Table 91. PROM Addr 1

31.0 PROM4716 Bits (47:16) of the PROM serial number R 0

1. R = Read only; W = Write only, R/W = Read/Write., LH = Latch High, LL = Latch Low, SC = Self Clearing.

Table 92. PROM Addr 2

31.16 Reserved Reserved R 0

1. R = Read only; W = Write only, R/W = Read/Write., LH = Latch High, LL = Latch Low, SC = Self Clearing.

7.0 Mechanical Specifications

Figure 42. LXT98x0 Package Specifications for Commercial Temperature

118 Datasheet

Figure 43. LXT98x0 Package Specifications for Extended Temperature