88CO196EC INTEL | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1.0 Product Overview
- 1.1 Nomenclature Overview
- 2.0 Pinout
- 3.0 Signals
- 4.0 Address Map
- 5.0 Electrical Characteristics
- 5.1 DC Characteristics
- 6.0 Explanation of AC Symbols
- 6.1 AC Characteristics — Multiplexed Bus Mode
- 6.2 AC Characteristics — Demultiplexed Bus Mode
- 6.3 Deferred Bus Timing Mode
- 6.4 AC Characteristics — Serial Port, Mode
- 6.5 AC Characteristics — Synchronous Serial Port
- 6.6 AC Characteristics — Serial Debug Unit
- 6.7 A/D Sample and Conversion Times
- 6.7.1 AC Characteristics — A/D Converter, 10-Bit Mode
- 6.7.2 AC Characteristics — A/D Converter, 8-Bit Mode
- 6.8 External Clock Drive
- 6.9 Test Output Waveforms
- 6.10 Flash Memory Erase Performance
- 7.0 Thermal Characteristics
- 1 Intel ® 88CO196EC CHMOS 16-Bit Microcontroller Block Diagram
- 2 Product Nomenclature
- 3 Intel
- 4 System Bus Timing Diagram (Multiplexed Bus Mode)
- 5 READY Timing Diagram (Multiplexed Bus Mode)
- 6 System Bus Timing Diagram (Demultiplexed Bus Mode)
- 7 READY Timing Diagram (Demultiplexed Bus Mode)
- 8 Deferred Bus Mode Timing Diagram
- 9 Serial Port Waveform — Mode
- 10 Synchronous Serial Port
- 11 Serial Debug Unit
- 12 External Clock Drive Waveforms
- 13 AC Testing Output Waveforms
Intel® 88CO196EC CHMOS 16-Bit Microcontroller Datasheet Product Features The Intel® 88CO196EC CHMOS 16-Bit Microcontroller is the first member of the MCS ® 96 family of microcontrollers to integrate flash memory on-chip. The Intel® 88CO196EC, with its integrated flash memory, brings a new level of integration that offers embedded system designers cost-effective solutions. 256 Kbytes on-chip flash program memory 40 MHz operation Optional clock quadrupler Programmable clock output signal (CLKOUT) 2 Mbytes of linear address space 1.25 Kbytes of register RAM 2.75 Kbytes of code RAM Register-to-register architecture Stack overflow/underflow monitor with user-defined upper and lower stack pointer boundary limits Two peripheral interrupt handlers (PIHs) provide direct hardware handling of up to 45 interrupts Up to 59 I/O port pins Full-duplex serial port with dedicated baud-rate generator Enhanced synchronous serial I/O unit (SSIO) 16 10-bit A/D channels with auto-scan mode and dedicated results registers Controller area network (CAN) 2.0 networking protocol Serial debug unit provides read and write access to code RAM with no CPU overhead Chip-select unit (CSU) — Three chip-select pins — Dynamic demultiplexed/multiplexed address/data bus for each chip-select — Programmable wait states (0, 1, 2, or 3) for each chip-select — Programmable bus width (8- or 16-bit) for each chip-select — Programmable address range for each chip-select Event processor array (EPA) — Two flexible 16-bit timer/counters — Five high-speed capture/compare channels with a lock feature for noise filtering — 10 enhanced high-speed capture/compare channels with period and duty cycle measurement capability, as well as a lock feature for noise filtering Complete system development support Packaging — 132-pin PQFP Temperature Offerings — Commercial (0C - 70C) — Extended (-40C - 85C) Order Number: 273970-002 August, 2004
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel ® 88CO196EC CHMOS 16-Bit Microcontroller may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. AnyPoint, AppChoice, BoardWatch, BunnyPeople, CablePort, Celeron, Chips, CT Media, Dialogic, DM3, EtherExpress, ETOX, FlashFile, i386, i486, i960, iCOMP, InstantIP, Intel, Intel Centrino, Intel logo, Intel386, Intel486, Intel740, IntelDX2, IntelDX4, IntelSX2, Intel Create & Share, Intel GigaBlade, Intel InBusiness, Intel Inside, Intel Inside logo, Intel NetBurst, Intel NetMerge, Intel NetStructure, Intel Play, Intel Play logo, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel TeamStation, Intel Xeon, Intel XScale, IPLink, Itanium, MCS, MMX, MMX logo, Optimizer logo, OverDrive, Paragon, PC Dads, PC Parents, PDCharm, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, RemoteExpress, SmartDie, Solutions960, Sound Mark, StorageExpress, The Computer Inside., The Journey Inside, TokenExpress, VoiceBrick, VTune, and Xircom are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © February, 2004, Intel Corporation
Intel® 88CO196EC Tables
2 Intel ® 88CO196EC CHMOS 16-Bit Microcontroller
4 Intel
9 Serial Port Timing — Mode 0
Intel® 88CO196EC
Revision History
February 2004 001 Initial release August 2004 002 To address the fact that many of the package prefix variables have changed, all package prefix variables in this document are now indicated with an "x".
Intel® 88CO196EC
1.0 Product Overview
Figure 1. Intel
2.75 Kbytes
5 Capture/
256 Kbytes
1.25 KbytesALU
10 Enhanced
8 Datasheet
1.1 Nomenclature Overview
Figure 2. Product Nomenclature Table 1. Description of Product Nomenclature
2.0 Pinout
Figure 3. Intel ® 88CO196EC CHMOS 16-Bit Microcontroller 132-Pin PQFP Package View of component as mounted on PC board.
10 Datasheet
Table 2. Intel ® 88CO196EC CHMOS 16-Bit Microcontroller 132-Pin PQFP Package Pin
15 V CC 59 XTAL1 103 EA#
24 V CC 68 A1 112 RXCAN
25 V SS 69 A2 113 TXCAN
34 A15 78 V
36 A13 80 V SS 124 V SS
37 A12 81 CRIN 125 V CC
38 V CC 82 V PP 126 ACH0
39 V SS 83 V SS 127 ACH1
40 A11 84 CRDCLK 128 ACH2
3.0 Signals
Table 3. Signal Descriptions (Sheet 1 of 9) cycle during both multiplexed and demultiplexed bus modes. addressing of the 2-Mbyte address space. memory or 1F2080H in external memory. A20:16 share package pins with P6.4:0 and PBUS20:16. These signals are analog inputs to the A/D converter. REF pins must be connected for the A/D converter to function. The function of these pins depends on the bus width and mode. receive data during the second half of the bus cycle. second half of the bus cycle. AD15:0 drive or receive data during the entire bus cycle. is currently on the high byte of the internal bus. AD15:8 share package pins with P4.7:0. AD7:0 share package pins with P3.7:0. This active-low output signal is asserted only during external memory accesses. returned high as soon as the bus cycle completes. bus. A decoder can also use this signal to generate chip selects for external memory. ADV# shares a package pin with P5.0 and ALE. During slave programming, this active-low input enables the auto-increment feature. AINC# shares a package pin with P2.4.
12 Datasheet
is available on the system address/data bus. address/data bus in multiplexed mode. ALE shares a package pin with P5.0 and ADV#. nominally at the same potential. BHE# shares a package pin with P5.5, TMODE1# and WRH#. configuration register 0 (CCR0) determines whether it functions as BHE# or WRH#. CCR0.2 = 1 selects BHE#; CCR0.2 = 0 selects WRH#. During test-ROM execution mode, the contents of pages FFH and FBH are swapped. bus-hold protocol is disabled (WSR.7 is cleared). The microcontroller can assert BREQ# at the same time as or after it asserts HLDA#. Once it is asserted, BREQ# remains asserted until HOLD# is deasserted. BREQ# shares a package pin with P5.4 and TMODE0#. f/8, or f/16. CLKOUT has a 50% duty cycle. CLKOUT shares a package pin with P2.7 and PACT#. Table 3. Signal Descriptions (Sheet 2 of 9)
CPVER shares a package pin with P2.6, HLDA#, and ONCE#. a code RAM command. No data can be transferred during this time. frequency equals one-half the operating frequency (f/2). sampled on the rising edge of CRDCLK. chip-select output is asserted and the bus configuration defaults to the CS2# values. (1F2000–1F20FFH if external). CS2:0# share package pins with P6.7:5 and PMODE2:0. held low. For an access to any other memory location, the value of EA# is irrelevant. High-speed input/output signals for the EPA capture/compare channels. Table 3. Signal Descriptions (Sheet 3 of 9)
14 Datasheet
EXTINT shares a package pin with P2.2 and PROG#. pin configuration is ignored until the bus-hold protocol is disabled (WSR.7 is cleared). An external device uses this active-low input signal to request control of the bus. pin configuration is ignored until the bus-hold protocol is disabled (WSR.7 is cleared). When high, INST indicates that an instruction is being fetched from external memory. The signal remains high during the entire bus cycle of an external instruction fetch. configuration byte reads. INST is low during internal memory fetches. INST shares a package pin with P5.1. In normal operating mode, a rising edge on NMI generates a nonmaskable interrupt. one state time to guarantee that it is recognized. microcontroller is in ONCE mode, you can debug the system using a clip-on emulator. ONCE# shares a package pin with P2.6, TMODE1#, and CPVER. Table 3. Signal Descriptions (Sheet 4 of 9)
selectable special-function signals. specification to prevent inadvertent entry into ONCE mode. P2.3 is a dedicated general-purpose I/O signal. bus, which has complementary drivers. P3.7:0 share package pins with AD7:0 and PBUS7:0. bus, which has complementary drivers. P4.7:0 share package pins with AD15:8 and PBUS15:8. hold it high during reset and ensure that your system meets the VIH specification. P6.5/CS0#/PMODE0, P6.6/CS1#/PMODE1, and P6.7/CS2#/PMODE2. selectable special-function signals. P7.7:0 share package pins with EPAPWM7:0. selectable special-function signals. P8.7 is a dedicated general-purpose I/O signal. Table 3. Signal Descriptions (Sheet 5 of 9)
16 Datasheet
selectable special-function signals. P9.6 and P9.7 are dedicated general-purpose I/O signals. progress, while a high signal indicates that the operation is complete. PACT# shares a package pin with P2.7 and CLKOUT. PALE# is multiplexed with P2.1 and RXD. Address and data input/output bus during slave and UPROM programming. pins with AD15:8 and P4.7:0; PBUS7:0 share package pins with AD7:0 and P3.7:0. changed at the time of reset. These pins, along with the TMODE1:0# pins, determine the programming mode. microcontroller is operating. PMODE2:0 share package pins with P6.7:5 and CS2:0#. the programming bus must remain stable while PROG# is active. be output on the PBUS, while a rising edge ends the data transfer. PROG# shares a package pin with P2.2 and EXTINT. RD# shares a package pin with P5.3. is reached, additional wait states are added until READY is pulled high. READY shares a package pin with P5.6. Table 3. Signal Descriptions (Sheet 6 of 9)
pull-down transistor connected to the RESET# pin for 16 state times. from FF2080H (or 1F2080H in external memory). Timing pin for the return-from-powerdown circuit. if either of the following conditions are true. Operating Modes” chapter of the for details on selecting the capacitor. the following conditions are true. If your application does not use powerdown mode, leave this pin unconnected. RPD shares a package pin with P5.7. either an input or an open-drain output for data. RXD shares a package pin with P2.1 and PALE#. both channels 0 and 1 and SC1 is not available. SC0 shares a package pin with P9.2, and SC1 shares a package pin with P9.4. high-impedance input signal. SD0 shares a package pin with P9.3, and SD1 shares a package pin with P9.5. rising edge, the falling edge, or both rising and falling edges of T1CLK. T1CLK shares a package pin with P8.2, EPA10, and BLK2#. External clock for the serial I/O baud-rate generator input (program selectable). T2CLK shares a package pin with P8.4 and EPA12. Table 3. Signal Descriptions (Sheet 7 of 9)
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falling edge, or both rising and falling edges of T1RST . T1RST shares a package pin with P8.3, EPA11, and BLK3#. falling edge, or both rising and falling edges of T2RST . T2RST shares a package pin with P8.5 and EPA13. meets the VIH specification to prevent inadvertent entry into test mode. package pin with P5.5, BHE#, WRH#. TXD shares a package pin with P2.0. Connect each VCC pin to the digital supply voltage. During Flash Program/Erase, the VPP pin is typically at +12 V (VPP voltage). During normal operation the VPP pin is tied to VSS . This pin supplies operating voltage to the A/D converter. through the lowest possible impedance path. VSS should be nominally at the same potential. asserted only during external memory writes. WR# shares a package pin with P5.2 and WRL#. configuration register 0 (CCR0) determines whether it functions as WR# or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#. Table 3. Signal Descriptions (Sheet 8 of 9)
WRH# shares a package pin with P5.5 and BHE#. configuration register 0 (CCR0) determines whether it functions as BHE# or WRH#. CCR0.2 = 1 selects BHE#; CCR0.2 = 0 selects WRH#. WRL# shares a package pin with P5.2 and WR#. configuration register 0 (CCR0) determines whether it functions as WR# or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#. input to XTAL1. The external clock signal must meet the VIH specification for XTAL1. an external clock source instead of the on-chip oscillator. Table 3. Signal Descriptions (Sheet 9 of 9)
Intel® 88CO196EC
20 Datasheet
4.0 Address Map
Table 4. Intel ® 88CO196EC CHMOS 16-Bit Microcontroller Address Map (Sheet 1 of 2)
002000 External memory or I/O Indirect, indexed,
- During test ROM execution mode, the contents of pages FFH and FBH are swapped. This allows the
microcontroller to enter a test ROM routine after reset.
- Accesses to these locations go to internal flash if EA# is high or an external device if EA# is low.
- Since the upper three address bits, A23:21, are not connected to external pins, these address locations are
externally on address pins A20:0 as 000F20H.
- The IRAM_CON register determines whether accesses to these locations go to internal code/data RAM or
22 Datasheet
000400 Internal code/data RAM or external memory (Note 4) Indirect, indexed,
000100 Upper register file (general-purpose register RAM)
000018 Lower register file (general-purpose register RAM) Direct, indirect,
000000 Lower register file (stack pointer and CPU SFRs) Direct, indirect,
Table 4. Intel ® 88CO196EC CHMOS 16-Bit Microcontroller Address Map (Sheet 2 of 2)
- During test ROM execution mode, the contents of pages FFH and FBH are swapped. This allows the
microcontroller to enter a test ROM routine after reset.
- Accesses to these locations go to internal flash if EA# is high or an external device if EA# is low.
- Since the upper three address bits, A23:21, are not connected to external pins, these address locations are
externally on address pins A20:0 as 000F20H.
- The IRAM_CON register determines whether accesses to these locations go to internal code/data RAM or
5.0 Electrical Characteristics
5.1 DC Characteristics
damage. These are stress ratings only.
- This device is static and should operate below 1 Hz, but has been tested only down to 16 MHz.
- When the phase-locked loop (PLL) circuitry is enabled, the minimum input frequency on XTAL1 is 6 MHz.
The PLL cannot be run at frequencies lower than 24 MHz in 4X mode.
- Assume an external clock. The maximum frequency for an external crystal oscillator is 20MHz.
- Flash programming and erase operations only guaranteed to work from 0°C to +70°C.
Table 5. DC Characteristics at VCC = 4.75 V – 5.25 V (Sheet 1 of 2)
- Typical values are based on a limited number of samples and are not guaranteed. The values listed are at
room temperature with VCC = 5.0 V.
- The maximum injection current is not tested. The device is designed to meet this specification.
- Pin capacitance is not tested. This value is based on design simulations.
24 Datasheet
Table 5. DC Characteristics at VCC = 4.75 V – 5.25 V (Sheet 2 of 2)
- Typical values are based on a limited number of samples and are not guaranteed. The values listed are at
room temperature with VCC = 5.0 V.
- The maximum injection current is not tested. The device is designed to meet this specification.
- Pin capacitance is not tested. This value is based on design simulations.
6.0 Explanation of AC Symbols
Table 6. AC Timing Symbol Definitions
26 Datasheet
6.1 AC Characteristics — Multiplexed Bus Mode
Test Conditions: Capacitive load on all pins = 50 pF, Rise and Fall Times = 3 ns. Table 7. AC Characteristics, Multiplexed Bus Mode (Sheet 1 of 2)
- 20MHz is the maximum input frequency when using an external crystal oscillator; however, 40MHz can be
applied with an external clock source.
- Device is static by design, but has been tested only down to 16MHz.
- If wait states are used, add 2t × n, where n = number of wait states.
- Assumes CLKOUT is operating in divide-by-two mode (f/2).
- Assuming back-to-back bus cycles.
- When forcing wait states using the BUSCONx register, add 2t × n, where n = number of wait states.
- Exceeding the maximum specification causes additional wait states.
- The first falling edge of READY is not synchronized to a CLKOUT edge; therefore, one programmed wait
Table 7. AC Characteristics, Multiplexed Bus Mode (Sheet 2 of 2)
- 20MHz is the maximum input frequency when using an external crystal oscillator; however, 40MHz can be
applied with an external clock source.
- Device is static by design, but has been tested only down to 16MHz.
- If wait states are used, add 2t × n, where n = number of wait states.
- Assumes CLKOUT is operating in divide-by-two mode (f/2).
- Assuming back-to-back bus cycles.
- When forcing wait states using the BUSCONx register, add 2t × n, where n = number of wait states.
- Exceeding the maximum specification causes additional wait states.
- The first falling edge of READY is not synchronized to a CLKOUT edge; therefore, one programmed wait
28 Datasheet
Figure 4. System Bus Timing Diagram (Multiplexed Bus Mode)
Figure 5. READY Timing Diagram (Multiplexed Bus Mode)
30 Datasheet
6.2 AC Characteristics — Demultiplexed Bus Mode
Test Conditions: Capacitive load on all pins = 50 pF, Rise and Fall Times = 3 ns. Table 8. AC Characteristics, Demultiplexed Bus Mode (Sheet 1 of 2)
- Device is static by design but has been tested only down to 16MHz.
- 20MHz is the maximum input frequency when using an external crystal oscillator; however, 40MHz can be
applied with an external clock source.
- If wait states are used, add 2t × n, where n = number of wait states.
- Assumes CLKOUT is operating in divide-by-two mode (f/2).
- Assuming back-to-back bus cycles.
- When forcing wait states using the BUSCON register, add 2t × n.
- Exceeding the maximum specification causes additional wait states.
- The first falling edge of READY is not synchronized to a CLKOUT edge; therefore, one programmed wait
Table 8. AC Characteristics, Demultiplexed Bus Mode (Sheet 2 of 2)
- Device is static by design but has been tested only down to 16MHz.
- 20MHz is the maximum input frequency when using an external crystal oscillator; however, 40MHz can be
applied with an external clock source.
- If wait states are used, add 2t × n, where n = number of wait states.
- Assumes CLKOUT is operating in divide-by-two mode (f/2).
- Assuming back-to-back bus cycles.
- When forcing wait states using the BUSCON register, add 2t × n.
- Exceeding the maximum specification causes additional wait states.
- The first falling edge of READY is not synchronized to a CLKOUT edge; therefore, one programmed wait
32 Datasheet
Figure 6. System Bus Timing Diagram (Demultiplexed Bus Mode)
Figure 7. READY Timing Diagram (Demultiplexed Bus Mode)
34 Datasheet
6.3 Deferred Bus Timing Mode
Figure 8. Deferred Bus Mode Timing Diagram
6.4 AC Characteristics — Serial Port, Mode 0
Table 9. Serial Port Timing — Mode 0† † These timings are not tested and not guaranteed. (SP_BAUD) register value for transmissions is x001H. Figure 9. Serial Port Waveform — Mode
36 Datasheet
6.5 AC Characteristics — Synchronous Serial Port
Table 10. Synchronous Serial Port Timing 88CO196EC CHMOS 16-Bit Microcontroller196EC User’s Manual. Figure 10. Synchronous Serial Port
6.6 AC Characteristics — Serial Debug Unit
Table 11. Serial Debug Unit Timing Figure 11. Serial Debug Unit
Intel® 88CO196EC
38 Datasheet
6.7 A/D Sample and Conversion Times
Two parameters, sample time and conversion time, control the time required for an A/D conversion. The sample time is the length of time that the analog input voltage is actually connected to the sample capacitor. If this time is too short, the sample capacitor will not charge completely. If the sample time is too long, the input voltage may change and cause conversion errors. The conversion time is the length of time required to convert the analog input voltage stored on the sample capacitor to a digital value. The conversion time must be long enough for the comparator and circuitry to settle and resolve the voltage. Excessively long conversion times allow the sample capacitor to discharge, degrading accuracy. The AD_TIME register programs the A/D sample and conversion times. Use the T SAM and TCONV specifications in Table 12 and Table 14 to determine appropriate values for SAM and CONV; otherwise, erroneous conversion results may occur. When the SAM and CONV values are known, write them to the AD_TIME register. Do not write to this register while a conversion is in progress; the results are unpredictable. Use the following formulas to determine the SAM and CONV values. where: SAM equals a number, 1 to 7, to be written to the AD_TIME register CONV equals a number, 2 to 31, to be written to the AD_TIME register T SAM is the sample time, in µsec (Table 12 and Table 14) TCONV is the conversion time, in µsec (Table 12 and Table 14) f is the operating frequency, in MHz B is the number of bits to be converted (8 or 10) SAM TSAM f 2–× CONV TCONV f× 3– 2 B×
6.7.1 AC Characteristics — A/D Converter, 10-Bit Mode
Table 12. 10-bit A/D Operating Conditions
- ANGND and VSS should nominally be at the same potential.
- VREF must not exceed VCC by more than + 0.5 V because VREF supplies both the resistor ladder and the
analog portion of the converter and input port pins.
- Program the AD_TIME register to meet the TSAM and TCONV specifications.
Table 13. 10-Bit Mode A/D Characteristics Over Specified Operating Conditions
- All conversions were performed with processor in idle mode.
- Most devices will need these values at 25
°C, but they are not tested or guaranteed.
- An LSB , as used here, has a value of approximately 5 mV.
- Multiplexer break-before-make guaranteed.
- Resistance from device pin, through internal multiplexer, to sample capacitor.
- Applying voltage beyond these specifications will degrade the accuracy of other channels being converted.
40 Datasheet
6.7.2 AC Characteristics — A/D Converter, 8-Bit Mode
Table 14. 8-Bit A/D Operating Conditions
- ANGND and VSS should nominally be at the same potential.
- VREF must not exceed VCC by more than + 0.5 V because VREF supplies both the resistor ladder and the
analog portion of the converter and input port pins.
- Program the AD_TIME register to meet the TSAM and TCONV specifications.
Table 15. 8-Bit Mode A/D Characteristics Over Specified Operating Conditions
- All conversions were performed with processor in idle mode.
- Most parts will need these values at 25°C, but they are not tested or guaranteed.
- An LSB , as used here, has a value of approximately 5 mV.
- Multiplexer break-before-make guaranteed.
- Resistance from device pin, through internal multiplexer, to sample capacitor.
- Applying voltage beyond these specifications will degrade the accuracy of other channels being converted.
6.8 External Clock Drive
Table 16. External Clock Drive applied with an external clock source. Figure 12. External Clock Drive Waveforms
42 Datasheet
6.9 Test Output Waveforms
6.10 Flash Memory Erase Performance
Figure 13. AC Testing Output Waveforms Figure 14. Float Waveforms During 5.0 Volt Testing Table 17. Flash Memory Erase Performance are at room temperature with VCC = 5 V; VPP = 12 V. level occurs with IOL /IOH ≤ 15 mA.
7.0 Thermal Characteristics
All thermal impedance data is approximate for static air conditions at 1 watt of power dissipation. Table 18. Thermal Characteristics