8XL52 INTEL | Alldatasheet
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*Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. November 1994COPYRIGHT © INTEL CORPORATION, 1995 Order Number: 272468-002 8XL52/54/58 LOW VOLTAGE CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLERS Commercial/Express 87L52/80L52/87L54/80L54/87L58/80L58 Y High Performance CHMOS OTP ROM Y Low Voltage Operation Y 20 MHz Commercial/16 MHz Express Operation Y Three 16-Bit Timer/Counters Y Up/Down Timer/Counter Y Three Level Program Lock System Y 8K/16K/32K On-Chip Program Memory Y 256 Bytes of On-Chip Data RAM Y Improved Quick Pulse Programming Algorithm Y Boolean Processor Y 32 Programmable I/O Lines Y 6 Interrupt Sources Y Four Level Interrupt Priority Y Programmable Serial Channel with: Ð Framing Error Detection Ð Automatic Address Recognition Y 64K External Program Memory Space Y 64K External Data Memory Space Y MCSÉ 51 Microcontroller Compatible Instruction Set Y Power Saving Idle and Power Down Modes Y ONCE (On-Circuit Emulation) Mode Y Extended Temperature Range b40§Ct o a85§C) MEMORY ORGANIZATION OTP ROM Version Version ROM ROM/ Bytes RAMOTP ROM Bytes 87L52 80L52 8K 256 87L54 80L54 16K 256 87L58 80L58 32K 256 These devices can address up to 64 Kbytes of external program/data memory. The Intel 8XL52/8XL54/8XL58 is a single-chip control oriented microcontroller which is fabricated on Intel’s reliable CHMOS III-E technology. Being a member of the MCS 51 microcontroller family, the 8XL52/8XL54/ 8XL58 uses the same powerful instruction set, has the same architecture, and is pin-for-pin compatible with the existing MCS 51 microcontroller products. The 8XL5X is a 3V version of current 8XC5X and will operate from 2.7V to 3.6V at a frequency range of 3.5 MHz to 16 MHz (Express)/20 MHz (Commercial). For the remainder of this document, the 8XL52, 8XL54, 8XL58 will be referred to as the 8XL5X, unless information applies to a specific device.
able at express temperature range. Figure 1. 8XL5X Block Diagram
Figure 2. Pin Connections
VCC: Supply voltage. VSS: Circuit ground. Port 0: Port 0 is an 8-bit, open drain, bidirectional I/O port. As an output port each pin can sink several inputs. Port 0 pins that have 1’s written to them float, and in that state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external Program and Data Memory. In this application it uses strong inter- nal pullups when emitting 1’s, and can source and sink several inputs. Port 0 also receives the code bytes during OTP ROM programming, and outputs the code bytes dur- ing program verification. External pullup resistors are required during program verification. Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can drive several inputs. Port 1 pins that have 1’s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 1 pins that are externally pulled low will source current IL, on the data sheet) because of the internal pull- ups. In addition, Port 1 serves the functions of the follow- ing special features of the 8XL5X: Port Pin Alternate Function P1.0 T2 (External Count Input to Timer/ Counter 2), Clock Out P1.1 T2EX (Timer/ Counter 2 Capture/ Reload Trigger and Direction Control) Port 1 receives the low-order address bytes during OTP ROM programming and verifying. Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can drive several inputs. Port 2 pins that have 1’s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 2 pins that are externally pulled low will source current IL, on the data sheet) because of the internal pull- ups. Port 2 emits the high-order address byte during fetches from external Program Memory and during accesses to external Data Memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pullups when emitting 1’s. Dur- ing accesses to external Data Memory that use 8-bit addresses (MOVX @Ri), Port 2 emits the contents of the P2 Special Function Register. Some Port 2 pins receive the high-order address bits during OTP ROM programming and program verifi- cation. Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers can drive several inputs. Port 3 pins that have 1’s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 3 pins that are externally pulled low will source current IL, on the data sheet) because of the pullups. Port 3 also serves the functions of various special features of the MCS-51 Family, as listed below: Port Pin Alternate Function P3.0 RXD (serial input port) P3.1 TXD (serial output port) P3.2 INT0 (external interrupt 0) P3.3 INT1 (external interrupt 1) P3.4 T0 (Timer 0 external input) P3.5 T1 (Timer 1 external input) P3.6 WR (external data memory write strobe) P3.7 RD (external data memory read strobe) RST: Reset input. A high on this pin for two machine cycles while the oscillator is running resets the de- vice. The port pins will be driven to their reset condi- tion when a minimum V IH2 voltage is applied wheth- er the oscillator is running or not. An internal pull- down resistor permits a power-on reset with only a capacitor connected to V CC.
ues until the Power Down mode is terminated. SFRs and the on-chip RAM to retain their values. and stabilize (normally less than 10 ms). 2) Hold ALE low as RST is deactivated. operation is restored when a normal reset is applied. Table 1. Status of the External Pins during Idle and Power Down
tended temperature range with or without burn-in. prefixes are listed in Table 2. from their commercial temperature range limits. Table 2. Prefix Identification EXPRESS prefix with the proper device.
ABSOLUTE MAXIMUM RATINGS * Ambient Temperature Under Bias À b40§Ct o a85§C Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b65§Ct o a150§C Voltage on EA/V PP Pin to V SS ÀÀÀÀÀÀÀ0V to a13.0V Voltage on Any Other Pin to V SS ÀÀb0.5V to a6.5V IOL per I/O Pin ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ15 mA Power DissipationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5W (based on PACKAGE heat transfer limitations, not device power consumption) NOTICE: This data sheet contains information on products in the sampling and initial production phases of development. It is valid for the devices indicated in the revision history. The specifications are subject to change without notice. *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability. OPERATING CONDITIONS Symbol Description Min Max Units TA Ambient Temperature Under Bias Commercial 0 a70 §C Express b40 a85 §C VCC Supply Voltage 2.7 3.6 V DC CHARACTERISTICS (Over Operating Conditions) All parameter values apply to all devices unless otherwise indicated. Symbol Parameter Min Max Units Test Conditions VIL Input Low Voltage b0.5 0.8 V (except XTAL1, RST) VIL1 Input Low Voltage b0.5 0.2 V CC b 0.1 V (XTAL1, RST) VIH Input High Voltage 2.0 V CC a 0.5 V (Except XTAL1, RST, EA ) VIH1 Input High Voltage (EA )V CC b 1.0 V CC a 0.5 V VIH2 Input High Voltage 0.7 V CC VCC a 0.5 V (XTAL1, RST) VOL Output Low Voltage (Note 4) 0.4 V I OL e 1.6 mA (Note 1) (Ports 1, 2 and 3) VOL1 Output Low Voltage (Note 4) 0.4 V I OL e 3.2 mA (Port 0, ALE/PSEN ) (Note 1) VOH Output High Voltage V CC b 0.7 V I OH eb 30 mA (Ports 1, 2 and 3, ALE, PSEN (Note 2) VOH1 Output High Voltage 2.4 V I OH eb 1.0 mA (Port 0 in External Bus Mode) (Note 2) IIL Logical 0 Input Current b50 mAV IN e 0.4V (Ports 1, 2 and 3) ILI Input Leakage Current (Port 0) g10 mA0 k VIN k VCC
- Capacitive loading on Ports 0 and 2 may cause noise pulses above 0.4V to be superimposed on the V OLs of ALE and
exceed 0.8V. It may be desirable to qualify ALE or other signals with a Schmitt Trigger, or CMOS-level input logic.
- Capacitive loading on Ports 0 and 2 cause the V
address lines are stabilizing.
- See Figures 6–9 for test conditions. Minimum V
- Under steady state (non-transient) conditions, I OL must be externally limited as follows:
than the listed test conditions. at a higher voltage than V CC sinks additional currrent. Where FREQ is in MHz, I CCMAX is given in mA. Figure 5. I CC vs Frequency
EXPLANATION OF THE AC SYMBOLS Each timing symbol has 5 characters. The first char- acter is always a ‘T’ (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. A: Address C: Clock D: Input Data H: Logic level HIGH I: Instruction (program memory contents) L: Logic level LOW, or ALE P: PSEN Q: Output Data R: RD signal T: Time V: Valid W: WR signal X: No longer a valid logic level Z: Float For example, TAVLL e Time from Address Valid to ALE Low TLLPL e Time from ALE Low to PSEN Low AC CHARACTERISTICS (Over Operating Conditions, Load Capacitance for Port 0, ALE/PROG and PSEN e 100 pF, Load Capacitance for All Other Outputs e 80 pF) EXTERNAL MEMORY CHARACTERISTICS All parameter values apply to all devices unless otherwise indicated. In this table, 8XL5X refers to 8XL5X and 8XL5X-1. Symbol Parameter
12 MHz 20 MHz Variable
UnitsOscillator Oscillator Oscillator Min Max Min Max Min Max 1/TCLCL Oscillator Frequency 8XL5X 3.5 12 MHz 8XL5X-1 3.5 16 MHz 8XL5X-20 3.5 20 MHz TLHLL ALE Pulse Width 127 60 2 TCLCL b 40 ns TAVLL Address Valid to 43 10 TCLCL b 40 ns ALE Low TLLAX Address Hold After 53 20 TCLCL b 30 ns ALE Low TLLIV ALE Low to Valid Instruction In 8XL5X 234 4 TCLCL b 100 ns 8XL5X-20 125 4 TCLCL b 75 ns TLLPL ALE Low to PSEN 53 20 TCLCL b 30 ns Low TPLPH PSEN Pulse Width 205 105 3 TCLCL b 45 ns TPLIV PSEN Low to Valid Instruction In 8XL5X 145 3 TCLCL b 105 ns 8XL5X-20 60 3 TCLCL b 90 ns TPXIX Input Instruction 0 0 0 ns Hold After PSEN
EXTERNAL MEMORY CHARACTERISTICS (Continued) All parameter values apply to all devices unless otherwise indicated. Symbol Parameter UnitsOscillator Oscillator Oscillator Min Max Min Max Min Max TPXIZ Input Instruction Float After PSEN 8XL5X 59 TCLCL b 25 ns 8XL5X-20 30 TCLCL b 20 ns TAVIV Address to Valid 312 145 5 TCLCL b 105 ns Instruction In TPLAZ PSEN Low to Address 10 10 10 ns Float TRLRH RD Pulse Width 400 200 6 TCLCL b 100 ns TWLWH WR Pulse Width 400 200 6 TCLCL b 100 ns TRLDV RD Low to Valid Data In 8XL5X 252 5 TCLCL b 165 ns 8XL5X-20 155 5 TCLCL b 95 ns TRHDX Data Hold After RD 00 0 n s TRHDZ Data Float After RD 107 40 2 TCLCL b 60 ns TLLDV ALE Low to Valid Data In 8XL5X 517 8 TCLCL b 150 ns 8XL5X-20 310 8 TCLCL b 90 ns TAVDV Address to Valid Data In 8XL5X 585 9 TCLCL b 165 ns 8XL5X-20 360 9 TCLCL b 90 ns TLLWL ALE Low to RD or WR 200 300 100 200 3 TCLCL b 50 3 TCLCL a 50 ns Low TAVWL Address Valid to WR Low 8XL5X 203 4 TCLCL b 130 ns 8XL5X-20 110 4 TCLCL b 90 ns TQVWX Data Valid before WR 8XL5X 33 TCLCL b 50 ns 8XL5X-20 15 TCLCL b 35 ns TWHQX Data Hold after WR 8XL5X 33 TCLCL b 50 ns 8XL5X-20 10 TCLCL b 40 ns TQVWH Data Valid to WR High 8XL5X 433 7 TCLCL b 150 ns 8XL5X-20 280 7 TCLCL b 70 ns TRLAZ RD Low to Address Float 0 0 0 ns TWHLH RD or WR High to ALE 43 123 10 90 TCLCL b 40 TCLCL a 40 ns High
EXTERNAL PROGRAM MEMORY READ CYCLE 272468–11 EXTERNAL DATA MEMORY READ CYCLE 272468–12 EXTERNAL DATA MEMORY WRITE CYCLE 272468–13
SERIAL PORT TIMING - SHIFT REGISTER MODE Test Conditions: Over Operating Conditions; Load Capacitance e 80 pF Symbol Parameter UnitsOscillator Oscillator Oscillator Min Max Min Max Min Max TXLXL Serial Port Clock 1 0.600 12 TCLCL ms Cycle Time TQVXH Output Data Setup to 700 367 10 TCLCL b 133 ns Clock Rising Edge TXHQX Output Data Hold after Clock Rising Edge 8XL5X 50 2 TCLCL b 117 ns 8XL5X-20 50 2 TCLCL b 50 ns TXHDX Input Data Hold After 0 0 0 ns Clock Rising Edge TXHDV Clock Rising Edge to 700 367 10 TCLCL b 133 ns Input Data Valid SHIFT REGISTER MODE TIMING WAVEFORMS 272468–14
Symbol Parameter Min Max Units 1/TCLCL Oscillator Frequency 8XL5X 3.5 12 MHz8XL5X-1 3.5 16 8XL5X-20 3.5 20 TCHCX High Time 20 ns TCLCX Low Time 20 ns TCLCH Rise Time 20 ns TCHCL Fall Time 20 ns EXTERNAL CLOCK DRIVE WAVEFORM 272468–15 AC TESTING INPUT, OUTPUT WAVEFORMS 272468–16 AC Inputs during testing are driven at V CCb0.5V for a Logic ‘‘1’’ and 0.45V for a Logic ‘‘0’’. Timing measurements are made at V IH min for a Logic ‘‘1’’ and V IL max for a Logic ‘‘0’’. FLOAT WAVEFORMS 272468–17 For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs, and begins to float when a 100 mV change from the loaded V OH/VOL level occurs. IOL/IOH e g20 mA (-L, I OL/IOH e g10 mA).
ROM location. The setup is shown in Figure 10. sections of this data sheet. el can cause permanent damage to the device. Table 3. OTP ROM Programming Modes Figure 10. Programming the OTP ROM
87L5X the following sequence must be exercised.
- Input the valid address on the address lines.
- Input the appropriate data byte on the data
- Activate the correct combination of control sig-
/VPP from V CC to 12.75V g0.25V.
- Pulse, ALE/PROG 5 times for the OTP ROM
Figure 11. Programming Signals Waveforms user must submit an encryption table. tion Array that are initially unprogrammed (all 1’s).
Table 4. Program Lock Bits and the Features
2 P U U MOVC instructions executed from external program memory are disabled from
and further programming of the OTP ROM is disabled. 3 P P U Same as 2, also verify is disabled. 4 P P P Same as 3, also external execution is disabled. Any other combination of the lock bits is not defined.
OTP ROM PROGRAMMING AND VERIFICATION CHARACTERISTICS (TA e 21§Ct o2 7 §C; V CC e 2.7V to 3.6V; V SS e 0V) Symbol Parameter Min Max Units VPP Programming Supply Voltage 12.5 13.0 V IPP Programming Supply Current 75 mA 1/TCLCL Oscillator Frequency 4 6 MHz TAVGL Address Setup to PROG Low 48TCLCL TGHAX Address Hold after PROG 48TCLCL TDVGL Data Setup to PROG Low 48TCLCL TGHDX Data Hold after PROG 48TCLCL TEHSH P2.7 (ENABLE) High to V PP 48TCLCL TSHGL V PP Setup to PROG Low 10 ms TGHSL V PP Hold after PROG 10 ms TGLGH PROG Width 90 100 ms TAVQV Address to Data Valid 48TCLCL TELQV ENABLE Low to Data Valid 48TCLCL TEHQZ Data Float after ENABLE 0 48TCLCL TGHGL PROG High to PROG Low 10 ms OTP ROM PROGRAMMING AND VERIFICATION WAVEFORMS 272468–20 NOTE: *5 pulses for the OTP ROM array, 25 pulses for the encryption table and lock bits.
All thermal impedance data is approximate for static air conditions at 1W of power dissipation. Values will change depending on operating conditions and ap- plications. See the Intel Packaging Handbook (Order Number 240800) for a description of Intel’s thermal impedance test methodology. Package iJA iJC Device N4 6 §C/W 16 §C/W All S8 7 §C/W 18 §C/W 52 96§C/W 24 §C/W 54 90§C/W 22 §C/W 58 DATA SHEET REVISION HISTORY This is the first issue of this data sheet.