87C51FB

EE87C51FC24 INTEL | Alldatasheet

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*Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. April 1996COPYRIGHT © INTEL CORPORATION, 1996 Order Number: 272322-004 8XC51FX CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLERS Commercial/Express 87C51FA/83C51FA/80C51FA/87C51FB/83C51FB/87C51FC/83C51FC *See Table 1 for Proliferation Options Y High Performance CHMOS EPROM/ROM/CPU Y 12/24/33 MHz Operation Y Three 16-Bit Timer/Counters Y Programmable Counter Array with: Ð High Speed Output, Ð Compare/Capture, Ð Pulse Width Modulator, Ð Watchdog Timer Capabilities Y Up/Down Timer/Counter Y Three Level Program Lock System Y 8K/16K/32K On-Chip Program Memory Y 256 Bytes of On-Chip Data RAM Y Improved Quick Pulse Programming Algorithm Y Boolean Processor Y 32 Programmable I/O Lines Y 7 Interrupt Sources Y Four Level Interrupt Priority Y Programmable Serial Channel with: Ð Framing Error Detection Ð Automatic Address Recognition Y TTL Compatible Logic Levels Y 64K External Program Memory Space Y 64K External Data Memory Space Y MCSÉ 51 Controller Compatible Instruction Set Y Power Saving Idle and Power Down Modes Y ONCE (On-Circuit Emulation) Mode Y Extended Temperature Range Except for 33 MHz Offering ( b40§Ct o a85§C) MEMORY ORGANIZATION Device ROM Version EPROM ROMLESS Version ROM/ Bytes RAMEPROM Bytes 83C51FA 87C51FA 80C51FA 8K 256 83C51FB 87C51FB 80C51FA 16K 256 83C51FC 87C51FC 80C51FA 32K 256 These devices can address up to 64 Kbytes of external program/data memory. The Intel 87C51FA/8XC51FB/8XC51FC is a single-chip control oriented microcontroller which is fabricated on Intel’s reliable CHMOS III-E technology. The Intel 83C51FA/80C51FA is fabricated on CHMOS III technology. Being a member of the MCS É 51 controller family, the 8XC51FA/8XC51FB/8XC51FC uses the same powerful instruction set, has the same architecture, and is pin-for-pin compatible with the existing MCS 51 controller products. The 8XC51FA/8XC51FB/8XC51FC is an enhanced version of the 8XC52/8XC54/8XC58. Its added features make it an even more powerful microcontroller for applications that require Pulse Width Modulation, High Speed I/O and up/down counting capabilities such as motor control. For the remainder of this document, the 8XC51FA, 8XC51FB, 8XC51FC will be referred to as the 8XC51FX, unless information applies to a specific device.

Table 1. Proliferation Options Figure 1. 8XC51FX Block Diagram

*Do not connect Reserved Pins. Figure 2. Pin Connections

VCC: Supply voltage. VSS: Circuit ground. VSS1: Secondary ground (not on DIP devices or any 83C51FA/80C51FA device). Provided to reduce ground bounce and improve power supply by-pass- ing. NOTE: This pin is not a substitution for the V SS pin. (Con- nection not necessary for proper operation.) Port 0: Port 0 is an 8-bit, open drain, bidirectional I/O port. As an output port each pin can sink several LS TTL inputs. Port 0 pins that have 1’s written to them float, and in that state can be used as high-im- pedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external Program and Data Memory. In this application it uses strong inter- nal pullups when emitting 1’s, and can source and sink several LS TTL inputs. Port 0 also receives the code bytes during EPROM programming, and outputs the code bytes during program verification. External pullup resistors are re- quired during program verification. Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can drive LS TTL inputs. Port 1 pins that have 1’s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 1 pins that are externally pulled low will source current IL, on the data sheet) because of the internal pull- ups. In addition, Port 1 serves the functions of the follow- ing special features of the 8XC51FX: Port Pin Alternate Function P1.0 T2 (External Count Input to Timer/ Counter 2), Clock Out P1.1 T2EX (Timer/Counter 2 Capture/ Reload Trigger and Direction Control) P1.2 ECI (External Count Input to the PCA) P1.3 CEX0 (External I/O for Compare/ Capture Module 0) P1.4 CEX1 (External I/O for Compare/ Capture Module 1) P1.5 CEX2 (External I/O for Compare/ Capture Module 2) P1.6 CEX3 (External I/O for Compare/ Capture Module 3) P1.7 CEX4 (External I/O for Compare/ Capture Module 4) Port 1 receives the low-order address bytes during EPROM programming and verifying. Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can drive LS TTL inputs. Port 2 pins that have 1’s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 2 pins that are externally pulled low will source current IL, on the data sheet) because of the internal pull- ups. Port 2 emits the high-order address byte during fetches from external Program Memory and during accesses to external Data Memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pullups when emitting 1’s. Dur- ing accesses to external Data Memory that use 8-bit addresses (MOVX @Ri), Port 2 emits the contents of the P2 Special Function Register. Some Port 2 pins receive the high-order address bits during EPROM programming and program verifica- tion. Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers can drive LS TTL inputs. Port 3 pins that have 1’s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 3 pins that are externally pulled low will source current IL, on the data sheet) because of the pullups.

cess to external Data Memory. the microcontroller is in external execution mode. age (V PP) during EPROM programming. XTAL1: Input to the inverting oscillator amplifier. Figure 3. Either a quartz crystal or ceramic resonator

2) Hold ALE low as RST is deactivated. operation is restored when a normal reset is applied. tended temperature range with or without burn-in. following guidelines in MlL-STD-883, Method 1015. prefixes are listed in Table 3. from their commercial temperature range limits. Table 3. Prefix Identification Contact distributor or local sales office to match EXPRESS prefix with proper device. P87C51FC indicates 87C51FC in a plastic package and specified for commercial temperature range, without burn-in. LD87C51FC indicates 87C51FC in a cerdip package and specified for extended temperature range with burn-in.

ABSOLUTE MAXIMUM RATINGS * Ambient Temperature Under Bias À b40§Ct o a85§C Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b65§Ct o a150§C Voltage on EA/V PP Pin to V SS ÀÀÀÀÀÀÀ0V to a13.0V Voltage on Any Other Pin to V SS ÀÀb0.5V to a6.5V IOL per I/O Pin ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ15 mA Power DissipationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5W (based on PACKAGE heat transfer limitations, not device power consumption) NOTICE: This data sheet contains preliminary infor- mation on new products in production. It is valid for the devices indicated in the revision history. The specifications are subject to change without notice. *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability. OPERATING CONDITIONS Symbol Description Min Max Units TA Ambient Temperature Under Bias Commercial 0 a70 §CExpress b40 a85 VCC Supply Voltage 8XC51FX-33 4.5 5.5 VAll Others 4.0 6.0 fOSC Oscillator Frequency 8XC51FX 3.5 12 8XC51FX-1 3.5 16 MHz8XC51FX-2 0.5 12 8XC51FX-24 3.5 24 8XC51FX-33 3.5 33 DC CHARACTERISTICS (Over Operating Conditions) All parameter values apply to all devices unless otherwise indicated. Symbol Parameter Min Typical Max Units Test Conditions(Note 4) VIL Input Low Voltage b0.5 0.2 V CC b 0.1 V VIL1 Input Low Voltage EA 0 0.2 V CC b 0.3 V VIH Input High Voltage 0.2 V CC a 0.9 V CC a 0.5 V (Except XTAL1, RST) VIH1 Input High Voltage 0.7 V CC VCC a 0.5 V (XTAL1, RST) VOL Output Low Voltage (Note 5) 0.3 I OL e 100 mA (Ports 1, 2 and 3) 0.45 V I OL e 1.6 mA (Note 1) 1.0 I OL e 3.5 mA VOL1 Output Low Voltage (Note 5) 0.3 I OL e 200 mA (Port 0, ALE/PROG , PSEN ) 0.45 V I OL e 3.2 mA (Note 1) 1.0 I OL e 7.0 mA VOH Output High Voltage V CC b 0.3 I OH eb 10 mA (Ports 1, 2 and 3 V CC b 0.7 V I OH eb 30 mA (Note 2) ALE/PROG and PSEN )V CC b 1.5 I OH eb 60 mA VOH1 Output High Voltage V CC b 0.3 I OH eb 200 mA (Port 0 in External Bus Mode) V CC b 0.7 V I OH eb 3.2 mA (Note 2) VCC b 1.5 I OH eb 7.0 mA 83C51FA/80C51FA (Express) I OH eb 6.0 mA IIL Logical 0 Input Current b50 mAV IN e 0.45V (Ports 1, 2 and 3)

1. Capacitive loading on Ports 0 and 2 may cause noise pulses above 0.4V to be superimposed on the V OLs of ALE and

exceed 0.8V. It may be desirable to qualify ALE or other signals with a Schmitt Trigger, or CMOS-level input logic.

1. Capacitive loading on Ports 0 and 2 cause the V

address lines are stabilizing.

1. See Figures 6–9 for test conditions. Minimum V
2. Typicals are based on limited number of samples, and are not guaranteed. The values listed are at room temperature and 5V.
3. Under steady state (non-transient) conditions, I

than the listed test conditions. CC max at 33 MHz is at 5V g10% V CC, while I CC max at 24 MHz and below is at 5V g20% V CC. Figure 5. 8XC51FA/FB/FC I CC vs Frequency

EXPLANATION OF THE AC SYMBOLS Each timing symbol has 5 characters. The first char- acter is always a ‘T’ (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. A: Address C: Clock D: Input Data H: Logic level HIGH I: Instruction (program memory contents) L: Logic level LOW, or ALE P: PSEN Q: Output Data R: RD signal T: Time V: Valid W: WR signal X: No longer a valid logic level Z: Float For example, TAVLL e Time from Address Valid to ALE Low TLLPL e Time from ALE Low to PSEN Low AC CHARACTERISTICS (Over Operating Conditions, Load Capacitance for Port 0, ALE/PROG and PSEN e 100 pF, Load Capacitance for All Other Outputs e 80 pF) EXTERNAL MEMORY CHARACTERISTICS All parameter values apply to all devices unless otherwise indicated. In this table, 8XC51FX refers to 8XC51FX, 8XC51FX-1 and 8XC51FX-2. Symbol Parameter Oscillator Units12 MHz 24 MHz 33 MHz Variable Min Max Min Max Min Max Min Max 1/TCLCL Oscillator Frequency MHz 8XC51FX 3.5 12 8XC51FX-1 3.5 16 8XC51FX-2 0.5 12 8XC51FX-24 3.5 24 8XC51FX-33 3.5 33 TLHLL ALE Pulse Width 127 43 21 2TCLCL b40 ns TAVLL Address Valid to ALE Low 8XC51FX 43 TCLCL b40 ns 8XC51FX-24 12 TCLCL b30 ns 8XC51FX-33 5 TCLCL b25 ns TLLAX Address Hold After ALE Low 8XC51FX/-24 53 12 TCLCL b30 ns 8XC51FX-33 5 TCLCL b25 ns TLLIV ALE Low to Valid Instr In 8XC51FX 234 4TCLCL b100 ns 8XC51FX-24 91 4TCLCL b75 ns 8XC51FX-33 56 4TCLCL b65 ns TLLPL ALE Low to PSEN Low 8XC51FX/-24 53 12 TCLCL b30 ns 8XC51FX-33 5 TCLCL b25 ns TPLPH PSEN Pulse Width 205 80 46 3TCLCL b45 TPLIV PSEN Low to Valid Instr In 8XC51FX 145 3TCLCL b105 ns 8XC51FX-24 35 3TCLCL b90 ns 8XC51FX-33 35 3TCLCL b55 ns TPXIX Input Instr Hold after PSEN 000 0 n s

EXTERNAL MEMORY CHARACTERISTICS (Continued) All parameter values apply to all devices unless otherwise indicated Symbol Parameter Oscillator Units12 MHz 24 MHz 33 MHz Variable Min Max Min Max Min Max Min Max TPXIZ Input Instr Float After PSEN 8XC51FX 59 TCLCL-25 ns 8XC51FX-24 21 TCLCL-20 ns 8XC51FX-33 5 TCLCL-25 ns TAVIV Address to Valid Instr In 8XC51FX/-24 312 103 5TCLCL b105 ns 8XC51FX-33 71 5TCLCL b80 ns TPLAZ PSEN Low to Address Float 10 10 10 10 ns TRLRH RD Pulse Width 400 150 82 6TCLCL b100 ns TWLWH WR Pulse Width 400 150 82 6TCLCL b100 ns TRLDV RD Low to Valid Data In 8XC51FX 252 5TCLCL b165 ns 8XC51FX-24 113 5TCLCL b95 ns 8XC51FX-33 61 5TCLCL b90 ns TRHDX Data Hold After RD 000 0 n s TRHDZ Data Float After RD 8XC51FX/24 107 23 2TCLCL b60 ns 8XC51FX-33 35 2TCLCL b25 ns TLLDV ALE Low to Valid Data In 8XC51FX 517 8TCLCL b150 ns 8XC51FX-24/33 243 150 8TCLCL b90 ns TAVDV Address to Valid Data In 8XC51FX 585 9TCLCL b165 ns 8XC51FX-24/33 285 180 9TCLCL b90 ns TLLWL ALE Low to RD or WR Low 200 300 75 175 41 140 3TCLCL b50 3TCLCL a50 ns TAVWL Address to RD or WR Low 8XC51FX 203 4TCLCL b130 ns 8XC51FX-24 77 4TCLCL b90 ns 8XC51FX-33 46 4TCLCL b75 ns TQVWX Data Valid to WR Transition 8XC51FX 33 TCLCL b50 ns 8XC51FX-24/33 12 0 TCLCL b30 ns TWHQX Data Hold After WR 8XC51FX 33 TCLCL b50 ns 8XC51FX-24 7 TCLCL b35 ns 8XC51FX-33 3 TCLCL b27 ns TQVWH Data Valid to WR High 8XC51FX 433 7TCLCL b150 ns 8XC51FX-24/33 222 142 7TCLCL b70 ns TRLAZ RD Low to Address Float 0 0 0 0 ns TWHLH RD or WR High to ALE High 8XC51FX 43 123 TCLCL b40 TCLCL a40 ns 8XC51FX-24 12 71 TCLCL b30 TCLCL a30 ns 8XC51FX-33 5 55 TCLCL b25 TCLCL a25 ns

EXTERNAL PROGRAM MEMORY READ CYCLE 272322–9 EXTERNAL DATA MEMORY READ CYCLE 272322–10 EXTERNAL DATA MEMORY WRITE CYCLE 272322–11

SERIAL PORT TIMINGÐSHIFT REGISTER MODE Test Conditions: Over Operating Conditions; Load Capacitance e 80 pF Symbol Parameter Oscillator Units12 MHz 24 MHz 33 MHz Variable Min Max Min Max Min Max Min Max TXLXL Serial Port 1 0.50 0.36 12TCLCL ms Clock Cycle Time TQVXH Output Data 700 284 167 10TCLCL b133 ns Setup to Clock Rising Edge TXHQX Output Data Hold After Clock Rising Edge 8XC51FX 50 2TCLCL b117 ns 8XC51FX-24/33 34 10 2TCLCL b50 ns TXHDX Input Data Hold 0 0 0 0 ns After Clock Rising Edge TXHDV Clock Rising 700 283 167 10TCLCL b133 ns Edge to Input Data Valid SHIFT REGISTER MODE TIMING WAVEFORMS 272322–12

Symbol Parameter Min Max Units 1/TCLCL Oscillator Frequency MHz 8XC51FX 3.5 12 MHz 8XC51FX-1 3.5 16 MHz 8XC51FX-2 0.5 12 MHz 8XC51FX-24 3.5 24 MHz 8XC51FX-33 3.5 33 MHz TCHCX High Time 20 ns 8XC51FX-24/33 0.35 T OSC 0.65 T OSC ns TCLCX Low Time 20 ns 8XC51FX-24/33 0.35 T OSC 0.65 T OSC ns TCLCH Rise Time 20 ns 8XC51FX-24 10 ns 8XC51FX-33 5 ns TCHCL Fall Time 20 ns 8XC51FX-24 10 ns 8XC51FX-33 5 ns EXTERNAL CLOCK DRIVE WAVEFORM 272322–13 AC TESTING INPUT, OUTPUT WAVEFORMS 272322–14 AC Inputs during testing are driven at V CCb0.5V for a Logic ‘‘1’’ and 0.45V for a Logic ‘‘0’’. Timing measurements are made at V IH min for a Logic ‘‘1’’ and V OL max for a Logic ‘‘0’’. FLOAT WAVEFORMS 272322–15 For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs, and begins to float when a 100 mV change from the loaded V OH/VOL level occurs. IOL/IOH e g20 mA.

location. The setup is shown in Figure 10. sections of this data sheet. el can cause permanent damage to the device. Table 4. EPROM Programming Modes Figure 10. Programming the EPROM

87C51FX the following sequence must be exercised.

1. Input the valid address on the address lines.
2. Input the appropriate data byte on the data
3. Activate the correct combination of control sig-

/VPP from V CC to 12.75V g0.25V.

1. Pulse, ALE/PROG 5 times for the EPROM ar-

Figure 11. Programming Signals Waveforms

1. If program protection is desired, the user submits

does not have protection features. Table 5. Program Lock Bits and the Features

2 P U U MOVC instructions executed from external program memory are disabled from

further programming of the EPROM is disabled. 3 P P U Same as 2, also verify is disabled. 4 P P P Same as 3, also external execution is disabled. Any other combination of the lock bits is not defined.

Within the EPROM array are 64 bytes of Encryption Array that are initially unprogrammed (all 1’s). Every time that a byte is addressed during a verify, 6 ad- dress lines are used to select a byte of the Encryp- tion Array. This byte is then exclusive-NOR’ed (XNOR) with the code byte, creating an Encryption Verify byte. The algorithm, with the array in the un- programmed state (all 1’s), will return the code in its original, unmodified form. For programming the En- cryption Array, refer to Table 4 (Programming the EPROM). When using the encryption array, one important fac- tor needs to be considered. If a code byte has the value 0FFH, verifying the byte will produce the en- cryption byte value. lf a large block ( l64 bytes) of code is left unprogrammed, a verification routine will display the contents of the encryption array. For this reason all unused code bytes should be pro- grammed with some value other than 0FFH, and not all of them the same value. This will ensure maxi- mum program protection. Program Lock Bits The 87C51FX has 3 programmable lock bits that when programmed according to Table 5 will provide different levels of protection for the on-chip code and data. Erasing the EPROM also erases the encryption ar- ray and the program lock bits, returning the part to full functionality. Reading the Signature Bytes The 87C51FX has 3 signature bytes in locations 30H, 31H, and 60H. The 83C51FA has 2 signature bytes in locations 30H and 31H. To read these bytes follow the procedure for EPROM verify, but activate the control lines provided in Table 4 for Read Signa- ture Byte. Location Device Contents 30H All 89H 31H All 58H 60H 83C51FA 7AH/FAH 87C51FA FAH 83C51FB 7BH/FBH 87C51FB FBH 83C51FC 7CH/FCH 87C51FC FCH Erasure Characteristics (Windowed Packages Only) Erasure of the EPROM begins to occur when the chip is exposed to light with wavelength shorter than approximately 4,000 Angstroms. Since sunlight and fluorescent lighting have wavelengths in this range, exposure to these light sources over an extended time (about 1 week in sunlight, or 3 years in room- level fluorescent lighting) could cause inadvertent erasure. If an application subjects the device to this type of exposure, it is suggested that an opaque la- bel be placed over the window. The recommended erasure procedure is exposure to ultraviolet light (at 2537 Angstroms) to an integrat- ed dose of at least 15 W-sec/cm. Exposing the EPROM to an ultraviolet lamp of 12,000 mW/cm rat- ing for 30 minutes, at a distance of about 1 inch, should be sufficient. Erasure leaves all the EPROM Cells in a 1’s state.

EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS (TA e 21§Ct o2 7 §C; V CC e 5V g20%; V SS e 0V) Symbol Parameter Min Max Units VPP Programming Supply Voltage 12.5 13.0 V IPP Programming Supply Current 75 mA 1/TCLCL Oscillator Frequency 4 6 MHz TAVGL Address Setup to PROG Low 48TCLCL TGHAX Address Hold after PROG 48TCLCL TDVGL Data Setup to PROG Low 48TCLCL TGHDX Data Hold after PROG 48TCLCL TEHSH P2.7 (ENABLE) High to V PP 48TCLCL TSHGL V PP Setup to PROG Low 10 ms TGHSL V PP Hold after PROG 10 ms TGLGH PROG Width 90 110 ms TAVQV Address to Data Valid 48TCLCL TELQV ENABLE Low to Data Valid 48TCLCL TEHQZ Data Float after ENABLE 0 48TCLCL TGHGL PROG High to PROG Low 10 ms EPROM PROGRAMMING AND VERIFICATION WAVEFORMS 272322–18 NOTE: *5 pulses for the EPROM array, 25 pulses for the encryption table and lock bits.

All thermal impedance data is approximate for static air conditions at 1W of power dissipation. Values will change depending on operating conditions and ap- plications. See the Intel Packaging Handbook (Order No. 240800) for a description of Intel’s thermal im- pedance test methodology. Package iJA iJC Device P4 5 §C/W 16 §C/W All D3 6 §C/W 13 §C/W 80C51FA, 83C51FA, 8XC51FC 45§C/W 15 §C/W 87C51FA, 8XC51FB N4 6 §C/W 16 §C/W All S9 7 §C/W 24 §C/W FA 96§C/W 24 §C/W FB 87§C/W 18 §C/W FC DATA SHEET REVISION HISTORY Data sheets are changed as new device information becomes available. Verify with your local Intel sales office that you have the latest version before finalizing a design or ordering devices. The following differences exist between this datasheet (272322-003) and the previous version (272322-002): 1. Removed 8XC51FX-3 and 8XC51FX-20, replaced with 8XC51FX-24. 2. Included 8XC51FX-24 and 8XC51FX-33 devices. 3. 80C51FA and 83C51FA now have the same features as 87C51FA, 8XC51FB and 8XC51FC; same DC spec used for all devices. The following differences exist between the ‘‘-002’’ and ‘‘-001’’ version of 8XC51FX datasheet: 1. Removed 8XC51FX-L from datasheet. 2. Include V OH1 for 83C51FA (Express)/80C51FA (Express). This 8XC51FX datasheet (272322-001) replaces the following datasheets: 87C51FA/83C51FA/80C51FA 270258-007 83C51FA/80C51FA EXPRESS 270620-001 87C51FA EXPRESS 270619-001 87C51FA-20/-3 272081-002 87C51FB/83C51FB 270563-005 87C51FB-20/-3 83C51FB-20/-3 272080-002 87C51FB/83C51FB EXPRESS 270767-002 87C51FC/83C51FC 270789-004 87C51FC/83C51FC EXPRESS 270903-001 87C51FC-20/-3 83C51FC-20/-3 272028-002