AS87C196CB20F8 INTEL | Alldatasheet
Document overview
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- PDF pages: 38
Technical content
Datasheet sections
- 1.0 Introduction
- 2.0 Architecture
- 2.1 CPU Features
- 2.2 Peripheral Features
- 2.3 New Instructions
- 2.3.1 XCH/XCHB
- 2.3.2 BMOVi
- 2.3.3 TIJMP
- 2.3.4 EPTS/DPTS
- 2.4 SFR Operation
- 3.0 Packaging Information
- 4.0 Electrical Characteristics
- 4.1 Absolute Maximum Ratings
- 4.2 Operating Conditions
- 4.3 DC Characteristics
- 4.4 AC Characteristics
- 4.4.1 Explanation of AC Symbols
- 4.4.2 EPROM Specifications
- 4.4.3 A to D Converter Specifications
- 4.4.4 AC Characteristics—Slave Port
- 4.4.5 AC Characteristics—Serial Port— Shift Register Mode
- 4.4.6 Waveform—Serial Port—Shift Register Mode
- 6.0 Design Considerations
- 7.0 Revision History
87C196KR, 87C196JV, 87C196JT, 87C196JR, and 87C196CA Advanced 16-Bit CHMOS Microcontrollers Automotive Datasheet Product Features ■ –40°C to +125°C Ambient ■ High Performance CHMOS 16-Bit CPU ■ Up to 48 Kbytes of On-Chip EPROM ■ Up to 1.5 Kbytes of On-Chip Register RAM ■ Up to 512 Bytes of Additional RAM (Code RAM) ■ Register-Register Architecture ■ Up to Eight Channel/10-Bit A/D with Sample/Hold ■ Up to 37 Prioritized Interrupt Sources ■ Up to Seven 8-Bit (56) I/O Ports ■ Full Duplex Serial I/O Port ■ Dedicated Baud Rate Generator ■ Interprocessor Communication Slave Port ■ High Speed Peripheral Transaction Server (PTS) ■ Two 16-Bit Software Timers ■ Up to 10 High Speed Capture/Compare (EPA) ■ Full Duplex Synchronous Serial I/O Port (SSIO) ■ Two Flexible 16-Bit Timer/Counters ■ Quadrature Counting Inputs ■ Flexible 8-/16-Bit External Bus ■ Programmable Bus (HLD/HLDA) ■ 1.75 µs 16 x 16 Multiply ■ 3 µs 32/16 Divide ■ 68-Pin and 52-Pin PLCC Packages ■ Supports CAN (Controller Area Network) Specification 2.0 (CA only) Order Number: 270827-007 April 1998
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 87C196KR, JV, JT, JR and CA microcontrollers may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © Intel Corporation, 1998 *Third-party brands and names are the property of their respective owners.
87C196KR, JV, JT, JR, and CA Microcontrollers — Automotive
4 Datasheet
14 Slave Programming Mode Data Program Mode with Single
15 Slave Programming Mode in Word Dump or Data Verify Mode with
16 Slave Programming Mode Timing in Data Program Mode with
Automotive — 87C196KR, JV, JT, JR, CA Microcontrollers Datasheet 5
1.0 Introduction
The MCS 96 microcontroller family members are all high performance microcontrollers with a 16- bit CPU. The 87C196Kx and Jx family members are composed of the high-speed (16 MHz) core as well as the following peripherals:
- Up to 48 Kbytes of Programmable EPROM
- Up to 1.5 Kbytes of register RAM and 512 bytes of code RAM (16-bit addressing modes) with the ability to execute from this RAM space
- Up to eight channels–10-Bit/ ± 3 LSB analog to digital converter with programmable S/H times with conversion times < 5 µs at 16 MHz
- An asynchronous/synchronous serial I/O port (8096 compatible) with a dedicated 16-bit baud rate generator
- Interprocessor communication slave port
- Synchronous serial I/O port with full duplex master/slave transceivers
- A flexible timer/counter structure with prescaler, cascading, and quadrature capabilities
- Up to ten modularized multiplexed high speed I/O for capture and compare (called Event Processor Array) with 250 ns resolution and double buffered inputs
- A sophisticated prioritized interrupt structure with programmable Peripheral Transaction Server (PTS). The PTS has several channel modes, including single/burst block transfers from any memory location to any memory location, a PWM and PWM toggle mode to be used in conjunction with the EPA, and an A/D scan mode.
- Serial communications protocol CAN 2.0 with 15 message objects of 8 bytes data length (CA only) The 87C196KR, JV, JT, JR, and CA devices represent the fourth generation of MCS ® 96 microcontroller products implemented on Intel' s advanced 1 micron process technology. These products are based on the 80C196KB device with improvements for automotive applications. The instruction set is a true super set of 80C196KB. The 87C196JR, JT, and JV are 52-pin versions of the 87C196KR device. The 87C196JV and JT devices are memory scalars of the 87C196JR and are designed for strict functional and electrical compatibility. The JT has 32 Kbytes of on-chip EPROM, 1.0 Kbytes of Register RAM and 512 bytes of Code RAM. The JV has 48 Kbytes of on-chip EPROM, 1.5 Kbytes of Register RAM and 512 bytes of Code RAM. The 87C196CA device is a memory scalar of the 87C196KR in a 68-pin package with 32 Kbytes of on-chip EPROM, 1.0 Kbytes of register RAM, and 256 bytes of code RAM. In addition, the CA contains an extra peripheral for serial communications protocol CAN 2.0. Table 1 summarizes the features of the 87C196Kx, Jx, and CA devices.
6 Datasheet
- 87C196JT 20 MHz Advanced 16-Bit CHMOS Microcontroller datasheet, order #272529
- 87C196JV 20 MHz Advanced 16-Bit CHMOS Microcontroller datasheet, order #272580.
2.0 Architecture
2.1 CPU Features
- Powerdown and Idle Modes
- 16 MHz Operating Frequency
- A High Performance Peripheral Transaction Server (PTS)
- Up to 37 Interrupt Vectors
- Up to 512 Bytes of Code RAM
- Up to 1.5 Kbytes of Register RAM
- “Windowing” Allows 8-Bit Addressing to Some 16-Bit Addresses
- 1.75 µs 16 x 16 Multiply
- 3 µs 32/16 Divide
- Oscillator Fail Detect
2.2 Peripheral Features
- Programmable A/D Conversion and S/H Times
- Up to 10 Capture/Compare I/O with 2 Flexible Timers
- Synchronous Serial I/O Port for Full Duplex Serial I/O
Table 1. 87C196Kx and Jx Features Summary
Automotive — 87C196KR, JV, JT, JR, CA Microcontrollers Datasheet 7
- Total Utilization of ALL Available Pins (I/O Mux' d with Control)
- Two 16-Bit Timers with Prescale, Cascading and Quadrature Counting Capabilities
- Up to 12 Externally Triggered Interrupts
2.3 New Instructions
2.3.1 XCH/XCHB
Exchange the contents of two locations, either Word or Byte is supported.
2.3.2 BMOVi
Interruptable Block Move Instruction, allows the user to be interrupted during long executing Block Moves.
2.3.3 TIJMP
Table Indirect JUMP. This instruction incorporates a way to do complex CASE level branches through one instruction. An example of such code savings: several interrupt sources and only one interrupt vector. The TIJMP instruction will sort through the sources and branch to the appropriate sub-code level in one instruction. This instruction was added especially for the EPA structure, but has other code saving advantages.
2.3.4 EPTS/DPTS
Enable and Disable PTS Interrupts (Works like EI and DI).
2.4 SFR Operation
An additional 256 bytes of SFR registers were added to the 8XC196Kx, Jx, and CA devices. These locations were added to support the wide range of on-chip peripherals that these devices have. This memory space (1F00–1FFFH) has the ability to be addressed as direct 8-bit addresses through the “windowing” technique. Any 32-, 64- or 128-byte section can be relocated in the upper 32, 64 or 128 bytes of the internal register RAM (080–FFH) address space. The CA contains an additional 256 bytes of SFR registers for CAN functions located in memory space IE00-1EFFh.
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Figure 1. Block Diagram Figure 2. 8XC196Kx, Jx, and CA Family Nomenclature
3.0 Packaging Information
Figure 3. 87C196KR 68-Pin PLCC Package Diagram
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Figure 4. 87C196JV, JT, JR 52-Pin PLCC Package Diagram
Figure 5. 87C196CA 68-Pin PLCC Package Diagram
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Table 2. Pin Descriptions (Sheet 1 of 2) VCC Main supply voltage (+5 V). connected to a single ground plane. connected for A/D and Port 0 to function. Programming voltage for the EPROM parts. It should be +12.5 V for programming. XTAL1 Input of the oscillator inverter and the internal clock generator. XTAL2 Output of the oscillator inverter. P2.7/CLKOUT Output of the internal clock generator. The frequency is ½ the oscillator frequency. It has a 50% duty cycle. Also LSIO pin when not used as CLKOUT. normal operation. RESET# has an internal pullup. 2 is “0”, all bus cycles are 16-bit. CCR bit 1 =”0'' and CCR1 bit 2 = “0” is illegal. Also an LSIO pin when not used as BUSWIDTH. options provide a latch to demultiplex the address from the address/data bus. external memory accesses. Also LSIO when not used as ALE. reads. LSIO when not used as RD#. writes. Also an LSIO pin when not used as WR#/WRL#.
selected, the pin will go low if the bus cycle is writing to an odd memory location. LSIO pin when not BHE#/WRH#. the CCR/CCR1. Also an LSIO pin when READY is not selected. P5.4/SLPINT Dual functional I/O pin. As a bidirectional port pin (LSIO) or as a system function. The system function is a Slave Port Interrupt Output Pin. or decrement on both positive and negative edges of this pin. increment when this pin is high and decrements when this pin is low. Dual function I/O port pins. Primary function is that of bidirectional I/O (LSIO). have yet another function of T2CLK and T2DIR of the TIMER2 timer/counter. inputs to EPROM parts to select the Programming Mode. P6.4–6.7/SSIO Dual function I/O ports that have a system function as Synchronous Serial I/O. Two pins are clocks and two pins are data, providing full duplex capability. PORT 2 8-bit multi-functional port. All of its pins are shared with other functions. multiplexed address/data bus which has strong internal pullups. TXCAN Push-pull output to the CAN bus line. RXCAN High-impedance input-only from the CAN bus line. Table 2. Pin Descriptions (Sheet 2 of 2)
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4.0 Electrical Characteristics
4.1 Absolute Maximum Ratings
Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only.
4.2 Operating Conditions
the “Operating Conditions” may affect device reliability. Table 3. Absolute Maximum Ratings Table 4. Operating Conditions
- ANGND and VSS should be nominally at the same potential.
- Device is static and should operate below 1 Hz, but only tested down to 4 MHz.
4.3 DC Characteristics
Table 5. DC Characteristics (Sheet 1 of 2)
2.0 V I
- All BD (bidirectional) pins except P5.5/INST and P2.7/CLKOUT which are excluded due to their not being
weakly pulled high in reset. BD pins include Port1, Port 2, Port3, Port4, Port5, and Port6.
- Standard Input pins include XTAL1, EA#, RESET#, and Ports 1,2,3,4,5,6 when configured as inputs.
- All bidirectional I/O pins when configured as outputs (push/pull).
- Typicals are based on limited number of samples and are not guaranteed. The values listed are at room
- VIH max for Port0 is VREF + 0.5 V.
- Refer to “VOH2/IOH2 Specification” errata #1 in errata section of this datasheet.
- This specification is not tested in production and is based upon theoretical estimates and/or product
- Violating these specifications in reset may cause the device to enter test modes (P5.4 and P2.6).
16 Datasheet
Figure 6. 87C196KR and JR ICC vs. Frequency Table 5. DC Characteristics (Sheet 2 of 2)
- All BD (bidirectional) pins except P5.5/INST and P2.7/CLKOUT which are excluded due to their not being
weakly pulled high in reset. BD pins include Port1, Port 2, Port3, Port4, Port5, and Port6.
- Standard Input pins include XTAL1, EA#, RESET#, and Ports 1,2,3,4,5,6 when configured as inputs.
- All bidirectional I/O pins when configured as outputs (push/pull).
- Typicals are based on limited number of samples and are not guaranteed. The values listed are at room
- VIH max for Port0 is VREF + 0.5 V.
- Refer to “VOH2/IOH2 Specification” errata #1 in errata section of this datasheet.
- This specification is not tested in production and is based upon theoretical estimates and/or product
- Violating these specifications in reset may cause the device to enter test modes (P5.4 and P2.6).
4 MHz 10 MHz 15 MHz
Figure 7. JT ICC vs. Frequency Figure 8. 87C196CA ICC vs. Frequency
4 MHz 10 MHz 20 MHz
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4.4 AC Characteristics
Table 6. AC Characteristics (Sheet 1 of 2) The system must meet these specifications to work with the 87C196KR, JV, JT, JR, CA Microcontroller. The 87C196KR, JV, JT, JR, CA Microcontroller meets these specifications.
- If max is exceeded, additional wait states will occur.
- Testing performed at 4 MHz; however, the device is static by design and will typically operate below 1 Hz.
- Typical specifications, not guaranteed.
- Assuming back-to-back bus cycles.
RLAZ (max) = 5 ns by design.
- TOFD is the time for the oscillator fail detect circuit (OFD) to react to a clock failure.
Table 6. AC Characteristics (Sheet 2 of 2)
- If max is exceeded, additional wait states will occur.
- Testing performed at 4 MHz; however, the device is static by design and will typically operate below 1 Hz.
- Typical specifications, not guaranteed.
- Assuming back-to-back bus cycles.
RLAZ (max) = 5 ns by design.
- TOFD is the time for the oscillator fail detect circuit (OFD) to react to a clock failure.
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Figure 9. System Bus Timing
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Figure 12. AC Testing Input, Output Waveforms Figure 13. Float Waveforms Table 8. Thermal Characteristics taken 1 ft. away from case in air flow environment. JC = Thermal resistance between junction and package surface (case).
- All values of θJA and θJC may fluctuate depending on the environment (with or without airflow, and how
much airflow) and device power dissipation at temperature of operation. Typical variations are ±2°C/W.
- Values listed are at a maximum power dissipation of 0.50 W.
level occurs with IOL /IOH ≤ 15 mA.
4.4.1 Explanation of AC Symbols
4.4.2 EPROM Specifications
Table 9. AC EPROM Programming Characteristics
- Run-time programming is done with FOSC = 6.0 MHz to 10.0 MHz, VCC , VPD , VREF =5V±0 . 5V ,
- Programming specifications are not tested, but guaranteed by design.
- This specification is for the word dump mode. For programming pulses, use 300 T
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Table 10. DC EPROM Programming Characteristics Figure 14. Slave Programming Mode Data Program Mode with Single Program Pulse Figure 15. Slave Programming Mode in Word Dump or Data Verify Mode with Auto Increment
4.4.3 A to D Converter Specifications
digital portion of the converter and input port pins. conversion is complete. Testing is performed at VREF = 5.12 V and 16 MHz operating frequency. offset adjustment. The absolute error listed is without doing any adjustments. Figure 16. Slave Programming Mode Timing in Data Program Mode with Repeated PROG Table 11. A/D Operating Conditions (Sheet 1 of 2)
- ANGND and VSS should nominally be at the same potential.
- VREF must not exceed VCC by more than +0.5 V.
- Testing is performed at VREF = 5.12 V.
- The value of AD_TIME must be selected to meet these specifications.
26 Datasheet
Table 12. A/D Operating Parameter Values † These values are expected for most parts at 25°C but are not tested or guaranteed.
- These values are not tested in production and are based on theoretical estimates and/or laboratory test.
- Multiplexer break-before-make guaranteed.
Table 11. A/D Operating Conditions (Sheet 2 of 2)
- ANGND and VSS should nominally be at the same potential.
- VREF must not exceed VCC by more than +0.5 V.
- Testing is performed at VREF = 5.12 V.
- The value of AD_TIME must be selected to meet these specifications.
Table 13. HOLD#/HLDA# Timings
- To guarantee recognition at next clock.
Table 14. DC Specifications in HOLD Figure 17. HOLD Timings
28 Datasheet
4.4.4 AC Characteristics—Slave Port
Figure 18. Slave Port Waveform (SLPL = 0) Table 15. Slave Port Timing–(SLPL = 0) (See notes 1, 2, 3)
- Test conditions: FOSC =1 6M H z , TOSC = 60 ns, Rise/Fall Time = 10 ns. Capacitive Pin Load = 100 pF.
- These values are not tested in production, and are based upon theoretical estimates and/or laboratory
3.Specifications above are advanced information and are subject to change.
Figure 19. Slave Port Waveform (SLPL = 1) Table 16. Slave Port Timing–(SLPL = 1) (See notes 1, 2, 3)
- Test conditions: FOSC =1 6M H z , TOSC = 60 ns, Rise/Fall Time = 10 ns. Capacitive Pin Load = 100 pF.
- These values are not tested in production, and are based upon theoretical estimates and/or laboratory
3.Specifications above are advanced information and are subject to change.
30 Datasheet
4.4.5 AC Characteristics—Serial Port— Shift Register Mode
4.4.6 Waveform—Serial Port—Shift Register Mode 0
Table 17. Serial Port Timing—Shift Register Mode Figure 20. Serial Port Waveform—Shift Register Mode
Automotive — 87C196KR, JV, JT, JR, CA Microcontrollers Datasheet 31 5.0 52-Lead Devices Intel offers 52-lead versions of the 87C196KR device: the 87C196JV, JT, and JR devices. The first samples and production units use the 87C196KR die and bond it out in a 52-lead package. It is important to point out some functionality differences because of future devices or to remain software consistent with the 68-lead device. Because of the absence of pins on the 52-lead device some functions are not supported. 52-Lead Unsupported Functions:
- Analog Channels 0 and 1
- INST Pin Functionality
- SLPINT Pin Support
- HLD#/HLDA# Functionality
- External Clocking/Direction of Timer1
- WRH# or BHE Functions
- Dynamic Buswidth
- Dynamic Wait State Control The following is a list of recommended practices when using the 52-lead device: 1. External Memory . Use an 8-bit bus mode only. There is neither a WRH# or BUSWIDTH pin. The bus cannot dynamically switch from 8- to 16-bit or vice versa. Set the CCB bytes to an 8-bit only mode, using WR# function only. 2. Wait State Control. Use the CCB bytes to configure the maximum number of wait states. If the READY pin is selected to be a system function, the device will lockup waiting for READY. If the READY pin is configured as LSIO (default after RESET#), the internal logic will receive a logic “0” level and insert the CCB defined number of wait states in the bus cycle. DON'T USE IRC = “111”. 3. NMI Support . The NMI is not bonded out. Make the NMI vector at location 203Eh vector to a Return instruction. This is for glitch safety protection only. 4. Auto-Programming Mode . The 52-lead device will ONLY support the 16-bit zero wait state bus during auto-programming. 5. EPA4 through EPA7 . Since the JR, JT, and JV devices use the KR silicon, these functions are in the device, just not bonded out. A programmer can use these as compare only channels or for other functions like software timer, start an A/D conversion, or reset timers. 6. Slave Port Support. The Slave port cannot be easily used on 52-lead devices due to 5.4/ SLPINT and P5.1/SLPCS not being bonded-out.
87C196KR, JV, JT, JR, CA Microcontrollers — Automotive
32 Datasheet
updated and read. The programmer should not use the corresponding bits associated with the removed port pins to conditionally branch in software. Treat these bits as RESERVED. Additionally, these port pins should be setup internally by software as follows: a. Written to PxREG as “1” or “0”. b. Configured as Push/Pull, PxIO as “0”. c. Configured as LSIO. Warning: This configuration will effectively strap the pin either high or low. DO NOT Configure as Open Drain output “1”, or as an Input pin. This device is CMOS.
6.0 Design Considerations
6.1 87C196KR, JV, JT, JR, and CA Design Considerations 1. EPA Timer RESET/Write Conflict If the user writes to the EPA timer at the same time that the timer is reset, it is indeterminate which will take precedence. Users should not write to a timer if using EPA signals to reset it. 2. Valid Time Matches The timer must increment/decrement to the compare value for a match to occur. A match does not occur if the timer is loaded with a value equal to an EPA compare value. Matches also do not occur if a timer is reset and 0 is the EPA compare value. 3. P6 PIN.4-.7 Not Updated Immediately Values written to P6 REG are temporarily held in a buffer. If P6 MODE is cleared, the buffer is loaded into P6 REG.x. If P6 MODE is set, the value stays in the buffer and is loaded into P6 REG.x when P6 MODE.x is cleared. Since reading P6 REG returns the current value in P6. REG and not the buffer, changes to P6 REG cannot be read until/unless P6 MODE.x is cleared. 4. Write Cycle during Reset If RESET occurs during a write cycle, the contents of the external memory device may be corrupted. 5. Indirect Shift Instruction The upper 3 bits of the byte register holding the shift count are not masked completely. If the shift count register has the value 32 x n, where n = 1, 3, 5, or 7, the operand will be shifted 32 times. This should have resulted in no shift taking place. 6. P2.7 (CLKOUT) P2.7 (CLKOUT) does not operate in open drain mode. 7. CLKOUT The CLKOUT signal is active on P2.7 during RESET for the KR, JV, JT, JR and CA devices.
Automotive — 87C196KR, JV, JT, JR, CA Microcontrollers Datasheet 33 8. EPA Overruns EPA “lock-up” can occur if overruns are not handled correctly, refer to Intel Techbit #DB0459 “Understanding EPA Capture Overruns”, dated 12-9-93. Applies to EPA channels with interrupts and overruns enabled (ON/RT bit in EPA_CONTROL register set to “1”). 9. Indirect Addressing with Auto-Increment For the special case of a pointer pointing to itself using auto-increment, an incorrect access of the incremented pointer address will occur instead of an access to the original pointer address. All other indirect auto-increment accesses will note be affected. Please refer to Techbit #MC0593. Incorrect sequence: Correct sequence: 10. JV Additional Register RAM The 8XC196JV has a total of 1.5 Kbytes of register RAM. The RAM is located in two memory ranges: 0000h – 03FFh and 1C00h – 1DFFh. 6.2 87C196JR C-step to JR D-step – or – JV/JT A-step Design Considerations This section documents differences between the 87C197JV A-step (JV-A)/87C196JT A-step (JT- A)/87C196JR D-step (JR-D) and the 87C196JR C-step/(JR-C). For a list of design considerations between 68-lead and 52-lead devices, please refer to the 52-lead Device Design Considerations section of this datasheet. Since the 87C196JV and JT are simply memory scalars of the 87C196JR, the term \\JR' ' in this section will refer to JV, JT, and JR versions of the device unless otherwise noted. The JR-C is simply a 87C196KR C-step (KR-C) device packaged within a 52-lead package. This reduction in pin count necessitated not bonding-out certain pins of the KR-C device. The fact that these “removed pins” were still present on the device but not available to the outside world allowed the programmer to take advantage of some of the 68-lead KR features. The JR-D is a fully-optimized 52-lead device based on the 87C196KR C-step device. The KR-C design data base was used to assure that the JR-D would be fully compatible with the KR-C, JR-C and other Kx family members. The main differences between the JR-D and the JR-C is that several of the unused (not bonded-out) functions on the JR-C were removed altogether on the JR-D. Following is a list of differences between the JR-C and the JR-D: 1. Port3 Push-Pull Operation It was discovered on JR-C that if Port3 is selected for push-pull operation (P34_DRV register) during low speed I/O (LSIO), the port was driving data when the system bus was attempting to input data. It is rather unlikely that this errata would affect an application because the application would have to use Port3 for both LSIO and as an external addr/data bus. Nonetheless, this errata was corrected on the JR-D. ld ax,#ax ; Results in ax being incremented by 1 and the contents of the address pointed to by ax+1 to be loaded into bx.ldb bx,[ax]+ ; ld ax,#bx ; where ax≠ bx. Results in the contents of the address pointed to by ax to be loaded into bx and ax incremented by 1.ldb cx,[ax]+ ;
87C196KR, JV, JT, JR, CA Microcontrollers — Automotive
34 Datasheet
- VOH2 Strengthened The DC Characteristics section of the Automotive KR datasheet contains a parameter, VOH2 (Output High Voltage in RESET (BD ports)), which is specified at VCC –1V m i n a t IOH2 = –15 µA. This specification indicates the strength of the internal weak pull-ups that are active during and after reset. These weak pull-ups stay active until the user writes to PxMODE (previously known as PxSSEL) and configures the port pin as desired. These pull-ups do not meet this V OH2 spec on the JR-C. The weak pull-ups on specified JR-D ports have been enhanced to meet the published specification of IOH2 =– 1 5µA. 3. ONCE Mode ONCE mode is entered by holding a single pin low on the rising edge of RESET#. On the KR, this pin is P5.4/SLPINT. The JR-C does not support ONCE mode since P5.4/SLPINT (ONCE mode entry pin) is not bonded-out on these devices. To provide ONCE mode on the JR-D, the ONCE mode entry function was moved from P5.4/SLPINT to P2.6/HLDA. This will allow the JR-D to enter ONCE mode using P2.6 instead of removed pin P5.4. 4. Port0 On the JR-C, P0.0 and P0.1 are not bonded out. However, these inputs are present in the device and reading them will provide an indeterminate result. On the JR-D, the analog inputs for these two channels at the multiplexer are tied to V REF . Therefore, initiating an analog conversion on ACH0 or ACH1 will result in a value equal to full scale (3FFh). On the JR-D, the digital inputs for these two channels are tied to ground, therefore reading P0.0 or P0.1 will result in a digital \
\0''. 5. Port1 On the JR-C, P1.4, P1.5, P1.6 and P1.7 are not bonded out but are present internally on the device. This allows the programmer to write to the port registers and clear, set or read the pin even though it is not available to the outside world. However, to maintain compatibility with D-step and future devices, it is recommended that the corresponding bits associated with the removed pins NOT be used to conditionally branch in software. These bits should be treated as reserved. On the JR-D, unused port logic for these four port pins has been removed from the device and is not available to the programmer. Corresponding bits in the port registers have been \\hard- wired'' to provide the following results when read: 6. Port2 On the JR-C, P2.3 and P2.5 are not bonded out but are present internally on the device. This allows the programmer to write to the port registers and clear, set or read the pin even though it is not available to the outside world. However, to maintain compatibility with D-step and future devices, it is recommended that the corresponding bits associated with the removed pins not be used to conditionally branch in software. These bits should be treated as reserved. On the JR-D, unused port logic for these two port pins has been removed from the device and is not available to the programmer. Corresponding bits in the port registers have been “hardwired” to provide the following results when read: Register Bits When Read P1_PIN.x (x = 4,5,6,7) 1 P1_REG.x (x = 4,5,6,7) 1 P1_DIR.x (x = 4,5,6,7) 1 P1_MODE.x (x = 4,5,6,7) 0 NOTE: Writing to these bits will have no effect.
Automotive — 87C196KR, JV, JT, JR, CA Microcontrollers Datasheet 35 7. Port5 the device. This allows the programmer to write to the port registers and clear, set or read the pin even though it is not available to the outside world. However, to maintain compatibility with D-step and future devices, it is recommended that the corresponding bits associated with the removed pins not be used to conditionally branch in software. These bits should be treated as reserved. On the JR-D, unused port logic for these five port pins has been removed from the device and is not available to the programmer. Corresponding bits in the port registers have been “hardwired” to provide the following results when read: 8. Port6 On the JR-C, P6.2 and P6.3 are not bonded out but are present internally on the device. This allows the programmer to write to the port registers and clear, set or read the pin even though it is not available to the outside world. However, to maintain compatibility with D-step and future devices, it is recommended that the corresponding bits associated with the removed pins not be used to conditionally branch in software. These bits should be treated as reserved. On the JR-D, unused port logic for these two port pins has been removed from the device and is not available to the programmer. Corresponding bits in the port registers have been “hardwired” to provide the following results when read: Register Bits When Read P2_PIN.x (x = 3,5) 1 P2_REG.x (x = 3,5) 1 P2_DIR.x (x = 3,5) 1 P2_MODE.x (x = 3,5) 0 NOTE: Writing to these bits will have no effect. Register Bits When Read P5_MODE.x (x = 1,4,6) 0 P5_MODE.x (x = 5)(EA# = 0) 1 P5_MODE.x (x = 5)(EA# = 1) 0 P5_MODE.x (x = 7) 1 NOTE: Writing to these bits will have no effect. Register Bits When Read P6_PIN.x (x = 2,3) 1 P6_REG.x (x = 2,3) 1 P6_DIR.x (x = 2,3) 1 P6_MODE.x (x = 2,3) 0 NOTE: Writing to these bits will have no effect.
87C196KR, JV, JT, JR, CA Microcontrollers — Automotive
36 Datasheet
- EPA Channels 4 through 7 The JR C-step device is simply a 68-lead KR-C device packaged in a 52-lead package. The reduced pin-out is achieved by not bonding-out the unsupported pins. EPA4–EPA7 are among these pins that are not bonded-out. The fact that EPA4–EPA7 are still present allows the programmer to use these channels as software timers, to start A/D conversions, reset timers, etc. All of the port pin logic is still present and it is possible to use the EPA to toggle these pins internally. Please refer to the 52-Lead Device section in this datasheet for further information. On the JR D-step, the EPA4–EPA7 logic has NOT been removed from the device. This allows the programmer to still use these channels (as on the C-step) for software timers, etc. The only difference is that the associated port pin logic has been removed and does not exist internally. To maintain C-step to D-step compatibility, programmers should make sure that their software does not rely upon the removed pins. 6.2.1 87C196CA Design Considerations The 87C196CA device is a memory scalar of the 87C196KR device with integrated CAN 2.0. The CA is designed for strict functional and electrical compatibility to the Kx family as well as integration of on-chip networking capability. The 87C196CA has fewer peripheral functions than the 196KR, due in part to the integration of the CAN peripheral. Following are the functionality differences between the 196KR and 196CA devices. 196KR Features Unsupported on the 196CA: 1. External Memory Removal of the Buswidth pin means the bus cannot dynamically switch from 8- to 16-bit bus mode or vice versa. The programmer must define the bus mode by setting the associated bits in the CCB. 2. Auto-Programming Mode The 87C196CA device will ONLY support the 16-bit zero wait state bus during auto- programming. 3. EPA4 through EPA7 Since the CA device is based on the KR design, these functions are in the device, however there are no associated pins. A programmer can use these as compare only channels or for other functions like software timer, start an A/D conversion, or reset timers. 4. Slave Port Support The Slave port can not be used on the 196CA due to a function change for P5.4/SLPINT and P5.1/SLPCS not being bonded-out. 5. Port Functions P0.1. The PxREG, PxSSEL, and PxIO registers can still be updated and read. The programmer should not use the corresponding bits associated with the removed port pins to conditionally branch in software. Treat these bits as RESERVED. Additionally, these port pins should be setup internally by software as follows:
- Analog Channels 0 and 1
- INST Pin Functionality
- SLPINT and SLPCS Pin Support
- HLD/HLDA Functionality
- External Clocking/Direction of Timer1
- Quadrature Clocking Timer 1
- Dynamic Buswidth
- EPA Capture Channels 4–7
Automotive — 87C196KR, JV, JT, JR, CA Microcontrollers Datasheet 37 a . W r i t t e n t o P x R E G a s \ \ 1 '' o r \ \ 0 ''. b. Configured as Push/Pull, PxIO as \\0' ' . c. Configured as LSIO. This configuration will effectively strap the pin either high or low. DO NOT Configure as Open Drain output \`' 1' ' , or as an Input pin. This device is CMOS. 6. EPA Timer RESET/Write Conflict If the user writes to the EPA timer at the same time that the timer is reset, it is indeterminate which will take precedence. Users should not write to a timer if using EPA signals to reset it. 7. Valid Time Matches The timer must increase/decrease to the compare value for a match to occur. A match does not occur if the timer is loaded with a value equal to an EPA compare value. Matches also do not occur if a timer is reset and 0 is the EPA compare value. 8. Write Cycle during Reset If RESET occurs during a write cycle, the contents of the external memory device may be corrupted. 9. Indirect Shift Instruction The upper 3 bits of the byte register holding the shift count are not masked completely. If the shift count register has the value 32 c n, where n e 1, 3, 5, or 7, the operand will be shifted 32 times. This should have resulted in no shift taking place. 10. P2.7 (CLKOUT) P2.7 (CLKOUT) does not operate in open drain mode.
7.0 Revision History
Removed the 87C196KQ and 87C196JQ products and related information from datasheet. Added 87C196CA product and related information to datasheet. 006 11/95 The 87C196JV datasheet status has been moved from “Product Preview” to that of “no marking. A ”by design” note was added to the TRLAZ specification. In the Design Considerations section, the #7.CLKOUT design consideration was corrected. Only the two most current revision histories of this datasheet were retained in the datasheet revision history section.