Microcontroller

8744AH

Intel Corporation

HIGH PERFORMANCE 8 BIT MICROCONTROLLER WITH ON CHIP SERIAL COMMUNICATION CONTROLLER

Manufacturer: Intel Corporation

Document: 26 Pages / 1Mb

Request Quote Download Datasheet Read online HTML view

More from Intel Corporation Browse 0-9 parts

Online Datasheet

Read 8744AH online.

8044AH INTEL | Alldatasheet

Document overview

Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 26

Technical content

intel. 8044AH/8344AH/8744H HIGH PERFORMANCE 8-BIT MICROCONTROLLER WITH ON-CHIP SERIAL COMMUNICATION CONTROLLER = 8044AH—Includes Factory Mask Programmable ROM = 8344AH—For Use with External Program Memory = 8744H—Includes User Programmable/Eraseable EPROM

8051 MICROCONTROLLER CORE SERIAL INTERFACE UNIT (SIU)

@ Optimized for Real Time Control 12 @ Serial Communication Processor that MHz Clock, Priority Interrupts, 32 Operates Concurrently to CPU Programmable I/O Lines, Two 16-bit Timer/Counters . ne eee ona ne ocked @ Boolean Processor . Loop bps using On-Chip Phase L m 4K X 6 ROM, 192 x 8 RAM Communication Software in Silicon: @ 64K Accessible External Program — Complete Data Link Functions Memory — Automatic Station Response @ 64K Accessible External Data Memory @ Operates as an SDLC Primary or = 41s Multiply and Divide Secondary Station The RUPI-44 family integrates a high performance 8-bit Microcontroller, the Intel 8051 Core, with an Intelli- gent/high performance HDLC/SDLC serial communication controller, called the Serial Interface Unit (SIU). See Figure 1. This dual architecture allows complex control and high speed data communication functions to be realized cost effectively. Specifically, the 8044's Microcontroller features: 4K byte On-Chip program memory space; 32 1/0 lines; two 16-bit timer/event counters; a 5-source; 2-level interrupt structure; a full duplex serial channel; a Boolean Processor; and on-chip oscillator and clock circuitry. Standard TTL and most byte-oriented MCS-80 and MCS- 85 peripherals can be used for I/O amd memory expansion. The Serial Interface Unit (SIU) manages the interface to a high speed serial link. The SIU offloads the On-Chip 8051 Microcontroller of communication tasks, thereby freeing the CPU to concentrate on real time contro! tasks. The RUPI-44 family consists of the 8044, 8744, and 8344. Alll three devices are identical except in respect of on-chip program memory. The 8044 contains 4K bytes of mask-programmable ROM. User programmable EPROM replaces ROM in the 8744. The 8344 addresses all program memory externally. The RUPI-44 devices are fabricated with Intel’s reliable +5 volt, silicon-gate HMOSII technology and pack- aged in a 40-pin DIP. The 8744H is available in a hermetically sealed, ceramic, 40-lead dual in-line package which includes a window that allows for EPROM erasure when exposed to ultraviolet light (See Erasure Characteristics). During normal operation, ambient light may adversely affect the functionality of the chip. Therefore applications which expose the 8744H to ambient light may require an opaque label over the window. 8044's Dual Controller Architecture Control ines BT HoLe/ controller port (231663-1 ; : Figure 1. Dual Controller Architecture October 1994 Order Number: 251663-004 5-19 @™§ 4826175 01640020 980

Table 1. RUPI-44 Family Pin Description Circuit ground potential. output. In loop mode, it serves as transmit pin. +5V power supply during operation and program input for counter 0. PORT 0 — TO (P3.4). Input to counter 0. for data output during program verification. Port 0 fal clock) input. Port 1 is an 8-bit quasi-bidirectional 1/O port. It is ternal Data Memory to Port 0. gram verification. Port 1 can sink/source four LS. dicates that the RUPI-44 is ready to transmit. (= 10yf) is also connected from this pin to Veo. dress and the control signals during program verifi- Programming the EPROM version. cation, Port 2 can sink/source four LS TTL loads. must be programmed to a one (1) for that function during internal program execution.

Figure 4. Block Diagram ler to He a ae tansd pees Sealy pei © two fully programmable 16-bit timer/counters. replaces the 8051's serial interface with an intelli vrs.

622 M™ 4826175 0164005 LIT

Memory space is subdivided into a 256-byte internal whether or not the serial channel is used.

Port 0 and Port 2 become the means by which the

icates with external program memory.

The stack can be located anywhere in the Inter- _ripherals can be memory mapped into the address

dress space are filled with on-chip RAM. Table 2. MCS®-51 instruction Set Description

Table 2. MCS®-51 Instruction Set Description (Continued)

to the execution of any particular section of code. To control. generated after address 191 is reached.

8 REGISTER 8 [247 through 240] 240 (Fon)

STATUS REGISTER ‘STs [207 through 200 200 (CBM). Figure 5. Mapping of Special Function Registers

With the addition of only a few bytes of code, the —_ lowing responses without CPU intervention: | (Infor- 8044's frame size is not limited to the size of its mation), RR (Receive Ready), and RNR (Receive internal RAM (192 bytes), but rather by the size of Not Ready). external buffer with no degradation of the RUPI's features (e.g. NRZI, zero bit insertion/deletion, ad-_ When the Receive Butfer Empty bit (RBE) indicates dress recognition, cyclic redundancy check). There _that the Receive Buffer is empty, the receiver is en- is a special function register called SIUST whose _abled, and when the RBE bit indicates that the Re- contents dictates the operation of the SIU. At low ceive Buffer is full, the receiver is disabled. Assum- data rates, one section of the SIU (the Byte Proces- _ing that the Receiver Butfer is empty, the SIU will sor) performs no function during known intervals. respond to a poll with an | frame if the Transmit Buff For a given data rate, these intervals (stand-by —_eris full. If the Transmit Buffer is empty, the SIU will mode) are fixed. The above characteristics make it respond to a polll with a RR command if the Receive possible to program the CPU to move data to/from Buffer Protect bit (RBP) is cleared, or an RNR com- external RAM and to force the SIU to perform some mand if RBP is set. desired hardware tasks while transmission or recep- tion is taking place. With these modifications, exter- nal RAM can be utilized as a transmit and received = FLEXIBLE (or NON-AUTO) Mode buffer instead of the internal RAM. In the FLEXIBLE mode all communications are un- der control of the CPU. It is the CPU's task to en- AUTO Mode code and decode control fields, manage acknowl- ‘edgements, and adhere to the requirements of the In the AUTO mode the SIU implements in hardware HDLC/SDLC protocols. The 8044 can be used as a a subset of the SDLC protocol such that it responds —_ primary or a secondary station in this mode. to many SDLC frames without CPU intervention. All AUTO mode responses to the primary station will —_To receive a frame in the FLEXIBLE mode, the CPU comform to IBM's SDLC definition. The advantages must load the Receive Buffer Start register, the Re- of the AUTO mode are that less software is required _—_ceive Buffer Length register, clear the Receive Butt- to implement a secondary station, and the hardware _er Protect bit, and set the Receive Buffer Emply bit. generated response to polls is much faster than do- If a valid opening flag is received and the address ing it in software. However, the Auto mode can not _field matches the byte in the Station Address regis- be used at a primary station. ter or the address field contains a broadcast ad- dress, the 8044 loads the control field in the receive To transmit in the AUTO mode the CPU must load —_control byte register, and loads the | field in the re- the Transmit Information Buffer, Transmit Buffer ceive buffer. If there is no CRC error, the SIU inter- Start register, Transmit Buffer Length register, and __rupts the CPU, indicating a frame has just been re- set the Transmit Buffer Full bit. The SIU automatical- ceived. If there is a CRC error, no interrupt occurs. ly responds to a poll by transmitting an information _The Receive Field Length register provides the num- frame with the P/F bit in the control field set. When _ber of bytes that were received in the information the SIU receives a positive acknowledgement from field. the primary station, it automatically increments the Ne field in the NSNR register and interrupts the To transmit a frame, the CPU must load the transmit CPU. A negative acknowledgement would cause the _ information buffer, the Transmit Buffer Start register, SIU to retransmit the frame. the Transmit Buffer Length register, the Transmit Control Byte, and set the TBF and the RTS bit. The To raceive in the AUTO mode, the CPU loads the _SIU, unsolicited by an HDLC/SDLC frame, will trans- Receive Buffer Start register, the Receive Buffer mit the entire information frame, and interrupt the Length register, clears the Receive Buffer Protect CPU, indicating the completion of transmission. For bit, and sets the Receive Buffer Empty bit. Ifthe SIU supervisory frames or unnumbered frames, the is polled in this state, and the TBF bit indicates that _ transmit butfer length would be 0. the Transmit Buffer is empty, an automatic RR re- sponse will be generated. When a valid information frame is received the SIU will automatically incre- CRC ment Nr in the NSNR register and interrupt the CPU. The FCS register is initially set to all 1’s prior to cal- While in the AUTO mode the SIU can recognize and culating the FCS field. The SIU will not interrupt the respond to the following commands without GPU in- CPU if a CRC error occurs (in both AUTO and FLEX: tervention: | (Information), RR (Receive Ready), IBLE modes). The CRC error is cleared upon receiv- RNA (Receive Not Ready), REJ (Reject), and UP ing of an opening flag. (Unnumbered Poll). The SIU can generate the fol- 5:28 wm 4826475 0164011 993 mm |

will incorporate the control or address bytes andthe _—register and the Status register. : becomes Address mode select. Figure 7. Frame Format Options

8044AH/8344AH/8744H | ntel ° Extended Addressing Brivis and receive data in this mode at rates up to .4 Mbps. To realize an extended control field or an extended address field using the HDLC protocol, the FLEX- This self clocked mode allows data transfer without IBLE mode must be used. For an extended control a common system data clock. An on-chip Digital field, the SIU is programmed to be in the non-butt- Phase Locked Loop is employed to recover the data ered mode. The extended control field will be the clock which is encoded in the data stream. The first and second bytes in the Receive and Transmit DPLL will converge to the nominal bit center within Buffers. For extended addressing the SIU is placed eight bit transitions, worst case. The DPLL requires a in the non-addressed mode. In this mode the CPU reference clock of either 16 times (16x) or 32 times must implement the address recognition for received (32x) the data rate. This reference clock may be ex- frames. The addressing field will be the initial bytes ternally applied or internally generated. When inter- in the Transmit and Receive buffers followed by the nally generated either the 8044’s internal logic clock contro! field. (crystal frequency divided by two) or the timer 1 overflow is used as the reference clock. Using the The SIU can transmit and receive only frames which internal timer 1 clock the data rates can vary from are multiples of 8 bits. For frames received with oth- 244 to 62.5 Kbps. Using the internal logic clock at a er than 8-bit multiples, a CRC error will cause the 16x sampling rate, receive data can either be 187.5 SIU to reject the frame. Kbps, or 375 Kbps. When the reference clock for the DPLL is externally applied the data rates can vary from 0 to 375 Kbps at a 16x sampling rate. SDLC Loop Networks To aid in a Phase Locked Loop capture, the SIU has. The SIU can be used in an SDLC loop as a second- a NRZI (Non Return to Zero inverted) data encoding ary or primary station. When the SIU is placed in the and decoding option. Additionally the SIU has a pre- Loop mode it receives the data on pin 10 and trans- frame sync option that transmits two bytes of alter- mits the data one bit time delayed on pin 11. It can nating 1's and 0's to ensure that the receive station also recognize the Go ahead signal and change it DPLL will be synchronized with the data by the time into a flag when it is ready to transmit. As a second- _it receives the opening flag. ary station the SIU can be used in the AUTO or FLEXIBLE modes. As a primary station the FLEX- IBLE mode is used; however, additional hardware is Control and Status Registers required for generating the Go Ahead bit pattern. In the Loop mode the maximum data rate is 1 Mbps There are three SIU Control and Status Registers: clocked or 375 Kpbs self-clocked. Serial Mode Register (SMD) Status/Command Register (STS) SDLC Multidrop Networks Send/Receive Count Register (NSNR) The SIU can be used in a SDLC non-loop configura- The SMD, STS, and NSNR, registers are all cleared tion as a secondary or primary station. When the SIU by system reset. This assures that the SIU will power is placed in the non-loop mode, data is received and up in an idle state (neither receiving nor transmit- transmitted on pin 11, and pin 10 drives a tri-state ting). buffer. In non-loop mode, modem interface pins, RTS and CTS, become available. These registers and their bit assignments are de- scribed below. Data Clocking Options SMD: Serial Mode Register (byte-addressable) The 8044's serial port can operate in an externally -Bit7: 6 5 4 3 2 14 0 clocked or self clocked system. A clocked system — feciaz] scm] SCMO] [LooP]Prs]NB|NFCS] provides to the 8044 a clock synchronization to the [SCM2|SCM1|SCMO| [nazi[Loor|Prs|Ne|NFos data. A self-clocked system uses the 8044's on-chip Digital Phase Locked Loop (DPLL) to recover the The Serial Mode Register (Address C9H) selects the clock from the data, and clock this data into the Seri- operational modes of the SIU. The 8044 CPU can al Receive Shift Register. both read and write SMD. The SIU can read SMD but cannot write to it. To prevent conflict between In this mode, a clock synchronized with the data is CPU and SIU access to SMD, the CPU should write externally fed into the 8044. This clock may be gen- SMD only when the Request To Send (RTS) and erated from an External Phase Locked Loop, or pos- sibly supplied along with the data. The 8044 can 5-30 WB 4826175 0164013 7bb ml

intel ° 8044AH/8344AH/8744H Receive Buffer Empty (RBE) bits (in the STS regis- CPU, and enables the SIU to post status information ter) are both false (0). Normally, SMD is accessed —_for the CPU’s access. The SIU can read STS, and only during initialization. can alter certain bits, as indicated below. The CPU can both read and write STS asynchronously. How- The individual bits of the Serial Mode Register are as ever, 2-cycle instructions that access STS during follows: both cycles (‘JBC/B, REL’ and ‘MOV/B, C.’) should not be used, since the SIU may write to STS be- [Bue [Wane [Desciption | _tWeen the two CPU accesses, [SMD.0 | NFCS | No FCS field in the SDLC frame._| The individual bits of the Status/Command Register Non-Buffered mode. No control are as follows: field in the SDLC frame. PFS | Pre-Frame Sync mode. In this [Bite [Name] Description mode, the 8044 transmits two STS.0| REP | Receive Buffer Protect. Inhibits bytes before the first flag of a wwiting of data into the receive frame, for DPLL synchronization. butfer In AUTO mode, REP If NRZI is enabled, OOH is sent; forces an RNR response instead otherwise, 55H is sent. In either ofan RR. Cases epretrame transitions are | rstsi TAM | AUTO Mode/Addressed Mode. = Selects AUTO mode where [SMD.3| LOOP] Loop configuration, | AUTO mode is allowed. f NB is SMD.4 NRZI coding option. If bit = 1, true, (= 1), the AM bit selects the NRZI coding is used. If bit = 0, addressed mode. AM may be then itis straight binary (NRZ). cleared by the SIU. | SMD.5 | SCMO | Select Clock Mode—Bit 0 sts.2|OPB | Optional Poll Bit. Determines [SMD.6 | SCM1 | Select Clock Mode—Bit 1 whether the SIV will generate an Select Glock Mode—Bit 2 poll (UP with P = 0), OPMmay ; be set or cleared by the SIU. The SCM bits decode as follows: ST8.3 | BOV | Receive Buffer Overrun. BOV may be set or cleared by the SIU. | [4] [_scm_| Data Rate STs4 SIU Interrupt. This is one of the [2 1 0| Clock Mode (Bits/sec)* five interrupt sources to the CPU. [Extomaly cocked o2ane> | The vector ocaion = 23H | Jo 0 0| Externally clocked 0-2.4M' May Eo tat Op the SIU. R shor [oo s[Resoved | be cleared by the CPU before | _1 0] Seif clocked, timer overflow | 244-62.5K_| returning from an interrupt for afReseves | rutin. STS.5|RTS | Request To Send. indicates that Ho tfeotascecoereta [eer] th eden rapa [10 1] Self clocked, external 32x _| 0-187.5K transmitting. RTS may be read or written by the CPU. RTS may be | Self clocked, internal fixed | 167.5K read by the SIU, and in AUTO [1 1 1] Self clocked, internal fixed | 187.5K ‘rode tney be witton by the SIU. NOTES: STS6 Receive Buffer Empty. RBE can (Based on a 12 Mhz crystal frequency be thought of as Receive Enable. ‘0-1 M bps in loop configuration RBE is set to one by the CPU when it is ready to receive a 7 - frame, or has just read the buffer, sts: 4 Register (bit- and to zero by the SIU when a uidreseabe) gg 2 1 frame has been received. $T8.7| TBF | Transmit Butfer Full. Written by [ABE [si] [aw the CPU to indicate that it has filled the transmit buffer. TBF may The Status/Command Register (Address C8H) pro- vides operational control of the SIU by the 8044 be cleared by the SIU. I ME 4826175 0164014 LT2 a 531

8044AH/8344AH/8744H | ntel ° NSNR: Send/Receive Count Register (bit- ‘TBS: Transmit Buffer Start Address Register addressable) (byte-addressable) it: 7 5 4 3 2 1 0 Bit 6 The Transmit Butter Start address register (Address [Ns2[Nsi]Nso] ses[NR2[NA1]NRO]SER] DCH) points to the location in on-chip RAM for the beginning of the I-field of the frame to be transmit. The Send/Receive Count Register (Address D8H) _ted. The CPU should access TBS only when the SIU contains the transmit and receive sequence num- _‘$ Not transmitting a frame (when TBF = 0). bers, plus tally error indications. The SIU can both read and write NSNR. The 8044 CPU can both read : and write NSNR asynchronously. However, 2cyclo aye“ nagreaeatio) en eo instructions that access NSNR during both cycles (JBC /8, REL,’ and ‘MOV /8,C’) should not be The Transmit Buffer Length register (Address DBH) used, since the SIU may write to NSMR between the contains the length (in bytes) of the |-field to be two 8044 CPU accesses. transmitted. A blank |-field (TBL = 0) is valid. The CPU should access TBL only when the SIU is not The individual bits of the Send/Receive Count Reg- transmitting a frame (when TBF = 0). ister are as follows: a wore [bite [Name|Description The transmit and receive buffers are not allowed to Receive Sequence Error: “wrap around” in the on-chip RAM. A “butfer end” NS (P) * NAS) is automatically generated if address 191 (BFH) is [NSNR.1/NFO [Receive Sequence Counter—Bito| “ached [NSNR.2|NR1_ [Receive Sequence Counter—Bit 1 TCB: Transmit Control Byte Register [NSNR.3|NR2_| Receive Sequence Counter—Bit 2| __(byte-addressable) NSNR4 ‘Send Sequence Error: The Transmit Control Byte register (Address DAH) NR (P) + NS (S) and contains the byte which is to be placed in the control NR (P) + NS(S) +1 field of the transmitted frame, during NON-AUTO - mode transmission. The GPU should access TCB [NSNR.5|NSO_ | Send Sequence Counter—Bit 0 only when the SIU is not transmitting a frame (when [NSNR.6|NS1_ | Send Sequence Counter—Bit 1 TBF = 0). The Ngand Np counters are not used in - the NON-AUTO mode. NSNR.7|NS2_ | Send Sequence Counter—Bit 2 RBS: Receive Butfer Start Address Register Parameter Registers (byte-addressable) , . _ The Receive Butfer Start address register (Address There are eight parameter registers that are used in CCH) points to the location in on-chip RAM where connection with SIU operation. All eight registers the beginning of the I-ield of the frame being ro. may be read or written by the 8044 CPU. FFL and — Guivedds te be stored, The CPU should write RBS RCB are normally loaded by the SIU. only when the SIU is not receiving a frame (when The eight parameter registers are as follows: ABE = 0}. RBL: Receive Butter Length Register STAD: Station Address Register (byte-addressable) (oyte ackdressable) ’ , Tho Receive Butfer Length register (Address CBH) The Station Address register (Address CEH) con- contains the length (in bytes) of the area in on-chip tains the station address. To prevent acess conflict. RAM allocated for the recewed fisid, PBL =O fo the CPU should access STAD only when the SIU is i ; 2 Whe RTS Od RSE OF Nommaly, STAD ig Valid: The CPU should write RBL only when RBE=0. accessed only during initialization,

502 ME 4826175 OLG4O1S 539 WM )

| ntel ° 8044AH/8344AH/8744H RFL: Receive Field Length Register The emulator operates with Intel's Intellec develop- (byte-addreseable) ment system. The development system interfaces . with the user’s 8044 system through an in-cable The Receive Field’Length register (Address CDH) __ buffer box. The cable terminates in a 8044 pin-com- contains the length (in bytes) of the received I-field _patible plug, which fits into the 8044 socket in the that has just been loaded into on-chip RAM. RFL is _user’s system. With the emulator plug in place, the loaded by the SIU. RFL = 0 is valid. RFL should be —_user can excercise his system in real time while col- accessed by the CPU only when RBE = 0. lecting up to 255 instruction cycles of real-time data. In addition, he can single-step the program. RCB: Receive Control Byte Register Static RAM is available (in the in-cable buffer box) to (byte-addressable) emulate the 8044 internal and extemal program . F memory and external data memory. The designer The Received Control Byte register (Address CAH) Can Gioblay and alter the contente of the replace. contains the control field of the frame that has just Oise Fat ett be tho internel data been received. RCB is loaded by the SIU. The CPU ‘Ment Memory i & | 2044 registers: includ can only read ACB, and should only access ROB Peru, and ine internal registers, including when RBE = 0. 1e SFR's. SIUST: SIU State Counter (byte-addressable) ICE Support The SIU State Counter (Address D9H) reflects the The 8044 In-Circuit Emulator (ICE-44) allows the state of the internal logic which is under SIU control. user to exercise the 8044 application system and Therefore, care must be taken not to write into this monitor the execution of instructions in real time, register. This register provides a useful means for debugging 8044 receiver problem. | ME 4826175 OLb4O1lb 475 a 5-33

8044AH/8344AH/8744H intel ° ABSOLUTE MAXIMUM RATINGS* NOTICE: This is a production data sheet. The specifi- _ Z faximum Ratings" may cause permanent damage. issinati tended exposure beyond the “Operating Conditions” D.C. CHARACTERISTICS Tp = 0°C to 70°C, VOC = 5V ~ 10%, VSS = OV [symbol Parameter Min | Max [Unit] Test Coneitions Vii [input High Voltage to XTAL2, RST | 25 [voc + 06 XTAL = VSS Output Low Voltage (Ports 1, 2, 3)* [| 045 | v [tor =1.6ma Vout ouputow votape Poncauereem> [|_| | | o60 | v [I0L=32ma Bo4daH/esa4aH | | 0.45 | Vv [IOL=32mA Output High Voltage (Ports 1, 2, 3) [24 | |_v [IOH= ~80pa VOHt | Output High Voltage (Port 0 in External V [10H = —400 pa Bus Mode, ALE, PSEN) Logical 0 Input Current (Ports 1, 2, 3) [| —s00_| ua | vin = 0.45v mut Logical 0 Input Current to EA Pin mA of 8744H only ha [aga pa an OA [a0 oer IL) Input Leakage Current (Port 0) 8744H +100 | wa |0.45 < Vin < voc 8044AH/8344AH #10__| pA [0.45 < Vin < VOC [H1 | input Current to RST to Activate Reset [| 500 | wa [Vin < (voc ~ 1.5v) 1CC— | Power Supply Current: ‘All Outputs Discon- 8744H 285 | mA| nected: EA = VCC 8044AH/8344AH 200 | mA “NOTES: 1. Sampled not 100% tested. Ta = 25°C. 2. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports 1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pin when these pins make 1-to- 0 transitions during bus operations. In the worst cases (capacitive loading > 100 pF), the noise pulse on the ALE line may exceed 0.8V. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.

5.34 MB 4826175 0164017 30]

8044AH/8344AH/8744H i ntel ° EXTERNAL DATA MEMORY CHARACTERISTICS es es ‘Symbol 1/TCLCL = 3.5 MHz to 12 MHz [win [wx [win |x| [TAIRA [RoPusewan | woo | erase | i we | [wwe | WaPusewian [400 [| eroucuto0 | ——~id n| [wax [AssessHowaterae [ae || races |_| vs | [Tau [ROLowtovaieoaiain [| ase | _——*|aTeuGLes | ne | [reHox [ostanowaterRD [9 [| 9} re | [rruoz [Daa Fost anerRO [|e [| aTcu70 | ne | [ruby [ALEtowieveisbaam [| si7 [| ercucitso | ne | [Tavov | AdsessiovaisDawin [| ses || srocires | ne | [TuLw. [ALELowoRBorWRLow | a0 | e0o | arouse | eric.c.+s0 | ne | [Taw [AssessioADorWRiow | 200 | | aTaucwao | | ne | ewe (S| | wez | [el 8744H TCLCL-70 8044AH/8344AH TCLCL-60 [Town | OataSeup Seine WRHan | «oo |_| rruccsso |__| ve | [rw [OnaHesatorwR [ea || ractso | __— ne | [tnaz [RO lowionssessrion [| || | ms | RD or WR High to ALE High 8744H 133 TCLCL-50 TCLCL+50 NOTE: 1, TLLAX for access to program memory is different from TLLAX for access data memory. Serial Interface Characteristics [symbot|__Parametor [wm <a [Un [rocy [wack eos [roc [bata Gost tae | [toch [bata ook gn t00 fs | [0 | Transtontaouay [| |e [ss__[_baasouptine [afr [ons | oaatostine [0d 5-36 Me 4826175 0164019 164 =

intel. 8044AH/8344AH/8744H WAVEFORMS Memory Access PROGRAM MEMORY READ CYCLE me ‘am Moa qf | men ruax o——-|rPxav ravi. Lega on a 231663-8 DATA MEMORY READ CYCLE a vont 6: 6 a TRLAZ vomrz AROSE, ADDRESS ATEN OR GFAP maeea-e DATA MEMORY WRITE CYCLE sen . w I Medd Tait Toren ro onto 5 SD CO port: Sharer: 4 "ADDRESS A15-AG OR SFR-P2 | ] MH 4826175 0164020 9Tb 5.37

8044AH/8344AH/8744H I ntel ° SERIAL 1/O WAVEFORMS SYNCHRONOUS DATA TRANSMISSION Tocy Toot seux TOCH ara 291669-11 SYNCHRONOUS DATA RECEPTION Tocy — ret seux TOCH pata Toss TOHS 2an6e9—12 5-38 MH 4826175 0164021 632 Me |

intel ° 8044AH/8344AH/8744H AC TESTING INPUT, OUTPUT, FLOAT WAVEFORMS INPUT/OUTPUT FLOAT

3 Fuoar

INTERNAL | stave 4 | stare s | s-ares | stares | stare2 | stares | stares | STATES | crock prfezter|re tortor | orl ez} er|ez| or] e2| rr | 2 | | pe me TULL apn np we oF Lis L__f — _—— THESE SIGNALS ARE NOT EXTERNAL PROGRAM MEMORY FETCH ACTIVATED DURING THE al EXECUTION OF A MOVK INSTRUCTION i5EN | een AS | PO Joaral PCL OUT DATA PCL OUT Ioaral PCLOUT l TAMPLED SAMPLED Loar +4 L__promrne? -— nar puext) _______[TNOIGATESADORESSTRANGIONS | f READ CYCLE rs es OOH IS EMITTED PCL OUT (If PROGRAM |_ DURING THIS PERIOD _ MEMORY IS EXTERNAL) OPLORAT p po —__I_ noice OPH ORP2 SFATO PCH TRANSITIONS LU waite cycLe i A TT MEMORY IS INTERNAL) vo ["oPLonm | i our he pata ouT- PCL OUT (IF PROGRAM P2 a | INDICATES DPH OR P2 SFR TO PCH TRANSITIONS [MEMORY IS EXT 1S EXTERNAL) PORT OPERATION MOV PORT, SAC. ‘oo para [NEW DATA PO PINS SAMPLED MoV 0€ST. 0 Fa FA MOV DEST, PORT (P1. P2.P3) PO PINS SAMPLED ncLUDES Te INTH ToT Fey Fal ‘1, P2. P3 PINS SAMPLED PA. P2, Po SERIAL PORT SHIFT CLOCK PINS SAMPLED TxD bf a (ODE oy AKO SAMPLED xD SAMPLED 231669-16 This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins, however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as tempera- ture and pin loading. Propagation also varies from output to output and component to component. Typically though, (Ta = 25°C, fully loaded) RD and WR propagation delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC specifications. 5-40 MH 4826175 0164023 bOS mw

intel ° 8044AH/8344AH/8744H 8744H EPROM CHARACTERISTICS ure 8, Detailed timing specifications are provided in the EPROM Programming and Verification Charac- teristics section of this data sheet. Erasure Characteristics Erasure of the 8744H Program Memory begins to. Program Memory Security ‘occur when the chip is exposed to light with wave- lengths shorter than approximately 4,000 Ang- The program memory security feature is developed stroms. Since sunlight and fluorescent lighting have around a "security bit” in the 8744H EPROM array. wavelengths in this range, canstant exposure to Once this “hidden bit” is programmed, electrical ac- these light sources over an extended period of time cess to the contents of the entire program memory (about 1 week in sunlight, or 3 years in room-level__—_ array becomes impossible. Activation of this feature fluorescent lighting) could cause unintentional era- is accomplished by programming the 8744H as de- sure. If an application subjects the 8744H to this _scribed in “Programming the EPROM” with the ex- type of exposure, it is suggested that an opaque la- ception that P2.6 is held at a TTL high rather than a bel be placed over the window. TTL low. In addition, Port 1 and P2.0-P2.3 may be in any state. Figure 9 illustrates the security bit pro- The recommended erasure procedure is exposure © gramming configuration. Deactivating the security to ultraviolet light (at 2537 Angstroms) to an integrat- feature, which again allows programmability of the ed dose of at least 15 W-sec/cmé rating for 20 to 30 EPROM, is accomplished by exposing the EPROM minutes, at a distance of about 1 inch, should be —_to ultraviolet light. This exposure, as described in sufficient. “Erasure Characteristics,” erases the entire EPROM array. Therefore, attempted retrieval of “protected Erasure leaves the array in an all 1s state. code" results in its destruction. Programming the EPROM Program Verification To be programmed, the 8744H must be running with Program Memory may be read only when the “‘secu- a 4 to 6 MHz oscillator. (The reason the oscillator _ity feature” has not been activated. Refer to Figure needs to be running is that the internal bus is being _—-10 for Program Verification setup. To read the Pro- used to transfer address and program data to appro- gram Memory, the following procedure can be used. priate registers.) The address of an EPROM location _—_The unit must be running with a 4 to 6 MHz oscilla to be programmed is applied to Port 1 and pins P2.0- tor. The address of a Program Memory location to P2.3 of Port 2, while the data byte is applied to Port ‘be read is applied to Port 1_and pins P2.0-P2.3 of P27 and RST high. (These are all TTL levels except _low, while the ALE/PROG, RST, and EA/VPP pins RST, which requires 2.5V for high.) EA/VPP is held are held at TTL high. (These are all TTL levels ex- normally high, and is pulsed to +21V. While EA/ cept RST, which requires 2.5V for high.) Port 0 will VPP is at 21V, the ALE/PROG pin, which is normally _be the data output lines. P2.7 can be used as a read being held high, is pulsed low for 50 msec. Then _ strobe. While P2.7 is held high, the Port 0 pins float. EA/VPP is returned to high. This is illustrated in Fig- | When P2.7 is strobed low, the contents of the ad- dressed location will appear at Port 0. External pull- ups (e.g., 10K) are required on Port 0 during program verification. MB 4826175 O1b4024 54, ml 541

Figure 10. Program Verification Configuration

8044AH/8344AH/8744H intel ° EPROM PROGRAMMING, SECURITY BIT PROGRAMMING AND VERIFICATION WAVEFORMS PROGRAMMING VERIFICATION (P20-P2.3 { y . | = [rover | Fonox Taven TaHAX, ALE PROG Tsuot ToHst ———lFeren av sv TILHGH TIL HIGH TTL Mic TILKIGH EXvep P27 a a (ENABLE) 291089-20 5-44 M™ 4826175 Olb402? 250

Product Information

8744AH specifications and overview.

Summary

HIGH PERFORMANCE 8 BIT MICROCONTROLLER WITH ON CHIP SERIAL COMMUNICATION CONTROLLER

Description

HIGH PERFORMANCE 8 BIT MICROCONTROLLER WITH ON CHIP SERIAL COMMUNICATION CONTROLLER

Source title 8744AH Datasheet(PDF) - Intel Corporation

Related Parts

More parts from the same family.

Browse manufacturer