November 1991 Order Number: 290256-001
Document overview
- PDF pages: 12
Technical content
memory, 128 bytes of data memory, 8-bit timer/counter, and clock generator in a single 40-pin package. complex motor control tasks, 80-column printers and process control applications as examples. Figure 1. Pin Configuration
Figure 2. Block Diagram
Table 1. Pin Description RESET 4I RESET: Input used to reset status flip-flops and to set the program counter to zero. RESET is also used during EPROM programming and verification. program through each instruction (EPROM). This should be tied to a5V when not used. connected to a common data bus. verification. This pin should be tied low if unused. the OUTPUT DATA BUS BUFFER or status register. during program and verify operations. to the UPI INPUT DATA BUS BUFFER. microcomputer to an 8-bit master system data bus. P10 –P17 27–34 I/O PORT 1: 8-bit, PORT 1 quasi-bidirectional I/O lines. (DRQ), and P 27 as DMA ACKnowledge (DACK ). PROG 25 I/O PROGRAM: Multifunction pin used as the program pulse input during PROM programming. During I/O expander access the PROG pin acts as an address/data strobe to the 8243. This pin should be tied high if unused. VCC 40 POWER: a5V main power supply pin. VSS 20 GROUND: Circuit ground potential.
- Two Data Bus Buffers, one for input and one for output. This allows a much cleaner Master/Slave protocol. 290256–3 2. 8 Bits of Status ST7 ST6 ST5 ST4 F1 F0 IBF OBF D7 D6 D5 D4 D3 D2 D1 D0 ST4 –ST7 are user definable status bits. These bits are defined by the ‘‘MOV STS, A’’ single byte, single cycle instruction. Bits 4–7 of the acccumu- lator are moved to bits 4–7 of the status register. Bits 0–3 of the status register are not affected. MOV STS, A Op Code: 90H 1 001000 0 D7 D0 3. RD and WR are edge triggered. IBF, OBF, F 1 and INT change internally after the trailing edge of RD or WR . 290256–4 During the time that the host CPU is reading the status register, the 8742 is prevented from updat- ing this register or is ‘‘locked out’’. 4. P 24 and P 25 are port pins or Buffer Flag pins which can be used to interrupt a master proces- sor. These pins default to port pins on Reset. If the ‘‘EN FLAGS’’ instruction has been execut- ed, P 24 becomes the OBF (Output Buffer Full) pin. A ‘‘1’’ written to P 24 enables the OBF pin (the pin outputs the OBF Status Bit). A ‘‘0’’ written to P 24 disables the OBF pin (the pin remains low). This pin can be used to indicate that valid data is avail- able from the UPI-41A (in Output Data Bus Buff- er). If ‘‘EN FLAGS’’ has been executed, P 25 becomes the IBF (Input Buffer Full) pin. A ‘‘1’’ written to P 25 enables the IBF pin (the pin outputs the inverse of the IBF Status Bit. A ‘‘0’’ written to P 25 disables the IBF pin (the pin remains low). This pin can be used to indicate that the UPI is ready for data. 290256–5 Data Bus Buffer Interrupt Capability EN FLAGS Op Code: 0F5H 1 111010 1 D7 D0 5. P26 and P 27 are port pins or DMA handshake pins for use with a DMA controller. These pins default to port pins on Reset. If the ‘‘EN DMA’’ instruction has been executed, P 26 becomes the DRQ (DMA Request) pin. A ‘‘1’’ written to P 26 causes a DMA request (DRQ is acti- vated). DRQ is deactivated by DACK #RD, DACK#WR, or execution of the ‘‘EN DMA’’ in- struction. If ‘‘EN DMA’’ has been executed, P 27 becomes the DACK (DMA Acknowledge) pin. This pin acts as a chip select input for the Data Bus Buffer reg- isters during DMA transfers. 290256–6 DMA Handshake Capability EN DMA Op Code: 0E5H 1 110010 1 D7 D0 6. The RESET input on the 8742, includes a 2-stage synchronizer to support reliable reset operation for 12 MHz operation. 7. When EA is enabled on the 8742, the program counter is placed on Port 1 and the lower three bits of Port 2 (MSB e P22, LSB e P10). On the 8742 this information is multiplexed with PORT DATA (see port timing diagrams at end of this data sheet).
PROGRAMMING, VERIFYING, AND ERASING THE 8742 EPROM Programming Verification In brief, the programming process consists of: acti- vating the program mode, applying an address, latching the address, applying data, and applying a programming pulse. Each word is programmed com- pletely before moving on to the next and is followed by a verification step. The following is a list of the pins used for programming and a description of their functions: Pin Function XTAL 1 Clock-Input Reset Initialization and Address Latching Test 0 Selection of Program or Verify Mode EA Activation of Program/Verify Modes BUS Address and Data Input Data Output During Verify P20–12 Address Input VDD Programming Power Supply PROG Program Pulse Input WARNING An attempt to program a missocketed 8742 will result in severe dam- age to the part. An indication of a properly socketed part is the ap- pearance of the SYNC clock output. The lack of this clock may be used to disable the programmer. The Program/Verify sequence is: 1. A 0 e 0V, CS e 5V, EA e 5V, RESET e 0V, TESTO e 5V, V DD e 5V, clock applied or inter- nal oscillator operating, BUS floating, PROG e 5V. 2. Insert 8742 in programming socket 3. TEST 0 e 0V (select program mode) 4. EA e 18V (active program mode) 5. Address applied to BUS and P 20–22 6. RESET e 5V (latch address) 7. Data applied to BUS ** 8. V DD e 21V (programming power) 9. PROG e VCC followed by one 50 ms pulse to 18V 10. V DD e 5V 11.TEST 0 e 5V (verify mode) 12. Read and verify data on BUS 13. TEST 0 e 0V 14. RESET e 0V and repeat from step 5 15. Programmer should be at conditions of step 1 when 8742 is removed from socket
8742 Erasure Characteristics
The erasure characteristics of the 8742 are such that erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 Angstroms ( Ð). It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000-4000 Ð range. Data shows that constant exposure to room level fluorescent lighting could erase the typical 8742 in approximately 3 years while it would take approximately one week to cause erasure when exposed to direct sunlight. If the 8742 is to be exposed to these types of lighting conditions for extended periods of time, opaque labels are available from Intel which should be placed over the 8742 window to prevent unintentional erasure. The recommended erasure procedure for the 8742 is exposure to shortwave ultraviolet light which has a wavelength of 2537 Ð. The integrated dose (i.e., UV intensity c exposure time) for erasure should be a minimum of 15 w-sec/cm 2. The erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with a 12,000 mW/cm 2 power rat- ing. The 8742 should be placed within one inch of the lamp tubes during erasure. Some lamps have a filter on their tubes which should be removed before erasure.
ABSOLUTE MAXIMUM RATINGS * Ambient Temperature Under Bias ÀÀÀÀÀÀ0 §Ct o7 0 §C Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b65§Ct o a150§C Voltage on Any Pin With Respect to Ground ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b0.5 to a7V Power DissipationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5W NOTICE: This is a production data sheet. The specifi- cations are subject to change without notice. *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability. D.C. CHARACTERISTICS TA e 0§ to a70§C, V CC e VDD ea 5V g10% Symbol Parameter 8742 Units Test Min Max Conditions VIL Input Low Voltage (Except XTAL1, XTAL2, RESET) b0.5 0.8 V VIL1 Input Low Voltage (XTAL1, XTAL2, RESET) b0.5 0.6 V VIH Input High Voltage (Except XTAL1, XTAL2, RESET) 2.0 V CC V VIH1 Input High Voltage (XTLA1, XTAL2, RESET) 3.5 V CC V VOL Output Low Voltage (D 0 –D7) 0.45 V I OL e 2.0 mA VOL1 Output Low Voltage (P 10 –P17,P 20 –P27, Sync) 0.45 V I OL e 1.6 mA VOL2 Output Low Voltage (PROG) 0.45 V I OL e 1.0 mA VOH Output High Voltage (D 0 –D7) 2.4 V I OH eb 400 mA VOH1 Output High Voltage (All Other Outupts) 2.4 I OH eb 50 mA IIL Input Leakage Current (T 0,T 1, RD, WR, CS, A 0, EA) g10 mAV SS s VIN s VCC IOFL Output Leakage Current (D 0 –D7, High Z State) g10 mA VSS a0.45 sVOUTsVCC ILI Low Input Load Current (P 10 –P17,P 20 –P27) 0.3 mA V IL e 0.8V ILI1 Low Input Load Current (RESET, SS) 0.2 mA V IL e 0.8V IDD VDD Supply Current 10 mA Typical e 5m A ICC a IDD Total Supply Current 125 mA Typical e 60 mA IIH Input Leakage Current (P 10 –P17,P 20 –P27) 100 mAV IN e VCC CIN Input Capacitance 10 pF C10 I/O Capacitance 20 pF D.C. CHARACTERISTICSÐPROGRAMMING TA e 25§C g5§C, V CC e 5V g5%, V DD e 21V g0.5V Symbol Parameter Min Max Units Test Conditions VDOH VDD Program Voltage High Level 20.5 21.5 V VDDL VDD Voltage Low Level 4.75 5.25 V VPH PROG Program Voltage High Level 17.5 18.5 V VPL PROG Voltage Low Level V CCb0.5 V CC V VEAH EA Program or Verify Voltage High Level 17.5 18.5 V VEAL EA Voltage Low Level 5.25 V IDD VDD High Voltage Supply Current 30.0 mA IPROG PROG High Voltage Supply Current 1.0 mA IEA EA High Voltage Supply Current 1.0 mA
A.C. CHARACTERISTICS TA e 0§Ct o a70§C, V SS e 0V, V CC e VDD ea 5V g10% DBB READ Symbol Parameter 8742 Units Min Max tAR CS, A 0 Setup to RD v 0n s tRA CS, A 0 Hold after RD u 0n s tRR RD Pulse Width 160 ns tAD CS, A 0 to Data Out Delay 130 ns tRD RDvto Data Out Delay 130 ns tDF RDuto Data Float Delay 85 ns tCY Cycle Time 1.25 15 ms(1) DBB WRITE Symbol Parameter Min Max Units tAW CS, A 0 Setup to WR v 0n s tWA CS, A 0 Hold after WR u 0n s tWW WR Pulse Width 160 ns tDW Data Setup to WR u 130 ns tWD Data Hold after WR u 0n s NOTE: 1. T CY e 15/f(XTAL) A.C. CHARACTERISTICS TA e 25§C g5§C, V CC e 5V g5%, V DD ea 21V g0.5 PROGRAMMING Symbol Parameter Min Max Units Test Conditions tAW Address Setup Time to RESET u 4tCY tWA Address Hold Time after RESET u 4tCY tDW Data in Setup Time to PROG u 4tCY tWD Data in Hold Time after PROG v 4tCY tPH RESET Hold Time to Verify 4t CY tVDDW VDD Setup Time to PROG u 0 1.0 mS tVDDH VDD Hold Time after PROG u 0 1.0 mS tPW Program Pulse Width 50 60 mS tTW Test 0 Setup Time for Program Mode 4t CY tWT Test 0 Hold Time after Program Mode 4t CY tDO Test 0 to Data Out Delay 4t CY tWW RESET Pulse Width to Latch Address 4t CY tr,t f VDD and PROG Rise and Fall Times 0.5 2.0 ms tCY CPU Operation Cycle Time 4.0 ms tRE RESET Setup Time before EA u 4tCY NOTE: If TEST 0 is high, t DO can be triggered by RESET u.
A.C. CHARACTERISTICS DMA Symbol Parameter 8642/8742 Units Min Max tACC DACK to WR or RD 0 ns tCAC RD or WR to DACK 0 ns tACD DACK to Data Valid 130 ns tCRQ RD or WR to DRQ Cleared 100 ns (1) NOTE: 1. C L e 150 pF. A.C. CHARACTERISTICS PORT 2 TA e 0§Ct o a70§C, V CC ea 5V g10% Symbol Parameter f(t CY) 8742/8642(3) Units Min Max tCP Port Control Setup before Falling Edge of PROG 1/15 t CYb28 55 ns (1) tPC Port Control Hold after Falling Edge of PROG 1/10 t CY 125 ns (2) tPR PROG to Time P2 Input Must Be Valid 8/15 t CYb16 650 ns (1) tPF Input Data Hold Time 0 150 ns (2) tDP Output Data Setup Time 2/10 t CY 250 ns (1) tPD Output Data Hold Time 1/10 t CYb80 45 ns (2) tPP PROG Pulse Width 6/10 t CY 750 ns NOTES: 1. C L e 80 pF. 2. C L e 20 pF. 3. t CY e 1.25 ms. A.C. TESTING INPUT/OUTPUT WAVEFORM INPUT/OUTPUT 290256–11 A.C. TESTING LOAD CIRCUIT 290256–12 CRYSTAL OSCILLATOR MODE 290256–13 Crystal Series Resistance Should be k750 at 12 MHz; k180X at 3.6 MHz. DRIVING FROM EXTERNAL SOURCE 290256–14 Rise and Fall Times Should Not Exceed 20 ns. Resis- tors to V CC are Needed to Ensure V IH e 3.5V if TTL Circuitry is Used.
2q0LCÊ L C NOMINAL 45 H 20 pF 5.2 MHz CÊ e C a 3Cpp 2120 H 20 pF 3.2 MHz Cpp j 5p F – 1 0p F Pin-to-Pin Capacitance 290256–15 Each C Should be Approximately 20 pF, including Stray Capacitance. WAVEFORMS READ OPERATIONÐDATA BUS BUFFER REGISTER 290256–16 WRITE OPERATIONÐDATA BUS BUFFER REGISTER 290256–17 CLOCK TIMING 290256–23
COMBINATION PROGRAM/VERIFY MODE 290256–18 VERIFY MODE 290256–19 NOTES: 1. PROG must float if EA is low or EA is low or if TEST 0 e 5V. 2. A 0 must be held low (i.e., e 0V) during program/verify modes. 3. Test 0 must be held high. The 8742 EPROM can be programmed by the fol- lowing Intel products: 1. Universal PROM Programmer (UPP 103) periph- eral of the Intellec Development System with a UPP-549 Personality Card. 2. iUP-200/iUP-201 PROM Programmer with the iUP-F87/44 Personality Module.
WAVEFORMS (Continued) DMA 290256–20 PORT 2 290256–21 PORT TIMING DURING EXTERNAL ACCESS (EA) 290256–22 On the Rising Edge of SYNC and EA is Enabled, Port Data is Valid and can be Strobed on the Trailing Edge of Sync the Program Counter Contents are Available.