83C51FA

80C51FA INTEL | Alldatasheet

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*Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. February 1995COPYRIGHT © INTEL CORPORATION, 1995 Order Number: 270501-007 80C51FA/83C51FA EVENT-CONTROL CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER Automotive Y Extended Automotive Temperature Range b40§Ct o a125§C Ambient) Y High Performance CHMOS Process Y Three 16-Bit Timer/Counters Ð Timer 2 is an Up/Down Timer/Counter Y Programmable Counter Array with: Ð High Speed Output, Ð Compare/Capture, Ð Pulse Width Modulator, Ð Watchdog Timer Capabilities Y 8K On-Chip ROM Y 256 Bytes of On-Chip Data RAM Y Boolean Processor Y 32 Programmable I/O Lines Y 7 Interrupt Sources Y Programmable Serial Channel with: Ð Framing Error Detection Ð Automatic Address Recognition Y TTL and CMOS Compatible Logic Levels Y 64K External Program Memory Space Y 64K External Data Memory Space Y MCSÉ 51 Microcontroller Fully Compatible Instruction Set Y Power Saving Idle and Power Down Modes Y ONCE (On-Circuit Emulation) Mode Y Available in PLCC and PDIP Packages (See Packaging Specification, Order Ý231369) Y Available in 12 MHz and 16 MHz Versions MEMORY ORGANIZATION PROGRAM MEMORY: Up to 8 Kbytes of the program memory can reside in the on-chip ROM. In addition the device can address up to 64K of program memory external to the chip. DATA MEMORY: This microcontroller has a 25 6 x 8 on-chip RAM. In addition it can address up to 64 Kbytes of external data memory. The Intel 80C51FA/83C51FA is a single-chip control oriented microcontroller which is fabricated on Intel’s CHMOS III (83C51FA) ROM technology. For the remainder of this datasheet references to the ROMless (80C51FA) and ROM (83C51FA) versions will be denoted as 83C51FA. Being a member of the MCS É 51 microcontroller family, the 83C51FA uses the same powerful instruction set, has the same architecture, and is pin-for-pin compatible with the existing MCS 51 microcontroller products. The 83C51FA is an enhanced version of the 87C51. It’s added features make it an even more powerful microcontroller for applications that require Pulse Width Modulation, High Speed I/O, and up/down counting capabilities such as brake and traction control. It also has a more versatile serial channel that facilitates multi-processor communications. NOTICE: This datasheet contains information on products in full production. Specifications within this datasheet are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.

Figure 1. 83C51FA Block Diagram

Figure 2. MCS É 51 Microcontroller Product Family Nomenclature Table 1. Temperature Options

**Do not connect reserved pins. Diagrams are for pin reference only. Package sizes are not to scale. Figure 3. Pin Connections

Figure 5. External Clock Drive Configuration SFRs and the on-chip RAM to retain their values. and stabilize (normally less than 10 ms). writes to a port pin or to external memory. 2) Hold ALE low as RST is deactivated. operation is restored when a normal reset is applied. Table 2. Status of the External Pins during Idle and Power Down

AUTOMOTIVE 80C51FA/83C51FA ABSOLUTE MAXIMUM RATINGS * Ambient Temperature Under Bias ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b40§Ct o a125§C Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b65§Ct o a150§C Voltage on Any Other Pin to V SS ÀÀb0.5V to a6.5V IOL I/O PinÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ15 mA Power DissipationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5W (Based on PACKAGE heat transfer limitations, not device power consumption) Typical Junction Temperature (T J) ÀÀÀÀÀÀÀÀ a135§C (Based upon Ambient Temperature at a125§C) Typical Thermal Resistance Junction-to-Ambient ( iJA) PDIP ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ45 §C/W PLCCÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ46§C/W NOTICE: This is a production data sheet. The specifi- cations are subject to change without notice. *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability. DC CHARACTERISTICS: (TA eb 40§Ct o a125§C; V CC e 5V g10%; V SS e 0V) Symbol Parameter Min Typ Max Unit Test Conditions VIL Input Low Voltage b0.5 0.2 V CCb0.1 V VIL1 Input Low Voltage EA 0 0.2 V CCb0.3 V VIH Input High Voltage 0.2 V CCa0.9 V CCa0.5 V (Except XTAL2, RST, EA ) VIH1 Input High Voltage 0.7 V CC VCCa0.5 V (XTAL, RST) VOL Output Low Voltage 0.45 V I OL e 1.6 mA (1) (Ports 1, 2 and 3) VOL1 Output Low Voltage 0.45 V I OL e 20 (Port 0, ALE/PROG , PSEN )I OL e 3.2 mA (1) IOL e 7.0 mA VOH Output High Voltage 2.4 V I OH eb 60 mA (Ports 1, 2 and 3 ALE/PROG and PSEN ) 0.9 V CC VI OH eb 10 mA(2) VOH1 Output High Voltage 2.4 V I OH eb 800 mA (Port 0 in External Bus Mode) 0.9 V CC VI OH eb 80 mA(2) IIL Logical 0 Input Current b10 b50 mAV IN e 0.45V (Ports 1, 2 and 3) ILI Input leakage Current 0.02 g10 mAV IN e VIL or V IH (Port 0)

AUTOMOTIVE 80C51FA/83C51FA DC CHARACTERISTICS: (TA eb 40§Ct o a125§C; V CC e 5V g10%; V SS e 0V) (Continued) Symbol Parameter Min Typ Max Unit Test Conditions ITL Logical 1 to 0 Transition Current b265 b650 mAV IN e 2V (Ports 1, 2, and 3) RRST RST Pulldown Resistor 40 100 225 K X CIO Pin Capacitance 10 pF @1MHz, 25 §C ICC Power Supply Current: (Note 3) Running at 12 MHz (Figure 5) 40 mA Idle Mode at 12 MHz (Figure 5) 15 mA Power Down Mode (I PD) 150 mA NOTES: 1. Capacitive loading on Ports 0 and 2 may cause noise pulses to be superimposed on the V OLs of ALE and Ports 1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0 transitions during bus operations. In applications where capacitance loading exceeds 100 pFs, the noise pulse on the ALE signal may exceed 0.8V. In these cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an Address Latch with a Schmitt Trigger Strobe input. 2. Capacitive loading on Ports 0 and 2 cause the V OH on ALE and PSEN to drop below the 0.9 V CC specification when the address lines are stabilizing. 3. See Figures 6–9 for test conditions. Minimum V CC for Power Down is 2.0V. 4. Typicals are based on limited number of samples, and are not guaranteed. The values listed are at room temperature and 5.0V. 5. Under steady state (non-transient) conditions, I OL must be externally limited as follows: Maximum I OL per Port Pin: 10 mA Maximum I OL per 8-Bit Port - Port 0: 26 mA Ports 1, 2, and 3: 15 mA Maximum Total I OL for all Output Pins: 71 mA If I OL exceeds the test condition, V OL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 6. Contact Intel for design-in information.

AUTOMOTIVE 80C51FA/83C51FA EXPLANATION OF THE AC SYMBOLS Each timing symbol has 5 characters. The first char- acter is always a ‘T’ (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. A: Address C: Clock D: Input Data H: Logic level HIGH I: Instruction (program memory contents) L: Logic level LOW, or ALE P: PSEN Q: Output Data R: RD signal T: Time V: Valid W: WR signal X: No longer a valid logic level Z: Float For example, T AVLL e Time from Address Valid to ALE Low TLLPL e Time from ALE Low to PSEN Low AC CHARACTERISTICS (TA eb 40§Ct o a125§C, V CC e 5V g10%, V SS e 0V, Load Capacitance for Port 0, ALE/PROG and PSEN e 100 pF, Load Capacitance for All Other Outputs e 80 pF) EXTERNAL MEMORY CHARACTERISTICS Symbol Parameter 12 MHz Oscillator Variable Oscillator Units Min Max Min Max 1/TCLCL Oscillator Frequency 3.5 16 MHz TLHLL ALE Pulse Width 127 2T CLCLb40 ns TAVLL Address Valid to ALE Low 43 T CLCLb40 ns TLLAX Address Hold After ALE Low 53 T CLCLb30 ns TLLIV ALE Low to Valid Instruction In 224 4T CLCLb110 ns TLLPL ALE Low to PSEN Low 53 T CLCLb30 ns TPLPH PSEN Pulse Width 205 3T CLCLb45 ns TPLIV PSEN Low to Valid Instruction In 135 3T CLCLb115 ns TPXIX Input Instr Hold After PSEN Trans 0 0 ns TPXIZ Input Instr Float After PSEN Trans 59 T CLCLb25 ns TAVIV Address to Valid Instruction In 302 5T CLCLb115 ns TPLAZ PSEN Low to Address Float 10 10 ns TRLRH RD Pulse Width 400 6T CLCLb100 ns TWLWH WR Pulse Width 400 6T CLCLb100 ns TRLDV RD Low to Valid Data In 242 5T CLCLb175 ns TRHDX Data Hold After RD High b10 b10 ns TRHDZ Data Float After RD High 107 2T CLCLb60 ns TLLDV ALE Low to Valid Data In 507 8T CLCLb160 ns TAVDV Address Valid to Valid Data In 575 9T CLCLb175 ns TLLWL ALE Low to RD or WR Low 200 300 3T CLCLb50 3T CLCLa50 ns TAVWL Data Valid to WR Low 203 4T CLCLb130 ns TQVWX Address Valid before WR Low 23 T CLCLb50 ns TWHQX Data Hold after WR High 33 T CLCLb50 ns TQVWH Data Valid to WE High 433 7T CLCLb150 ns TRLAZ RD Low to Address Float 0 0 ns TWHLH RD or WR High to ALE High 43 123 T CLCLb40 T CLCLa40 ns

AUTOMOTIVE 80C51FA/83C51FA EXTERNAL PROGRAM MEMORY READ CYCLE 270501–12 EXTERNAL DATA MEMORY READ CYCLE 270501–13 EXTERNAL DATA MEMORY WRITE CYCLE 270501–14

AUTOMOTIVE 80C51FA/83C51FA SERIAL PORT TIMINGÐSHIFT REGISTER MODE Test Conditions: TA eb 40§Ct o a125§C; V CC e 5V g10%; V SS e 0V; Load Capacitance e 80 pF Symbol Parameter 12 MHz Oscillator Variable Oscillator Units Min Max Min Max TXLXL Serial Port Clock Cycle Time 1 12T CLCL ms TQVXH Output Data Setup to Clock 700 10T CLCLb133 ns Rising Edge TXHQX Output Data Hold after 50 2T CLCLb117 ns Clock Rising Edge TXHDX Input Data Hold After Clock 0 0 ns Rising Edge TXHDV Clock Rising Edge to Input 700 10T CLCLb133 ns Data Valid SHIFT REGISTER MODE TIMING WAVEFORMS 270501–15 EXTERNAL CLOCK DRIVE Symbol Parameter Min Max Units 1/TCLCL Oscillator Frequency 3.5 16 MHz TCHCX High Time 20 ns TCLCX Low Time 20 ns TCLCH Rise Time 20 ns TCHCL Fall Time 20 ns EXTERNAL CLOCK DRIVE WAVEFORM 270501–16

AUTOMOTIVE 80C51FA/83C51FA AC TESTING INPUT, OUTPUT WAVEFORMS 270501–17 AC Inputs during testing are driven at V CCb0.5V for a Logic ‘‘1’’ and 0.45V for a Logic ‘‘0’’. Timing measurements are made at V IH min for a Logic ‘‘1’’ and V OL max for a Logic ‘‘0’’. FLOAT WAVEFORMS 270501–18 For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs, and begins to float when a 100 mV change from the loaded V OH/VOL level occurs. IOL/IOH t g20 mA. This is for Ports 1, 2 and 3. DATASHEET REVISION HISTORY The following are key differences between this datasheet and the -006 version: 1. The ‘‘preliminary’’ status was dropped and replaced with production status (no label). 2. Trademarks were updated. The following are key differences between the -006 and the -005 version of the datasheet: 1. Preliminary notice has been added to the Title page. 2. Figure 3 Pin Connections has been modified, RST pin is now RESET pin. 3. RST pin description is now RESET pin description. 4. Figure 6 I CC vs. Frequency has been corrected to show test conditions. 5. I CC Max spec has been corrected. 6. A.C. Characteristic table 1/T CLCL spec has been changed to have a Max frequency of 16 MHz. The following are key differences between the -005 and the -004 version of the datasheet: 1. ‘‘NC’’ pin labels changed to ‘‘Reserved’’ in Figure 3. 2. Capacitor value for ceramic resonators deleted in Figure 4. The following are the key differences between the -003 version of the 8XC51FA datasheet and the -004 version of the 80C51FA/83C51FA datasheet: 1. Removed references to EPROM from the 8XC51FA datasheet. 2. Revised Figure 4, ‘‘Oscillator Connections’’. The following are the key differences between the -002 and the -003 version of this datasheet: 1. Dropped word ‘‘maximum’’ from I OL in the Absolute Maximum Rating table. 2. Dropped EA from I LI specification of the DC table. 3. Corrected TQVWH specification (from TTCLCL b 70 to TCLCL b 150). 4. Added note on external clock capacitance loading. 5. Changed the title to 80C51FA/83C51FA Event-Control CHMOS Single-Chip 8-Bit Microcontroller. 6. Added pin count to Figure 1. 7. Changed I LI to g10 mA. 8. Added I CC Power Down Mode 150 nA.