87C196KD20 INTEL | Alldatasheet
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Table 1. 128-Byte Windows Table 2. 64-Byte Windows Table 3. 32-Byte Windows
This device is manufactured on PX29.5 or PX29.9, a CHMOS III process. Additional process and reliabili- ty information is available in the Intel® Quality System Handbook: http://developer.intel.com/design/quality/quality.htm NOTE: 1. EPROMs are available as One Time Programmable (OTPROM) only. Figure 3.The 8XC196KD Family Nomenclature Table 4.ThermalCharacteristics Package θja θjcType PLCC 35°C/W 13°C/W QFP 56°C/W 12°C/W SQFP 68°C/W 15.5°C/W All thermal impedance data is approximate for static air conditions at 1W of power dissipation. Values will change depending on operation conditions and application. See the Intel Packaging Handbook (order number 240800) for a description of Intel’s thermal impedance test methodology. Table 5.8XC196KD Memory Map Description Address External Memory orI/O 0FFFFH 0A000H Internal ROM/OTPROM orExternal 9FFFH Memory (Determined byEA) 2080H Reserved.Mustcontain FFH. 207FH (Note 5) 205EH PTS Vectors 205DH 2040H UpperInterruptVectors 203FH 2030H ROM/OTPROM Security Key 202FH 2020H Reserved.Mustcontain FFH. 201FH (Note 5) 201AH Reserved.MustContain 20H 2019H (Note 5) CCB 2018H Reserved.Mustcontain FFH. 2017H (Note 5) 2014H LowerInterruptVectors 2013H 2000H Port 3and Port4 1FFFH 1FFEH External Memory 1FFDH 0400H
1000 Bytes RegisterRAM(Note 1) 03FFH
CPU SFR’s (Notes 1,3) 0017H 0000H NOTES: 1. Code executed in locations 0000H to 03FFH will be forced external. 2. Reserved memory locations must contain 0FFH unless noted. 3. Reserved SFR bit locations must contain 0. 4. Refer to 8XC196KC for SFR descriptions. 5. WARNING: Reserved memory locations must not be written or read. The contents and/or function of these lo- cations may change with future revisions of the device. Therefore, a program that relies on one or more of these locations may not function properly. x x x
272145–3 Figure 4.68-PinPLCC Package
N.C. means No Connect (do not connect these pins). Figure 5. 80-Pin QFP Package
N.C. means No Connect (do not connect these pins). Figure 6. 80-Pin SQFP Package
VCC Main supply voltage (5V). VSS Digital circuit ground (0V). There are multiple VSS pins, all of which must be connected. VREF Reference voltage for the A/D converter (5V). V REF is also the supply voltage to the analog portion of the A/D converter and the logic used to read Port 0. Must be connected for A/D and Port 0 to function. ANGND Reference ground for the A/D converter. Must be held at nominally the same potential as VSS. VPP Timing pin for the return from powerdown circuit. This pin also supplies the programming voltage on the EPROM device. XTAL1 Input of the oscillator inverter and of the internal clock generator. XTAL2 Output of the oscillator inverter. CLKOUT Output of the internal clock generator. The frequency of CLKOUT is (/2 the oscillator frequency. RESET Reset input and open drain output. BUSWIDTH Input for buswidth selection. If CCR bit 1 is a one, this pin selects the bus width for the bus cycle in progress. If BUSWIDTH is a 1, a 16-bit bus cycle occurs. If BUSWIDTH isa0a n 8-bit cycle occurs. If CCR bit 1 is a 0, the bus is always an 8-bit bus. NMI A positive transition causes a vector through 203EH. INST Output high during an external memory read indicates the read is an instruction fetch. INST is valid throughout the bus cycle. INST is activated only during external memory accesses and output low for a data fetch. EA Input for memory select (External Access). EA equal high causes memory accesses to locations 2000H through 9FFFH to be directed to on-chip ROM/E PROM. EAequal low causes accesses to those locations to be directed to off-chip memory. Also used to enter programming mode. ALE/ADV Address Latch Enable or Address Valid output, as selected by CCR. Both pin options provide a signal to demultiplex the address from the address/data bus. When the pin is ADV , it goes inactive high at the end of the bus cycle. ALE/ADV is activated only during external memory accesses. RD Read signal output to external memory. RDis activated only during external memory reads. WR/WRL Write and Write Low output to external memory, as selected by the CCR. WRwill go low for every external write, while WRLwill go low only for external writes where an even byte is being written. WR/WRL is activated only during external memory writes. BHE/WRH Bus High Enable or Write High output to external memory, as selected by the CCR. BHEwill go low for external writes to the high byte of the data bus. WRHwill go low for external writes where an odd byte is being written. BHE/WRH is activated only during external memory writes. READY Ready input to lengthen external memory cycles, for interfacing to slow or dynamic memory, or for bus sharing. When the external memory is not being used, READY has no effect. Two of them (HSI.2 and HSI.3) are shared with the HSO Unit. HSO Outputs from High Speed Output Unit. Six HSO pins are available: HSO.0, HSO.1, HSO.2,
PIN DESCRIPTIONS (Continued) Symbol Name and Function Port 0 8-bit high impedance input-only port. These pins can be used as digital inputs and/or as analog inputs to the on-chip A/D converter. Port 1 8-bit quasi-bidirectional I/O port. Port 2 8-bit multi-functional port. All of its pins are shared with other functions in the 8XC196KD. Pins 2.6 and 2.7 are quasi-bidirectional. Ports 3 and 4 8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the multiplexed address/data bus which has strong internal pullups. HOLD Bus Hold input requesting control of the bus. HLDA Bus Hold acknowledge output indicating release of the bus. BREQ Bus Request output activated when the bus controller has a pending external memory cycle. PMODE Determines the EPROM programming mode. PACT A low signal in Auto Programming mode indicates that programming is in process. A high signal indicates programming is complete. PALE A falling edge in Slave Programming Mode and Auto Configuration Byte Programming Mode indicates that ports 3 and 4 contain valid programming address/command information (input to slave). PROG A falling edge in Slave Programming Mode indicates that ports 3 and 4 contain valid programming data (input to slave). PVER A high signal in Slave Programming Mode and Auto Configuration Byte Programming Mode indicates the byte programmed correctly. CPVER Cummulative Program Output Verification. Pin is high if all locations have programmed correctly since entering a programming mode. AINC Auto Increment. Active low input enables the auto increment mode. Auto increment allows reading or writing sequential EPROM locations without address transactions across the PBUS for each read or write.
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS * Ambient Temperature Voltage On Any Pin to V SS Voltage from EA or NOTES: 1. This includes VPP and EA on ROM or CPU only devices. 2. Power dissipation is based on package heat transfer lim- itations, not device power consumption. NOTICE: This data sheet contains information on products in the sampling and initial production phases of development. It is valid for the devices indicated in the revision history. The specifications are subject to change without notice. *WARNING: Stressing the device beyond the \\Absolute Maximum Ratings'' may cause permanent damage. These are stress ratings only. Operation beyond the \\Operating Conditions'' is not recommended and ex- tended exposure beyond the \\Operating Conditions'' may affect device reliability. OPERATING CONDITIONS Symbol Description Min Max Units TA Ambient Temperature Under Bias Commercial Temp. 0 a70 §C VCC Digital Supply Voltage 4.50 5.50 V VREF Analog Supply Voltage 4.00 5.50 V ANGND Analog Ground Voltage VSS b 0.4 V SS a 0.4 V (1) FOSC Oscillator Frequency (8XC196KD) 8 16 MHz FOSC Oscillator Frequency (8XC196KD20) 8 20 MHz NOTE: 1. ANGND and VSS should be nominally at the same potential. DC CHARACTERISTICS (Over Specified Operating Conditions) Symbol Description Min Max Units Test Conditions VIL Input Low Voltage b0.5 0.8 V VIH Input High Voltage (Note 1) 0.2 V CC a 1.0 V CC a 0.5 V VHYS Hysteresis on RESET 300 mV V CC e 5.0V VIH1 Input High Voltage on XTAL 1 0.7 V CC VCC a 0.5 V VIH2 Input High Voltage on RESET 2.2 V CC a 0.5 V VOL Output Low Voltage 0.3 V I OL e 200 mA 0.45 V I OL e 2.8 mA
1.5 V I OL e 7m A
VOL1 Output Low Voltage 0.8 V IOL ea 0.4 mA in RESET on P2.5 (Note 2) VOH Output High Voltage VCC b 0.3 V I OH eb 200 mA (Standard Outputs) (Note 4) V CC b 0.7 V I OH eb 3.2 mA VCC b 1.5 V I OH eb 7m A VOH1 Output High Voltage VCC b 0.3 V I OH eb 10 mA (Quasi-bidirectional Outputs) V CC b 0.7 V I OH eb 30 mA (Note 3) VCC b 1.5 V I OH eb 60 mA TA Ambient Temperature Under Bias Extended Temp. -40 +85 °C
DC CHARACTERISTICS (Over Specified Operating Conditions) (Continued) Symbol Description Min Typ Max Units Test Conditions IOH1 Logical 1 Output Current in Reset b0.8 mA V IH e VCC b 1.5V on P2.0. Do not exceed this or device may enter test modes. IIL2 Logical 0 Input Current in Reset b12.0 mA V IN e 0.45V on P2.0. Maximum current that must be sunk by external device to ensure test mode entry. IIH1 Logical 1 Input Current. Maximum a200 mAV IN e 2.4V current that external device must source to initiate NMI. ILI Input Leakage Current (Std. g10 mA0 k VIN k VCC b 0.3V Inputs) (Note 5) ILI1 Input Leakage Current (Port 0) g3 mA0 k VIN k VREF ITL 1 to 0 Transition Current (QBD b650 mAV IN e 2.0V Pins) IIL Logical 0 Input Current (QBD Pins) b70 mAV IN e 0.45V IIL1 AD Bus in Reset b70 mAV IN e 0.45V ICC Active Mode Current in Reset 65 75 mA XTAL1 e 16 MHz (8XC196KD) VCC e VPP e VREF e 5.5V ICC Active Mode Current in Reset 80 92 mA XTAL1 e 20 MHz (8XC196KD20) VCC e VPP e VREF e 5.5V IIDLE Idle Mode Current (8XC196KD) 17 25 mA XTAL1 e 16 MHz VCC e VPP e VREF e 5.5V IIDLE Idle Mode Current (8XC196KD20) 21 30 mA XTAL1 e 20 MHz VCC e VPP e VREF e 5.5V IPD Powerdown Mode Current 8 15 mAV CC e VPP e VREF e 5.5V IREF A/D Converter Reference Current 2 5 mA V CC e VPP e VREF e 5.5V RRST Reset Pullup Resistor 6K 65K X VCC e 5.5V, VIN e 4.0V CS Pin Capacitance (Any Pin to VSS)1 0 pF NOTES: 1. All pins except RESET and XTAL1. 2. Violating these specifications in Reset may cause the part to enter test modes. 3. QBD (Quasi-bidirectional) pins include Port 1, P2.6 and P2.7. 4. Standard Outputs include AD0±15, RD ,W R, ALE, BHE , INST, HSO pins, PWM/P2.5, CLKOUT, RESET, Ports 3 and 4, TXD/P2.0 and RXD (in serial mode 0). The V OH specification is not valid for RESET. Ports 3 and 4 are open-drain outputs. 6. Maximum current per pin must be externally limited to the following values if V OL is held above 0.45V or V OH is held below VCC b 0.7V: IOL on Output pins: 10 mA IOH on quasi-bidirectional pins: self limiting IOH on Standard Output pins: 10 mA 7. Maximum current per bus pin (data and control) during normal operation is g3.2 mA. 8. During normal (non-transient) conditions the following total current limits apply: Port 1, P2.6 IOL:2 9m A IOH is self limiting HSO, P2.0, RXD, RESET IOL:2 9m A IOH:2 6m A P2.5, P2.7, WR, BHE IOL:1 3m A IOH:1 1m A AD0±AD15 IOL:5 2m A IOH:5 2m A RD, ALE, INST±CLKOUT I OL:1 3m A IOH:1 3m A
Frequencies below 8 MHz are shown for reference only; no testing is performed. Figure 7. I CC and IIDLE vs Frequency For use over specified operating conditions.
- If max is exceeded, additional wait states will occur.
- If wait states are used, add 2 T
OSC * N, where N e number of wait states.
AC CHARACTERISTICS (Continued) For use over specified operating conditions. Test Conditions: Capacitive load on all pins e 100 pF, Rise and fall times e 10 ns, FOSC e 16/20 MHz The 80C196KD will meet these specifications: Symbol Description Min Max Units Notes FXTAL Frequency on XTAL1 (8XC196KD) 8 16 MHz (Note 1) FXTAL Frequency on XTAL1 (8XC196KD20) 8 20 MHz (Note 1) TOSC I/F XTAL (8XC196KD) 62.5 125 ns TOSC I/F XTAL (8XC196KD20) 50 125 ns TXHCH XTAL1 High to CLKOUT High or Low a20 a110 ns TCLCL CLKOUT Cycle Time 2 TOSC ns TCHCL CLKOUT High Period TOSC b 10 T OSCa15 ns TCLLH CLKOUT Falling Edge to ALE Rising b5 a15 ns TLLCH ALE Falling Edge to CLKOUT Rising b20 a15 ns TLHLH ALE Cycle Time 4 TOSC ns (Note 4) TLHLL ALE High Period TOSC b 10 T OSCa10 ns TAVLL Address Setup to ALE Falling Edge T OSC b 15 TLLAX Address Hold after ALE Falling Edge T OSC b 35 ns TLLRL ALE Falling Edge to RDFalling Edge T OSC b 30 ns TRLCL RD Low to CLKOUT Falling Edge a4 a30 ns TRLRH RD Low Period TOSC b 5 ns (Note 4) TRHLH RD Rising Edge to ALE Rising Edge T OSC TOSC a 25 ns (Note 2) TRLAZ RD Low to Address Float a5n s TLLWL ALE Falling Edge to WRFalling Edge T OSC b 10 ns TCLWL CLKOUT Low to WR Falling Edge 0 a25 ns TQVWH Data Stable to WR Rising Edge T OSC b 23 (Note 4) TCHWH CLKOUT High to WRRising Edge b5 a15 ns TWLWH WR Low Period TOSC b 20 ns (Note 4) TWHQX Data Hold after WR Rising Edge T OSC b 25 ns TWHLH WR Rising Edge to ALE Rising Edge T OSC b 10 T OSC a 15 ns (Note 2) TWHBX BHE, INST after WR Rising Edge T OSC b 10 ns TWHAX AD8±15 HOLD after WR Rising T OSC b 30 ns (Note 3) TRHBX BHE, INST after RD Rising Edge T OSC b 10 ns TRHAX AD8±15 HOLD after RD Rising T OSC b 25 ns (Note 3) NOTES: 1. Testing performed at 8 MHz. However, the device is static by design and will typically operate below 1 Hz. 2. Assuming back-to-back bus cycles. 3. 8-Bit bus only. 4. If wait states are used, add 2 T OSC * N, where N e number of wait states.
272145±6
READY Timings (One Wait State) 272145±7 Buswidth Timings 272145±8
Symbol Description Min Max Units Notes THVCH HOLD Setup a55 ns (Note 1) TCLHAL CLKOUT Low to HLDA Low b15 a15 ns TCLBRL CLKOUT Low to BREQ Low b15 a15 ns THALAZ HLDA Low to Address Float a15 ns THALBZ HLDA Low to BHE, INST, RD,W R Weakly Driven a20 ns TCLHAH CLKOUT Low to HLDA High b15 a15 ns TCLBRH CLKOUT Low to BREQ High b15 a15 ns THAHAX HLDA High to Address No Longer Float b15 ns THAHBV HLDA High to BHE, INST, RD,W R Valid b10 a15 ns TCLLH CLKOUT Low to ALE High b5 a15 ns NOTE: 1. To guarantee recognition at next clock. DC SPECIFICATIONS IN HOLD Description Min Max Units Weak Pullups on ADV,R D, 50K 250K V CC e 5.5V, VIN e 0.45V WR,W RL, BHE Weak Pulldowns on ALE, INST 10K 50K VCC e 5.5V, VIN e 2.4 272145±9
Internal Execution 1.5 States 16-Bit External Execution 2.5 States 8-Bit External Execution 4.5 States EXTERNAL CLOCK DRIVE (8XC196KD) Symbol Parameter Min Max Units 1/T XLXL Oscillator Frequency 8 16.0 MHz TXLXL Oscillator Period 62.5 125 ns TXHXX High Time 20 ns TXLXX Low Time 20 ns TXLXH Rise Time 10 ns TXHXL Fall Time 10 ns EXTERNAL CLOCK DRIVE (8XC196KD20) Symbol Parameter Min Max Units 1/T XLXL Oscillator Frequency 8 20.0 MHz TXLXL Oscillator Period 50 125 ns TXHXX High Time 17 ns TXLXX Low Time 17 ns TXLXH Rise Time 8 ns TXHXL Fall Time 8 ns EXTERNAL CLOCK DRIVE WAVEFORMS 272145±10
EXTERNAL CRYSTAL CONNECTIONS 272145±13 NOTE: Keep oscillator components close to chip and use short, direct traces to XTAL1, XTAL2 and V SS. When using ceramic crystals, C1 e 20 pF, C2 e 20 pF. When using ceramic resonators consult manufacturer for recommended capacitor values. EXTERNAL CLOCK CONNECTIONS 272145±14 NOTE: *Required if TTL driver used. Not needed if CMOS driver is used. AC TESTING INPUT, OUTPUT WAVEFORMS 272145±11 AC Testing inputs are driven at 2.4V for a Logic \\1'' and 0.45V for a Logic \\0'' Timing measurements are made at 2.0V for a Logic \\1'' and 0.8V for a Logic \\0''. FLOAT WAVEFORMS 272145±12 For Timing Purposes a Port Pin is no Longer Floating when a 150 mV change from Load Voltage Occurs, and Begins to Float when a 150 mV change from the Loaded V OH/V OL Level occurs; IOL/I OH e g15 mA. EXPLANATION OF AC SYMBOLS Each symbol is two pairs of letters prefixed by \\T'' for time. The characters in a pair indicate a signal and its condition, respectively. Symbols represent the time between the two signal/condition points. Conditions: H - High L - Low V - Valid X - No Longer Valid Z - Floating Signals: A - Address B - BHE C - CLKOUT D - DATA G - Buswidth H - HOLD HA - HLDA L - ALE/ADV BR - BREQ R - RD W - WR/WRH /WRL X - XTAL1 Y - READY Q - Data Out
AC CHARACTERISTICS-SERIAL PORT-SHIFT REGISTER MODE SERIAL PORT TIMING-SHIFT REGISTER MODE (MODE0) Symbol Parameter Min Max Units TXLXL Serial Port Clock Period (BRRt 8002H) 6 TOSC ns TXLXH Serial Port Clock Falling Edge 4 TOSC b50 4 T OSC a50 ns to Rising Edge (BRR t 8002H) TXLXL Serial Port Clock Period (BRR e 8001H) 4 TOSC ns TXLXH Serial Port Clock Falling Edge 2 TOSC b50 2 T OSC a50 ns to Rising Edge (BRR e 8001H) TQVXH Output Data Valid to Clock Rising Edge 2 TOSC b 50 ns TXHQX Output Data Hold after Clock Rising Edge 2 T OSC b 50 ns TXHQV Next Output Data Valid after Clock Rising Edge 2 TOSC a 50 ns TDVXH Input Data Setup to Clock Rising Edge TOSC a50 ns TXHDX Input Data Hold after Clock Rising Edge 0 ns TXHQZ Last Clock Rising to Output Float 1 TOSC ns WAVEFORM-SERIAL PORT-SHIFT REGISTER MODE SERIAL PORT WAVEFORM-SHIFT REGISTER MODE (MODE 0) 272145±15
The A/D converter is ratiometric, so absolute accuracy is dependent on the accuracy and stability of V REF. 10-BIT MODE A/D OPERATING CONDITIONS Symbol Description Min Max Units TA Ambient Temperature Commercial Temp. 0 a70 §C VCC Digital Supply Voltage 4.50 5.50 V VREF Analog Supply Voltage 4.00 5.50 V ANGND Analog Ground Voltage VSS b 0.40 V CC a 0.40 V TSAM Sample Time 1.0 ms(1) TCONV Conversion Time 10 20 ms(1) FOSC Oscillator Frequency (8XC196KD) 8.0 16.0 MHz FOSC Oscillator Frequency (8XC196KD20) 8.0 20.0 MHz NOTE: 1. The value of AD_TIME is selected to meet these specifications. 10-BIT MODE A/D CHARACTERISTICS (Over Specified Operating Conditions) Parameter Typical(1) Minimum Maximum Units* Notes Resolution 1024 1024 Levels 10 10 Bits Absolute Error 0 g3 LSBs Full Scale Error 0.25 g 0.5 LSBs Zero Offset Error 0.25 g 0.5 LSBs Non-Linearity 1.0 g 2.0 0 g3 LSBs Differential Non-Linearity Error lb1 a2 LSBs Channel-to-Channel Matching g0.1 0 g1 LSBs Repeatability g0.25 LSBs Temperature Coefficients: Offset 0.009 LSB/ §C Full Scale 0.009 LSB/ §C Differential Non-Linearity 0.009 LSB/ §C Off Isolation b60 dB 2, 3 Feedthrough b60 dB 2 VCC Power Supply Rejection b60 dB 2 Input Series Resistance 750 1.2K X 4 Voltage on Analog Input Pin ANGND b 0.5 V REF a 0.5 V 5, 6 DC Input Leakage 0 g3.0 mA Sampling Capacitor 3 pF NOTES: *An \\LSB'' as used here has a value of approxiimately 5 mV. (See Embedded Microcontrollers and Processors Handbook for A/D glossary of terms.) 1. These values are expected for most parts at 25 §C but are not tested or guaranteed. 2. DC to 100 KHz. 3. Multiplexer Break-Before-Make is guaranteed. 4. Resistance from device pin, through internal MUX, to sample capacitor. 5. These values may be exceeded if the pin current is limited to g2 mA. 6. Applying voltages beyond these specifications will degrade the accuracy of other channels being converted. 7. All conversions performed with processor in IDLE mode. TA Ambient Temperature Extended Temp. -40 +85 °C
8-BIT MODE A/D OPERATING CONDITIONS Symbol Description Min Max Units TA Ambient Temperature Commercial Temp. 0 a70 §C VCC Digital Supply Voltage 4.50 5.50 V VREF Analog Supply Voltage 4.00 5.50 V ANGND Analog Ground Voltage VSS b0.40 V SS a 0.40 V TSAM Sample Time 1.0 ms(1) TCONV Conversion Time 7 20 ms(1) FOSC Oscillator Frequency (8XC196KD) 8.0 16.0 MHz FOSC Oscillator Frequency (8XC196KD20) 8.0 20.0 MHz NOTE: 1. The value of AD_TIME is selected to meet these specifications. 8-BIT MODE A/D CHARACTERISTICS (Over Specified Operating Conditions) Parameter Typical(1) Minimum Maximum Units* Notes Resolution 256 256 Levels 8 8 Bits Absolute Error 0 g1 LSBs Full Scale Error g0.5 LSBs Zero Offset Error g0.5 LSBs Non-Linearity 0 g1 LSBs Differential Non-Linearity Error lb1 a1 LSBs Channel-to-Channel Matching g1 LSBs Repeatability g0.25 LSBs Temperature Coefficients: Offset 0.003 LSB/ §C Full Scale 0.003 LSB/ §C Differential Non-Linearity 0.003 LSB/ §C Off Isolation b60 dB 2, 3 Feedthrough b60 dB 2 VCC Power Supply Rejection b60 dB 2 Input Series Resistance 750 1.2K X 4 Voltage on Analog Input Pin VSS b 0.5 V REF a 0.5 V 5, 6 DC Input Leakage 0 g3.0 mA Sampling Capacitor 3 pF NOTES: *An \\LSB'' as used here has a value of approximately 20 mV. (See Embedded Microcontrollers and Processors Handbook for A/D glossary of terms). 1. These values are expected for most parts at 25 §C but are not tested or guaranteed. 2. DC to 100 KHz. 3. Multiplexer Break-Before-Make is guaranteed. 4. Resistance from device pin, through internal MUX, to sample capacitor. 5. These values may be exceeded if pin current is limited to g2 mA. 6. Applying voltages beyond these specifications will degrade the accuracy of other channels being converted. 7. All conversions performed with processor in IDLE mode. TA Ambient Temperature Extended Temp. -40 +85 °C
Symbol Description Min Max Units TA Ambient Temperature During Programming 20 30 C VCC Supply Voltage During Programming 4.5 5.5 V (1) VREF Reference Supply Voltage During Programming 4.5 5.5 V (1) VPP Programming Voltage 12.25 12.75 V (2) VEA EA Pin Voltage 12.25 12.75 V (2) FOSC Oscillator Frequency during Auto and Slave 6.0 8.0 MHz Mode Programming FOSC Oscillator Frequency during 6.0 16.0 MHz Run-Time Programming(8XC196KD) FOSC Oscillator Frequency during 6.0 20.0 MHz Run-Time Programming(8XC196KD20) NOTES: 1. VCC and VREF should nominally be at the same voltage during programming. 2. VPP and VEA must never exceed the maximum specification, or the device may be damaged. 3. VSS and ANGND should nominally be at the same potential (0V). 4. Load capacitance during Auto and Slave Mode programming e 150 pF. AC OTPROM PROGRAMMING CHARACTERISTICS (SLAVE MODE) Symbol Description Min Max Units TSHLL Reset High to First PALE Low 1100 TOSC TLLLH PALE Pulse Width 50 TOSC TAVLL Address Setup Time 0 TOSC TLLAX Address Hold Time 100 TOSC TPLDV PROG Low to Word Dump Valid 50 TOSC TPHDX Word Dump Data Hold 50 TOSC TDVPL Data Setup Time 0 TOSC TPLDX Data Hold Time 400 TOSC TPLPH(1) PROG Pulse Width 50 TOSC TPHLL PROG High to Next PALE Low 220 TOSC TLHPL PALE High to PROG Low 220 TOSC TPHPL PROG High to Next PROG Low 220 TOSC TPHIL PROG High to AINC Low 0 TOSC TILIH AINC Pulse Width 240 TOSC TILVH PVER Hold after AINCLow 50 TOSC TILPL AINC Low to PROG Low 170 TOSC TPHVL PROG High to PVER Valid 220 TOSC NOTE: 1. This specification is for the Word Dump Mode. For programming pulses, use the Modified Quick Pulse Algorithm.
DC OTPROM PROGRAMMING CHARACTERISTICS Symbol Description Min Max Units IPP VPP Supply Current (When Programming) 100 mA NOTE: Do not apply V PP until VCC is stable and within specifications and the oscillator/clock has stabilized or the device may be damaged. OTPROM PROGRAMMING WAVEFORMS SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE 272145±16 NOTE: P3.0 must be high (\\1'')
SLAVE PROGRAMMING MODE IN WORD DUMP WITH AUTO INCREMENT 272145±17 NOTE: P3.0 must be low (\\0'') SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM WITH REPEATED PROG PULSE AND AUTO INCREMENT 272145±18
8XC196KC TO 8XC196KD DESIGN CONSIDERATIONS 1. Memory Map. The 8XC196KD has 1024 bytes of RAM/SFRs and 32K of OTPROM. The extra 512 bytes of RAM reside in locations 0200H to 03FFH, and the extra 16 Kbytes of OTPROM re- side in locations 6000H to 9FFFH. On the 87C196KC these locations are always external, so KC code may have to be modified to run on the KD. 2. The vertical window scheme has been extended to include all on-chip RAM. 3. IOC3.1 controls the CLKOUT signal. This bit must be 0 to enable CLKOUT. 4. The 87C196KD has a different autoprogramming algorithm to support 32K of on-chip OTPROM. 8XC196KD ERRATA 1. 83C196KD can possibly miss interrupts on P0.7. See techbit MC0893. DATA SHEET REVISION HISTORY This data sheet is valid for devices with a \\D'' and \\E'' at the end of the topside tracking number. Data sheets are changed as new device information be- comes available. Verify with your local Intel sales office that you have the latest version before finaliz- ing a design or ordering devices. The following are important differences between the 272145-004 and 272145-005 datasheets: 1. Package prefix variables have been changed. Variables are now indicated with an "x". The following are important differences between the 272145-002 and 272145-003 data sheets: 1. I IL1 specification (logic 0 input current in reset) was misnamed. It is renamed I IL2. 2. T LLYV and TLLGV were removed. These specifi- cations are not necessary for high-speed system designs. 3. An errata with 83C196KD P0.7 EXTINT was add- ed to the errata section. The following are important differences between the 272145-001 and 272145-002 data sheets: 1. Added 20 MHz specifications. 2. Added 80-lead SQFP package pinout. 3. Changed QFP Package i JA to 56 §C/W from 42§C/W. 4. Changed V HYS to 300 mV from 150 mV. 5. Changed I CC Typical specification at 16 MHz to 65 mA from 50 mA. 6. Changed I CC Maximum specification at 16 MHz to 75 mA from 70 mA. 7. Changed I IDLE Typical specification to 17 mA from 15 mA. 8. Changed I IDLE Maximum specification to 25 mA from 30 mA. 9. Changed I PD Typical specification to 8 mA from 15 mA. 10. Added I PD Maximum specification. 11. Changed T CLDV Maximum specification to TOSC b 45 from T OSC b 50. 12. Changed T LLAX Minimum specification to TOSC b 35 from T OSC b 40. 13. Changed T CHWH Minimum specification to b5 from b10. 14. Changed T RHAX Minimum specification to TOSC b 25 from T OSC b 30. 15. Changed T HALAZ Maximum specification to a15 from a10. 16. Changed T HALBZ Maximum specification to a20 from a15. 17. Added T HAHBV Maximum specification. 18. Changed T SAM for 10-bit mode to 1 ms from 3 ms. 19. Changed T SAM for 8-bit mode to 1 ms from 2 ms. 20. Changed I IH1 test condition to V IN e 2.4V from 5.5V. 21. Changed I IH1 maximum specification to a200 mA from a100 mA. 22. Removed NMI from list of standard inputs. 23. Updated I CC and IIDLE vs frequency graph. 24. Updated note under DC EPROM Programming Characteristics. 25. Changed I LI1 maximum specification to b12 mA from b6 mA.