83C196EA INTEL | Alldatasheet

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Technical content

Datasheet sections

  • 1.0 Product Overview
  • 2.0 Nomenclature Overview
  • 3.0 Pinout
  • 4.0 Signals
  • 5.0 Address Map
  • 6.0 Electrical Characteristics
  • 6.1 DC Characteristics
  • 6.2 AC Characteristics — Multiplexed Bus Mode
  • 6.3 AC Characteristics — Demultiplexed Bus Mode
  • 6.4 Deferred Bus Timing Mode
  • 6.5 AC Characteristics — Serial Port, Shift Register Mode
  • 6.6 AC Characteristics — Synchronous Serial Port
  • 6.7 A/D Sample and Conversion Times
  • 6.7.1 AC Characteristics — A/D Converter, 10-bit Mode
  • 6.7.2 AC Characteristics — A/D Converter, 8-bit Mode
  • 6.8 External Clock Drive
  • 6.9 Test Output Waveforms
  • 7.0 Thermal Characteristics
  • 9.0 DataSheet Revision History

Datasheet sections

COPYRIGHT © INTEL CORPORATION, 1997 March 1997 Order Number: 272788-002 83C196EA CHMOS 16-BIT MICROCONTROLLER Automotive The 83C196EA is the first member of a new family of microcontrollers with features that are useful in automotive applications, such as powertrain control. Two Mbytes of linear address space provide more space for high-level language compilation. A demultiplexed address/data bus and three chip-select signals make it easier to design low-cost memory solutions. The external bus can dynamically switch between multiplexed and demultiplexed operation. NOTE This datasheet contains information on products being sampled or in the initial production phase of development. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. ■ 40 MHz operation ■ Optional clock doubler ■ 2 Mbytes of linear address space ■ 1 Kbyte of register RAM ■ 3 Kbytes of code RAM ■ 8 Kbytes of ROM ■ Register-to-register architecture ■ Stack overflow/underflow monitor with user-defined upper and lower stack pointer boundary limits ■ 2 peripheral interrupt handlers (PIH) provide direct hardware handling of up to 16 peripheral interrupts ■ Peripheral transaction server (PTS) with high-speed, microcoded interrupt service routines ■ Up to 83 I/O port pins ■ 2 full-duplex serial ports with dedicated baud-rate generators ■ Enhanced synchronous serial unit ■ 8 pulse-width modulator (PWM) outputs with 8-bit resolution ■ 16-bit watchdog timer ■ Sixteen 10-bit A/D channels with auto- scan mode and dedicated results registers ■ Serial debug unit provides read and write access to code RAM with no CPU overhead ■ Chip-select unit (CSU) ■ 3 chip-select pins ■ Dynamic demultiplexed/multiplexed address/data bus for each chip-select ■ Programmable wait states (0, 1, 2, or 3) for each chip-select ■ Programmable bus width (8- or 16-bit) for each chip-select ■ Programmable address range for each chip-select ■ Event processor array (EPA) ■ 4 flexible 16-bit timer/counters ■ 17 high-speed capture/compare channels ■ 8 output-only channels capture value of any other timer upon compare, providing easy conversion between angle and time domains ■ Programmable clock output signal ■ 160-pin QFP package ■ Complete system development support ■ High-speed CHMOS technology

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel dis- claims any express or implied warranty, relating to sale and/or use of Intel products including liability or war- ranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel retains the right to make changes to specifications and product descriptions at any time, without notice. *Third-party brands and names are the property of their respective owners. Copies of documents which have an ordering number and are referenced in this document, or other Intel liter- ature, may be obtained from: Intel Corporation P.O. Box 7641 Mt. Prospect, IL 60056-7641 or call 1-800-548-4725

1.0 PRODUCT OVERVIEW

Figure 1. 83C196EA Block Diagram

3 Kbytes

17 Capture/

8 Kbytes

1 KbyteALU

8 Output/

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2.0 NOMENCLATURE OVERVIEW

Figure 2. Product Nomenclature Table 1. Description of Product Nomenclature 125° C case) with Intel standard burn-in.

3.0 PINOUT

Figure 3. 83C196EA 160-pin QFP Package This pin supplies voltage to the phase-locked loop circuitry, so use extra care to keep it stable. This pin supplies voltage to the code RAM. Maintain at 5 volts to retain data in code RAM. NC pins must be unconnected to prevent accidental entry into a test mode.

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Table 2. 83C196EA 160-pin QFP Package Pin Assignments

Table 3. Pin Assignment Arranged by Functional Categories

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4.0 SIGNALS

†† This pin supplies voltage to code RAM. To retain data, maintain 5 volts. Table 4. Signal Descriptions memory cycle during both multiplexed and demultiplexed bus modes. memory cycle, supporting extended addressing of the 2 Mbyte address space.

16 Mbytes (000000–FFFFFFH) and the external address space is 2

memory or 1F2080H in external memory. A20:16 are multiplexed with EPORT.4:0. These pins are analog inputs to the A/D converter. REF pins must be connected for the A/D converter to function. Table 3. Pin Assignment Arranged by Functional Categories (Continued)

access is not occurring, these pins revert to their I/O port function. receive data during the second half of the bus cycle. during the second half of the bus cycle. AD15:0 drive or receive data during the entire bus cycle. that is currently on the high byte of the internal bus. This active-high output signal is asserted only during external memory cycles. for a multiplexed bus; A20:0 for a demultiplexed bus). address/data bus in multiplexed mode. ALE shares a package pin with P5.0. should be nominally at the same potential. BHE# shares a package pin with P5.5 and WRH#. controller has a pending external memory cycle. You must enable the bus-hold protocol before using this signal. BREQ# shares a package pin with P5.4. Table 4. Signal Descriptions (Continued)

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XTAL 1). CLKOUT has a 50% duty cycle. frequency equals the operating frequency (f) divided by two. sampled on the rising edge of CRDCLK. FF2000–FF20FFH (1F2000–1F20FFH if external). CS2:0# share package pins with EPORT.7:5. memory location, the value of EA# is irrelevant. level of EA# after reset has no effect. High-speed input/output signals for the EPA capture/compare channels.

This is a standard 8-bit, bidirectional port. high time is one state time. EXTINT shares a package pin with P2.2. This active-high output signal is valid only during external memory bus cycles. INST shares a package pin with P5.1. greater than one state time to guarantee that it is recognized. system. The value of ONCE# is latched when the RESET# pin goes inactive. ONCE# shares a package pin with P2.6. port 9 and may be configured as standard I/O. OS7:0 share package pins with P9.7:0.

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multiplexed address/data bus, which has complementary drivers. P3.7:0 share package pins with AD7:0. multiplexed address/data bus, which has complementary drivers. P4.7:0 share package pins with AD15:8. selectable special-function signals. selectable special-function signals. P8.7:0 share package pins with EPA15:8. selectable special-function signals. P9.7:0 share package pins with OS7:0.

selectable special-function signals. selectable special-function signals. P11.7:0 share package pins with PWM7:0. This active-high input pin enables the on-chip clock doubler. These are PWM output pins with high-current drive capability. PWM7:0 share package pins with P11.7:0. RD# shares a package pin with P5.3. READY shares a package pin with P5.6. is from FF2080H (or 1F2080H in external memory).

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Timing pin for the return-from-powerdown circuit. and VSS if either of the following conditions are true.

  • the internal oscillator is the clock source
  • the phase-locked loop (PLL) circuitry is enabled (see PLLEN signal description) The capacitor causes a delay that enables the oscillator and PLL circuitry to stabilize before the internal CPU and peripheral clocks are enabled. The capacitor is not required if your application uses powerdown mode and if both of the following conditions are true.
  • an external clock input is the clock source
  • the phase-locked loop circuitry is disabled If your application does not use powerdown mode, leave this pin unconnected. RPD shares a package pin with P5.7. RXD1:0 I/O Receive Serial Data 0 and 1 In modes 1, 2, and 3, RXD0 and 1 receive serial port input data. In mode 0, they functions as either inputs or open-drain outputs for data. RXD0 shares a package pin with P2.1 and RXD1 shares a package pin with P2.4. SC1:0 I/O Clock Pins for SSIO0 and 1 For handshaking mode, configure SC1:0 as open-drain outputs. This pin carries a signal only during receptions and transmissions. When the SSIO port is idle, the pin remains either high (with handshaking) or low (without handshaking). SC0 shares a package pin with P10.0, and SC1 shares a package pin with P10.2. SD1:0 I/O Data Pins for SSIO0 and 1 These pins are the data I/O pins for SSIO0 and 1. SD0 shares a package pin with P10.1, and SD1 shares a package pin with P10.1. T1CLK I Timer 1 External Clock External clock for timer 1.Timer 1 is programmable to increment or decement on the rising edge, the falling edge, or both rising and falling edges of T1CLK. and External clock for the serial I/O baud-rate generator input (program selectable). T1CLK shares a package pin with P7.0 and EPA0. T2CLK I Timer 2 External Clock External clock for timer 2. Timer 2 is programmable to increment or decement on the rising edge, the falling edge, or both rising and falling edges of T2CLK. T2CLK shares a package pin with P7.2 and EPA2.

on the rising edge, the falling edge, or both rising and falling edges of T3CLK. T3CLK shares a package pin with P7.4 and EPA4. on the rising edge, the falling edge, or both rising and falling edges of T4CLK. T4CLK shares a package pin with P7.6 and EPA6. the falling edge, or both rising and falling edges of T1RST. T1RST shares a package pin with P7.1 and EPA1. the falling edge, or both rising and falling edges of T2RST. T2RST shares a package pin with P7.3 and EPA3. the falling edge, or both rising and falling edges of T3RST. T3RST shares a package pin with P7.5 and EPA5. the falling edge, or both rising and falling edges of T4RST. T4RST shares a package pin with P7.6 and EPA6. IH specification to prevent inadvertent entry into test mode. TMODE# shares a package pin with P5.4 and BREQ#. mode 0, they are the serial clock output. Connect each VCC pin to the digital supply voltage.

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ground through the lowest possible impedance path. asserted only during external memory writes. WR# is multiplexed with P5.2 and WRL#. tions as WR# or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#. asserted for all write operations. WRH# shares a package pin with P5.5 and BHE#. asserted for all write operations. WRL# shares a package pin with P5.2 and WR#. tions as WR# or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#. uses an external clock source instead of the on-chip oscillator.

5.0 ADDRESS MAP

Table 5. 83C196EA Address Map

004000 External device (memory or I/O) connected to address/data bus Indirect, indexed,

002000 External device (memory or I/O) connected to address/data bus Indirect, indexed,

001000 External device (memory or I/O) connected to address/data bus Indirect, indexed,

000400 Internal code/data RAM (identically mapped into page FFH) Indirect, indexed,

  1. Unless otherwise noted, write 0FFH to reserved memory locations and write 0 to reserved SFR bits.
  2. The contents or functions of reserved locations may change in future device revisions, in which case a

program that relies on one or more of these locations might not function properly.

  1. External memory if EA# is low; internal ROM if EA# is high.

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000100 Upper register file (general-purpose register RAM) Indirect, indexed,

000000 Lower register file (stack pointer and CPU SFRs) Direct, indirect,

Table 5. 83C196EA Address Map (Continued)

  1. Unless otherwise noted, write 0FFH to reserved memory locations and write 0 to reserved SFR bits.
  2. The contents or functions of reserved locations may change in future device revisions, in which case a

program that relies on one or more of these locations might not function properly.

  1. External memory if EA# is low; internal ROM if EA# is high.

6.0 ELECTRICAL CHARACTERISTICS

6.1 DC Characteristics

  1. This device is static and should operate below

1 Hz, but has been tested only down to 20 MHz. specifications are subject to change without notice. Table 6. DC Characteristics at VCC = 4.5 V – 5.5 V

  1. Typical values are based on a limited number of samples and are not guaranteed. The values listed

are at room temperature with VCC = 5.0 V. PLLEN, NMI, TDI, TCLK, ONCE#, and XTAL1.

  1. The maximum injection current is not tested. The device is designed to meet this specification.
  2. Pin capacitance is not tested. This value is based on design simulations.

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Table 6. DC Characteristics at VCC = 4.5 V – 5.5 V (Continued)

  1. Typical values are based on a limited number of samples and are not guaranteed. The values listed

are at room temperature with VCC = 5.0 V. PLLEN, NMI, TDI, TCLK, ONCE#, and XTAL1.

  1. The maximum injection current is not tested. The device is designed to meet this specification.
  2. Pin capacitance is not tested. This value is based on design simulations.

6.2 AC Characteristics — Multiplexed Bus Mode

Test Conditions: Capacitive load on all pins = 50 pF, Rise and Fall Times = 3 ns. Table 7. AC Characteristics, Multiplexed Bus Mode

  1. 16 MHz is the maximum input frequency when using an external crystal oscillator; however, 40MHz

can be applied with an external clock source.

  1. If wait states are used, add 2t × n, where n = number of wait states.
  2. Assuming back-to-back bus cycles.
  3. When forcing wait states using the BUSCON register, add 2t ×
  4. Exceeding the maximum specification causes additional wait states.
  5. The first falling edge of READY is not synchronized to a CLKOUT edge; therefore, one programmed
  6. Device is static by design but has been tested only down to 20 MHz.
  7. Assumes CLKOUT is operating in divide-by-two mode (f/2).

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Table 8. AC Timing Symbol Definitions Table 7. AC Characteristics, Multiplexed Bus Mode (Continued)

  1. 16 MHz is the maximum input frequency when using an external crystal oscillator; however, 40MHz

can be applied with an external clock source.

  1. If wait states are used, add 2t × n, where n = number of wait states.
  2. Assuming back-to-back bus cycles.
  3. When forcing wait states using the BUSCON register, add 2t ×
  4. Exceeding the maximum specification causes additional wait states.
  5. The first falling edge of READY is not synchronized to a CLKOUT edge; therefore, one programmed
  6. Device is static by design but has been tested only down to 20 MHz.
  7. Assumes CLKOUT is operating in divide-by-two mode (f/2).

Figure 4. System Bus Timing Diagram (Multiplexed Bus Mode)

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Figure 5. READY Timing Diagram (Multiplexed Bus Mode)

6.3 AC Characteristics — Demultiplexed Bus Mode

Test Conditions: Capacitive load on all pins = 50 pF, Rise and Fall Times = 3 ns. Table 9. AC Characteristics, Demultiplexed Bus Mode

  1. 16 MHz is the maximum input frequency when using an external crystal oscillator; however, 40 MHz

can be applied with an external clock source.

  1. If wait states are used, add 2t × n, where n = number of wait states.
  2. Assuming back-to-back bus cycles.
  3. When forcing wait states using the BUSCON register, add 2t ×
  4. Exceeding the maximum specification causes additional wait states.
  5. The first falling edge of READY is not synchronized to a CLKOUT edge; therefore, one programmed
  6. Device is static by design but has been tested only down to 20 MHz.
  7. Assumes CLKOUT is operating in divide-by-two mode (f/2).

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Table 9. AC Characteristics, Demultiplexed Bus Mode (Continued)

  1. 16 MHz is the maximum input frequency when using an external crystal oscillator; however, 40 MHz

can be applied with an external clock source.

  1. If wait states are used, add 2t × n, where n = number of wait states.
  2. Assuming back-to-back bus cycles.
  3. When forcing wait states using the BUSCON register, add 2t ×
  4. Exceeding the maximum specification causes additional wait states.
  5. The first falling edge of READY is not synchronized to a CLKOUT edge; therefore, one programmed
  6. Device is static by design but has been tested only down to 20 MHz.
  7. Assumes CLKOUT is operating in divide-by-two mode (f/2).

Figure 6. System Bus Timing Diagram (Demultiplexed Bus Mode)

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Figure 7. READY Timing Diagram (Demultiplexed Bus Mode)

6.4 Deferred Bus Timing Mode

Figure 8. Deferred Bus Mode Timing Diagram

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6.5 AC Characteristics — Serial Port, Shift Register Mode

Figure 9. Serial Port Waveform — Shift Register Mode Table 10. Serial Port Timing — Shift Register Mode (SP_BAUD) register value for transmit is x001H.

6.6 AC Characteristics — Synchronous Serial Port

Figure 10. Synchronous Serial Port Table 11. Synchronous Serial Port Timing

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83C196EA CHMOS 16-BIT MICROCONTROLLER — AUTOMOTIVE

6.7 A/D Sample and Conversion Times

Two parameters, sample time and conversion time, control the time required for an A/D conversion. The sample time is the length of time that the analog input voltage is actually connected to the sample capacitor. If this time is too short, the sample capacitor will not charge completely. If the sample time is too long, the input voltage may change and cause conversion errors. The conversion time is the length of time required to convert the analog input voltage stored on the sample capacitor to a digital value. The conversion time must be long enough for the comparator and circuitry to settle and resolve the voltage. Excessively long conversion times allow the sample capacitor to discharge, degrading accuracy. The AD_TIME register programs the A/D sample and conversion times. Use the T SAM and TCONV specifica- tions in Tables 12 and 14 to determine appropriate values for SAM and CONV; otherwise, erroneous conversion results may occur. When the SAM and CONV values are known, write them to the AD_TIME register. Do not write to this register while a conversion is in progress; the results are unpredictable. Use the following formulas to determine the SAM and CONV values. where: SAM equals a number, 1 to 7 CONV equals a number, 2 to 31 T SAM is the sample time, in µsec (Tables 12 and 14) TCONV is the conversion time, in µsec (Tables 12 and 14) f is the operating frequency, in MHz B is the number of bits to be converted (8 or 10) At 40 Mhz, to meet TSAM and TCONV minimum specifications: 10-bit mode: 8-bit mode: SAM TSAM f2–× TCONV f× 3– 2B× S A M 567,,[]=T SAM 1µ s≥⇒ CONV 18 19 20 … 31,,,,[]=T CONV 10µs≥⇒ S A M 567,,[]=T SAM 1µ s≥⇒ CONV 23 24 … 31,,,[]=T CONV 10µs≥⇒

6.7.1 AC CHARACTERISTICS — A/D CONVERTER, 10-BIT MODE

Table 12. 10-bit A/D Operating Conditions (1)

  1. ANGND and V SS should nominally be at the same potential.
  2. V REF must not exceed VCC by more than + 0.5 V because VREF supplies both the resistor ladder and

the analog portion of the converter and input port pins.

  1. Program the AD_TIME register to meet the TSAM and TCONV specifications.

Table 13. 10-bit Mode A/D Characteristics Over Specified Operating Conditions (7) LSB , as used here, has a value of approximately 5 mV.

  1. Most parts will need these values at 25°C, but they are not tested or guaranteed.
  2. Multiplexer break-before-make guaranteed.
  3. Resistance from device pin, through internal multiplexer, to sample capacitor.
  4. Applying voltage beyond these specifications will degrade the accuracy of other channels being con-
  5. All conversions were performed with processor in idle mode.

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6.7.2 AC CHARACTERISTICS — A/D CONVERTER, 8-BIT MODE

Table 14. 8-bit A/D Operating Conditions (1)

  1. ANGND and V SS should nominally be at the same potential.
  2. V REF must not exceed VCC by more than + 0.5 V because VREF supplies both the resistor ladder and

the analog portion of the converter and input port pins.

  1. Program the AD_TIME register to meet the TSAM and TCONV specifications.

Table 13. 10-bit Mode A/D Characteristics Over Specified Operating Conditions (7) (Continued)

  1. An LSB , as used here, has a value of approximately 5 mV.
  2. Most parts will need these values at 25°C, but they are not tested or guaranteed.
  3. Multiplexer break-before-make guaranteed.
  4. Resistance from device pin, through internal multiplexer, to sample capacitor.
  5. Applying voltage beyond these specifications will degrade the accuracy of other channels being con-
  6. All conversions were performed with processor in idle mode.

Table 15. 8-bit Mode A/D Characteristics Over Specified Operating Conditions (7)

  1. An LSB , as used here, has a value of approximately 20 mV.
  2. Most parts will need these values at 25°C, but they are not tested or guaranteed.
  3. Multiplexer break-before-make guaranteed.
  4. Resistance from device pin, through internal multiplexer, to sample capacitor.
  5. Applying voltage beyond these specifications will degrade the accuracy of other channels being con-
  6. All conversions were performed with processor in idle mode.

34 ADVANCE INFORMATION

6.8 External Clock Drive

Figure 11. External Clock Drive Waveforms Table 16. External Clock Drive

  1. 16 MHz is the maximum input frequency when using an external crystal oscillator; however, 32 MHz

can be applied with an external clock source.

  1. These values represent PLL-bypass mode.

6.9 Test Output Waveforms

Figure 12. AC Testing Output Waveforms Figure 13. Float Waveforms During 5.0 Volt Testing level occurs with IOL /IOH ≤15 mA.

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7.0 THERMAL CHARACTERISTICS

210997) provides quality and reliability information.

9.0 DATASHEET REVISION HISTORY

  1. The status of the datasheet was revised from

“Product Preview” to “Advance Information”.

  1. The frequency designation was changed from
  2. The following DC characteristics specifications
  • I IDLE (max)
  • I OH 2
  • I OH 3 4. The following AC characteristics multiplexed bus mode specifications were changed: CHCL (max)
  • T LLCH (min/max)
  • T RLCL (max)
  • T CHWH (min)
  • T WHLH (max)
  • T AVYV (max)
  • T CLYX (max)
  • T WHQX (min)
  • T LLAX (min)
  • T RLDV (max) 5. The following AC characteristics demulti- plexed bus mode specifications were changed: AVDV (max)
  • T RLDV (max)
  • T SLDV (max)
  • T CHDV (max)
  • T XHCH min/(max)
  • T CHCL (min/max)
  • T CLLH (min/max)
  • T RLCL (min)
  • T RLRH (min)
  • T RHLH (max)
  • T WLCL (min)
  • T QVWH (min)
  • T CHWH (min)
  • T WLWH (min)
  • T WHQX (max)
  • T WHBX (min)
  • T RHBX (min)
  • T AVYV (max)
  • T CLYX (max) 6. The following AC characteristics demulti- plexed bus mode specifications were removed: LLCH
  • T LHLH
  • T LHLL
  • T WHLH 7. Address out line in the System Bus Timing Diagram (Demultiplexed Bus Mode) was cor- rected from A20:16 to A20:0. 8. T CHYX (max) timing was corrected in the Ready Timing Diagram to show the rising edge of READY after the falling edge of CLKOUT. 9. HOLD#/HLDA# timings section was removed, and all references to either HOLD# or HLDA# were removed. 10. Synchronous Serial timing specifications changed in table. 11. A/D sample and conversion times example added. 12. Note 1 of the 8-bit mode A/D characteristics table changed to state 20 mV, instead of 5 mV. This is the -001 version of the datasheet. The following changes were made in this version: 1. Package thermal characteristics changed.

Table 17. Thermal Characteristics