Microcontroller

8398

Intel Corporation

COMMERCIAL/EXPRESS HMOS MICROCONTROLLER

Manufacturer: Intel Corporation

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speed of a 16-bit microcontroller but are limited by board space and cost requirements to an 8-bit external bus. The 8X96 members are produced using Intel's HMOS-1i! process. multiply or 32/16 divide in 6.25 ys. Instruction execution times average 1 to 2 js in typical applications. simultaneously perform software timer functions. Up to four 16-bit software timers can be in operation at once. ’ channels to 10-bit digital values. With a 12 MHz crystal, each conversion takes 22 4s.

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Figure 1. 8X98 Block Diagram

With the commercial (standard) temperature option, STD-883, Method 1015. tended temperature range option, operational char- ature and extended burn-in designators. the specifications are the same for both options. own [rsitae (co) | [sore (oy | « seve or00. Figure 2. 8X98 Memory Map

8098/8398/8798 I ntel ® PACKAGING The 8098 is available in a 48-pin package with and without on-chip ROM or EPROM. The MCS-96 numbering system for the 8X98 devices is shown in Figure 4. Figure 6 shows the pinout for the 48-pin package. The 48-pin version is offered in a Dual-In-Line package Factory User Masked Programmable Figure 3, MCS®-96 Packaging—8098 Package Designators: Prefix Designators: C = Ceramic DIP T = Extended Temperature P = Plastic DIP L = Extended Temperature with 160 Hours Burn-in Paciage Tipe [ty [te]

481 Plastic DIP 38°C/W

Figure 4, 8X98 Thermal Characteristics All thermal impedance data is approximate for static air conditions at 1W of power dissipation. Values will change depending on operating conditions and application. See the Intel Packaging Handbook (Order Number 240800) for a description of Intel’s thermal impedance test methodology.

744 PRELIMINARY |

Figure 5. 48-Pin Package

8098/8398/8798 intel : PIN DESCRIPTIONS Main supply voltage (5V). Digital circuit ground (OV). There are two Vs pins, both of which must be connected. Veo RAM standby supply voltage (5V). This voltage must be present during normal operation. ina Power Down condition (.8. Voe drops to zora) if RESET is activated before Vor crops below spec and Vpp continues to be held within spec., the top 16 bytes in the Register File will retain their contents, VRer Reference voltage for the A/D converter (5V). Vper is also the supply voltage to the analog Portion of the A/D converter and the logic used to read Port 0. Must be connected for A/D and Port 0 to function. | Avene | Reference ground for the A/D converter. Must be held at nominally the same potential as Vss. Vpp Programming voltage for the EPROM devices. It should be 12.75V when programming and will float to 5V otherwise. The pin should not be above Vcc for ROM or CPU devices. This pin ‘must float in the application circuit on EPROM devices. XTAL1__| Input of the oscillator inverter and of the internal clock generator. Output of the oscillator inverter. Reset input to the chip. Input low for a minimum 10XTAL1 cycles to reset the chip. The subsequent low-to-high transition re-synchronizes CLKOUT and commences a 10-state-time RESET sequence. Input for memory select (External Access). EA equal to a TTL-high causes memory accesses to locations 2000H through 3FFFH to be directed to on-chip ROM. EA equal to a TTL-low causes accesses to these locations to be directed to off-chip memory. EA equal to + 12.75V Causes the device to enter the Programming Mode. ALE/ADV | Address Latch Enable or Address Valid output, as selected by CCR. Both pin options provide a latch to demultiplex the address from the address/data bus. When the pin is ADV, it goes inactive high at the end of the bus cycle. ALE/ADV is activated only during external memory accesses. [ FD __| Read signal output to external memory. FD is activated only during external memory reads. | WR | Write output to external memory. WA is activated only during external memory writes. READY | Ready input to lengthen external memory cycles. If the pin is low prior to the falling edge of CLKOUT, the memory controller goes into a wait mode until the next positive transition of CLKOUT occurs with READY high. When the external memory is not being used, READY has no effect. internal control of the number of wait states inserted into a bus cycle held not ready is available in the CCR. 7-46 PRELIMINARY |

intel ° 8098/8398/8798 PIN DESCRIPTIONS (Continued) Inputs to High Speed Input Unit. Four HSI pins are available: HS|.0, HSI.1, HSI.2 and Outputs from High Speed Output Unit. Six HSO pins are available: HSO.0, HSO.1, HSO.2, 4-bit high impedance input-only port. These pins can be used as digital inputs and/or as analog inputs to the on-chip A/D converter. [ Pot2 __| 4-bit multi-tunctional port. Its pins are shared with other functions in the 8098. Ports 3 and 4 | 8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the multiplexed address/data bus which has strong internal pullups. Ports 3 and 4 are also used as a command, address and data path by EPROM devices in the Programming Mode, | PMODE _| Determines the EPROM programming mode. PACT A low signal in Auto Programming Mode indicates that programming is in progress. A high signal indicates programming is complete. A low signal in Auto Programming Mode indicates that the device programmed correctly. SALE A falling edge in Auto Programming Mode indicates that Ports 3 and 4 contain valid programming address/command information (output from master). SPROG A falling edge in Auto Programming Mode indicates that Ports 3 and 4 contain valid programming data (output from master). [sio__| Assigns a pin of Ports 3 and 4 to each slave to pass programming verification. PALE ‘falling edge in Slave Programming Mode and Auto Configuration Byte Programming Mode indicates that Ports 3 and 4 contain valid programming address/command information (input to slave). PROG A falling edge in Slave Programming Mode indicates that Ports 3 and 4 contain valid programming data (input to slave). PVER A high signal in Slave Programming Mode and Auto Configuration Byte Programming Mode indicates the byte programmed correctly. PVAL A high signal in Slave Programming Mode indicates the device programmed correctly. A low signal in Slave Programming Mode indicates that the PROG pulse was applied for longer than allowed. 7 | PRELIMINARY 7-47

ves intel. ELECTRICAL CHARACTERISTICS NOTICE: This data sheet contains preliminary infor- ABSOLUTE MAXIMUM RATINGS* mation on new products in production. It is valid for the devices indicated in the revision history. The Ambient Temperature Under Bias —55°C to + 125°C _| specifications are subject to change without notice. Voltage trom EA or Vep ‘Maximum Ratings” may cause permanent damage. ‘Operating Conditions” is not recommended and ex- Voltage from Any Other Pin to tended exposure beyond the “Operating Conditions” NOTES: 1. This includes Vpp on ROM and CPU only devic- es. 2. Power dissipation is based on package heat transfer limitations, not device power consumption. OPERATING CONDITIONS (All characteristics specified in this data sheet apply to these operating conditions unless otherwise noted.) Ambient Temperature Under Bias CommercialTemp. | 0 | +70 | C | Ambient Temperature Under Bias Extended Temp. | 40 | +85 | C | Digital Supply Voltage | 450 | 550 [ov | Analog Supply Voltage | 450 | sso | ov | Oscillator Frequency [| so | 12 | we Power Down Sup Vinge aso [50] v NOTE: ANGND and Vsg should be nominally at the same potential. DC CHARACTERISTICS [-symbot | Parameter [Min | Max | Units | Test Conditions | tcc__| Voc Supply Current Commercial Temp. |_| 240 | mA | AllOutputs [tcc | YooSupplyGurentextended Temp. || 270_ | ma _| Disconnected | tcc___| Voc Supply Gurrent (Ta = 70°C) {| | tes | ma Vpp Supply Current Normal operation and Power-Down. Vaer Supply Current Commercial Temp. | | 8 [| ma | | | tact | Vaee Supply Curent Extended Temp. | | 10 | ma |__| 7-48 PRELIMINARY |

intel ° 8098/8398/8798 DC CHARACTERISTICS (Continued) ['Symbor[ Parameter | min | Max | units | Test Conditions Vin Input High Voltage Veo +05} V (except RESET, NMI, XTAL1) Input High Votage, RESET Faling Hysteresis | 21 |Voc+os| v [| lu Input Leakage Current to each pin of HSI, P3, +10 | pA | Vin = 0t0Voc P4, and to P2.1. DC Input Leakage Current to each pin of PO | | +3 | pa | Vin = 0 to Voc Ie Input Low Current to each pin of P1 and to HA | Vy = 0.45V P2.6, P2.7 Commercial Temp. he Input Low Current to each pin of Pt and to =150 | pA P2.6, P2.7 Extended Temp. Input Low Current to RESET [-o25| -2 | mA | Vi =0.45v Vo. —_ | Output Low Voltage on P3, P4 when used as. V_ | to, = 0.8 mA ports (Note 1) Voi: — | Output Low Voltage on P3, P4 when used as 0.75 V_ | lo. = 20mA Ports (Notes 1, 2, 3) Voz _ | Output Low Voltage on Standard Output Vv | to = 20mA pins, RESET and Bus/Control Pins (Notes 1, 2, 3) Vou: | Output High Voltage on Standard Output V | tox = —200 na pins and Bus/Control pins (Note 1) Output High Current on RESET [=so| | ua [Von=24v__ | Pin Capacitance (Any Pin to Vss) [| | _10 | oF | Frest = 1.0MHz NOTES: 1. Standard Output Pins include TXD, RXD (Mode 0 only), PWM, and HSO pins. Bus/Control pins include ALE, RD, WR, ADO-AD7 and AB-A15, 7 2. Maximum current per pin must be externally limited to the following values if Vo, is held above 0.45V. lo, on Ports 3 and 4 when used as ports: 4.0 mA lo. on standard output pins and RESET. 8.0 mA gt on Bus/Control pins: 2.0 mA 8. During normal (non-transient) operation the following limits apply: Total Io on P2.0, RESET and all HSO pins must not exceed 15 mA. Total Io on Port 3 must not exceed 10 mA. Total igi. on P2.5 and Port 4 must not exceed 20 mA. | PRELIMINARY 7-49

I ntel ° 8098/8398/8798 TIMING RESPONSES (8X98 devices meet these specs.) (Continued) EndotADIoALE/ADVHigh | Toso- 45 | |r| FDHightoAB-Atsinactve | Tosc- 25 | Toso +30 | ne | WRHigh to AB-A15 inactive | Toso- 50 | Toso +100 | ns__| ALE/ADVLowtoWRtow | Tosc— 40 | | ns ALE/ADV Low to WA Low 2Tosc+65_| ns | Output DatavaidtoWRlow | Tosco | | ns | Ouput Daa Vaid e WFitow | Tosc—90 [| —~| me | NOTES: 2. If more than one wait state is desired, add 3 Tosc for each additional wait state. 3. Max spec applies only to ALE. Min spec applies to both ALE and ADV. 4. The term “Address Valid" applies to ADO-AD7, A8-A15. 5. The term “Address” in this definition applies to ADO-AD7. 6. Write Strobe Mode is not selected. 7, Write Strobe Mode is selected. WAVEFORM—SYSTEM BUS TIMINGS tose de S/d a Tue wea cote Tan Qe RLRH we \\ Tay 1 } 7; Hox toon : baled 7 fam ——_ of Ton aos a eaennant i be Tatty Fart ti [Troe Twaex ——si" Trax meee n ee NOTES: 1. When ADV selected. 2. When Write Strobe Mode selected | PRELIMINARY 7-51

8098/8398/8798 I ntel ° WAVEFORM—Tripy Power Supply Rie Time 5.5¥o¢ vee 45% Stort Time from Power Supply Ree to External Output Low a, IAM — oe Prowr2s a a Pes Gaiies| [| | 780% External RESET Low to rot 270892-38 EXTERNAL CLOCK DRIVE [_svmbot | Parameter [win [Max [nts | | VToun | Oseitator Frequency | 6 || | Towox | Hightime ss [| Tovox | towtime | Ts [town | Reet [Town | rantime ss EXTERNAL CLOCK DRIVE WAVEFORMS ToHox ToLon ToHou 25 25) Touox 25 0.8 0.8 Tovot 270532-24 An external oscillator may encounter as much as a 100 pF load at XTAL1 when it starts up. This is due to interaction between the amplifier and its feedback capacitance. Once the external signal meets the Vy and Vy specifications the capacitance will not exceed 20 pF. 7-62 PRELIMINARY |

intel ° 8098/8398/8798 EXTERNAL CRYSTAL CONNECTIONS EXTERNAL CLOCK CONNECTIONS Gl watt Yoo Vss I = 8X9X wma EXTERNAL @ tock input —[ >O mat clock driver Quartz Crystal or 8X9X Ceramic Resonator "s70502-40 no connect —J xTAL2 NOTE: Keep oscillator components close to chip and use 270892-41 short, direct traces to XTAL1, XTAL2 and Vgs. When using crystals, C1 = 30 pF, C2 = 30 pF. When using ceramic resonators, consult manutacturer for recom- mended capacitor values. ‘AC TESTING INPUT, OUTPUT WAVEFORMS FLOAT WAVEFORMS

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Ex? 20 os 08 ous Vioa0"0.20¥ Vo.+0.20¥ 270592-25 on 27059226 AAC Testing inputs are driven at 2.4V for a Logic “1” and 0.45 for cor ing input or 8 Logi Timing Purposes a Port Pin is no Longer Floating when & a hoge “O,Timing messurmon 66 ade at 20V fr 8 Logle 200 mV change rom Loed Votage Gece and Boge 0 Fat won a 200 mV change from the Loaded Vow/Vo. Level occurs loullon 2 28 mA. MINIMUM HARDWARE CONFIGURATION CIRCUIT Ve or.oar —_ ‘ ast of — 4g cap “eer FT nowy OES EA 7 Ves? a7 uF SS" TAL) XTAL2 0.01 uF leur 30.5 so wns FL1SO oF ak = 270832-42 | PRELIMINARY 7-53

8098/8398/8798 intel . AC CHARACTERISTICS—SERIAL PORT—SHIFT REGISTER MODE SERIAL PORT TIMING—SHIFT REGISTER MODE Test Conditions: Load Capacitance = 80 pF | Tax | SerialPort Giock Period | Tosco =| |_| Serial Port Clock Falling Edge to Rising Edge Output Data Setup to Clock Rising Edge | 3stose | os | Output DataHold Atter Glock RisingEdge | 2Tosc—70 | | ns Next Output Data Valid After Glock RisingEdge | | 2Tosc +50 | ns _| | Tove | inputData Setup to CiockRisingEdge | 2Tosc +200 | | ns Input Data Hold After Clock Rising Edge re Last Clock Rising to Output Float es WAVEFORM—SERIAL PORT—SHIFT REGISTER MODE SERIAL PORT WAVEFORM—SHIFT REGISTER MODE LE L$ ee Toven >| [+ Trond Taney eyed fe Tenor Tavaz--} r tn CD CD CT CTD CD GD GED Gra i CD GD CD GD CTD GED CD) DD DD) DCD. DZD, 7082-23 7-54 PRELIMINARY |

10 Bits

Absolute Error Poe ses | Full Scale Error [-ossos | | ses [| | Zeroonserenor | os fT ts | [ Nontinearty PT ae ss Channelto-ChannelMatching | | oT et tse [| Repeatability [ soa | | tse | Temperature Coefficients: Offset 0.009 LSB/*C Full Scale 0.009 LSB/°C Differential Non-Linearity 0.009 LsB/°C Ott Isolation poo Re VogPowerSuppiyRejecton | -eo | | wT InputSeriesResistance | aK TK To || DC Input Leakage a | Sampledeay || 8 Toso 80 | sTosc +50 | ns | 2 | | Sampietime || 12 Toso = 80 | 12Tosc +50 | ns || Sampling Capacitor a NOTES: * These values are expected for most parts at 25°C. ** An "LSB", as used here, is defined in the MCS-96 A/D Converter Quick Reference and has a value of approximately S mv. 1, DC to 100 KHz. 7 2. For starting the A/D with an HSO Command. ‘3, Multiplexer Break-Before-Make Guaranteed. 4. Resistance from device pin, through internal MUX, to sample capacitor. | PRELIMINARY 7-55

8098/8398/8798 intel ° EPROM SPECIFICATIONS EPROM PROGRAMMING OPERATING CONDITIONS [__svmbot [Parameter |Min_ | Max | Unite | [ta | Ambiont Temperatura during Programming | 20_| 30 | -o_| [ Veo. Veo. Vner | Supply Voltages during Programming | 45 (| 55 | v_| [ven _____| Programming Mode SuppiyVotage | 80 | 130 | ve | | vep____| EPROM Programming SupplyVonage | 1260 | 130 | ve | | ves-ANGND® | DigtalandAnslogGrund | | | Fosct | Osciator Frequency during Auto and Siave Programming | 60 | 6.0 | MHz | ee NOTES: 1. Voc. Vpp and Vper should nominally be at the same voltage during programming. 2. Vea and Vpp must never exceed the maximum voltage for any amount of time or the device may be damaged. 3. Vgg and ANGND should nominally be at the same voltage (OV) during Programming. AC EPROM PROGRAMMING CHARACTERISTICS [ symbor [ Parameter Min | Max | Unite | | Tav__| ADDRESS/COMMANDVaidtoPALELow | 0 | + ‘Toso _| | Tuax | ADORESS/COMMANDHold AtterPALELOw [60 | ‘| _Tosc_| | Tove, | OuiputDataSeupBetoroPAOGLow | | | ‘Tose | | triox | DataHoldAtterPROGFating | 80 | S| CTosc | [tun | PaLePusewitm Eto | «Toso | [en [renew ee

144 Tosco

| Tune, [PALE High toPROGLow Taso || Tos | | Tew | PROGHighioNewtPateLow | 00 || Toso | Tenox | DataHoldAterPROGHgh | 80 | —Tosc | | Tew | PROGHightoPvER/PDOVaia | 00 || Toso | | Tuvn | PALELowtoPVER/POOHigh | 100 | | ‘Tose | | Trrov | PROGLowioVERIFICATION/DUMPDatavaid | 100 | —_—‘|‘Tosc_| [ Ton. | RESETHightoFistPALE Low (not shown) | 2000 | ——*(| Toso _| OC EPROM PROGRAMMING CHARACTERISTICS [_symbot [Parameter |Min | Max | Unite | L_te __| Ver Supply Gurent Whenever Programming) [| 100 | ma _| 7-66 PRELIMINARY |

intel ° 8098/8398/8798 WAVEFORM—EPROM PROGRAMMING \\y Tove. Tax + t> Trupx PORTS 5,4 Teh — TeHLL PROG Tave Tux Tew eeeee Tewox irc ae ee 700 val Va 27059297 DIFFERENCES BETWEEN THE red 28 one or more pin franaitions. “Entries” are 8X9XBH AND 8X98 ief as the recording of one or more events. A. The resolution is nine states instead of eight 1. CCB.1 must be set to a logical 0 on the 8X98. states. Events occurring on the same pin more 2. The following 8X9XBH pins and corresponding frequently than once every nine states may be functions are not available on the 8X98: lost. BUSWIDTH B. A mismatch between the nine state HSI resolu- cLKOUT tion and the eight state hardware timer causes one time-tag value to be skipped every nine timer INST counts. Events may receive a time-tag one count NMI later than expected. Port 0.0-0.3 (ACHO-3) C. If the FIFO and Holding Register are empty, the Port 1.0-1.7 first event will transfer into the Holding Register, ba leaving the FIFO empty again. The next event Port 2.6 that occurs will be the first event loaded into the Port 2.7 empty FIFO. If the first two events into an empty P2.3 (T2CLK) FIFO (not counting the Holding Register) occur ; ) coincident with each other, both are recorded as P2.4 (T2RST). ‘one entry with one time-tag. If the second event occurs within nine states after the first, the IA events will be entered separately with time-tags 8X98 ERRATA at least one count apart. If the second event en- ; ; ; ters the FIFO coincident with the “skipped time- Devices covered by this data sheet (see Revision tag situation (see B above) the time-tags will be History) have the following errata. at least two counts apart. 1. INDEXED, 3 OPERAND MULTIPLY 3, RESERVED LOCATION 2019H The displacement portion of an indexed, three oper- The 1990 Architectural Overview recommended that and (byte or word) multiply may not be in the range address 2019H be filled with hex value OFFH. The of 200H thru 17FFH inclusive. If you must use these recommendation is now 20H. displacements, execute an indexed, two operand multiply and a move if necessary. 4, RESERVED LOCATION 201CH 2. HSI FIFO OPERATION Reading reserved location 201CH, either internally or externally, will return ““201C” as data. The High Speed Input (HS!) has three deviations from the specifications. Note that “events” are de- | PRELIMINARY 7-87

8098/8398/8798 intel ; 5. SERL. T SE The following differences exist between the -005 ‘AL. PORT SECTION data sheet and the -004 data sheet. Serial Port Flags—Reading SP_STAT may not 4. Most of the functional description h . clear the TI or Rl fag if that flag was set within two" (howl of the Tunctionsl descrintion has been re- state times prior to the read. In addition, the parity tectural Overview error bit (RPE/RB8) may not be correct if it is read : : . ; within two state times after RI is set. Use the follow. 2. Information on programming the Chip Configura- ing code to replace ORB sp_image, SP_STAT. tion Register has been added. SP_READ: LDB TEMP, SP_STAT 3. Txnax changed from Min = 2 Togc — 50 ns to ORB SP_IMAGE, TEMP Min = 2 Tosc — 70 ns. JBS TEMP, 5, SPREAD; if 4. Touox changed from Min = 25 ns to Min = TI is set then read again 30 ns. JBS TEMP, 6, SPREAD; if 5. Added AC timi ificati larity Writ RI is set then read again Strobe Mode epecinnaeneston® 10 clarity Write ANDB SP_IMAGE,#7FH; clear f false RB8/RPE 6. The differences between the 8X9XBH and the ORB SP_IMAGE, TEMP; load 8X98 have been added. correct RB8/RPE 7. An errata has been added changing the recom- mendation for address 2019H from OFFH to 20H. DATA SHEET REVISION HISTORY Differences between the -004 and -003 data sheets. This data sheet (270532-008) is valid for devices 1. All EPROM programming mode information has with an “E” at the end of the topside tracking num- been moved to the Hardware Design Information ber. Data sheets are changed as new device infor- Chapter. mation becomes available. Verity with your local >. CCB RESET FETCH and JBS/JBC on Port 0 an- Intel sales office that you have the latest version amolies have been corrected on the current stop. before finalizing a design or ordering devices. pings of the 8X98. Th r 008 i nn 3. New information regarding T2CLK and new infor- 0 etferance betwaen -007 and -008 is the lo./lon mation about RESET of the Quasi Ports have for the float waveform testing changed trom +15 mAto +8 mA, been added to the Errata section. 4, The Extended Reset errata has been eliminated The following differences exist between (-007) data on the silicon and in the data sheet. Sheet and the (-008). 5. HSI Mode register is undefined until the user 1. The Express (extended temperature and burn-in code initializes this register. options) were added to this data sheet. The 8X98 i - Express data sheet (270914-002) is now obso- & Minimum DNL us now > —1 LSB. lete. 7. HSI FIFO overtlow description added. 2. Changes were made to the format of the data sheet and the SFR descriptions wore removed. Differences between the -002 and -003 data sheets, No specification changes were made. 1. All 8788 EPROM information has been added as 8. Added Reserved Location 201CH errata. complete section after the Analog Section. 2. The chip configuration byte values now indicate The following differences exist between the -006 the use of WRITE STROBE with 8-bit systems. data sheet and the -005 data sheet. Write Strobe design text was added to the expla- 1. The -005 data sheet was valid for devices nation, marked with a "D” at the end of the top side 3. The interrupt information now includes a worst tracking number. case timing diagram. 2. The following errata were removed: RESET and = 4. The EPROM 8798 was added as necessary the Quasi-Bidirectional Ports, Software RESET throughout the text. Timing, and Using T2CLK as the source for Tim- 5, NMI pin information was deleted. ore. ; 6. Reset Register Status was added and the state 3. The HSI FIFO Operation errata definition was of the HSO pins after RESET. changed to match a change in the HSI FIFO op- > 5 Giccram of the interrupt Pending Register is : now included 7-58 PRELIMINARY |

intel ° 8098/8398/8798 8. A diagram of the PSW Register was added. 10. The Differential Non-Linearity specification in 9. Viti was deleted. This was a RESET pin charac- the A/D converter specifications was corrected teristic that has been improved to match the oth- toread +2 LSBs. er characteristics. 11. Power On Reset — New information on Extend- ed Reset Time was added to the Errata Section. | PRELIMINARY 7-59

Product Information

8398 specifications and overview.

Summary

COMMERCIAL/EXPRESS HMOS MICROCONTROLLER

Description

COMMERCIAL/EXPRESS HMOS MICROCONTROLLER

Source title 8398 Datasheet(PDF) - Intel Corporation

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