82C54

82C54 INTEL | Alldatasheet

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Table 1. Pin Description connected to system data bus. CLK 0 9 10 I Clock 0: Clock input of Counter 0. OUT 0 10 12 O Output 0: Output of Counter 0. GATE 0 11 13 I Gate 0: Gate input of Counter 0. GND 12 14 Ground: Power supply connection. OUT 1 13 16 O Out 1: Output of Counter 1. GATE 1 14 17 I Gate 1: Gate input of Counter 1. CLK 1 15 18 I Clock 1: Clock input of Counter 1. GATE 2 16 19 I Gate 2: Gate input of Counter 2. OUT 2 17 20 O Out 2: Output of Counter 2. CLK 2 18 21 I Clock 2: Clock input of Counter 2. VCC 24 28 Power: a5V power supply connection. designed for use with Intel microcomputer systems. variable length delays can easily be accommodated.

After power-up, the state of the 82C54 is undefined.

11 Read-Back Command

0 1 Read/Write least significant byte only. 1 0 Read/Write most significant byte only. compatibility with future Intel products.

0 Binary Counter 16-bits

1 Binary Coded Decimal (BCD) Counter

Figure 7. Control Word Format

written before the initial count is written. nificant byte and then most significant byte). must follow the programmed count format. be loaded with an incorrect count. In all four examples, all counters are programmed to read/write two-byte counts. These are only four of many possible programming sequences. Figure 8. A Few Possible Programming Sequences Latch Command, and the Read-Back Command. when it is read, giving an undefined result.

read-back command was issued. some hardware from a system. Figure 11. Status Byte count goes to 1 when the second byte is written. Figure 12. Null Count Operation read-back command was issued. first are ignored. This is illustrated in Figure 13.

11000010 Read back count and status of Count and status latched

11100100 Read back status of Counter 1 Status latched for Counter 1

11101100 Read back status of Counters 2, 1 Status latched for Counter

11011000 Read back count of Counter 2 Count latched for Counter 2

11000100 Read back count and status of Count latched for Counter 1,

11100010 Read back status of Counter 1 Command ignored, status

Figure 13. Read-Back Command Example

1 X X X X No-Operation (3-State)

Figure 14. Read/Write Operations Summary that order, of a Counter’s CLK input. counting. GATE has no effect on OUT. 1) Writing the first byte does not disable counting. be loaded on the next CLK pulse. and rolled over to FFFFh, WILL stop the counter. a 1 CLK pulses after the new count of N is written.

loads the initial count and the process is repeated. Figure 17. Mode 2 counting cycle. In mode 2, a COUNT of 1 is illegal. Mode 3 is typically used for Baud rate generation. used to synchronize the Counter. at the end of the current half-cycle.

a1 CLK pulses after a trigger. counting will continue from there. Figure 20. Mode 5

0 Disables Ð Enables

4 Disables Ð Enables

Figure 21. Gate Pin Operations Summary Figure 22. Minimum and Maximum initial Counts

Operation Common to All Modes Programming When a Control Word is written to a Counter, all Control Logic is immediately reset and OUT goes to a known initial state; no CLK pulses are required for this. GATE The GATE input is always sampled on the rising edge of CLK. In Modes 0, 2, 3, and 4 the GATE input is level sensitive, and the logic level is sampled on the rising edge of CLK. In Modes 1, 2, 3, and 5 the GATE input is rising-edge sensitive. In these Modes, a rising edge of GATE (trigger) sets an edge-sensi- tive flip-flop in the Counter. This flip-flop is then sam- pled on the next rising edge of CLK; the flip-flop is reset immediately after it is sampled. In this way, a trigger will be detected no matter when it occursÐa high logic level does not have to be maintained until the next rising edge of CLK. Note that in Modes 2 and 3, the GATE input is both edge- and level-sensi- tive. In Modes 2 and 3, if a CLK source other than the system clock is used, GATE should be pulsed immediately following WR of a new count value. COUNTER New counts are loaded and Counters are decre- mented on the falling edge of CLK. The largest possible initial count is 0; this is equiva- lent to 2 16 for binary counting and 10 4 for BCD counting. The Counter does not stop when it reaches zero. In Modes 0, 1, 4, and 5 the Counter ‘‘wraps around’’ to the highest count, either FFFF hex for binary count- ing or 9999 for BCD counting, and continues count- ing. Modes 2 and 3 are periodic; the Counter reloads itself with the initial count and continues counting from there.

ABSOLUTE MAXIMUM RATINGS * Ambient Temperature Under Bias.ÀÀÀÀÀÀ0 §Ct o7 0 §C Storage Temperature ÀÀÀÀÀÀÀÀÀÀÀÀ b65§ to a150§C Supply Voltage ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b0.5 to a8.0V Operating Voltage ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ a4V to a7V Voltage on any InputÀÀÀÀÀÀÀÀÀÀGND b2V to a6.5V Voltage on any Output ÀÀGND b0.5V to V CC a 0.5V Power Dissipation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1 Watt NOTICE: This is a production data sheet. The specifi- cations are subject to change without notice. *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability. D.C. CHARACTERISTICS (TAe0§Ct o7 0 §C, V CCe5Vg 10%, GND e0V) (T A eb 40§Ct o a85§C for Extended Temperature) Symbol Parameter Min Max Units Test Conditions VIL Input Low Voltage b0.5 0.8 V VIH Input High Voltage 2.0 V CC a 0.5 V VOL Output Low Voltage 0.4 V I OL e 2.5 mA VOH Output High Voltage 3.0 V I OH eb 2.5 mA VCC b 0.4 V I OH eb 100 mA IIL Input Load Current g2.0 mAV INeVCC to 0V IOFL Output Float Leakage Current g10 mAV OUTeVCC to 0.0V ICC VCC Supply Current 20 mA Clk Freq e 8MHz 82C54 10MHz 82C54-2 ICCSB VCC Supply Current-Standby 10 mA CLK Freq e DC CS e VCC. All Inputs/Data Bus V CC All Outputs Floating ICCSB1 VCC Supply Current-Standby 150 mA CLK Freq e DC CS e VCC. All Other Inputs, I/O Pins e VGND, Outputs Open CIN Input Capacitance 10 pF f c e 1 MHz CI/O I/O Capacitance 20 pF Unmeasured pins COUT Output Capacitance 20 pF returned to GND (5) A.C. CHARACTERISTICS (TA e 0§Ct o7 0 §C, V CC e 5V g10%, GND e0V) (T A eb 40§Ct o a85§C for Extended Temperature) BUS PARAMETERS (Note 1) READ CYCLE Symbol Parameter 82C54-2 Units Min Max tAR Address Stable Before RD v 30 ns tSR CS Stable Before RD v 0n s tRA Address Hold Time After RD u 0n s tRR RD Pulse Width 95 ns tRD Data Delay from RD v 85 ns tAD Data Delay from Address 185 ns tDF RDuto Data Floating 5 65 ns tRV Command Recovery Time 165 ns NOTE: 1. AC timings measured at V OH e 2.0V, V OL e 0.8V.

A.C. CHARACTERISTICS (Continued) WRITE CYCLE Symbol Parameter 82C54-2 Units Min Max tAW Address Stable Before WR v 0n s tSW CS Stable Before WR v 0n s tWA Address Hold Time After WR u 0n s tWW WR Pulse Width 95 ns tDW Data Setup Time Before WR u 95 ns tWD Data Hold Time After WR u 0n s tRV Command Recovery Time 165 ns CLOCK AND GATE Symbol Parameter 82C54-2 Units Min Max tCLK Clock Period 100 DC ns tPWH High Pulse Width 30 (3) ns tPWL Low Pulse Width 50 (3) ns TR Clock Rise Time 25 ns tF Clock Fall Time 25 ns tGW Gate Width High 50 ns tGL Gate Width Low 50 ns tGS Gate Setup Time to CLK u 40 ns tGH Gate Hold Time After CLK u 50(2) ns TOD Output Delay from CLK v 100 ns tODG Output Delay from Gate v 100 ns tWC CLK Delay for Loading (4) 05 5n s tWG Gate Delay for Sampling (4) b54 0 n s tWO OUT Delay from Mode Write 240 ns tCL CLK Set Up for Count Latch b40 40 ns NOTES: 2. In Modes 1 and 5 triggers are sampled on each rising clock edge. A second trigger within 70 ns for the 82C54-2 of the rising clock edge may not be detected. 3. Low-going glitches that violate t PWH,t PWL may cause errors requiring counter reprogramming. 5. Sampled not 100% tested. T A e 25§C. 6. If CLK present at T WC min then Count equals N a2 CLK pulses, T WC max equals Count N a1 CLK pulse. T WC min to TWC max, count will be either N a1o rN a2 CLK pulses. 7. In Modes 1 and 5, if GATE is present when writing a new Count value, at T WG min Counter will not be triggered, at T WG max Counter will be triggered. 8. If CLK present when writing a Counter Latch or ReadBack Command, at T CL min CLK will be reflected in count value latched, at T CL max CLK will not be reflected in the count value latched. Writing a Counter Latch or ReadBack Command between T CL min and T WL max will result in a latched count vallue which is g one least significant bit. EXTENDED TEMPERATURE (TA eb 40§Ct o a85§C for Extended Temperature) Symbol Parameter 82C54-2 Units Min Max tWC CLK Delay for Loading b25 25 ns tWG Gate Delay for Sampling b25 25 ns

231244–14 READ 231244–15 RECOVERY 231244–16

231244–17 * Last byte of count being written A.C. TESTING INPUT, OUTPUT WAVEFORM INPUT/OUTPUT 231244–18 A.C. Testing: Inputs are driven at 2.4V for a logic ‘‘1’’ and 0.45V for a logic ‘‘0.’’ Timing measurements are made at 2.0V for a logic ‘‘1’’ and 0.8V for a logic ‘‘0.’’ A.C. TESTING LOAD CIRCUIT 231244–19 CL e 150 pF CL includes jig capacitance REVISION SUMMARY The following list represents the key differences be- tween Rev. 005 and 006 of the 82C54 Data Sheet. 1. References to and specifications for the 8 MHz 82C54 are removed. Only the 10 MHz 82C52-2 remains in production.