82C501AD INTEL | Alldatasheet
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Table 1. Pin Description floating, an internal pull-up resistor biases the input inactive high. CLSN/CLEN or on ROV/ACV will force CRS active. test. The [PBK signal should be driven high once Vcc is stabilized. through a 1 k2 resistor will disable the on-chip watchdog timer. received bit stream is assumed to be Manchester encoded. RCV/RCV inputs. When NOOR ~ 0, CAS is not inhibited.
7 COLLISION DETECT: An active-low, MOS-level signal which drives
(heartbeat) test in loopback. lock. During idle (no incoming frames) FXC is forced low.
13 RECEIVE DATA: A MOS-level output tied directly to the RXD input of
the controller, This output remains high during idle.
Table 1. Pin Description (Continued) Xe 13 driven by an external MOS level input clock. serial data output, TXD, of the Intel LAN Controller. TRMT | 18| 27 of the transceiver cable. The output bit stream is Manchester encoded. ENETV1 is asserted this voltage stepping is disabled.
20 MHz parallel resonant crystal is used to control pends on the PC Weel fareneneis, theetons ab
Itis recommended that a crystal meeting the follow Petween 22 and 35 pF.
- Quartz Crystal plied to pin X; while pin Xp is left floating.
- M-Tron Industries, Inc by two to produce the 10-MHz clock required by the
Figure 3. Start of Transmission and Manchester Encoding going low. Since the first bit is a ‘1’, the first tran- cation. delay is introduced by the 82C501AD between its SQE (heartbeat) test. sition. The undershoot for return to idle is less than _ before the transmission ends, the frame is aborted.
(including the IEEE 802.3 transceiver transformers) _ure 4. signal by the Manchester decode circuitry. For best operation, a decoupling capacitor should be used between Voc and GND. Figure 4. LAN Controller/82C501AD/Transceiver Interface
intel. 82C501AD ETHERNET The input circuits can also be driven with ECL volt- jitter. Slow phase variations, such as those caused age levels. In either case, the input common mode by small differences between the data frequency voltage must be in the range of 0-Vcc volts to allow and the clock frequency, are passed unfiltered by for wide driver supply variation at the transceiver. To the low-pass filter. provide additional high voltage protection, if the ca- ble is shorted, an isolation transformer can be used The AXC generator digitally sets the phases of the to isolate the RCV and RCV inputs from the cable. two RXC transitions to respectively lead and lag the bit-center transition by 1/4 bit time. RXC is used to recover RXD by sampling the incoming data with an Manchester Decoder and Clock edge-triggered flip-flop. Recovery oo The Frame__Detect signal informs the decoder that ‘The Manchester-encoded data stream is decoded to _the first valid negative transition of a new frame has separate the Receive Clock (RXC) and the Receive been detected. This signal is used to initiate the Data (RXD) from the stream. The 82C501AD uses _lock-on sequence of the decoder. Lock is achieved an advanced digital technique to perform the decod- _by reducing the time constant of the digital filter to ing function. The use of digital circuitry instead of zero at the start of a new frame. With a time con- analog circuitry (e.g., a phase-lock loop) to perform stant of zero, the filter immediately outputs the the decoding ensures that the decoding function is __ phase of the second bit-center transition. Any uncer- less sensitive to variations in operating conditions. tainty in the bit-center phase of the first transition . that is caused by jitter is subsequently removed by A simplified diagram of the decoder appears in Fig- gradually increasing the filter time constant during ure 5. A high-resolution phase reference is used to _the following preamble. By that time, the exact digitize the phase of the incoming data bit-center _ phase of the bit center is output by the filter, and the transition. The digitizer has a phase resolution of —_ lock is achieved. Lock is achieved within the first 14 1/32 bit time. bit times as seen by the RCV/RCV inputs. The maxi- mum bit-cell timing distortion (jitter) tolerated by the The digitized phase is filtered by a digital low-pass Manchester Decoder Circuitry is + 12 ns for the pre- filter to remove rapid phase variations; i.e., phase amble and + 18 ns for the data. 1OMHz HIGH SOLUTION REFERENCE MANCHESTER > PHASE LOW-PASS C> Rrxc oicmizeR FILTER oe | ts ak FRAME, oerecr) 231926-11 Figure 5, Manchester Decoder 1-318,
intel. 82C501AD ETHERNET 7 © The filter is turned on again when no positive COLLISION-PRESENCE SECTION The iter {s tumed on again when no positive The CLSN/CLSN input signal is a 10 MHz +25%/ for 160 ns. —15% square-wave generated by the transceiver whenever two or more data frames are superim- posed on the coaxial cable. The pulse width of the Internal Loopback CLSN/CLSN signal can be no less than 35 ns and : No greater than 70 ns measured at the 0-V crossing. | When asserted, [PBK causes the 82C501AD to route serial data from its TXD input through its trans- The common-mode wonage.and external termination mit logic (retiming and Manchester encoding); re- are identical to the RCV/RCV input. (See Figure 4.) turning it through the receive logic (Manchester de- coding and receive clock generation) to RXD output. A valid collision presence signal will assert the The internal routing prevents the data from passing 82C501AD CDT output, which can be directly tied to through the. output drivers and onto the transmit out- i] the CDT input of the Intel LAN Controller. During —_put pair TRMT/TRMT. When in loopback mode all of normal operation the 82C501AD logically “ORs” the —_the transmit and receive circuits, are tested except collision presence signal with an internal sig indi- for the transceiver cable output driver and input re- cating valid data reception on the RCV/I ACY pair. to ceivers. Also, at the end of each frame transmitted generate CRS output. If, however, the input in loopback mode the 82C501AD generates the is asserted low, this “OR” function is removed and —_SQE test (heartbeat) signal within 1 ys after the end CRS is only asserted by the presence of valid data of the frame. Thus, the collision circuits are also ‘on the RCV/RCV pair. This mode of operation is tested in loopback mode. During loopback, as in any required for repeater design. normal reception, the 82C501AD receive circuitry uses 14 bit times while the Manchester Decoder During the time that valid collision-presence tran- _iocks on the data. As a result, the first 14 bits are sitions are present on the CLSN/CLEN input, invalid Jost and XC is held low during that time. data transitions may be present on the receive data Pair due to the superposition of signals from two or The watchdog timer remains enabled in loopback more stations transmitting simultaneously. It is pos- mode, terminating test frames that exceed its time- sible for RCV/FICV to lose transitions for a few bit out period. The watchdog timer can be inhibited by times due to perfect cancellation of the signals; this connecting LPBK to a 1 kMt resistor connected to 10 may cause the 82C501AD to abort the reception. to 16V. The loopback feature can still be used to test in it if i ircuit The CRE signal is asserted low (along with CDT) 7°, maegeee. 82C501AD by using the circui whenever a valid collision-presence signal is present and NOOR = 1. If this collision-presence signal ar- rives within 5 4s to 7 ys after the last transmission, s10v te s16v only CDT is generated. This ensures that the LAN Voc Controller recognizes the active COT as a valid SQE (heartbeat) test signal. 10K 1K ‘82C501AD TFRK/woro NOISE FILTERING ON RCV AND woro So \\ CLSN PAIRS > T Both the receive and collision pairs have the follow- vex >—fSo ing characteristics. * At idle, the noise filter is turned on. += Open Collector 231826-6 * A pulse is rejected if: a. Its peak voltage is more positive than -150 mV. [Tpex | woTD | Function | with no restriction on width, or: LPBK wero bts peak vot sive than 600 mvt} —X | bPBKmode | . Its peak voltage is more positive than —600 mi and its width is loss than Se (measured atarefer- | 0 | 0 | Normalmode | ence level of — 285 mV). Normal mode with © The filter is turned off by the first valid negative watchdog timer disabled pulse on the RCV or CLSN pair. A pulse whose peak voltage is more negative than —300 mV Figure 6. Watchdog Timer Disable Sr eee a) 8 condoned vata. (MP8S4E4 The B2C5O1AD operates as a fullduplex device, be- ing able to transmit and receive simultaneously. By 1-319
intel . 82C501AD ETHERNET combining the internal and external loopback modes —_If additional high voltage protection is desired, a of the Intel LAN Controller, and the internal loop- —_ pulse transformer should be included for Ethernet back and normal modes of the 82C501AD, incre- applications, IEEE 802.3 10BASES (Ethernet) speci- mental testing of an Intel LAN Controller/ fications require at least 16V protection for the 82C501AD-based interface can be performed under Transmit, Receive, and Collision pairs. In 10BASE2 Program control for systematic fault detection and (Cheapernet) a pulse transformer is required to be fault isolation. inserted between the DTE (Intel LAN Controller/ 82C501AD) and the transceiver. In an Ethernet/ Cheapernet design, a single transformer can be Interface Example used for both connections at minimal additional cost. The 82C501AD is designed to work directly with the The pulse transformer should have the following Intel LAN Controller in IEEE 802.3 10 Mb/s, as well characteristics: as other 10 Mb/s LAN applications, The control and 7 data signals connect directly between the two devic-_ 1 A Minimum inductance of 75 wH. es without the need for additional external logic. The 2. 2000V isolation between primary and secondary complete Intel LAN Controller/82C501AD Ethernet windings. Transceiver interface is shown in Figure 4. The 3, 2000V isolation between primaries of separate 82C501AD provides the driver and receivers needed transformers. to directly connect to the transceiver cable or requir- ing only terminating resistors on each input signal _Since Ethernet Version 1.0 transceivers can require Pair and 2402 pull-down resistors. a positive differential on the TRMT pair during idle, check with the transceiver vendor before including It is recommended that a decoupling capacitor be _the pulse transformer. used between Voc and GND. The Transmit, Receive, and Collision pairs have a maximum 10V overvoltage protection. 1-320
intel. 82C501AD ETHERNET ABSOLUTE MAXIMUM RATING* NOTICE: This is a production data sheet. The specifi- r ‘ . cations are subject to change without notice. Allin vot So etoae® =1.0V to +6.0vi1) Operating Conditions” is not recommended and ox. D.C. CHARACTERISTICS Tc = 0°C to + 85°C, Voc = 5V +10% Vit Input Low Voltage TL -0.5V 0.8V MOS -0.5V o6v Vin Input High Voltage TTL 20V Voc + 0.5V MOS 3.9V Voc + 0.5V Differential Input Accept Voltage | szssmv [| Differential input Reject Voltage | tomy | Input Common Mode Vottago Common Mode Output Vottaget®) Output High Voltage (MOS) @ lon = =800nA | aev [| Differential Output Voltage) £0.45V Vu TRMT Pair Differential Return to _ TRMT Pair Differential Idle Voltage(2) [| e40mve Input Leakage Current @ Vw = OVtoVec® | | et0wa | Input Load Current) [ttm | Input Capacitance @ fo = 1 MHz(?) [tone | NOTES: 1. The voltage levels for CLSN/CLSN, RCV/RCV inputs are —0.75V to + 10V. 2. The testing load is a 78 41% resistor in parallel with a 27 wH + 1% inductor and two 2400 +5% pulldown resistors. 3. Applies to TXD and TEN pins. 4. Part of the power is dissipated through the pulldown resistors connected to the TRMT/TRMT outputs. 5. Measured after tyg has expired. 6. Applies to RCV/ACY. X1, CLSN/CLSN, LPBK/WDTD, NOOR, and ENETV7 inputs for input voltages from OV to Voo. 7. Characterized, not tested. 1-321
intel. 82C501AD ETHERNET A.C. MEASUREMENT CONDITIONS Clock Timing(1) 1. Te = O°C to +85°C, Voo = BV #10%. [ Symbot | Parameter | win | Max | Unit] 2, The AC MOS, TTL and differential signals arere- | _ty__| Xr Cyclo Time_| 49.995 | 50.005 | ns | ferred to in Figures 7, 8, 9, 10 and 10A. Te | Xj Fall Timel2) r [5 | rs | 3. AC Loads: a) MOS: a 20 pF total capacitance to ground, i b) Ditforentia: a 10 pF total capacitance trom | 4 | Xitowtime® | 1s | | rs | each terminal to ground, two 2409 +5% pull [ts | X+ High Time | down resistors, and a load resistor of 780. ‘s stignTine® | is || ne | 1% in parallel with a 27 wH +1% inductor —_NoTES: between terminals. 1. Refer to Figure 9. 4, AIlAC Parameters become valid 100 ys after the 2: Applies to external clock inputs. supply voltage has stabilized. TRANSMIT TIMING(1) [6 | TRC cycle Time | 99.90 | 10001 | ns_| TRC Riso/Fall Time | fs | ns | [to | TCtowtime wo Ts [to | TC High Time [| 4 [| ns | Trane Enable /Daable wo THC Low a | te | TxD Stable to TXC Low Pas [rs | | tra | Bit CellCenter to Bit Coll Genter of Transmit Pair Data) [99.5 | 1005 | ns | | tis __| Transmit Differential Signal Rise/Fall Time [| so | ns | [tie __| Bit Cell Center to Bit Cell Boundary of Transmit Pair Data) | 495 | 505 | ns_| tW7 TRMT held low trom Last Positive Transition of the Transmit Pair at the End of Frame From Last Positive Transition of Transmit Pair Differential 8000 Output Approaches Within 40 mV of zero volts. Notes: 1. Refer to Figure 11. 2. This parameter is exactly twice t;. 3. Characterized, not tested. 1-322
intel. 82C501AD ETHERNET RECEIVE TIMING(1) [ tio | Duration which the FXC is held at Low State at the StartofaPacket__ |__| 1400 | ns | | too __| Receive Pair Signal Rise/Fall Time(S) [| 10 | rs | Receive Pair Bit Cell Center Jitter in Preamble) [| 12 [ns | | tz2___| Receive Pair Bit Cell Center Jitter in Datal2) |_| #18 | ns | | ta _| Receive Idle Time after Transmission in a Transmitting Station [es | [os | Receive Pair Signal Return to Zero Level from Last Valid Positive Transition { tes TRE Assertion Delay from the First Received Valid Negative Transition of Receive Pair Signal TRS Deassertion Delay from the Last Valid Positive Transition Received (when no Collision-Presence Signal Exists on the Transceiver Cable)(9) PKC Cycle Time [26 | 104 | ns | bes | REGLowTine i re | [tar __| Receive Data Stable Before the Negative Edge of AXC [30 | | ns | Receive Data Held Valid Past the Negative Edge of XC [30 | | ns | [tsa __| Carrier Sense Active — Inactive Hold Time from AXC High [10 | 40 | ns | | ts4 | Receive Data Rise/Fall Time( [| 10 | ns | Ltas___ | GRS inhibit Time After Frame Transmission(®) Ls | 7 [os | NOTES: 1. Refer to Figures 12 and 13. 3. CRS is deasserted synchronously with the RXC. This condition is not specified in the IEEE 802.3 specification. 4. Required for SQE test. Applies when NOOR = 1. For NOOR = 0 there is no inhibit of CRS. 5. Characterized, not tested. 1-328
intel. 82C501AD ETHERNET COLLISION TIMING(1) CLSN/CLSN Rise/Fall Time(?) [| 10 | ns | GLSN Pair Return to Zero from Last Positive Transition [160 [ | ns | SDT Assertion from the First Valid Negative Edge of Collision Pair Signal | | 75 | ns | EDT Deassortion from the Last Positive Edge of CLSN/CLSN Signal |__| 300 | ns | ta TRE Deassertion from the Last Positive Edge of CLSN/CLSN Signal (if no Post-Collision Signal Remains on the Receive Pair) NOTE: 1. Refer to Figure 14. 2. Characterized, not tested. LOOPBACK TIMING(1) TPB asserted before the first attempted transmission 2) [500] | ns | Simulated collision test delay from the end of each attempted transmission | 0.5 | 1.5 | us | Simulated collision test duration(®) [os | 16 | us | TPBK deasserted after the last attempted transmission [5s [| os | NOTES: 1, Refer to Figure 15. 2. In Loopback mode, RXC and CRS function in the same manner as a normal Receive. 3. SQE test (heartbeat) signal NOISE FILTER() ACV/ACY Noise Fiter Pulse Wisth ejected ||| ns CLSN/GTER Noo Fit Puse wan acconied [a5 [| NOTE: 1, Refer to Figure 16. 1-324
intel. 82C501AD ETHERNET RECEIVE TIMING: END OF FRAME | 0 | ° | RCV = — = — J} eo [4 i tas {?. my = = fry 26 Aa = — RC ° 1 tss, RXD \\ L..2 A Figure 13 COLLISION TIMING SEEK Od ——
88 OOO OOO} >
tao: tye. tarey cor -/ t42—oy RS / Figure 14 1-327
intel. 82C501AD ETHERNET ee
20 LEAD CERDIP DUAL IN-LINE PACKAGE INTEL TYPE D
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intel. 82C501AD ETHERNET PLASTIC LEADED CHIP CARRIER RECTANGULAR p78 eT emtcon Ge AG 2G 9S worm suwace ; o rey " aucromsce TS Ay a | oan a a — poe cn — searma rune ==” ;tmenaon | a Tn Overall Height (A) [ore | oro | azo | ase | |__ShouldertoBoardHeight (Any | 0.076 | oon | 193 | eae | [Outside Dimension (o) =| ses | oases | ave | 10.0 | Plastic Body Dimension (D1) [ose | ossa [eer | aor Foot Print (O2) ozo [oss | 7a7_ | sae | Foot Print (Ds) Outside Dimension (E) | oses [oes | so | t81 | | Platic Body Dimension) | oa? | ose | t39 | 140 | Footprint ey |= aso | oso | tea] ts | Foot Print (E) # of Leads (N) [ew #otleadsonShonSide(N) | 8 | #ofleadsontongsideN) [| | Seating Plane Goplanariy(cP) | __0.000 | aoa | ono | oto Twoezing Coplanarity (TCP) [0000 [oooe | 0.000 | oto Lead Thickness (LT) | o009 | oors | ozs ose 1-330