82C288

M82C288 INTEL | Alldatasheet

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separate data enable and direction control signals. Figure 1. M82C288 Block Diagram

20 Pin Cerdip Package

Figure 2. M82C288 Pin

Table 1. Pin Description The following pin function descriptions are for the M82C288 bus controller. LOW at the falling edge of CLK. Setup and hold times must be met for proper operation. times must be met for proper operation. strapping option and not dynamically changed. controller for each bus cycle in a system where the CPU has more than one bus it can use. inputs affect CENL. Setup and hold times must be met for proper operation. command. This input has no effect on M82C288 control outputs. READY I READY indicates the end of the current bus cycle. READY is an active LOW input. must be LOW during reset, to force the M82C288 into the idle state.

Table 1. Pin Description (Continued) outputs of the bus controller. CEN/AEN inputs may be asynchronous to CLK. command outputs into 3-state OFF and DEN inactive (LOW). input which allows the bus controller to activate its command and DEN outputs. for the halt bus cycle and is not affected by any of the control inputs. latches which save the cascade address on the falling edge of ALE. cycles in the MULTIBUS I mode. affected by any of the control inputs. IOWC O I/O WRITE COMMAND instructs an I/O device to read the data on the data bus. controls when it becomes inactive. IORC O I/O READ COMMAND instructs an I/O device to place data onto the data bus. controls when it become inactive. controls when it becomes inactive. when this output becomes active. READY controls when it becomes inactive.

Table 2. Command and Control Outputs for Each Type of Bus Cycle input is strapped HIGH, MULTIBUS I timing is used. the timing of the command and DEN outputs. ing interrupt acknowledge cycles. ate from DC to the appropriate upper frequency limit.

The clock may be stopped in either state (HIGH/ LOW) and held there indefinitely. Power dissipation is directly related to operating fre- quency. As the system frequency is reduced, so is the operating power. When the clock is stopped to the M82C288, power dissipation is at a minimum. This is useful for low-power and portable applica- tions. FUNCTIONAL DESCRIPTION

Description

The M82C288 bus controller is used in M80286 sys- tems to provide address latch control, data trans- ceiver control, and standard level-type command outputs. The command outputs are timed and have sufficient drive capabilities for large TTL buses and meet all IEEE-796 requirements for MULTIBUS I. A special MULTIBUS I mode is provided to satisfy all address/data setup and hold time requirements. Command timing may be tailored to special needs via a CMDLY input to determine the start of a com- mand and READY to determine the end of a com- mand. Connection to multiple buses are supported with a latched enable input (CENL). An address decoder can determine which, if any, bus controller should be enabled for the bus cycle. This input is latched to allow an address decoder to take full advantage of the pipelined timing on the M80286 local bus. Buses shared by several bus controllers are sup- ported. An AEN input prevents the bus controller from driving the shared bus command and data signals except when enabled by an external MULTI- BUS I type bus arbiter. Separate DEN and DT/R outputs control the data transceivers for all buses. Bus contention is eliminat- ed by disabling DEN before changing DT/R . The DEN timing allows sufficient time for tristate bus driv- ers to enter 3-state OFF before enabling other driv- ers onto the same bus. The term CPU refers to any M80286 processor or M80286 support component which may become an M80286 local bus master and thereby drive the M82C288 status inputs. Processor Cycle Definition Any CPU which drives the local bus uses an internal clock which is one half the frequency of the system clock (CLK) (see Figure 3). Knowledge of the phase of the local bus master internal clock is required for proper operation of the M80286 local bus. The local bus master informs the bus controller of its internal clock phase when it asserts the status signals. Status signals are always asserted beginning in Phase 1 of the local bus master’s internal clock. M82C284 271077–3 (FOR REFERENCE) Figure 3. CLK Relationship to the Processor

selected bus controller (CENL was latched HIGH). than provided by the basic command output timing. put can delay the activation of command outputs. Figure 12. System Use of AEN and CENL

CMDLY is first sampled on the falling edge of the CLK ending T S. If sampled HIGH, the command out- put is not activated, and CMDLY is again sampled on the next falling edge of CLK. Once sampled LOW, the proper command output becomes active immediately if MB e 0. If MB e 1, the proper com- mand goes active no earlier than shown in Figures 9 and 10. READY can terminate a bus cycle before CMDLY allows a command to be issued. In this case no commands are issued an the bus controller will de- activate DEN and DT/R in the same manner as if a command has been issued. Waveforms Discussion The waveforms show the timing relationships of in- puts and outputs and do not show all possible tran- sitions of all signals in all modes. Instead, all signal timing relationships are shown via the general cas- es. Special cases are shown when needed. The waveforms provide some functional descriptions of the M82C288; however, most functional descriptions are provided in Figures 5 through 11. To find the timing specification for a signal transition in a particular mode, first look for a special case in the waveforms. If no special case applies, then use a timing specification for the same or related func- tion in another mode.

ABSOLUTE MAXIMUM RATINGS * Case Temperature Under Bias ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b55§Ct o a125§C Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b65§Ct o a150§C Voltage on Any Pin with Respect to GND ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b0.5V to a7V Power Dissipation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1 Watt NOTICE: This data sheet contains information on products in the sampling and initial production phases of development. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest data sheet be- fore finalizing a design. *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability. Operating Conditions Symbol Description Min Max Unis TC Case Temperature (Instant On) b55 a125 §C VCC Digital Supply Voltage 4.75 5.25 V D.C. CHARACTERISTICS (Over Specified Operating Conditions) Symbol Parameter Min Max Units Comments VIL Input LOW Voltage b0.5 0.8 V VIH Input HIGH Voltage 2.0 V CC a 0.5 V VILC CLK Input LOW Voltage b0.5 0.6 V VIHC CLK Input HIGH Voltage 3.8 V CC a 0.5 V VOL Output LOW Voltage Command Outputs 0.45 V I OL e 32 mA (Note 1) Control Outputs 0.45 V I OL e 16 mA (Note 2) VOH Output HIGH Voltage Command Outputs 2.4 V I OH eb 5 mA (Note 1) VCC b 0.5 V I OH eb 1 mA (Note 1) Control Outputs 2.4 V I OH eb 1 mA (Note 2) VCC b 0.5 V I OH eb 0.2 mA (Note 2) IIL Input Leakage Current g10 mA0 V s VIN s VCC ILO Output Leakage Current g10 mA 0.45V s VOUT s VCC ICC Power Supply Current 75 mA ICCS Power Supply Current (Static) 3 mA (Note 3) CCLK CLK Input Capacitance 12 pF F C e 1 MHz CI Input Capacitance 10 pF F C e 1 MHz CO Input/Outut Capacitance 20 pF F C e 1 MHz NOTES: 1. Commands Outputs are INTA , IORC , IOWC , MRDC and MWRC . 2. Control Outputs are DT/R , DEN, ALE and MCE. 3. Tested while outputs are unloaded, and inputs at V CC or V SS.

A.C. CHARACTERISTICS (Over Specified Operating Conditions) AC timings are referenced to 0.8V and 2.0V points of signals as illustrated in data sheet waveforms, unless otherwise noted. Symbol Parameter

6 MHz 8 MHz 10 MHz

(Advance) (Advance) (Advance) Min Max Min Max Min Max

1 CLK Period 83 250 62 250 50 250 ns

2 CLK HIGH Time 25 20 16 ns at 3.6V 3 CLK LOW Time 20 15 12 ns at 1.0V 4 CLK Rise Time 10 10 8 ns 1.0V to 3.6V 5 CLK Fall Time 10 10 8 ns 3.6V to 1.0V

6 M/IO and Status 28 22 18 ns

7 M/IO and Status 1 1 1 ns

8 CENL Setup Time 30 20 15 ns

9 CENL Hold Time 1 1 1 ns

10 READY Setup Time 50 38 26 ns

11 READY Hold Time 35 25 25 ns

12 CMDLY Setup Time 25 20 15 ns

13 CMDLY Hold Time 1 1 1 ns

14 AEN Setup Time 25 20 15 ns (Note 3)

15 AEN Hold Time 0 0 0 ns (Note 3)

16 ALE, MCE Active 3 25 3 20 3 16 ns (Note 4)

17 ALE, MCE Inactive 35 25 19 ns (Note 4)

18 DEN (Write) 35 35 23 ns (Note 4)

19 DT/R LOW from CLK 40 25 23 ns (Note 4)

20 DEN (Read) Active 0 50 0 35 0 21 ns (Note 4)

21 DEN (Read) Inactive 5 40 5 35 5 21 ns (Note 4)

22 DT/R HIGH from 3 45 3 35 3 20 ns (Note 4)

23 DEN (Write) Active 35 30 23 ns (Note 4)

24 DEN (Write) Inactive 3 35 3 30 3 19 ns (Note 4)

A.C. CHARACTERISTICS (Over Specified Operating Conditions) AC timings are referenced to 0.8V and 2.0V points of signals as illustrated in data sheet waveforms, unless otherwise noted. (Continued) Symbol Parameter (Advance) (Advance) (Advance) Min Max Min Max Min Max

25 DEN Inactive from CEN 40 30 25 ns (Note 4)

26 DEN Active from CEN 35 30 24 ns (Note 4)

27 DT/R HIGH from CLK 50 35 25 ns (Note 4)

(when CEN eLOW)

28 DEN Active from AEN 35 30 26 ns (Note 4)

29 CMD Active Delay from CLK 3 40 3 25 3 21 ns (Note 5)

30 CMD Inactive Delay from CLK 5 30 5 25 5 20 ns (Note 5)

31 CMD Active from CEN 45 25 25 ns (Note 5)

32 CMD Inactive from CEN 25 25 25 ns (Note 5)

33 CMD Inactive Enable from AEN 40 40 40 ns (Note 5)

34 CMD Float Delay from AEN 40 40 40 ns (Note 6)

35 MB Setup Time 25 20 15 ns

36 MB Hold Time 0 0 0 ns

37 Command Inactive Enable 40 40 40 ns (Note 5)

38 Command Float Time from MB u 40 40 40 ns (Note 6)

39 DEN Inactive from MB u 40 30 26 ns (Note 4)

40 DEN Active from MB v 35 30 26 ns (Note 4)

NOTES: 3. AEN is an asynchronous input. This specification is for testing purposes only, to assure recognition at a specific CLK edge. 4. Control output load: CI e 150 pF. 5. Command output load: CI e 300 pF. 6. Float condition occurs when output current is less than I LO in magnitude. 271077–13 Note 7: AC Drive and Measurement PointsÐCLK Input

271077–14 Note 8: AC Setup, Hold and Delay Time MeasurementÐGeneral 271077–15 Note 9: AC Test Loading on Outputs WAVEFORMS CLK CHARACTERISTICS 271077–16

WAVEFORMS (Continued) STATUS, ALE, MCE, CHARACTERISTICS 271077–17 CENL, CMDLY, DEN CHARACTERISTICS WITH MB e 0 AND CEN e 1 DURING WRITE CYCLE 271077–18 READ CYCLE CHARACTERISTICS WITH MB e 0 AND CEN e 1 271077–19

WAVEFORMS (Continued) WRITE CYCLE CHARACTERISTIC WITH MB e 0 AND CEN e 1 271077–20 CEN CHARACTERISTICS WITH MB e 0 271077–21

WAVEFORMS (Continued) AEN CHARACTERISTICS WITH MB e 1 271077–22 NOTE: 1. AEN is an asynchronous input. AEN setup and hold time is specified to guarantee the response shown in the waveforms. MB CHARACTERISTICS WITH AEN /CEN e HIGH 271077–23

WAVEFORMS (Continued) MB CHARACTERISTICS WITH AEN /CEN e HIGH (Continued) 271077–24 271077–25 NOTES: 1. MB Is an asynchronous input. MB setup and hold times specified to guarantee the response shown in the waveforms. 2. If the setup time, t35, is met two clock cycles will occur before CMD becomes active after the falling edge of MB. INTEL CORPORATION, 2200 Mission College Blvd., Santa Clara, CA 95052; Tel. (408) 765-8080 Printed in U.S.A./xxxx/1296/B10M/xx xx