82C288-10

82C288 INTEL | Alldatasheet

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intel. 82C288 BUS CONTROLLER FOR 80286 PROCESSORS (82C288-12, 82C288-10, 82C288-8) @ Provides Commands and Controls for @ Fully Static Device Local and System Bus 1 Available in 20 Pin PLCC (Plastic @ Wide Flexibility in System Leaded Chip Carrier) and 20 Pin Cerdip Configurations Packages @ High Speed CHMOS II! Technology (See Packaging Spec, Order #291969) @ Fully Compatible with the HMOS 82288 The Intel 82C268 Bus Controller is a 20-pin CHMOS III component for use in 80286 microsystems. The 820288 is fully compatible with its predecessor the HMOS 82288. The bus controller is fully static and ‘supports a low power mode. The bus controller provides command and contro! outputs with flexible timing options. Separate command outputs are used for memory and I/O devices. The data bus is controlled with separate data enable and direction control signals. 2 Two modes of operation are possible via a strapping option: MULTIBUS | compatible bus cycles, and high speed bus cycles, SSS COMMANO- status ‘ourpuTs & H |_| 1 TTA B~[]seeoeEn FF commawo | ORE wid toa, ff~we IRS He] CONTROL cure oenaen— i Hoon cent Mae Sure [Toe CMOLY- rl LOGIC: ‘LOGIC ALE READY: — | remce mB 240082-1 Figure 1, 820288 Block Diagram September 1980 (Order Number: 240042-003 2-149

20 Pin Cerdip Package

nent side of the P.C. board. side of component when mounted on the board.

20 Pin PLCC Package

Figure 2. 820288 Pin Configuration

Table 1. Pin Description The following pin function descriptions are for the 82C288 bus controller.

80286 Bus Cycle Status Definition

hold times must be met for proper operation. MULTIBUS MODE SELECT determines timing of the command and control outputs. typically a strapping option and not dynamically changed. required before starting a command. This input has no effect on 82C288 control outputs. READY indicates the end of the current bus cycle. READY is an active LOW input.

Table 1. Pin Description (Continued) outputs of the bus controller. CEN/AEN inputs may be asynchronous to CLK. ‘synchronous inputs. This input may be connected to Vcc or GND. inactive but does not tristate them. controllers so only one of them will respond to the interrupt acknowledge cycle. é address on the falling edge of ALE. for write cycles in the MULTIBUS | mode. active. DT/R is not affected by any of the control inputs. when this output becomes active. READY controls when it becomes inactive. 1/0 READ COMMAND instructs an I/O device to place data onto the data bus. this output becomes active. READY controls when it becomes inactive.

Table 2. Command and Control Outputs for Each Type of Bus Cycle In MULTIBUS | mode, the 82C288 delays command _ing interrupt acknowledge cycles. master is encoded in the M/TO, Stand SO inpute, $0. associated read command outputs (I , JORG, from DC to the appropriate upper frequency limit.

quency. As the system frequency is reduced, so is MULTIBUS | type bus arbiter. to provide address latch control, data transceiver 82C288 status inputs. control, and standard level-type command outputs. Connection to multiple buses are supported with a clock phase when it asserts the status signals. can determine which, if any, bus controller should be Phase 1 of the local bus master’s internal clock. the pipelined timing on the 80286 local bus. Figure 3. CLK Relationship to the Processor Clock and Bus T-States

cycle. For Figures 6 through 10, the CMDLY input is gj.

72 TOO LZ

Figure 6. Idle-Read-idle Bus Cycles with MB = 0 Figure 7. Idle-Write-Idle Bus Cycles with MB = 0

outputs immediately g0,10 the sppropriate state (see than provided by the basic command output timing. to terminate a bus cycle if CEN remains LOW for a put can delay the activation of command outputs. control outputs ALE, MCE, DEN, and DT/R. Figure 12. System Use of AEN and CENL

CMDLY is first sampled on the falling edge of the sitions of all signals in all modes. Instead, all signal CLK ending Ts. If sampled HIGH, the command out- timing relationships are shown via the general cas- put is not activated, and CMDLY is again sampled es. Special cases are shown when needed. The ‘on the next falling edge of CLK. Once sampled waveforms provide some functional descriptions of LOW, the proper command output becomes active the 820288; however, most functional descriptions immediately if MB = 0. If MB = 1, the proper com- —_are provided in Figures 5 through 11. mand goes active no earlier than shown in Figures 9 and 10. To find the timing specification for a signal transition in a particular mode, first look for a special case in READY can terminate a bus cycle before CMDLY __ the waveforms. If no special case applies, then use allows a command to be issued. In this case no a timing specification for the same or related func- commands are issued an the bus controller will de- tion in another mode. activate DEN and DT/R in the same manner as if a command had been issued. Waveforms Discussion The waveforms show the timing relationships of in- puts and outputs and do not show all possible tran- ] 2-161

szczae intel. ABSOLUTE MAXIMUM RATINGS* NOTICE: This is a production data sheet. The specifi- Ambient T. Under Bi + cations are subject to change without notice. ient Temperature Bias §—O'Cto +70°C Seana: Sressing the The 7 Storage Temperature —65°Cto +150°C Maximum Ratings” may cause permanent damage. Voltage on Any Pin with These are stress ratings only. Operation beyond the Respect to GND -0.5Vto +7V ‘Operating, Conditions ig not recommended and ex. Power Dissipation ‘Watt may affect device reliability. na D.C. CHARACTERISTICS Voc = 5V +5%, Tcase = 0°C to 85°C* ['symbor | __Parameter_ [Min | Max | Units | Test Conettions Input LOW Voltage | -os [| os [ov [| Input HIGH Voltage [| 20 |vooros| v [| CLK InputLow voltage | -o5 [| o6 | v [| CLK InputHIGH Voltage | 38 [voct+os| v [| Vou Output LOW Voltage Command Outputs 0.45 V_ | lo. = 32mA (Note 1) Control Outputs 0.45 V_| lou = 16 mA (Note 2) Vou Output HIGH Voltage Command Outputs 24 V_ | lox = —5mA (Note 1) Voc — 0.5 V_ | lon = —1 mA (Note 1) Control Outputs 24 V_ | lon = —1 mA (Note 2) Voc ~ 0.5 V_| lon = —0.2 mA (Note 2) InputLeakage Curent | | 10 w_| OVS Vin = Voc Output Leakage Curent || #10 _| 048 = Vour = Voo Power SuppyCurent [| sm [too | Powersupply Currant State) | [am | (Notes) CukinputCapactance ||| [rom tMne | Input Capacitance ee | Input/Output Capacitance [| 20 | oF Fo = 1 MHz *Ta is guaranteed from 0°C to + 70°C as long as Tcase is not exceeded. NoTEs: 1. Command Outputs are INTA, [ORC, IOWC, MAIDT and MWAC. 2. Control Outputs are DT/R, DEN, ALE and MCE. 3. Tested while outputs are unloaded, and inputs at Voc or Vss- 2-162 |

intel ° 820288 A.C. CHARACTERISTICS Voc = 5V, +5%, Tcase = 0°C to +85°C.* AC timings are referenced to 0.8V and 2.0V points of signals as illustrated in data sheet waveforms, unless otherwise noted. [omni [tome | 125MeHe | srot| me a aaa [+ [euxrenoa [62 | 260 | 60 | 250 | ao [250 | ms | | [2 [euxnchtime [2 | [ie | [ts [| ns | atzev | [3 [oxvowtime [ss [fe [fi [Tine | atrov | [4 [auxrisotme [| wo | [6 | [6 | ns | 10vwaev | [5 [exrartme — [ [ wo [fe | [6 | ns [ savior | M/1O and Status a ge PE Hold Time [_@ [censenptime [2 [ [is | [as [ [sf | [2 [cenrostime [a [ [+ | t+ ffs P| [10 | READY seuptime [se [| 2 | |e [fins [| [11 | RemovHowtime [2s | [as | [a [fins [| [12 [omorvsewotime [2 | [as { [is |= | | [13 [omovwoatime [1 [ [x | [a [ [os [| [4 [Aenseuptime [20 [fs [fs [ [ns [ motes) | [15 | aeNroatime | o [fo [| o [ [ns [ mote | Cela CTC TE Lee me Delay from CLK [7 [simmers | [=] [ey [etme | Delay from CLK P* [easton | [*] Pe] faim i | Inactive from CENL [te | ovRvowiromoux [| 2s || 2s [| a3 | ns | wotesy | a a from DT/ P= [ence [2 [= [sells] [eee Diy from CLK [= femme [ete Tete iets oe | DEN Inactive P= leer | fe] Tet faim i | Delay from CLK [= [aamares |? Te [ eT eis t eile | Dly from CLK *Ta is guaranteed from 0°C to + 70°C as long as Tcase is not exceeded. | 2-163

82C288 intel ° A.C. CHARACTERISTICS Voc = 5V, +5%, Tcase = 0°C to +85°C.* AC timings are referenced to 0.8V and 2.0V points of signals as illustrated in data sheet waveforms, unless otherwise noted. (Continued) [emer | tome izsmne |] ces me | mm [Bia zate a coat [= pment et ey Le | CEN Pees EE Ere |CEN a (when CEN = LOW) [28 [DEN ActwetromaEN || a0 [| a6 | 26 [ns fivoteay | a ca di ‘from CLK | fence | * Les Les |e [ef from CLK Pee Ea CEN | 32 [eowDinactvetomcen || a5 | [25 | 25 [ns [evotos)_| | 32 [CWB inactive EnabietromAEN | | ao [| 40 | [40 | ns [eiotes) | | 34 [CMD Fioat Delay tomaeN [| ao [| 40 | [40 | ns [eioiee)_| | 95 |wesewptime | 20 | [ao [| 2 | [ne] | 96 |msuotime fo To [fo Trl | Pee TE EER from MB J [28 [Command FiostTimetrommat| [40 | [40 | | 40 [ns [rvotos) | | 30 [DEN inactvetrommet [| ao | [26 | | 26 [ne [eioto) | L_40 [oenacivetommed | [ao | [30 [20 [ns [eiote)_| "T, is guaranteed from 0°C to +70°C as long as Tcase is not exceeded. 3. THEN ie ‘an asynchronous input. This specification is for testing purposes only, to assure recognition at a specific CLK $ Beetol ouput load: CI = 150 pF. 5. Command output load: Cl = 300 pF. 6. Float condition occurs when output current is less than Io in magnitude. 2-164 |

‘CLK INPUT tov 10v oasy \\ ‘\\gevur ‘tHoLD:

2 SIRERY URKESERRE

Device Se oY vy ‘aearatetet PUT A Peete SN Lrorrorrroxse easy 2k DENSE peice Soros y Bement SRR RRR RR AN ootatateterotanetcteate Low EEOC C COO CRTC OT SN 240042-16 Note 7: AC Setup, Hold and Delay Time Measurement—General DEVICE oureuT a L ; - 240042-17 Note 8: AC Test Loading on Outputs WAVEFORMS CLK CHARACTERISTICS 240042-18 | 2-165

roo intel. WAVEFORMS (Continued) STATUS, ALE, MCE, CHARACTERISTICS u_S \\, a, “ dg. <5 “e 240042-19 CENL, CMDLY, DEN CHARACTERISTICS WITH MB = 0 AND CEN = 1 DURING WRITE CYCLE om oo as OY «TTL SX 240042-20 READ CYCLE CHARACTERISTICS WITH MB = 0 AND CEN = 1 ows S| VUE mes ae =e | 4 ee) Ow | 2-166 |

intel. s2case WAVEFORMS (Continued) WRITE CYCLE CHARACTERISTIC WITH MB = 0 AND CEN = 1 DONA — tel 0) Oa CEN CHARACTERISTICS WITH MB = 0 a ae (C) oA, o om TUN

saczas intel. WAVEFORMS (Continued) KEN CHARACTERISTICS WITH MB = 1 cu. TER (C) io) Nore? e q ® a - ) BECEEC) . pen a 240042-24 NOTE: 1. AEN is an asynchronous input. AEN setup and hold time is specified to guarantee the response shown in the waveforms. MB CHARACTERISTICS WITH AEN/CEN = HIGH 1 1s 1 Te 1 Te 1 To fl 1s 1 cux Ba ® +® we FloatING = = -® o- “re ® oen OU LE. oa o> 0) EADY —— — 24004225 2-168 |

WAVEFORMS (Continued) MB CHARACTERISTICS WITH AEN/CEN = HIGH (Continued) ed 1 Te 1 fe 1 Ts 1 cu ar ue ® ® > 0) mage ---—----- re @ orm — = ® EN ‘READY 240042-28 : te 1 Te | Tet ax eH ® + =-@ were --— emg co @__ nose © ® pen WenY 240042-27 NOTES: 1. MB is an asynchronous input. MB setup and hold times specified to guarantee the response shown in the waveforms. 2, If the setup time, £35, is mot two clock cycles will occur before CMD becomes active atter the falling edge of MB. DATA SHEET REVISION REVIEW The following list represents key differences between this and the -002 data sheet. Please review this summa- ty carefully. 1. The Iocs specification was changed from 1 mA to 3 mA maximum. 2. The “PRELIMINARY” markings have been removed from the data sheet. | 2-169