8284A | DigiCamel IC Datasheet

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Clock Generator and Driver for 8086, 8088 Processors DISTINCTIVE CHARACTERISTICS g © Generates the System Clock for the 8086, 8088 Proces- © Generates system reset output from Schmitt trigger 2 sors: 5MHz, 8MHz with 62844; 10MHz with 8264A-1 ‘input g @ Uses a crystal or a TTL signal for frequency source © Capable of clock synchronization with other 6284As > © Provides local READY and Multibus* READY synchroni- i zation : GENERAL DESCRIPTION The 8284 is a single chip clock generator/driver for the trolled oscillator, a divide-by-three counter, complete 8086, 8068 processors. The chip contains a crystal-con- MULTIBUS* “Ready” synchronization and reset logic. BLOCK DIAGRAM Cd x ? x ™ e ot) we LW [Ls ~ + ROY, oo > > 0%, " D> [ i, —D>o [) READY Tae 0001440 RELATED AMD PRODUCTS [Part No. [Description | aman reemma

3.309 Iove Date: April 1987

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2 DiPs PLoc

® 883 Be nono fo2 2 1 mo \\ esync (1° 18D) Veg . pou C]2 wOx, en, 4 Ox. mn, Cs 16H) Xe roy, 5 17 Asvne roy, Cs 418() ABYRO READY (]5 62844 14[7] EFI Reapy {] 6 6 L) Rove Ce were roy, (7 Ore nen, C7 seD osc ax Ge tyres wn, (6 4 Dose oo Le 70H PESE| eo Hn 2 9 ‘0001582 coodoo 38298 ‘coo0s272 Note: Pin 1 is marked for orientation. 3-390

AMD commodity products are available in several packages and operating ranges. The order number (Valid Combination) is formed = by acombination of: a. Temperature Range = b. Package Type ©. Device Number d. Speed Option ©. Optional Processing L ‘¢. OPTIONAL PROCESSING Blank = Standard Processing B= Burin . SPEED OPTION Blank = For 5-MHz & &MHz Applications =1'= For 10-MHz Applications ©. DEVICE NUMBER/DESCRIPTION 82848 ‘Glock Generator and Driver ‘for 8088, 8088 Processors b. PACKAGE TYPE P= 18-Pin Plastic DIP (PD 018) D= 18-Pin Ceramic DIP (CD 018) Ruben Ha Lal Cn Ca P02 4. TEMPERATURE RANGE Biank = Commercial (0 to +70°O) ‘M= Miltary* (-58 to + 125°C) Valid Combinations Valid Combinations list configurations planned to be [vad Combinations supported in volume for this device. Consuit the local AMD | sales office to confirm availability of specific valid | combinations, to check on newly released valid combinations, | and to obtain additional data on AMD's standard military [lezen grade products. “Military temperature range products are NPL (Non- Compliant Products List) or Non-MIL-STD-883C Compliant products only. 3.991

$ PIN DESCRIPTION S [Pin No. [Name [vo [Description Sia7 ‘adress Enable. The AEN signal is used to quailty the Bus Ready signal (RDY or RDV2). AEN; validates ADY; while s ZEN; vacates RDY2. It is possible Tor the processor to access two Muli-Mkastor Syatom Busses i you use both signa, Both signals are tied LOW in non MultrMaster Systems. 2 IRDY;, Bus Ready. These signals are indications from a device located on the system bus that it is available or data has been ROY? recowved. ROY; and ROY are qualified by AEN; and AENa respectively. Roady Synchronous Select. The ASYNC signal defines the synchronizalion mode of the READY logic. When RSYRE ‘gener (ternal pull-up resistor is provided) or pulled HIGH, there is one stage of READY Synchronization. When 4s LOW, there are two stages of READY Synchronization. Roady. READY is the synchronized RDY signal input. Atr the quaranteod hold ime to the processor haa been mat, the READY signat is cleared. 7, 16 Xe Crystal In. These are the input pins for the attached crystal. The crystal frequency is 3 times the desired process clock a a Gd Frequency/Ciystal Select When FC's siapped HIGH, CLK le genorated from the EFI input When strapped LOW, the F/C allows the processor clock to be generated by the crystal Exiomal Frequency. Used in conjunction with @ HIGH signal on F7C, CLK Ts gonerated fom the input frequancy appearing on this pin. The input signal is a square wave 3 times the frequency of the desired CLK output. CLK Processor Clock. CLK is the clock output used by the processor and all devices which directly connect to the processor's local bus (including bipolar support chips and other MOS devices). An output HIGH of 4.5V (Voc = 5V) is. Provided on his pinto drive MOS devices. The output frequency of CLK is 1/3 ofthe crystal on EFI input Frequency and a 1/3 duty cycle. ipheral lock, Ths “TTL level peripheral clock signal whose output 172 that of CLK and has Pt [aka ecnereererernesrmecan a a Ouclog Oui. Te ili the TT ove up tho ntl oot ey Wo Woguony som Tal of FRoset In. This signal used to gonorato a RESET. The 204A provides a Schmit wager input so that an AO connection can be used to establish the power-up reset of proper duration. [vo [Reset {0 | Reset. This signal is used to reset the 8086 family processors ‘Clock Synchronization. This signal is designed to allow multiple 8284As to be synchronized to provide locks that are in.phase, CSYNC HIGH wil reget tho intemal counter, whan CSYNC goos LOW the counters wil resume counting. CSYING needs to be externally synchronized to EFI. When used with the internal oscilator, CSYNC should be hard wired to ground, DETAILED DESCRIPTION CLOCK OUTPUTS 1LLATOR The CLK output is a 33% duty cycle MOS clock driver ose' dosigned to drive the 8086 or 8088 processors directly. PCLK The oscillator circuit of the 82844 is designed primarily for use _is a TTL level peripheral clock signal whose output frequency with a fundamental mode, series resonant crystal from which _ is ¥2 that of CLK. PCLK has a 50% duty cycle. the operating frequency is derived. RESET LOGIC ‘The crystal frequency should be selected at three times the Reset gic fr the 8284A is provided by @ Schmitt tigger input required CPU clock. X1 and Xp are the two crystal input crystal (FES) ‘ang a synchronizing fipslop to generate the recat connections. The output of the oscilator is buffered and — fining brought out on OSC so that other system timing signals can be 4 derived from this stable, crystal-controlled source. The reset signal is synchronized to the falling edge of CLK. A ir RC network can be used to provide power- reset Two 5102 series resistors are optional for systems which Sante ths trneton of the eZee on reset by have a Voc ramp time greater than (or equal to) 1V/ms and/or inherent board capacitance between X; or Xp exceeding READY SYNCHRONIZATION 10pF.. This capacitance value should not include the 8284A'S two READY inputs (ROY, RDY2) are provided to accommo- pin capacitance. By limiting the stray capacitance to less than 40pF on Xj oF Xo, the deviation from the desired fundamental 98te two _Mult-Master system busses. Each input has a fr 1 OF 2s qualifier (AEN; and AENo, respectively). The AEN signals requency is, minimized. validate their respective RDY signals. If a Multi-Master system. CLOCK GENERATOR is not being used the AEN pin should be tied LOW. The clock generator consists of a synchronous divide-by-three T°. assure ADY setup and hold times are met, synchronization counter with a special clear input that inhibits the counting. _'$ Fequired for all asynchronous active going edges of either This clear input, (CSYNC), allows the output clock to be RY input. Inactive-going edges of ROY (in normally ready synchronized with an external event (such as another 82844 _SYStems) do not require synchronization, but must satisfy RDY clock). It is necessary to synchronize the CSYNC input to the Setup and hold as a matter of proper system design. EFI clock external to the 8284A (see Figure 1). This is The two modes of RDY synchronization operation are defined accomplished with two Schottky flip-flops. The counter output by the ASYNC input. 3% it third the input is @ 89% duty cycle clock at one input Frequency. Wen SYNC is LOW, two stages of synchronization are The F/T input is a strapping pin that selects either the EFI _provided for active RDY input signals. Positive-going asyn- input or the crystal oscillator as the clock for the + 3 counter. If chronous RDY inputs will first be synchronized to flip-flop one the EFI input is selected as the clock source, the oscillator _at the rising edge of CLK and then synchronized to flip-flop ‘section can be used independently for another clock source, two at the next falling edge of CLK; after which time the Output is taken from OSC. READY output will go active (HIGH). Negative-going asynchro- 3.992

bypassed in the READY synchronization logic. RDY inputs aro system. Figure 1. CSYNC Synchronization

& READY TO CLOCK (USING X;, X2) S v 8 ‘CC LOAD 3 mR ou 3 30 pF

24 MHz Fj EAD (SEE NOTE 2)

Generator ROY, osc Trigger Fe Ry = Ro [| HER, t | osvno Ry = Ro= 5102. READY TO CLOCK (USING EFI) PULSE LOAD " o Fe THGGER Ulm, PULSE ROY. GENERATION FEN, [Be ‘AF000611 Notes: 1. CL = 100pF 2. CL = 30pF 3394

ABSOLUTE MAXIMUM RATINGS. OPERATING RANGES 8 ‘Ambiont Temperature with Powers Temperature ...csesessessseeiueenseen OS to +70 | & Applied SUPPIY VOIEEQC crc rnrnnennnrnn +ATBV to +5.28V | B (COML, AA) cosssccsecsssseseeeenseseeenesseeesO°C tO +70°C i De ni ns Sassy age sr BE 10 4125S lt ae ccecuneaneB8°C 10 +1256 z Stresses above those listed under ABSOLUTE MAXIMUM functionality and parameters of the device are guaranteed. RATINGS may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device raliabilty. DC CHARACTERISTICS over operating ranges unless otherwise specified [Parameters [Description | Test Conditions] min [Max [Unite | [Forward toput Current (RSYNC) [Vem oasy ts T [Other puts emo os [Reverse input Current SYNE) [Vasco TT 80 [omerimus | ass TT | [Ve [input Forward Camp Votiage [cm esma 10 Vos | [toc | Power Supply Curent Pee ma [Vu | tpt LOW Vottago evs | [Vin | impat HIGH Votage ag vote | [Wiig [Reset toput HIGH Votage a Votes [ Vo. [Output Low Vonage Sma oes vos | [Output HIGH Votiage GK mao as You [omer Oupts TAT TNS TES input Hysteresis (Nowe 1D Pas Tots | 3.395

[Parameter | Description __—=—|__—‘Test Conditions [min | typ | Max | Unite | 5 a ee eee ‘LK Oyele Pood bial on a 3 [wi come | tae | || z a ce ee [wn cow eR wo toot auc ton Tine a eames [| [ew | ROR me S| a Cinsw [Pouk tower Cinnce | Ready iasive w CK Boone a ‘eercn Reaay Aewwe w CLK (eo Nel 9) a re ST a [tea feu PORNGH Dewy] de | ican [oe Pout Dewy] Cd Od | [ose oso UK HGH Day |] ae [rower fos AK LOW Dey | | | Coton [Oto Fie Time (ecept GK) _———iFomoavweaow | iY fos | [owor— | Output Fa Tire except C10 [From 20vteo6v |_| 1 | | Notes: 1. 6 = EFI rise (Sns max) + EFI fall (Sms max), 2 Setup and hold necessary only to guarantee recognition at next clock. Fees Ty ane Ta ote. & Bbles ory te TS sate SWITCHING WAVEFORMS CLOCKS AND RESET SIGNALS on _ wut te ‘on 4 MU evaras A aed I 4 ef % —— aa. na | bh Vo — ‘am. _ oe a ms mano WF002530 Note: All timing requirements are made at 1.5 volts, unless otherwise noted. 9397

z READY SIGNALS (FOR ASYNCHRONOUS DEVICES) 2 } _ 2 am oO rH i} ‘wane ] a neo ~ | we002520 READY SIGNALS (FOR SYNCHRONOUS DEVICES) ox ‘mx —{ ‘we. ™ -- fF aves _ “| sane | ewe bt | oe 9 W002510 3.398

Product Information

8284A specifications and overview.

Summary

Clock Generator and Driver for 8066, 8088 Processors

Description

Clock Generator and Driver for 8066, 8088 Processors

Source title 8284A Datasheet(PDF) - Intel Corporation

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