8279

8279 INTEL | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 16

Technical content

™ 2-Key Lockout or N-Key Rollover with @ Available in EXPRESS. debounced and strobed in an 8-character FIFO. if more than 8 characters are entered, overrun status is set. Key entries set the interrupt output line to the CPU. write of the display RAM can be done with auto-increment of the display RAM address. Figure 1. Logic Symbol

The 8279 is packaged in a 40 pin DIP. The following is a functional description of each pin. Table 1. Pin Description and the 8279 are transmitted on these lines. [CLK _————|__ 8 _| CLOCK: Clock from system used to generate internal timing. 1) 16 8-bit character display—left entry. 2) Encoded scan keyboard—2 key lockout. Along with this the program clock prescaler is set to 31. interpreted as a command or status. A low indicates that they are data. to either send data to the external bus or receive it from the external bus. [Vss.Voc_____| 20,40 | GROUND AND POWER SUPPLY PINS. bit input in the Strobed Input mode. keep it high until a switch closure pulls it low. strobe line that enters the data into the FIFO in the Strobed Input mode. independently. These two ports may also be considered as one 8-bit port. switching or by a display blanking command.

intel. 8279/8279-5 FUNCTIONAL DESCRIPTION 1/0 Control and Data Buffers Since data input and display are an integral part of | The I/O control section uses the CS, Ao, RD and many microprocessor designs, the system designer WR lines to control data flow to and from the various needs an interface that can contro! these functions internal registers and buffers. All data flow to and without placing a large load on the CPU. The 8279 from the 8279 is enabled by CS. The character of Provides this function for 8-bit microprocessors. the information, given or desired by the CPU, is iden- tified by Ag. A logic one means the information is a The 8279 has two sections: keyboard and display. command or status. A logic zero means the informa- The keyboard section can interface to regular type- __tion is data. RD and WR determine the direction of writer style keyboards or random toggle or thumb —_diata flow through the Data Buffers. The Data Butfers switches. The display section drives alphanumeric —_are bi-directional butfers that connect the internal displays or a bank of indicator lights. Thus the CPU _bus to the external bus. When the chip is not select- is relieved from scanning the keyboard or refreshing ed (CS = 1), the devices are in a high impedance the display. state. The drivers input during WR « CS and output ~ during RO « CS. The 8279 is designed to directly connect to the mi- croprocessor bus. The CPU can program all operat- ing modes for the 8279. These modes include: Control and Timing Registers and Timing Control Input Modes These registers store the keyboard and display * Scanned Keyboard—with encoded (6 x 8 key modes and other operating conditions programmed iG} keyboard) or decoded (4 x 8 key keyboard) scan _—by the CPU. The modes are programmed by pre- lines. A key depression generates a 6-bit encod- senting the proper command on the data lines with ing of key position. Position and shift and control © Ao = 1 and then sending a WR. The command is status are stored in the FIFO. Keys are automati- _ latched on the rising edge of WR. The command is cally debounced with 2-key lockout or N-key roll: ther decoded and the appropriate function is set. over. The timing control contains the basic timing counter . ne wit chain. The first counter is a + N prescaler that can Scanned Sensor Matrix—with encoded (8 x8Ma- he programmed to yield an internal frequency of 100 trix switches) or decoded (4 x 8 matrix switches) —_F47 which gives a &1 ms Keyboard soan time and a lines. Key status (open or closed) stored in 9 ; ‘ PAM ad ‘oe by CPU. 10.3 ms debounce time. The other counters divide addressable by CPU. . down the basic internal frequency to provide the * Strobed Input—Data on return lines during con- proper key scan, row scan, keyboard matrix scan, trol line strobe is transferred to FIFO. and display scan times. Output Modes Scan Counter © 8 of 16 character multiplexed displays that can be organized as dual 4-bit or single 8-bit (By = ‘The scan counter has two modes. In the encoded Do, Ag = D7). mode, the counter provides a binary count that must : a be externally decoded to provide the scan lines for © Right entry or left entry display formats. the keyboard and display. In the decoded mode, the , scan counter decodes the least significant 2 bits and Other features of the 8279 include: provides a decoded 1 of 4 scan. Note that when the * Mode programming from the CPU. keyboard is in decoded scan, so is the display. This © Clock Prescaler means that only the first 4 characters in the Display * Interrupt output to signal CPU when there is key. "AM are displayed. board or sensor data available. In the encoded mode, the scan lines are active high. * An 8 byte FIFO to store keyboard information. outputs. In the decoded mode, the scan lines are * 16 byte internal Display RAM for display refresh. active low outputs. This RAM can also be read by the CPU. PRINCIPLES OF OPERATION The following is a description of the major elements of the 8279 Programmable Keyboard/Display inter- face device. Refer to the block diagram in Figure 3. 3-217

Figure 3. Internal Block Diagram

intel. 8279/8279-5 Return Buffers and Keyboard SOFTWARE OPERATION Debounce and Control The 8 return lines are buffered and latched by the #8279 Commands Return Butfers. In the keyboard mode, these lines ; are scanned, looking for key closures in that row. If The following commands program the 8279 operat- the debounce circuit detects a closed switch, it waits ing modes. The commands are sent on the Data Bus about 10 ms to check if the switch remains closed. if with CS low and Ap migrand are loaded to the 8279 it does, the address of the switch in the matrix plus ON the rising edge of WR. the status of SHIFT and CONTROL are transferred to the FIFO. In the scanned Sensor Matrix modes, the contents of the return lines is directly transferred Keyboard/Display Mode Set to the corresponding row of the Sensor RAM (FIFO) MSB LsB each key scan time. In Strobed Input mode, the con- . {oTo[o[o[o[x[x|[xk] tonis of the rotum lines are transfered to moriro oo: LO] of of ojo] x] x] k] on the rising edge of the CNTL/STB {ine pulse. Where DD is the Display Mode and KKK is the Key- board Mode. FIFO/Sensor RAM and Status pp This block is a dual function 8 x 8 RAM. In Keyboard i ‘ of Strobed Input modes, itis a FIFO. Each new entry 9 9 88-bit character display—Left entry is written into successive RAM positions andeachis 9 1 16 8-bit character display—Left entry’ 3 then read in order of entry. FIFO status keeps stack 1 0 88-bit character display—Right entry of the number of characters in the FIFO and whether F ' itis full or empty. Too many reads or writes will bo | 1 16 8-bit character display—Right entry recognized as an error. The status can be read by For des: i cription of right and left entry, see Interface an FD win S low and Ao high. The status logic also Considerations. Note that when decoded scan is set Provides an IRQ signal when the FIFO is not empty. —_in keyboard mode, the display is reduced to 4 char- In Scanned Sensor Matrix mode, the memory is @ acters independent of display mode set Sensor RAM. Each row of the Sensor RAM is loaded " with the status of the corresponding row of sensorin KK the sensor matrix. In this mode, IRQ is high if a change in a sensor is detected. ooo Encoded Scan Keyboard—2 Key Lock- 0 0 1 Decoded Scan Keyboard—2-Key Lock- Display Address Registers and Display out RAM © 1 0 Encoded Scan Keyboard—N-Key Roll- The Display Address Registers hold the address of over the word currently being written or read by the CPU 9 +1 1 Decoded Scan Keyboard—N-Key Roll- and the two 4-bit nibbles being displayed. The read/ over write addresses are programmed by CPU command. 1 0 0 Encoded Scan Sensor Matrix They also can be set to auto increment after each D i read or write. The Display RAM can be directly read 1 ° 1 Scan Sensor Matrix by the CPU after the correct mode and address is 1 1 0 Strobed Input, Encoded Display Scan set. The addresses for the A and B nibbles are auto- 1 1 1 Strobed Input, Decoded Display Scan matically updated by the 8279 to match data entry “Default after reset. by the CPU. The A and B nibbles can be entered independently or as one word, according to the Program Clock mode that is set by the CPU. Data entry to the dis- face Gonsterators fer delais ne Co[el+Te[r[elelr] face Considerations for details. cot: [olo[s[rlrlrlr|r| All timing and multiplexing signals for the 8279 are generated by an internal prescaler. This prescaler divides the external clock (pin 3) by a programmable : integer. Bits PPPPP determine the value of this inte- ger which ranges from 2 to 31. Choosing a divisor that yields 100 kHz will give the specified scan and 3.219

intel. 8279/8279-5 debounce times. For instance, if Pin 3 of the 8279 is Display Write Inhibit/Blanking being clocked by a 2 MHz signal, PPPPP should be A B A B set to 10100 to divide the clock by 20 to yield the proper 100 kHz operating frequency. code: [1 Jo] 1] x] w[ w]e [au] Read FIFO/Sensor RAM The IW Bits can be used to mask nibble A and nibble B in applications requiring separate 4-bit display . Aa] — Don" ports. By setting the IW flag (IW = 1) for one of the code: [o]sJolai[x[a]a]A] x = Don't Care ports, the port becomes marked so that entries to the Display RAM from the CPU do not affect that The CPU sets the 8279 for a read of the FIFO/Sen- _port. Thus, if each nibble is input to a BCD decoder, sor RAM by first writing this command. In the Scan _the CPU may write a digit to the Display RAM with- Keyboard Mode, the Auto-Increment flag (Al) and out affecting the other digit being displayed. It is im- the RAM address bits (AAA) are irrelevant. The 8279 portant to note that bit By corresponds to bit Dp on will automatically drive the data bus for each subse- _the CPU bus, and that bit Ag corresponds to bit D7. quent read (Ag = 0) in the same sequence in which the data first entered the FIFO. All subsequent reads _If the user wishes to blank the display, the BL flags will be from the FIFO until another command is is- are available for each nibble. The last Clear com- sued mand issued determines the code to be used as a “blank.” This code defaults to all zeros after a reset. In the Sensor Matrix Mode, the RAM address bits Note that both BL flags must be set to blank a dis- AAA select one of the 8 rows of the Sensor RAM. If play formatted with a single 8-bit port. the Al flag is set (Al = 1), each successive read will be from the subsequent row of the sensor RAM. Clear Read Display RAM Code: (s+ To] co [co] co | ce | ca] Code: Loli [sfafafalala] The Cp bits are available in this command to clear all rows of the Display RAM to a selectable blanking The CPU sets up the 8279 for a read of the Display _code as follows: RAM by first writing this command. The address bits AAAA select one of the 16 rows of the Display RAM. © > Co if the Al flag is set (A1 = 1), this row address will be ad incremented after each following read or write to the © X All Zeros (X= Don't Care} Display RAM. Since the same counter is used for 1 0 AB= Hex 20 010 0000) both reading and writing, this command sets the 11 AulOnes next read or write address and the sense of the Enablectea display when = 1 (or by Ca = 3) Auto-Increment mode for both operations. 290123-19 Write Display RAM During the time the Display RAM is being cleared [7] [ATA[A] (= 160n8),itmay not be written to. The most signit- Code: tfofofaqayalaya cant bit of the FIFO status word is set during this time. When the Display RAM becomes available The CPU sets up the 8279 for a write to the Display again, it automatically resets. RAM by first writing this command. After writing the command with Ap = 1, all subsequent writes with Ag _If the Cr bit is asserted (Cr = 1), the FIFO status is = 0 will be to the Display RAM. The addressing and cleared and the interrupt output line is reset. Also, Auto-Increment functions are identical to those for —_the Sensor RAM pointer is set to row 0. the Read Display RAM. However, this command does not affect the source of subsequent Data Ca, the Clear All bit, has the combined effect of Cp Reads; the CPU will read from whichever RAM (Dis- _and Gr; it uses the Cp clearing code on the Display play of FIFO/Sensor) which was last specified. If, RAM and also clears FIFO status. Furthermore, it indeed, the Display RAM was last specified, the —_resynchronizes the internal timing chain. Write Display RAM will, nevertheless, change the next Read location. 3-220

intel. 8279/8279-5 End interrupt/Error Mode Set FIFO along with the status of CNTL and SHIFT lines. if the FIFO was empty, IRQ will be set to signal the code: [1] 1] 1]E[x]X]x]x] X= Don'tcare CPU that there is an entry in the FIFO. if the FIFO was full, the key will not be entered and the error ; . flag will be set. If another closed switch is encoun- For the sensor matrix modes nis Reilly tered, no entry to the FIFO can occur. If all other (The IRQ line would have been raised upon the de. KovS, are released patch one, then I tone ny tection of a change in a sensor value. This would ; . I this have also inhibited further writing into the RAM until other. t wil be ontely ignored. A key is entered to reset), the FIFO only once per depression, no matter how many kays were pressed along with it or in what . der they were released. If two keys are depressed For the N-key rollover mode—if the E bit is pro- O m °y moc ; ithin the debounce cycle, it is a simultaneous de- grammed fo (Far neice deta oe terace Com pression. Neither key will be recognized until one Siderations Section) J key remains depressed alone. The last key will be : treated as a single key depression. Status Word Scanned Keyboard Mode, N-Key The status word contains the FIFO status, error, and Rollover dis lable signals. rd ie luna ao one oe and FD are low See With N-key Rollover each key depression is treated Irrertene Considerations for more detail on status Mdependently from all others. When @ key is de- i) word. pressed, the debounce circuit waits 2 keyboard scans and then checks to see if the key is stil down. Ifitis , the key is entered into the FIFO. Any number Data Read of keys can be depressed and another can be rec- ‘ognized and entered into the FIFO. If a simultaneous Data is read when Ap, CS and’AD are all low. The depression occurs, the keys are recognized and en- source of the data is Specified by the Read FIFO or tered according to the order the keyboard scan Read Display commands. The trailing edge of RD ound them. - will cause the address of the RAM being read to be incremented if the Auto-Increment flag is set. FIFO reads always increment (if no error occurs) indepen- | Scanned Keyboard—Special Error dent of Al. Modes For N-key rollover mode the user can program a special error mode. This is done by the “End Inter- Data Write rupt/Error Mode Set” command. The debounce cy- Data that is written with Ao, CS and WA low is al cle and key-validity check are as in normal N-key ways written to the Display RAM. The address is mode. If during a single debounce cycle, two keys specified by the latest Read Display or Write Display 7° found depressed, this is considered a simulta- command. Auto-Incrementing on the rising edge neous multiple depression, and sets an error flag. of WH occurs if Al is set by the latest display This flag will prevent any further writing into the FIFO command. and will set interrupt (if not yet set). The error flag could be read in this mode by reading the FIFO STATUS word. (See “FIFO STATUS" for further de- INTERFACE CONSIDERATIONS tails.) The error flag is reset by sending the normal CLEAR command with CF = 1 Scanned Keyboard Mode, 2-Key Lockout Sensor Matrix Mode ‘There are three possible combinations of conditions In Sensor Matrix mode, the debounce logic is inhibit- that can occur during debounce scanning. When a _@d. The status of the sensor switch is inputted di- key is depressed, the debounce logic is set. Other rectly to the Sensor RAM. In this way the Sensor depressed keys are looked for during the next two RAM keeps an image of the state of the switches in scans. If none are encountered, it is a single key the sensor matrix. Although debouncing is not pro- depression and the key position is entered into the __vided, this mode has the advantage that the CPU knows how long the sensor was closed and when it 3-221

intel. 8279/8279-5 eee was released. A keyboard mode can only indicate a__by the rising edge of a CNTL/STB line pulse. Data validated closure. To make the software easier, the can come from another encoded keyboard or simple designer should functionally group the sensors by —_switch matrix. The return lines can also be used as a row since this is the format in which the CPU will general purpose strobed input. read them. MsB ise The IRQ tine goes high if any sensor value change is detected at the end of a sensor matrix scan. The IRQ line is cleared by the first data read operation if the Auto-Increment flag is set to zero, or by the End pig Interrupt command if the Auto-Increment flag is set isplay to one. Lett Entry NOTE: . Multiple changes in the matrix Addressed by Left Entry mode is the simplest display format in that (Slo-3 = 0) may cause multiple interrupts. (SLo = each display position directly corresponds to a byte 0 in the Decoded Mode.) Reset may cause the (or nibble) in the Display RAM. Address 0 in the 8279 to see multiple changes. RAM is the left-most display character and address. 15 (or address 7 In 8 character display) is the right most display character. Entering characters from po- Data Format sition zero causes the display to fill from the left. The 17th (9th) character is entered back in the left most In the Scanned Keyboard mode, the character en- Position and filling again proceeds from there. tered into the FIFO corresponds to the position of the switch in the keyboard plus the status of the CNTL and SHIFT lines (non-inverted). CNTL is the on 14. 15+ —uplay MSB of the character and SHIFT is the next most twewy [TT TT) pa significant bit. The next three bits are from the scan cree Adress counter and indicate the row the key was found in. ot 1415 The last three bits are from the column counter and aed entry a7 77 indicate to which return line the key was connected. ~ OPI" "> TT MSB isa ot us on 415 SCANNED KEYBOARD DATA FORMAT vmeny [rT] > > ~The] in Sensor Matrix mode, the data on the return lines 01 1418 is entered directly in the row of the Sensor RAM that 18th entry oo corresponds to the row in the matrix being scanned. ---- : Therefore, each switch position maps directly to a 290123-14 Sensor RAM position. The SHIFT and CNTL inputs Leh Erury Mode (Auto increment) are ignored in this mode. Note that switches are not necessarily the only thing that can be connected to the return lines in this mode. Any logic that can be «Right Entry triggered by the scan lines can enter data to the . . return line inputs. Eight multiplexed input ports could Bight ony ne weston aed by most ll th the . : be tied to the return lines and scanned by the 8279. daplay charactor The tent ooee in dee acer MsB LSB the right most character after the display is shifted [rty [Rts [AUs [RL [Als] Ale] AL; [Alp] left one character. The left most character is shifted Riz [Ale | Als | Als | Als| Ale] ALi] Alo} Si the end and is lost, In Strobed Input mode, the data is also entered to the FIFO from the return lines. The data is entered 3-222

intel. 8279/8279-5 Sa 01234567 < Display 121415 0 istay RAM weer CLD ODER setonty GTTTT TTT) iathess 23 Ot Taran" andenty (i]27 TT TTT] seo CTT DEP] 01234567 ot 13s command [1]2]} [| 1 [1] . vonenry [2] | [hiss] 10010101 a aie Enter next at Location 5 Auto Increment 1th entry CEL] ) PsP) 01234567 2a 0 arsonery (]2] TT Ts] 1] ranenry [BT4T Pepa pe] 01234567 Aight Enry Mode (Ate ronan) atventry [1]2] TT [sf] | : LEFT ENTRY MODE Note that now the display position and register ad- (AUTO INCREMENT) 3 dress do not correspond. Consequently, entering a 7 i dress do not correspond. Consequently, omer @ Inthe Right Entry mode, Auto incrementing and non Character 10 an aria Poston ne ate Entry erementing have the same effect asin the Left starting at Display RAM address 0 with sequential EMMY except if the address sequence is interrupted. entry is recommended. 12345670 + Display Auto Increment In the Left Entry mode, Auto incrementing causes 23456701 the address where the CPU will next write 10 68 i” — ongentry [1 | T1112) cemented by one and the character appears in the next location. With non-Auto Incrementing the entry 23456701 is both to the same RAM address and display posi- fon Entry to an arbitrary address intho Auto Incre. command [| | | | | [s]2] ment mode has no undesirable side effects and the ‘10010101 result is predictable: Enter next at Location 5 Auto Increment 34567012 45670123 amonty ([s[e] [s]2] J | RIGHT ENTRY MODE (AUTO INCREMENT) 3.223

intel. 8279/8279-5 ee Starting at an arbitrary location operates as shown _the FIFO and to indicate whether an error has oc- below: curred. There are two types of errors possible: over- 01234567 ¢ Display tun and underrun. Overrun occurs when the entry of RAM another character into a full FIFO is attempted. Un- command [TTT TT TT) ‘Address _derrun occurs when the CPU tries to read an empty 10010101 FIFO. Enter next at Location 5 Auto Increment .

12345670 The FIFO status word also has a bit to indicate that

the Display RAM was unavailable because a Clear 1st entry (LETT TT Display or Clear All command had not completed its . clearing operation. 23456701 In a Sensor Matrix mode, a bit is set in the FIFO andentry [TT TsJ2] [ [| status word to indicate that at least one sensor clo- atventy [a] s]6]7]@|1[2[3] sure indication is contained in the Sensor RAM. In Special Error Mode the S/E bit is showing the ‘9th entry (s[6]7[e[o]2]3[4] error flag and serves as an indication to whether a RIGHT ENTRY MODE simultaneous multiple closure error has occurred. (AUTO INCREMENT) FIFO STATUS WORD Entry appears to be from the intial entry point. TT FIFO Full 8/16 Character Display Formats [o,|se[ ofulr [n[n In] If the display mode is set to an 8 character display, [Number of the on duty-cycle is double what it would be for a 16 characters in FIFO character display (e.g., 5.1 ms scan time for 8 char- ~ Error-Underrun acters vs. 10.3 ms for 16 characters with 100 kHz Error-Overrun internal frequency). Sensor Closure/Error Flag for Multiple Closures: G. FIFO Status ————— Display unavailable 290129-4 FIFO status is used in the Keyboard and Strobed Input modes to indicate the number of characters in 3-224

Figure 4. System Block Diagram

intel. 8279/8279-5 ABSOLUTE MAXIMUM RATINGS* cations are subject to change without notice. Voltage on any Pin with These are stress ratings only. Operation beyond the . tended exposure beyond the “Operating Conditions” D.C. CHARACTERISTICS T, = 0°C to 70°C Vsg = OV (Note 3)* ['Symbot [__Parameter_____-|-Min | Max | Unit | TestConaltions | [vur | Taputlow VotagetorRewmunes [os] ia [vt [Viz | Input Low Votage orAlOners | -os |_o@ | v | [Von | laputhigh Vottage forRetwntines | 22 || v [| [Viie | Inputhigh VotagetoraiOmers | 20 | |v [OY [You outputtow vatags | ams | VP ee [Yor | Ouiputtigh Votage oninierupitne | 35 |_| V_| Wowa) + pee [een | Ga aaa ES Return Lines -100 | pA | Vin= ov [iz | InputLeakage Guventon ar Others |_| 210 | wA | Vw=Veotoov | [ior | OuputFicatueakage |_| #10. | WA | Vour= Vegwoaav | [co | PowerSuppiyGurent «i | va pm [on | taput Capacitance =| | 10 | pF | te = 1 He Unmoasirod [cour | outputCapactance [| 20 |p] Pins Retumedto Vas) A.C. CHARACTERISTICS T, = 0°C to 70°C, Vsg = OV (Note 3)* Bus Parameters READ CYCLE od [tsa | Address Stabie Before READ [so | fo [|e [tra |" AddressHoldTimeforREAD | 5 [To [| ns _| | tan | READPusewieth | azo [| aso || ns | [tao | Data DelaytomREAD | g00 | t50 | ns | | tao | Address toDatavaid | a0 | a50 | ns | tor | FEADtoDataFioating [10 | too | 10_[ 400 ~| ons | tay | Readcyciotime Tt TT at | ds | tw | Address Stable Beforewrime | so [| o [| ons | [wa | AddressHoidTimetorWnITE | 20 [Jo [| ns | 3-226

intel. 8279/8279-5 A.C. CHARACTERISTICS (Continued) WRITE CYCLE WRITE Pulse Wieth [oo ff so | Ts | [tow | DataSerUptinetorwarre | 300 [| so | | ns DataHoldTimerorwarme [40 | To | [ns | Ltwor | witecyctetime Ts Tt sf OTHER TIMINGS [ew | GiookPutsewiatn [20 [| tao Ts Clock Period [soo [Teo fs NOTES: 2. lon = —100 pA 4. 8279, Cy = 100 pF; 8279-5, C. = 150 pF. 5. The Prescaler should be programmed to provide a 10 us internal clock cycle. 6. Sampled not 100% tested. Ta = 25°C. * For Extended Temperature EXPRESS, use M8279A electrical parameters. A.C. TESTING INPUT, OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT TRPUTTOUTEUT SS sesronee 2 45 28 oe C= 120 pF mms i ‘AC. Testing: Inputs are driven at 2.4V for @ Logic "1" and 0.45V = tora Loge" Ting meesurens fe ade at 20V fora a00%20-7 eae tant oaV ova Lage a c= 12096 Cr includes ig Caputance 3-227

intel. 8279/8279-5 WAVEFORMS READ OPERATION : = _ ; WRITE OPERATION CLOCK INPUT

intel. 8279/8279-5 WAVEFORMS (Continued) SCAN pe ~FLELIPL UU UU ears) a a a 0123-11 3-229

intel. 8279/8279-5 WAVEFORMS (Continued) DISPLAY sont Co ee i ae CS a C2 GRD "3 So Se S24 MS SC ATONED FIFO RETURN LINES ARE SAMPLED ONE AT A TIME AS SHOWN. NOTE: Shown is encoded scan left entry ‘S2-S3 are not shown but they are simply S; divided by 2 and 4. 3-230