8278

8278 INTEL | Alldatasheet

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a Simultaneous Keyboard and Display a N-Key Rollover with Programmable Operations Error Mode on Multiple New Closures = Interface Signals for Contact and a= 16-Character 7-Segment Display Capacitive Coupled Keyboards Interface = 128-Key Scanning Logic y 9 *e9 = Right or Left Entry Display RAM = 10.7 msec Matrix Scan Time for 128 Keys and 6 MHz Clock = Depress/Release Mode Programmable a 8-Character Keyboard FIFO a Interrupt Output on Key Entry The Intel® 8278 is a general purpose programmable keyboard and display interface device designed for use with 8-bit microprocessors such the mps-80"™ and MCS-85™, The keyboard portion can provide a scanned interface to 128-key contact or capacitive-coupled keyboards. The keys are fully debounced with N-key rollover and Programmable error generation on multiple new key closures. Keyboard entries are stored in an 8-character FIFO with overrun status indication when more than 8 characters are entered. Key entries set an interrupt request output to the master CPU. The display portion of the 8278 provides a scanned display interface for LED, incandescent, and other popular display technologies. Both numeric displays and simple indicators may be used. The 8278 has a 16X4 display RAM which can be loaded or interrogated by the CPU. Both right entry calculator and left en- try typewriter display formats are possible. Both read and write of the display RAM can be done with auto- increment of the display RAM address. P+ DP rey, e © PIN CONFIGURATION PIN NAMES BLOCK DIAGRAM adh 0 bvce 07-29 | oaTA sus - ‘AD. WA | READ, WRITE STROBES LEVEL eset 4 x fe X).%2__| PREG. REFERENCE INPUT {i — Neds he, s¥nc HIGH FREQUENCY OUTPUT pata oars Coun Me Bde fe. AL KEYBOARD RETURN LINE sus EY) eorren KO | eaten Kez : ctr CLEAR ERROR Mo moOe aa DM | MoMo MATRIX SCAN LINES. _2 Wg Pm ia INTERRUPT REQUEST Ko) otiecr LL insreness Pee sync xo fim or TONE ENABLE eagunce key cLock = po 12 apm, 7 Ly 110, r " syne on 7 Dm » " os 24 DJ ERROR Ogre aire “ ort 19 2 pave TIMING | OUT 16-01GIT 10 ow apier a ow | ex ke ait” INTERNAL “3s ous Pwr ano 11-142 waw.chipdocs .com Be sure to visit ChipDocs web site for more information.

PIN DESCRIPTION £8 x The 8278 is packaged in a 40-pin DIP. The following is a % oF brief functional description of each pin. AF pe: Signal Pin No. Description Signal Pin No. Description « & Do-D7 12-19 Three-state, bi-directional data bus ERROR 24 ~— Error signal. This line is high when- lines used to transfer data and com- ever two new key closures are de- mands between the CPU and the tected during a single scan or when 8278. too many characters are entered WR 10 — Write strobe which enables the mas- into the keyboard FIFO. Itis reset by ter CPU to write data and com- a system RESET pulse or by a “1 mands between the CPU and the input on the CLA pin or by the 8278. CLEAR ERROR command. AD 8 Read strobe which enablesthemas- CLA 39 Input used to clear an ERROR con- ter CPU to read data andstatus from dition in the 8278. the 8278 internal registers. BP 21 Tone enable output. This line is high cs 6 Chip select input used to enable for 10ms following a valid key reading and writing to the 8278. closure; it is set high and remains high during an ERROR condition. Ao 9 Address input used by the CPU to . indicate control or data. Vcc, Voo 40,26 +5 volt power input: +5V + 10%. RESET 4 A low signal on this pin resets the GND 20,7 Signal ground. 6278. X1, X2 2.3. Inputs for crystal, L-C or external PRINCIPLES OF OPERATION timing signal to determine internal oscillator frequency. The following is a description of the major elements of the IRQ 23 Interrupt Request Output to the Programmable Keyboard: Display interface device. Refer master CPU. In the keyboard mode 0 lock diagram in Figure 1. the IRQ line goes low with each 1/10 Control and Data Buffers FIFO read and returns high if there ee is still information in the FIFO or an The I/O contro! section uses the CS, Ao, RD, and WR lines ERROR has occurred to control data flow to and from the various internal 7 registers and buffers (see Table 1). All data flow to and - ro h - abl Mo-Ms 27-33 Matrix scan outputs. These out- trom the 8278 is enabled by CS. The 8-bits of information puts control a decoder which scans le i fi the key matrix columns and the 16 being transferred by the CPU is identified by Ao. A logic ini ‘one means information is command or status. A logic zero r . Also, ‘ SO a4 WH 4 SO oa seria eietpten the means the information is data. RD and WR determine the return lines from the key matrix direction of data flow through the Data Bus Buffer (DBB) The DBB register is a bi-directional 8-bit buffer register RL 1 input from the multiplexer which in- which connects the internal 8278 bus butter register to the dicates whether the key currently external bus. When the chip is not selected (CS = 1) the being scanned is closed. DBB is in the high impedance state. The DBB acts as an HYS 22 Hysteresis output to the anaiog de- input when (RD, WA, CS) = (1, 0, 0) and an output when tector. (Capacitive keyboard config- (RD, WR, CS) = (0, 1, 0). uration). A “0” means the key cur- o ny being scanned has already CS Ac WR RD Condition 3& een recordet rT neepeee =z KCL 34K lock output to th log dt ° ° ' 0 Read DBB Data =: ‘ey clock output to the analog de- Pa tector (capacitive keyboard config- ° 1 1 0 Read STATUS uration) used to reset the detector o 0 0 1 Write Data to DBB before scanning a key. 0 1 0 1 Write Command to OBB SYNC 11 High frequency (400 KHz) output 1X XX Disable 8278 Bus is signal used in the key scan todetect High impedance a closed key (capacitive keyboard configuration). Scan Counter Bo-Bs 35-38 These four lines contain binary The scan counter provides the timing to scan the coded decimal display information keyboard and display. The four MSB’s (Ms-Me) scan the synchronized to the keyboard col- display digits and provide column scan to the keyboard via umn scan. The outputs are for a 4 to 16 decoder. The three LSB's (Mo-Mz) are used to multiplexed digital displays. multiplex the row return lines into the 8278. 11-143 waw.chipdocs .com Be sure to visit ChipDocs web site for more information.

Figure 1. System Configuration for Capacitive-Coupled Keyboard multiplexed by the 8278. When a key closure is detected, whenever the FIFO is not empty. matrix is transferred into a FIFO buffer. register keeps track of the number of characters in the be set to either left or right entry.

4 MULTIPLEXER

Figure 2. System Configuration for Contact Keyboard waw.chipdocs .com Be sure to visit ChipDocs web site for more information.

8278 * NNN

8278 COMMANDS Where Al indicates Auto Increment arid AgiAy, is the

. address of the next display character to be reat guty The 8278 operating mode is programmed by the master _ . ‘ SF ep CPU using the Ao, WR, and Do-D7 inputs as shown below: Al=1__ AUTO increment “So By Al=0 no AUTO increment oP a Write Display Command cooe [so | o [aos fue [oe] . Where Al indicates Auto Increment and A3-Ao is the = address of the next display character to be written. Clear/Blank Command wom Ke Komen Ge eels) Where the command bits are defined as follows: The master CPU presents the proper command on the Do- CE = Clear ERROR D7 data lines with Ao=1 and then sends a WR pulse. The CF = Clear FIFO commane is latched by the 6278 on Hie rising edge ofthe CD = Clear Display RAM to all High and is decoded internally to set the proper operating BD = Blank Display to all High (Display RAM mode. unaffected) UD = Unblank Display COMMAND SUMMARY : , The display is cleared and blanked following a Reset. Keyboard/Display Mode Set

8278 Status Read

an ne The status register in the 8278 can be read by the master . CPU using the Ao, RD, and Do-D7 inputs as shown below: where the mode set bits are defined as follows: K — the keyboard mode select bit 0 — normal key entry mode ag. 8 VALID 4 — special function mode: Entry on key closure and on key release D — the display entry mode select bit 0 — left display entry 1— right display entry RD }— the interrupt request (IRQ) output enable bit. O— enable IRQ output 1— disable IRQ output TT ELEY, TT, & — the error mode select bit EEL ELL, LS 0 — error on multiple key depression 1— no error on multiple key depression N-— the number of display digits select The 8278 places 8-bits of status information on the Do-D7 3 0— 16 display digits lines following (Ao, CS, RD) = 1, 0, 0 inputs from the ER 1— 8display digits master. 2 NOTE: The default mode following a RESET input a is all bits zero. Status Format oes ned Read FIFO Command Dy Dg Ds Dy Da Dz Di Do CODE o'r) 0) o}o0\\0)} 0/0; Where the status bits are defined as follows: OBF = Output Buffer Full Flag IBF = Input Buffer Full Flag Read Display Command KE = Keyboard Error Flag (multiple depression) ° y Aa | Az | At [Ao SySp = FIFO Status 11-145 waw.chipdocs .com Be sure to visit ChipDocs web site for more information.

8278 ; Status Description Data Read Sequence ea . The S3-So status bits indicate the number of entries (Oto 8) Before reading data, the master CPU must Bend: a in the 8-level FIFO. A FIFO overrun will lock status at 1114 command to select FIFO or Display data- Followingrine é The overrun condition will prevent further key entries until command, the master must read STATUS arid test thes” cleared. BUSY flag and the OBF flag to verify that the 8278 has . A multiple key closure error will set the KE flag and responded to the previous command. A typical DATA prevent further key entries until cleared. READ sequence is as follows: The IBF and OBF flags signify the status of the 8278 data buffer registers used to transfer information (data, status eusy J or commands) to and from the master CPU. The IBF flag is set when the master CPU writes Data or oer l J Commands to the 8278. The IBF flag is cleared by the 8278 during its response to the Data or Command. | } ‘ | The OBF flag is set when the 8278 has output data ready READ DISPLAY inst waster NEXT F for the master CPU. This flag is cleared by a master CPU from macro Ne ReROeYTE —-READSDATA un BYTE READY Data READ. PROCESSING NEXT BYTE The Busy flag in the status register is used as a LOCK- QUT signal to the master processor during response to

4 After the first read following a Read Display or Read FIFO

any command or data write trom the master. command, successive reads may occur as soon as OBF The master must test the Busy flag before each read rises. (during a sequence) to be sure that the 8278 is ready with valid DATA 8278 Data Write The ERROR and TONE outputs from the 8276 are set high The master CPU can write DATA to the 8278 Display for either type of error. Both types of error are cleared by buffers by using the Ao, WR and Do-D7 inputs as follows: the CLR input, by the CLEAR ERROR command, or by a reset. The FIFO and Display buffers are cleared saneeananiilvhtalitin * i (cn Giced FIFO status is used to indicate the number of characters in the FIFO and to indicate whether an error has occurred Overrun occurs when the entry of another character intoa tull FIFO is attempted. Underrun occurs when the CPU tries to read an empty FIFO. The character read will be the wa last one entered. FIFO status will remain at 0000 and the error condition will not be set.

8278 Data Read 04-0 nani Xe X HE

The master CPU can read DATA from the 8278 FIFO or Display buffers by using the Ao, RD, and Do-D7 inputs as follows: The master CPU presents the Data on the Do-D7 tines with Ao=0 and then sends a WR pulse. The data is latched by the 8278 on the rising edge of WR. Data Write Sequence 2S send a command to select the desired display entry mode = = and to specify the address of the next data byte. Following = the commands, the master must read STATUS and test the _ BUSY flag (B) and IBF flag to verify that the 8278 has RD responded. A typical sequence is shown below: ‘ 1 ' a 4 t The master sends a RD pulse with Ao=0 and CS=Oand the Comman Ye, aren Reoy 8278 responds by outputing data on lines Do-Dr. The data FOR yy FIRST BYTE MASTER WRITES is strobed by the trailing edge of RD. ORDATA NEXT BYTE 11-146 waw.chipdocs .com Be sure to visit ChipDocs web site for more information.

which indicates which column the key was found in. The and is lost. last three bits are from the row counter. filling again proceeds from there. this mode. Figure 5. Display Timing waw.chipdocs .com Be sure to visit ChipDocs web site for more information.

Auto Increment In the Right Entry mode, Auto ‘Incrementing’and non In the Left Entry mode, Auto Incrementing causes the Incrementing have the same effect as in the Lett Entry address where the CPU will next write to be incremented @xcept that the address sequence is interrupted: °F? by one and the character appears in the next location. i red With non-Auto Incrementing the entry is both to the same pispvay : RAM address and display position. Entry to an arbitrary 1.2 3 4 5 6 7 O0+~RAM address in the Left Entry — Auto Increment mode has no 1st ENTRY LLTTI TT tr) ADDRESS undesirable side effects and the result is predictable: 203 4 5 6 7 oO 1 wow TT TTT Ee) DISPLAY o 1 2 3 4 5 6 7+ RAM 2.3 4 § 6 7 oO 4 ADDRESS COMMAND 1ST ENTRY yo010101 o 1 2 3 4 5 6 7 ENTER NEXT AT LOCATION 5 AUTO INCREMENT o 1 2°53 4 5 6 7 coMmAND ENTER NEXT AT LOCATION 5 AUTO INCREMENT o 1 2.3 4 5 6 7 GRD ENTRY [tel |] 7 [si 7 | Starting at an arbitrary location operates as shown below: o 1 2 3 4 5 6 7 DISPLAY ‘COMMAND ADDRESS voovo107 ENTER NEXT AT LOCATION 5 AUTO INCREMENT 12 3 4 5 6 7 0 203 4 5 6 7 O14 OTH ENTRY | 5 i7 8 — 6 el2isaia Entry appears to be from the initial entry point. 11-149 waw.chipdocs .com Be sure to visit ChipDocs web site for more information.

ABSOLUTE MAXIMUM RATINGS* “COMMENT: Stresses above those listed Und gLAbsolute Maximum Ratings” may cause permanent dam he in yi above those indicated in the operational sections ‘of.fhis, = +> Wotage on Any en with ~0.8V1047V specification is not implied. Exposure to absolute © pectto Gro corer esseeeseeeesees maximum rating conditions for extended periods may D.C. CHARACTERISTICS Commercial: Ta = 0°C to 70°C; Vcc = +5V +5%; Vss = OV Viv input Low Voltage (All Inputs. v Except Xi, X2 Vina Input High Voitage (All Inputs Vee Vv Except X1, X2, RESET Vine RESET High Voltage Vou Output Low Voltage (Do-D7) [ff 04s |v [to =2.0ma Vov2 Output Low Voltage (All v lou = 1.6mA Other Outputs) Vou Output High Voltage (Dp-D7) [24 [| Vv ‘[ton=-400uA Von2 Output High Voltage (All Vv lon = -50nA Other Outputs) tie input Leakage Current (All +10 BA | VIN = Veo Inputs Except RESET) ToL Output Leakage Current (Do-D7) +10 HA | Vin = Vss + 0.45V or Vin = Veco lop + Icc_| Total Supply Current [| 435 [oma ‘| Veo = 5.5V hi Low Input Source Current (RESET) [ [02 | ma | Vi = 0.8V

8278 CLOCK OPTIONS

_ 6 a7 1 ante 12 | e278 x Xe 1-6 MHz 40 wh-130 uh EXTERNAL CRYSTAL INDUCTOR cLock 41-150 waw.chipdocs .com Be sure to visit ChipDocs web site for more information.

8278 &.. i 7 Te tet 2 A.C. CHARACTERISTICS Fae . Ta = 0°C to 70°C; Vcc = +5V +10%; Vss = OV ay Symbol | ___Parameter | Min | Max. [ Units | Condition. TA» tac ‘Address (CS, Ao) Setup to 5 Control (RD, WA) ae toa ‘Address Hold from Control jo [| [ns | tec Control Pulse Width | 20 | | ns | . two Data in Hold After WR T.E fo | | os | tro AD L.E. to Data Out Valid [_{[ 10 | ns | tor RD T.E. to Data Out Float [1 | 100 | ns | tucy Matrix Cycle Time [| 17 | ms | With 6MHz Crystai Recovery Time Between Reads nS WAVEFORMS Read Operation — Data Bus Buffer Register [eta 2] $ + | ee I~ ‘so I+ ‘or Write Operation — Data Bus Buffer Register fe tac 2} [4 tcc | + ten tf wa ! 1 (WRITE CONTROL! - oe | ‘wo Sz 11-151 waw.chipdocs .com Be sure to visit ChipDocs web site for more information.