8274

8274 INTEL | Alldatasheet

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8089 I/O Processor in polled, interrupt driven, or DMA driven modes of operation. The MPSC is a 40 pin device fabricated using Intel's High Performance HMOS TeFnology. Figure 1. Block Diagram

Table 1. Pin Description set the 8274 will not enable the serial receiver until CDg. data bytes until CTS has been activated. falling edge of the Transmit Clock. serial data to the communications channel (Channel B). data from the communications channel (Channel B). itis a general purpose input (Channel B). ‘SYNDETs or RTSg selection is done by WR2; D7.

Table 1. Pin Description (Continued) transmitter to request a DMA transfer. state lines which interface with the system's Data Bus. data bytes until CTS has been activated. falling edge of the Transmit Clock. data from the communications channel (Channel A). is a general purpose input (Channel A).

Py vo INTERRUPT PRIORITY IN/RECEIVER DMA. receive operation (Channel B).

28 INTERRUPT: The interrupt signal indicates that the

interrupt controller or a daisy-chain scheme. pin must be pulled high (inactive) in non-vector mode. or command transfers. A low selects Channel A. information transfer. A low means data. enables reading from or writing into registers.

intel. 8274 RESET ASYNCHRONOUS OPERATIONS When the 8274 RESET line is activitated, both MPSC channels enter the idle state. The serial out- Transmitter/Receiver Initialization But ines ara forced to the making state (igh) and ; the modem interface signals (RTS, DTA) are forced (See Detailed Command Description Section for high. In addition, the pointers registers are set to complete information) zero. In order to operate in asynchronous mode, each MPSC channel must be initialized with the following GENERAL DESCRIPTION information: 1. Transmit/Recei k Rate. This parameter is The Intel 6274 Muki-Protocol Serial Controller Is a spoctiod by bis 6 fond 7 of WRA The clock rate microcomputer peripheral device which supports may be set to 1, 16, 32, or 64 times the data-link Asynchronous, Byte Synchronous (Monosync, IBM bit rate. if the X1 clock mode is selected, the bit Bisync), and Bit Synchronous (ISO's HDLC, IBM's synchronization must be accomplished externally. SDLC) protocols. This controller's flexible architec- , men ture allows easy implementation of many variations 2: Number of Stop Bits. This parameter is specified of these three protocols with low software and hard- by bits 2 and 9 of WR4. The number of stop bits ware overheaa may be set to 1, 11%, oF 2. 3. Parity Selection. Parity may be set for odd, even, The Multi-Protoco! Serial controller (MPSC) imple- oF no parity by bits 0 and.1 of WR4. ments two independent serial receiver/transmitter 4. Receiver Character Length. This parameter sets channels. the length of received characters to 5, 6, 7, or 8 its. This rameter is specified by bits 6 Tot The MPSC supports several microprocessor inter- tag, 'S Parameter is specified by bits 6 and 7 face options: Polled, Wait, Interrupt driven and DMA , ; driven. The MPSC is designed to support INTEL's 5: Receiver Enable. The serial-channel receiver op- MCS-85 and iAPX 86, 88, 186, 188 families. eration may be enabled or disabled by setting or clearing bit 0 of WR. 6. Transmitter Character Length. This parameter FUNCTIONAL DESCRIPTION sets the length of transmitted characters to 5, 6, 7, oF 8 bits. This parameter is specified by bits 5 Additional information on Asynchronous and Syn- and 6 of WR5. Characters of less than 5 bits in chronous Communications with the 8274 is available length may be transmitted by setting the transmit- respectively in the Applications Notes AP 134 and ted length to five bits (set bits 5 and 6 of WRS to AP 145. 0. Command, parameter, and status information is The MPSC then determines the actual number of pains Wane a NTSC emi bits to be transmitted from the character data stored in 21 registers within the ( le byte. The bits to be transmitted must be right justi- registers for each channel, 2 readable registers for fied in the data byte, the next three bits must be Channel A and 3 readable registers for Channel B). set oO and all remaining bits must be set to 1. In the following discussion, the writable registers will he following table illustrates the Gata formats for be referred to as WRO through WR7 and the read- I able registers will be feferred to as RRO through Number of RR2. Bits Transmitted This section of the data sheet describes how the [97 D6 D5 D4 D3 D2 D1 DO} (Character Length) Asynchronous and Synchronous protocols are im- 1141 100 0c 1 plemented in the MPSC. It describes general consid- 11100 0ce 2 erations, transmit operation, and receive operation |1 1 0 0 0c cc 3 for Asynchronous, Byte Synchronous, and Bit Syn- 1 0 0 0c ccc 4 chronous protocols. ©000ccecee 5 7. Transmitter Enable. The serial channel transmit- ter operation may be enabled or disabled by set- ting or clearing bit 3 of WRE. 8. Interrupt Mode. Specified by bits 3 and 4 of WR1. 2-118

intel. 8274 For data transmission via a modem or RS-232-C in- ° The Transmit Buffer Empty bit (RRO; D2) is set by terface, the following information must also be spec- the MPSC when the data byte from the buffer is ified: loaded in the transmit shift register. Data should be 1, The Request To Send (RTS) (WAS; D1) and Data_—_Witten to the MPSC only when the Tx butfer be- Terminal Ready (DTR) (WR5; D7) bits must be set COMes empty to prevent overwriting. along with the Transmit Enable bit (WR5; D3). 2. Auto Enable may be set to allow the MPSC to ecel automatically enable the channel transmitter Receive when the clear-to-send signal is active and to au- The receive function begins when the Receive En- tomatically enable the receiver when the carrier- —_ able (WR3; DO) bit is set. If the Auto Enable (WR3; detect signal is active. However, the Transmit En- 5) option is selected, then Carrier Detect (CD) able bit (WR3; D3) and Receive Enable bit (WR3; must also be low. A valid start bit is detected if a low D1) must be set in order to use the Auto Enable persists for at least 1% bit time on the Receive Data mode. Auto Enable is controlled by bit 5 of WR3. (RxD) input. When loading Initialization parameters into the The data is sampled at mid-bit time, on the rising MPSC, WRG information must be written before the edge of RxC, until the entire character is assembled. WR1, WR3, WR5 parameters commands. The receiver inserts 1's when a character is loss During intaization, itis desirable to guarantee that {yan,8, bis. party (WE: DO) Is enatles ant rs the external/status latches reflect the latest inter- Syinned from the character. face information. Since up to two state changes are ° internally stored by the MPSC, at least two Reset External/Status interrupt commands must be is- sued. This procedure is most easily accomplished by Etror Reporting simply issuing this reset command whenever the The receiver also stores error status for each of the pointer register is set during initialization. 3 data characters in the data butter. Three error con- ‘An MPSC initialization procedure (MPSCSRXSINIT) {ions may be encountered during data reception in for asynchronous communication is listed in Intel pus mode: ; Application Note AP 134, 1. Parity. if parity bits are computed and transmitted with each character and the MPSC is set to check parity (bit 0 in WRG is set), a parity error will occur TRANSMIT whenever the number of 1” bits within the char- , . ; acter (including the parity bit) does not match the The transmit function begins when the Transmit En- ‘odd/even setting of the parity check flag (bit 1 in able bit (WRS5; D3) is set. The MPSC automatically WR4). When a parity error is detected, the parity adds the start bit, the programmed parity bit (odd, error flag (RR1; D4) is set and remains set until it ‘even or no parity) and the programmed number of is reset by the Error Reset command (WRO; D5, stop bits (1, 1.5 of 2 bits) to the data character being D4, D3). transmitted. 1.5 stop bits option must be used with : , ; , "2. Framing. A framing error will occur if a stop bit is X16, X32 or X64 clock options only. The data char. not detected immediately following the parity bit (if acter is transmitted least significant bit first. parity checking is enabled) or immediately follow: The serial data are shifted out from the Transmit ing the rege Wron Sata bit Bority chock ing Data (TxD) output on the falling edge of the Transmit oath : Framing Ever ot aR Dé) is set an 4 Clock (TxC) input at a rate programmable to 1, eth, Z t nat set by the Error Reset Com. Yaand, oF Yeath of the clock rate supplied to the TxC. ewa0. DS, ba Bh Ne Tor foset Cam. input. Framing Error adds an additional Y bit time to the The TxD output is held high when the transmitter character time so the Framing Error is not inter- has no data to send, unless, under program control, preted as a new start bit. the Send Break (WR5; D4) command is issued to 3, Overrun. If the CPU fails to read a data character hold the TxD low. while more than three characters have been re- . ceived, the Receive Overrun bit (RR1; D5) is set. If the External/Status Interrupt bit (WR1; DO) is set, When this occurs, the fourth character assembled the status of CD, CTS and SYNDE are monitored replaces the third character in the receive buffers. and, if any changes occur for a period of time great- Only the overwritten character is flagged with the or than the minimum specified pulse width, an inter- Receive Overrun bit. The Receive Overrun bit rupt is generated. CTS is usually monitored using (RR1; DS) is reset by the Error Reset command this interrupt feature (e.g., Auto Enable option). (WRO; DS, 04, D3). 2-419

The MPSC continuously monitors the state of five are set.

1. CTS—clear-to-send input pin. stored in 21 registers within the MPSC (8 writable
2. CD—carrier-detect input pin. registers for each channel, 2 readable registers for
3. SYNDET—sync-detect input pin. This pin may be Channel A and 3 readable registers for Channel B).

used as a general-purpose input in the asynchro- They are all accessed via the command ports. to be latched (and optionally cause an interrupt). the data to be loaded into Write Register 0 (WRO). read or write operation is completed. Figure 4. Command/Status Register Architecture (each serial channel)

intel. 8274 Asynchronous Mode Register Setup

00 Rx 5b/char

01 Rx 7b/char AUTO Rx

10 Tx6b/char ENABLE ENABLE

11_Rx8b/char

00 X1 Clock EVEN/

01 X16 Clock 01 1STOPBIT opp | EAE

10 X32 Clock 10 1% STOP BITS PARITY

00 Tx < 5b/char

01 1x7 b/char SEND ™ DTR 40 Tx6b/char BREAK | ENABLE RTS 11_Tx8b/char SYNCHRONOUS OPERATION— Transmit Set-Up—Monosync, Bisync MONOSYNC, BISYNC Transmit data is held high after channel reset, or if the transmitter is not enabled. A break may be pro- General grammed to generate a spacing line that begins as soon as the Send Break (WR5; D4) bit is set. With The MPSC must be initialized with the following pa- _the transmitter fully initialized and enabled, the de- rameters: odd or even parity (WR4; D1, DO), X1 fault condition is continuous transmission of the 8- or clock mode (WR4; D7, D6), 8- or 16-bit sync charac- _16-bit sync character. ter (WR4; D5, D4), CRC polynomial (WAS; D2), Transmitter Enable (WR5; D3), interrupt modes Using interrupts for data transfer requires that the (WR1, WR2), transmit character length (WR5; D6, Transmit Interrupt/DMA Enable bit (WR1; D1) be D5) and receive character length (WR3; D7, D6). _set. An interrupt is generated each time the transmit WR4 parameters must be written before WR1, WR3, —_— buffer becomes empty. The interrupt can be satis- WR5, WR6 and WR7. fied either by writing another character into the transmitter or by resetting the Transmitter Interrupt/ The data is transmitted on the falling edge of the © DMA Pending latch with a Reset Transmitter Inter- Transmit Clock, (TxC) and is received on the rising ‘edge of Receive Clock (RxC). The X1 clock is used for both transmit and receive operations for all three sync modes: Mono, Bi and External. Synchronous Mode Register Setup—Monosync, Bisync [ov [ps [os [oo fT os | oe | os | mo |

00 Ax 5b/char ENTER SYNC

01 Rx7b/char AUTO HUNT Rx CRC CHAR Rx

10 1x6b/char ENABLE MODE ENABLE LOAD | ENABLE 11_Rx8b/char INHIBIT 00 8 bit Sync EVEN/ 01 16 bit Sync ODD ee 11_ Ext Syne PARITY 00 1x < 5b/char 1 01 x7 b/char SEND Tx Tx CRC 10 1x6 b/char BREAK | ENABLE analy RTS | ENABLE 11_Tx8b/char 2421

intel. 8274 rupt/DMA Pending Command (WRO; D5, D4, D3). If The Transmit CRC Enable bit can be changed on nothing more is written into the transmitter, there _the fly any time in the message to include or exclude can be no further Transmit Buffer Empty interrupt, @ particular data character from CRC accumulation. but this situation does cause a Transmit Underrun The Transmit CRC Enable bit should be in the de- condition (RRO; D6). sired state when the data character is loaded into the transmit shift register. To ensure this bit in the Data Transfers using the RDY signal are for soft- Proper state, the Transmit CRC Enable bit must be ware controlled data transfers such as block moves. issued before sending the data character to the DY tells the CPU that the MPSC is not ready to MPSC. accept/provide data and that the CPU must extend the output/input cycle. DMA data transfers use the Transmit Transparent Mode. Transparent mode TxDRQ A/B signals which indicate that the transmit (Bisync protocol) operation is made possible by the butfer is empty, and that the MPSC is ready to ac- _abiility to change Transmit CRC Enable on the fly cept the next data character. If the data character is and by the additional capability of inserting 16 bit not loaded into the MPSC by the time the transmit ‘sync characters. Exclusion of DLE characters from shift register is empty, the MPSC enters the Trans- CRC calculation can be achieved by disabling CRC mit Underrun condition. calculation immediately preceding the DLE charac- ter transfer to the MPSC. The MPSC has two programmable options for solv- ing the transmit underrun condition: it can insert In the transmit mode, the transmitter always sends sync characters, or it can send the CRC characters _the programmed number of sync bits (8 or 16) (WR4; generated so far, followed by sync characters. Fol- D5, 04). When in the Monosync mode, the transmit- lowing a chip or channel reset, the Transmit Under- ter sends from WR6 and the receiver compares run/EOM status bit (RRO; D6) is in a set condition against WR7. One or two CRC polynomials, CRC 16 allowing the insertion of sync characters when there or SDLC, may be used with synchronous modes. In is no data to send. The CRC is not calculated on the transmit initialization process, the CRC genera- these automatically inserted sync characters. When tor is initialized by setting the Reset Transmit CRC the CPU detects the end message, a Reset Transmit Generator command (WRO; D7, D6). Underrun/EOM command can be issued. This al- lows CRC to be sent when the transmitter has no The External/Status interrupt (WR1; Do) rode can data to send. be used to monitor the status of the input as well as the Transmit Underrun/EOM latch. Optional- In the case of sync insertion, an interrupt is generat- _ty, the Auto Enable (WR3; D5) feature can be used ed only after the first automatically inserted sync _to enable the transmitter when CTS is active. The character has been loaded in the Transmit Shift first data transfer to the MPSC can begin when the Register. The status register indicates the Transmit xternal/Status interrupt (CTS (RRO; D5) status bit Underrun/EOM bit and the Transmit Buffer Empty set) occurs following the Transmit Enable command bit are set. (WR5; D3). In the case of CRC insertion, the Transmit Under- run/EOM bit is set and the Transmit Buffer Empty bit Receive is reset while CRC is being sent. When CRC has been completely sent, the Transmit Buffer Empty After a channel reset, the receiver is in the Hunt status bit is set and an interrupt is generated to indi- phase, during which the MPSC looks for character cate to the CPU that another message can begin synchronization. The Hunt begins only when the re- (this interrupt occurs because CRC has been sent ceiver is enabled and data transfer begins only when and sync has been loaded into the Tx Shift Regis- character synchronization has been achieved. If ter). If no more messages are to be sent, the pro- character synchronization is lost, the hunt phase can gram can terminate transmission by resetting RTS, be re-entered by writing the Enter Hunt Phase (WR3; and disabling the transmitter (WR5; D3). D4) bit. The assembly of received data continues until the MPSC is reset or until the receiver is dis- Bisync CRC Generation. Setting the Transmit CRC _—_ abled (by command or by CD while in the Auto En- enable bit (WRS5; DO) indicates CRC accumulation ables mode) or until the CPU sets the Enter Hunt when the program sends the first data character to Phase bit. Under program control, all the leading the MPSC. Although the MPSC automatically trans- sync characters of the message can be inhibited mits up to two sync characters (16 bit sync), it is from loading the receive buffers by setting the Sync wise to send a few more sync characters ahead of Character Load Inhibit (WR3; D1) bit. After character the message (before enabling Transmit CRC) to en- synchronization is achieved the assembled charac- ‘sure synchronization at the receiving end. ters are transferred to the receive data FIFO. After 2122

intel. 8274 receiving the first data character, the Sync Charac- modes. The Special Receive Condition interrupt is ter Load Inhibit bit should be reset to zero so that all caused by the Receive Overrun (RR1; DS) error con- characters are received, including the sync charac- dition. The error status reflects an error in the cur- ters. This is important because the received CRC _rent word in the receive butfer, in addition to any may look like a sync character and not get received. Parity or Overrun errors since the last Error Reset (WRO; D5, D4, D3). The Receive Overrun and Parity Data may be transferred with or without interrupts. error status bits are latched and can only be reset by Transferring data without interrupts is used for a _the Error Reset (WRO; DS, D4, 03) command. purely polled operation or for off-line conditions. There are two interrupt modes available for data © The CRC check result may be obtained by checking transfer: Interrupt on First Character Only and inter- for CRC bit (RR1; D6). This bit gives the valid CRC rupt on Every Character. result 16 bit times after the second CRC byte has been read from the MPSC. After reading the second Interrupt on First Character Only mode is normally CRC byte, the user software must read two more used to start a polling loop, a block transfer se- characters (may be sync characters) before check- quence using RDY to synchronize the CPU to the _ing for CRC result in RR1. Also for proper CRC com- incoming data rate, or a DMA transfer using the _putation by the receiver, the user software must re- RxDRQ signal. The MPSC interrupts on the first set the Receive CRC Checker (WRO; D7, D6) after character and thereafter only interrupts after a Spe- receiving the first valid data character. The receive 2 cial Receive Condition is detected. This mode can CRC Enable bit (WR3; D3) may also be enabled at be reinitialized using the Enable Interrupt On Next this time. Receive Character (WRO; D5, D4, D3) command which allows the next character received to gener- ate an interrupt. Parity Errors do not cause inte- © SYNCHRONOUS OPERATION—SDLC rupts, but End of Frame (SDLC operation) and Re- ceive Overrun do cause interrupts in this mode. If the external status interrupts (WR1; DO) are enabled © General an interrupt may be generated any time the CD - changes state. Like the other synchronous operations the SDLC mode must be initialized with the following parame- Interrupt On Every Character mode generates an in- _—ters: SDLC mode (WR4; D5, D4), SDLC polynomial terrupt whenever a character enters the receive (WAS; D2), Request to Send, Data Terminal Ready, buffer. Errors and Special Receive Conditions gener _‘ttansmit character length (WAS; D6, D6), interrupt ate a special vector if the Status Affects Vector modes (WA1; WR2), Transmit Enable (WR5; D3), (WR1B: D2) is selected. Also the Parity Error may be Fleceive Enable (WR3; D0), Auto Enable (WR3; D5) programmed (WR1; D4, D3) not to generate the spe- and External/Status Interrupt (WR1; DO). WR4 pa- cial vector while in the Interrupt On Every Character —_fameters must be written before WR1, WR3, WRS, mode. WRé and WR7. The Special Receive Condition interrupt can only oc- ‘The Interrupt modes for SDLC operation are similar cur while in the Receive Interrupt On First Character ‘to those discussed previously in the synchronous Only or the Interrupt On Every Receive Character operations section. Synchronous Mode Register Setup—SDLC/HDLC [or [os [os [oe | oe | oe [or] oo |

00 Rx 5 b/char ENTER px | ADDRESS

01 Rx 7 b/char AUTO

10Rx6b/char | ENABLES Hobe NRE vail 41. Rx 8 b/char 1 0 (SELECTS SDLC/ HDLC MODE)

00 Tx < 5b/char ° x

01 Tx7 b/char SEND 1x (SELECTS

OTR 10 Tx 6 b/char pReAK | ENABLE | soLc/Hotc | PTS ENABLE

11 Tx8 b/char CRC)

intel. 8274 Transmit The MPSC can be programmed to receive all frames or it can be programmed to the Address Search After a channel reset, the MPSC begins sending Mode. In the Address Search Mode, only frames SDLC flags. with addresses that match the value in WR6 or the global address (OFFH) are received by the MPSC. Following the flags in an SDLC operation the 8-bit Extended address recognition must be done by the address field, control field and information field may ‘microprocessor software. be sent to the MPSC by the microprocessor. The MPSC transmits the Frame Check Sequence using The control and information fields are received as the Transmit Underrun feature. The MPSC automati- data. cally inserts a zero after every sequence of § con- secutive 1's except when transmitting Flags or | SDLC/HDLC CRC calculation does not have an 8- Aborts. bit delay, since all characters are included in the cal- culation, unlike Byte Synchronous Protocols. SDLC—like protocols do not have provision for fill characters within a message. The MPSC therefore Reception of an abort sequence (7 or more 1's) will automatically terminates an SDLC frame when the cause the Break/Abort bit (RRO; D7) to be set and transmit data buffer and output shift register have no _will cause an External/Status interrupt, if enabled. more bits to send. It does this by sending the two After the Reset External/Status Interrupts Com- bytes of CRC and then one or more flags. This al- mand has been issued, a second interrupt will occur lows very high-speed transmissions under DMA or _at the end of the abort sequence. CPU control without requiring the CPU to respond quickly to the end-of-message situation. MPSC After a reset, the Transmit Underrun/EOM status bit is in the set state and prevents the insertion of CRC characters during the time there is no data to send. / Detailed Command/Status Description Flag characters are sent. The MPSC begins to send the frame when data is written into the transmit buf; GENERAL er. Between, the time the first data byte is written, and the end of the message, the Reset Transmit The MPSC supports an extremely flexible set of seri- Underrun/EOM (WRO; 07, D6) command must be —_al and system interface modes. issued. The Transmit Underrun/EOM status bit (RRO; D6) is in the reset state at the end of the The system interface to the CPU consists of 8 ports message which automatically sends the CRC char- or buffers: “en [e5[Ar[Ao] Read Operation | The MPSC Wehr Programmed to issue a Send 0|0]|0|Ch.ADataRead |Ch. A Data Write Abort command (WRO; D5, D4, D3). This command causes at least eight 1's butless than fourteen t'sto. | >|) : ce 4 Slats Read or 4 Gornmane/ Parameter be sent before the line reverts to continuous flags. ©| 11+ [one status Reaal Ch. B Commana/Par 1| x] x |High impedance _|High Impedance Receive oe Data butfers are addressed by Ay = 0, and Com- After initialization, the MPSC enters the Hunt phase, — mand ports are addressed by Ay = 1. and remains in the Hunt phase until the first Flag is received. The MPSC never again enters the Hunt phase unless the microprocessor writes the Enter © COMMAND/STATUS DESCRIPTION Hunt command. The MPSC will also detect flags . separated by a single zero. For example, the bit pat. The following command and status bytes are used tern 011111101111110 will be detected as two during initialization and execution phases of opera- flags tion. All Command/Status operations on the two channels are identical, and independent, except where noted. 2124

intel. 8274 Detailed Register Description Command 2 Reset External/Status interrupts— 3 p resets the latched status bits of RRO and re-enables them, allowing inter- Write Register 0 (WRO): rupts to occur again. Command 3 Channel Reset—resets the Latched tse Status bits of RRO, the interrupt prior- itization logic and all control registers [om | baal head tae [ee] for the channel. Four extra system clock cycles should be allowed for MPSC reset time before any addition- al commands or controls are written into the channel COMMANO/STATUS POINTER ‘REGISTER POINTER Command 4 Enable Interrupt on Next Receive Character—i the Interrupt on First Receive Character mode is selected, this command reactivates that mode after each complete message is re- De un cooe ceived to prepare the MPSC for the [mv oft Rexoanone ote) next message eo 1 0 eaey exists orennurrs Command Reset Transmitter Interrupt/DMA ed Pending—if The Transmit Interrupt/ "ee Guanscren TONNE DMA Enable mode is selected, the roo 8 RESET THINTIOMA PENOING MPSC automatically interrupts or re- 1 400 ERROR RESET quests DMA data transfer when the rors END OF INTERRUPT" transmit buffer becomes empty. When there are no more characters to be sent, issuing this command pre- “Channel A onty vents further transmitter interrupts or DMA requests until the next charac- ter has been completely sent. Command6 Error Reset—error latches, Parity DY nuteone and Overrun errors in RR1 are reset. oo ESET RECRC CHECKER Command7 End of Interrupt—resets the inter- 1} rns rupin-sorvice latch of the highest 470102-4 priority internal device under service. 07, 06 CRC Reset Code. 00 Null—has no effect. WRO 01 Reset Receive CRC Checker—re- D2, D1, DO—Command/Status Register Pointer bits Sets tne CAC acer to Os determine which write-register the next byte is to be taized to all 1's written into, or which read-register the next byte is to = be read from. After reset, the first byte written into 10 Reset Transmit CRC Generator—re- either channel goes into WRO. Following a read or sets the CRC generator to 0's. if in write to any register (except WRO) the pointer will SDLC mode the CRC generator's ini- point to WRO. tialized to all 1's. 1" Reset Tx Underrun/End of Message D5, D4, D3—Command bits determine which of the Latch. basic seven commands are to be performed. Command 0 Null—has no effect. Command 1 Send Abort—causes the generation of eight to thirteen 1's when in the SDLC mode. 2-125

intel. 8274 Write Register 1 (WR1): D4, D3 Receive Interrupt Mode. 00 Receive Interrupts/DMA Disabled. uss tse o1 Receive Interrupt on First Character [= [=[otele lot] Ierupt on Al cow

10 Interrupt on All Receive Characters

oT or Special Condition (Parity Error is a ext wrenmuer Special Receive Condition). ENABLE 14 Interrupt on All Receive Characters or Special Condition (Parity Error is emrennuer, not a Special Receive Condition). MAENABLE D5 Wait on Receive/Transmit—when + vananie the following conditions are met the starusarvects vecron RDY pin is activated, otherwise it is NecTONCHe OMT —o— PaED, held in the High-Z state. (Conditions: wntorupt Enabled Mode, Wait En- an abled, CS = 0, AO = 0/1, and At = © 0 MAINTIOMA OCEABLE 0). The RDY pin is pulled low when . avec the transmitter buffer is full or the ro- Ot oer oman On ceiver butfer is empty and it is driven +0 INTOM ALL Rs CHAR (PARITY AFFECTS High when the transmitter buffer is EcTOn)on Srecial conoimoN empty or the receiver buffer is full. ++ wrow aus me cHan pantry 0088 The RDY, and RDYg may be wired Comprrion, SOTOn OR SPECIAL OR connected since only one signal is active at any one time while the 1 wart on na.0-- wart On Te other is in the High Z state. D6 Must be Zero. tausy 8€76R0

07 Wait Enable—enables the wait func-

WAITEMABLE 1 EWABLE.o O4UABLE tion. 470102-5. WR2 Channel A Only D1, Do ‘System Configuration—These speci- fy the data transfer from MPSC chan- wri nels to the CPU, either interrupt or Do Exteral/Status Interrupt Enable—al- OMA based. lows interrupt to occur as the result 0 0 Channel A and Channel 8 both use of tanaitons on the CD, CTS or interrupts. inputs. Also allows inter- 1 1 168 rupts as the result of a Break/Abort © arene OMA: Channel detection and termination, or at the ; beginning of CRC, or sync character 10 Channel A and Channel B both use transmission when the Transmit Un- OMA. derrun/EOM latch becomes set. 14 Illegal Code. ot Transmitter Interrupt/DMA Enable— D2 Priority—this bit specifies the relative allows the MPSC to interrupt or re- priorities of the internal MPSC inter- quest a DMA transfer when the rupt/DMA sources. transmitter buffer becomes empty. 0 (Highest) RxA, TxA, RxB, TxB, ExTA, be Status Affects vector—(WR1, D2 ac- ExTB (Lowest). tive in channel B only.) If this bit is Highest) RxA, xB, TxA, not set, then the fixed vector, pro- Cee ee BETA, grammed in WR2, is returned from , an interrupt acknowledge sequence, 05:D4,D3 _ Interrupt Code—speciifies the behav- If the bit if set then the vector re- lor of the MPSC when it receives an turned from an interrupt acknowl- interrupt acknowledge _ sequence edge is variable as shown in the In- from the CPU. (See Interrupt Vector terrupt Vector Table. Mode Table.) 2-126

intel. 8274 0x x Non-vectored interrupts—intended 1 0 1 8085 Vector Mode 2—intended tor for use with external DMA CON- use as any secondary MPSC in a dai- TROLLER. The Data Bus remains in sy chained priority structure. (See a high impedance state during INTA System Interface section). Sequences. 110 8086/88 Vector Mode—intended for 100 8085 Vector Mode 1—intended for use as either a primary or secondary use as the primary MPSC in a daisy in a daisy chained priority structure. chained priority structure. (See Sys- (See System Interface section). tem Interface section). De Must be zero. or zero Pin 10 = ATS ‘one Pin 10 = SYNDETg Write Register 2 (WR2): Channel A Only us8 ise a [2 | © 0 BOTH INTERRUPT © 1 AMA. BINT 1 0 BOTHOMA + 4 LEGAL 1_PRIORITY RxA_AXB TxA TxB EXTAY EXTB® © PRIORITY AxA TxA AxB xB EXTAY EXTBY ——_ © 0 8085 MODE + © 1 8085 MODE 2 + 0 8086/88 MODE 14 eeGaL 1_VECTORED INTERRUPT

0 NON VECTORED INTERRUPT

(MUST BE ZERO

1 PIN1O SYNDET,

0 PINTO ATE,

NOTE: *External Status Interrupt only if EXT Interrupt Enable (WR1; DO) is set. 2127

intel. 8274 The following table describes the MPSC’s response to an interrupt acknowledge sequence: [os[os[os[ii[ mone [ wra [ atepue | 07 Do Steffens | wtiNTA | 1 1 0 0 1 1 OF 14 85Mode1 | 2ndINTA| V7 V6 V5 V4 vst v2" Vi vO adINTA} 0 0 0 0 © O OO O itiNTA| 7 1 0 0 4 +1 +O 9 1 85Mode1 | 2nd INTA | High Impedance 3rd INTA_| High Impedance 1stINTA | High Impedance [+ [+ [o| e | ccmade | arts VS va vo ver vor {stINTA | High Impedance 85Mode2 | 2ndINTA| V7 V6 V5 V4 vst v2t v1 vO adiNTA | 0 0 0 © 0 O 0 0 TstINTA | High impedance 85Mode 2 | 2ndINTA | High Impedance 3rd INTA_| High Impedance TstINTA | High Impedance [Lee] [oowe [asi [eines NOTE: “These bits are variable if the “status affects vector” mode has been programmed, (WA1B, 02). Interrupt/DMA Mode, Pin Functions, and Priority xno] "St Bork |horea | REOR od mony RXDRQ, | TxDRQa | RxDRQg | TxDRQs ba[ bao RASH az" | Pinte nz Pn 20 [ght Lowen [ofolo[ wr] wr] poy, | rove RxA, TxA, XB, TxB, EXTa, EXTa [+ [oo] wr | int | RxA, FxB, TxA, TxB, EXTs, EXTs jefe fs At AXA, TxA (OMA) [ int | | [INT | pono, | TORQ, RXA(), XB, TXB, EXTa, EXTa (INT) 1 [oma] | [ [int | RxA(t), AxB, TxB, EXTa, EXTs (INT) =) elon Scie (1) (1) PxDRQa | TxDRQ, | RXDRQg | TxDRQg | P*A™ xB), EXTa, EXT, (INT)

1 RxA, xB, TxA, TxB, (OMA)

RxA\\!), AxB("), EXT, EXTg (INT) NOTE: 1. Special Receive Condition 2-128

intel. 8274 Interrupt Vector Mode Table

8085 Modes

0 ° 0 Tx Buffer Empty ) 0 1 Ext/Status Change 0 1 0 Rx Char. Available ° 1 1 Special Rx Condition (Note 1) 1 ° 0 ‘Tx Butfer Empty 1 ° 1 Ext/Status Change 1 1 ° Rx Char. Available 1 1 1 Special Rx Condition (Note 1) NOTE: 1. Special Receive Condition = Parity Error, Rx Overrun Error, Framing Error, End of Frame (SDLC). 2 Write Register 2 (WR2): Channel B 'WR2 CHANNEL B D7-Do Interrupt vector—This register con- we .sB tains the value of the interrupt vector tupt acknowledge sequences. Interrupt Vector 170102-7 Write Register 3 (WR3): mse us ARE ENABLE SYNC CHAR LOAD INMIBIT AADOR SCH MODE (soc) x CRC ENABLE ENTER MUNT MODE AUTO ENABLES

00 RxSarTsicHaR

© 1 nev eirecHan +0 ee nirecHan 104 aeeeirecHan 170102-8 2-129

intel. 8274 WR3 Write Register 4 (WR4): Do Receiver Enable—A one enables the Teceiver to begin. This bit should be usp se set only after the receiver has been sagt BOGoGEc Dt Syne Character Load inhibit—A one prevents the receiver from loading [ENABLE PARITY sync characters into the receive butft- 7 DISABLE PARTY ers. In SDLC, this bit must be zero. 4 — EVEN PARITY b2 Address Search Mode—if the SDLC 7 O00 PARITY mode has been selected, the MPSC will receive all frames unless this bit is a 1. If this bit is a 1, the MPSC will © 0 ENABLE SYNC MODES receive only frames with address (OFFH) or the value loaded into WR8. 0 1 sstoren mis bt must be zero in non-SDLC +0 tssror ents D3 Receive CRC Enable—A one in this 1 1 Bstopeis bit enables (or re-enables) CRC cal- © 0 (BaITsyNCCHAR culation. CRC calculation starts with the last character placed in the Re- 04 wearrsynccHan ceiver FIFO. A zero in this bit dis- ables, but does not reset, the Receiv- 10 SPLEMOLEMODE(ONTTHITOVFLAG er CRC generator. 14 EXTERNAL SYNC MODE D4 Enter Hunt Phase—After initializa- tion, the MPSC automatically enters 9 0 xctock the Hunt mode. If synchronization is © + xiweLock lost, the Hunt phase can be re-en- tered by writing a one to this bit. 1 © x2ctock Ds ‘Auto Enable—A one written to this +4 xesctock bit causes CD to be automatic enable 170102-9 signal for the receiver and CTS to be an automatic enable signal for the py Even/Odd Parity—It parity is en- transmitter. A zero written to this bit abled, a one in this bit causes the limits the effect of CD and CTS sig- MPSC to transmit and expect even nals to setting/resetting their corre- parity, and a zero causes it to send sponding bits in the status register and expect odd parity. (ARO), , ls 07, Dé Receive Character length 03, 02 Stop bite/eync mode : ‘ 00 Selects synchronous modes

00 Receive 5 Data bits/character

01 Receive 7 Data bits/character o! Agyne mode, 4 stop bit/cheracter . , 10 Asyne mode, 1 stop bits/character

10 Receive 6 Data bits/character

14 Receive 8 Data bits/character 1 Asyne mode, 2 stop bits/character

D5, D4 Sync mode select 00 8-bit sync character wre 01 veh» haract DO Parity—A one in this bit causes a par- ‘syne character ity bit to be added to the pro- 1 0 SDLC mode (Flag sync) grammed number of data bits per 4 4 External sync mode eat Te oe ime mpse 07.08 Clock Mode—Selects the clock/data and receiv : ! fate multiplier for both the receiver is programmed to receive 8 bits per and the transmitter. 1x mode must be character, the parity bit is not trans- ated ioe ochreous a7 ferred to the microprocessor. With tei ao eclected bit inns Sheen other receiver character lengths, the nization must be done external parity bit is transferred to the micro- y. processor. 2-130

intel. 8274

00 Clock rate = Data rate x 1 D1 Request to Send—A one in this bit

01 Clock rate = rate X 16 forces the RTS pin active (low) and

fate = Data rate coe th t forsee tho RS pin in-

10 Clock rate = Data rate x 32 active (high),

v4 Clock rate = Data rate x 64 2 CRC Select—A one in this bit selects the CRC— 16 polynomial (x16 + x15 te Register 6 (WRE}: + X2 + 1) and a zero in this bit se- Write Register § (WRS): lects the CCITT-CRC polynomial (x16 . + X12 + X8 + 1). In SDLC mode, = < CCITT-CRC must be selected. [oT To [= [= [>] =] be Transmitter Enable—A 2010 in this bit forces a marking state on the trans- cnc name mitter output. If this bit is set to zero during data or sync character trans- ats mission, the marking state is entered after the character has been sent. If ° -18 (CRC MODE) this bit is set to zero during transmis- sion of a CRC character, sync or flag A Te enaste bits are substituted for the remainder evo oneax of the CRC bits. D4 Send Break—A one in this bit forces ye mserrs ontessonn the transmit data low. A zero in this bit allows normal transmitter opera- © 4 merersicnan tion. 06, DS Transmit Character length 10 reemsicnan

00 Transmit 1-5 bits/character

tt mesrwcnan o4 Transmit 7 bits/character orn 10 Transmit 6 bits/character 17010210 11 Transmit 8 bits/character Bits to be sent must be right justified least significant WRS bit first, e.g.: Do Transmit CRC Enable—A one in this bit enables the transmitter CRC gen- D7 D6 DS D4 D3 D2 DI DO erator. The CRC calculation is done 0 0 BS B4 63 B2 BI BO i from th anon butler into te shit regio. 07 Data Terminal Ready—When set, this bit forces A zero in this bit disables CRC calcu- the DTF preactive (ow). winen reset, this bit lations. If this bit is not set when a forces the DTA pin inactive (high). transmitter underrun occurs, the CRC will not be sent. Five or less mode allows transmission of one to five bits per character. The microprocessor must format the data in the following way: D7 D6) «6D5) «6A SBs«éesCéiSs«éi 1 1 14 1. 0 © 0 BO — Sends one data bit 1 1 1 0 0 © Bt BO — Sends two data bits 1 1° 0 0 © B82 Bt BO — Sends three data bits 1 0 0 0 83 B82 B1 80 — Sends four data bits o 0 0 B4 83 B2 __B1__BO___Sends five data bits 2131

intel. 8274 Write Register 6 (WR6): Write Register 7 (WR7): MSB .ss8 SB LsB Least significant Most Signitcant iSoLEnoLe Mose) onlin, 170102-11 SDLC/HDLC Mode) 170102-12 wre RRO D7-Do Sync/Address—This register con- 00 Receive Character Available—This tains the transmit sync character in bit is set when the receive FIFO con- Monosync mode, the low order 8 tains data and is reset when the sync bits in Bisync mode, or the Ad- FIFO is empty. dress byte in SDLC mode. o1 Interrupt In-Service’—If an Internal Interrupt is pending, this bit is set at wr the falling edge of the second INTA is steal pulse of an INTA cycle. In non-vec- D7-Do Syne/Flag—This register contains aes ous, tne Bie cat at tro fal the receive sync character in Mono- t , x ing edge of RD after pointer 2 is sync mode, the high order 8 sync bits 1 nae syne specified. This bit is reset when an in Bisync mode, or the Flag character bit | (01111110) in SDLC mode. WR7 is £0! omnand tarroate ih acviee ot not used in External Sync mode. are fe b2 Transmit Buffer Empty—This bit is set whenever the transmit butfer is *This bit is only valid when IPI is active low and is always zero in Channel B. Read Register 0 (RRO): se tse Rx CHAR AVAILABLE INT IN-BERVICE (CHA only) 1x BUFFER EMPTY CARRIER DETECT SYNCHUNT ors INTERRUPT MODE Tx UNDERRUN/EOM BREAW/ABORT 170102-13 2-132

intel. 8274 empty except when CRC characters ter the sync pattern is detected, the are being sent in a synchronous external logic must wait for two full mode. This bit is reset when the Receive Clock cycles to activitate the transmit buffer is loaded. This bit is SYNDET input. Once SYNDET is set after an MPSC reset. forced Low, it is good practice to D3 Cartier Detect—This bit contains the keep it Low until the CPU informs the state of the CD pin at the time of the ‘external sync logic that synchroniza- last change of any of the External/ tion has been lost or a new message Status bits (CD, CTS, Sync/Hunt, is about to start. The High-to-Low Break/Abort, or Tx Underrun/EOM). transition of the SYNDET output sets Any change of state of the CD pin the Sync/Hunt bit, which sets the Ex- causes the CD bit to be latched and ternal/Status interrupt. The CPU causes an External/Status interrupt. must clear the interrupt by issuing the This bit indicates current state of the Reset _External/Status Interrupt TD pin immediately following a Reset Command. External/Status Interrupt command. When the SYNDET input goes High D4 .¢/Hunt—In asynchronous modes, again, another External/Status inter- te aperuion ot thle bh le skndlar to rupt is generated that must also bo Ii) the CD status bit, except that Syno/ cleared. The Enter Hunt Mode con- Hunt shows the siato of the SYNOET trol bit is set whenever character syn- input. Any High-to-Low transition on chronization is lost or the end of the SONDET pin sets this bit, and message is detected. In this case, causes an External/Status interrupt the MPSC again looks for a High-to- (if enabled). The Reset External/ Low transition on the SYNDET input Status Interrupt command is issued and the operation repeats as ex- to clear the interrupt. A Low-to-High plained previously. This implies the transition clears this bit and sets the CPU should also Inform the extemal External/Status interrupt. When the logic that character synchronization External/Status interrupt is set by the has been lost and that the MPSC is change in state of any other input or waiting for SYNDET to become ac- condition, this bit shows the inverted tive. state of the SYNDET pin at time of In the Monosync and Bisyne Receive the change. This bit must be read im- modes, the Sync/Hunt status bit is mediately following a Reset Exter- initially set to 1 by the Enter Hunt nal/Status Interrupt command to Mode bit. The Sync/Hunt bit is reset read the current state of the when the MPSC establishes charac- SYNDET input. ter synchronization. The High-to-Low In the External Sync mode, the transition of the Sync/Hunt bit caus- Syno/Hunt bit persion in a fashion es an External/Status interrupt that similar to the Asynchronous mode, must be cleared by the CPU issuing ‘except the Enter Hunt Mode control the Reset External/Status Interrupt bit enables the external sync detec- command. This enables the MPSC to tion logic. When the External Sync detect the next transition of other Ex- Mode and Enter Hunt Mode bits are ternal/Status bits. set (for example, when the receiver is When the CPU detects the end of enabled following a reset), the message or that character synchroni- SYNDET input must be held High by zation is lost, it sets the Enter Hunt the external logic until external char- Mode control bit, which sets the acter synchronization is achieved. A Sync/Hunt bit to 1. The Low-to-High High at the SYNDET input holds the transition of the Sync/Hunt bit sets ‘Sync/Hunt status in the reset condi- the External/Status Interrupt, which tion. must also _be cleared by the Reset iz it External/Status Interrupt Command. eed SIMDEY met ee aan Note that the SYNDET pin acts as an Low on the second rising edge of output in this mode, and goes low ev- RxC after the rising edge of 7c on ery time a sync pattern is detected in which the last bit of the sync charac- the data stream. ter was received. In other words, af- 2-193

intel. 8274 In the SDLC mode, the Sync/Hunt bit Break sequence also causes the Ex- is initially set by the Enter Hunt mode ternal/Status interrupt to be set. The bit, or when the receiver is disabled. Reset External/Status Interrupt com- In any case, it is reset to 0 when the mand must be issued to enable the opening flag of the first frame is de- break detection logic to look for the tected by the MPSC. The External/ next Break sequence. A single extra- Status interrupt is also generated, neous null character is present in the and should be handled as discussed receiver atter the termination of a previously. break; it should be read and discard- Unlike the Monosync and Bisync ed. modes, once the Sync/Hunt bit is re- In the SDLC Receive mode, this set in the SDLC mode, it does not status bit is set by the detection of an need to be set when the end of mes- Abort sequence (seven or more 1's). sage is detected. The MPSC auto- The External/Status interrupt is han- matically maintains synchronization. dled the same way as in the case of The only way the Sync/Hunt bit can a Break. The Break/Abort bit is not be set again is by the Enter Hunt used in the Synchronous Receive Mode bit, or by disabling the receiver. mode. Ds Clear to Send—This bit contains the D0 All Sent—This bit is set when all inverted state of the CTS pin at the characters have been sent, in asyn- time of the last change of any of the chronous modes. It is reset when External/Status bits (CD, CTS, Sync/ characters are in the transmitter, in Hunt, Break/Abort, or Tx Underrun/ asynchronous modes. in synchro- EOM). Any change of state of the nous modes, this bit is always set. CTS pin causes the CTS bit to be RY: Residue Codes—Bit synchronous latched and causes an External/ 1, 44 54 protocols allow I-fields that are not Status interrupt. This bit indicates the , D2, an integral number of characters. inverse of the current state of the Since transfers from the MPSC to the CTS pin immediately following a Re- CPU are character oriented, the resi- set External/Status Interrupt com- due codes provide the capability of mand. receiving leftover bits. Residue bits De Transmitter Underrun/End of Mes- are right justified in the last data byte sage—This bit is in a set condition received or first CRC byte. following a reset (internal or exter- 4 Parity Error—if is enabled, this nal). The only command that can re- Farity Error ¥ parity is enabled, this set this bit is the Reset Transmit Un- whose parity does not match the pro- derrun/EOM Latch command (WRO, grammed sense (Even/Odd). This bit Og and D7). When the Transmit Un- is latched. Once an error occurs, it derrun condition occurs, this bit is remains set until the Error Reset set, which causes the Extemal/ command is written. Status Interrupt which must be reset : “bit j by issuing a Reset External/Status 05 Receive Overrun Error—This bit indi- command (WRO; command 2). cates that the receive FIFO has been overloaded by the receiver. The last D7 Break/Abort—in the Asynchronous Character in the FIFO is overwritten Receive mode, this bit is set when a and flagged with this error. Once the Break sequence (null character plus overwritten character is read, this er- framing error) is detected in the data ror condition is latched until reset by stream. The External/Status inter- the Error Reset command. If the upt, if enabled, is set when break is MPSC is in the status affects vector detected. The interrupt service rou- mode, the overrun causes a special tine must issue the Reset External/ Receive Condition Vector. Status Interrupt command (WRO, ° Command 2) to the break detection 96 CRC/Framing Error—in async logic so the Break sequence termina- modes, a one in this bit indicates a tion can be recognized. receive framing error. In synchronous ee modes, a one in this bit indicates that ‘The Break/Abort bit is reset when the calculated CRC value does not the termination of the Break se- match the last two bytes received. It quence is detected in the incoming Gan be reset by issuing an Error Re- data stream. The termination of the set command. 2-134

intel. 8274 SDLC Residue Code Tabie (| Field Bits in 2 Previous Bytes) [RR | First CRC First CRC | Last Data Last Data | First CRC | Last Data [ps pz p1| Byte Byte Byte Byte Byte Byte [so of o | » | o | 2] of: ]o]s | [oof o | « | o | a | o | 2] of] CE fr o1/ o | 7].of. |e --|-| fo+ +f o |e] of-j|-|,- |)- ]-]| Read Register 1 (RR1): (Special Receive Condition Mode) vse ws for Joe Jos [m+ [os joe jos | | ne ee ALL SENT | FIRST CRC ———ow eyTE LAST DATA BYTE ove ° 8 RESIDUE DATA. 8 BITS/CHAR. MODE ‘Rx OVERRUN ERROR cncirnabna ERROR .END OF FRAME (SDLC/HOLC MODE) 2-135

intel. 8274 07 End of Frame—This bit is valid only an interrupt acknowledge signal. When the internal in SDLC mode. A one indicates that a or external interrupt controller receives the acknowl- valid ending flag has been received. _ edge, it vectors the microprocessor to a service rou- This bit is reset either by an Error Re- _ tine, in which the transaction occurs. set command or upon reception of the first character of the next frame. DMA operation is accomplished via an external DMA controller. When the MPSC needs a data transfer, it requests a DMA cycle from the DMA controller. The Read Register 2 (RR2): DMA controller then takes control of the bus and simultaneously does a read from the MPSC and a use use write to memory or vice-versa. The folowing secon decries the many oni tions of these basic types of system interface tech- niques for both serial channels. erie in Vector Veaeruecetwns:0 | POLLED OPERATION 170102-15 In the polled mode, the CPU must monitor the de- sired conditions within the MPSC by reading the ap- RR2 Channel B propriate bits in the read registers. All data ‘wallable, D7-D0 Interrupt Vector—Contains the inter- status, and error conditions are represented by the Tupt vector programmed into WR2. If appropriate bits in read registers 0 and 1 for chan- the status affects vector mode is se- nels A and B. fected (WR1; D2), it contains the modified vector (See WR2). RR2 There are two ways in which the software task of contains the modified vector for the monitoring the status of the MPSC has been re- highest priority interrupt pending. If duced. One is the “ORing” of all conditions into the no interrupts are pending, the vari- Interrupt Pending bit. (RRO; D1 channel A only). This able bits in the vector are set to one. _bit is set when the MPSC requires service, allowing the CPU to monitor one bit instead of four status registers. The other is available when the “status-af- SYSTEM INTERFACE fects-vector” mode is selected. By reading RR2 Channel B, the CPU can read a vector who's value will indicate that one or more of group of conditions General has occurred, narrowing the field of possible condi- The MPSC to Microprocessor System interface can fons. .Se8 WAZ and RAZ in the Detailed Command be configured in many flexible ways. The basic inter- face types are polled, wait, interrupt driven, or direct memory access driven. WAIT OPERATION Polled operation is accomplished by repetitively _ Wait Operation is intended to facilitate data trans- reading the status of the MPSC, and making deci- mission or reception using block move operations. If sions based on that status. The MPSC can be polled —_—_@ block of data is to be transmitted, for example, the at any time. CPU can execute a String 1/O instruction to the MPSC. After writing the first byte, the CPU will at- Wait operation allows slightly faster data throughput tempt to write a second byte immediately as is the for the MPSC by manipulating the Ready input to the case of block move. The MPSC forces the RDY sig- microprocessor. Block Read or Write Operations to —_—‘"al low which inserts wait states in the CPU's write the MPSC are started at will by the microprocessor ©YCle until the transmit buffer is ready to accept a and the MPSC deactivates its RDY signal if it is not "ew byte. At that time, the RDY signal is high allow- yet ready to transmit the new byte, or if reception of _ing the CPU to finish the write cycle. The CPU then new byte is not completed. attempts the third write and the process is repeated. Interrupt driven operation is accomplished via an in- Similar operation can programmed for the receiver. ternal or external interrupt controller. When the During initialization, wait on transmit (WR1; D5 = 0) MPSC. requires service, it sends an interrupt réquest signal to the microprocessor, which responds with 2-136

intel. 8274 Software Flow, Polled Operation INTERRUPT DRIVEN OPERATION The MPSC can be programmed into several inter- rupt_ modes: Non-Vectored, 8085 vectored, and 8088/86 vectored. In both vectored modes, multiple MPSC’s can be daisy-chained. [oom | [ wom ] In the vectored mode, the MPSC responds to an interrupt acknowledge sequence by placing a call in- struction (8085 mode) and interrupt vector (8085 can, (he BUF Emer £ and 8088/86 mode) on the data bus. q The MPSC can be programmed to cause an inter- rupt due to up to 14 conditions in each channel. The [reno soars] fener ara status of these interrupt conditions is contained in Read Registers 0 and 1. These 14 conditions are all directed to cause 3 different types of internal inter- necewve rananrt rupt request for each channel: receive/interrupts, 17010216 transmit interrupts and external/status intorupts (t [WA enabled). NOTES: - . 1 BR: D0 is reset automatically when the data is This results in up to 6 internal interrupt request sig- a iswit. | als. The priority of those signals can be pro-

2 RRO, D2 is reset automatically when the data is writ: grammed to one ot two fixed modes:

Highest Priority Lowest Priority or wait on receive (WR1; DS = 1) can be selected. The wait operation can be enabled/disabled by set- RxA AxB TxA TxB EXxTA ExTB ting/resetting the Wait Enable Bit (WR1; D7). RxA TxA RxB TxB ExTA ExT8 NOTE: CAUTION: ANY CONDITION THAT CAN CAUSE The interrupt priority resolution works differently for THE TRANSMITTER TO STOP (E.G., CTS GOES —_vectored and non-vectored modes. INACTIVE) OR THE RECEIVER TO STOP (E.G., AX DATA STOPS) WILL CAUSE THE MPSC TO HANG THE CPU UP IN WAIT STATES UNTIL RE- SET. EXTREME CARE SHOULD BE TAKEN WHEN USING THIS FEATURE. Hardware Configuration, Polied Operation oF 7 ; WA oe Vee bp B07 Tha b b Ao p Ay mPsC 5 qc RO wa 17010217 2-137

intel. 8274 Interrupt Condition Grouping INTERNAL INTERRUPT conoirion mooe meauesr RECEIVE CHARACTER coos RECEIVE ovennun ERROR a a] Reece Berar ea [it Fingt NoW-SYNC CHARACTER (SING MODES INTERRUPT OW FIRST Se eee eas co rnANsition ey Ets Teast Svc tnansrrioi SUNG nnUWeSe TRANSUIT BUFFER EMPTY [raz] 170102-18 erent Gf—> Lowen prionITy INTERRUPTS NOT ACCEPTED IACeEPTED " 4 INTERRUPT (Brennan) centennial R R -— set, —-| _ a _ mower wonen conven wfTennurs NosccErTeD werennuers——* iPS . 170102-19 PRIORITY RESOLUTION: VECTORED MODE ing) edge of the first External INTA pulse and reset on the trailing (rising) edge of the second External Any interrupt condition can be accepted internally to INTA pulse. After an interrupt is accepted intone the MPSC at any time, unless the MPSC’s internal and External INT request is generated and the INTA signal is active, unless a shiher priority inter- goes inactive. IPO and IPI are used for daisy-chain- rupt is currently accepted, or if IPI is inactive (high). ing MPSC's together. The MPSC’s internal INTA is set on the leading (fall- 2-138

intel. 8274 Sa In-Service Timing INTERNAL INTERRUPT / ‘ACeEPTED cal —_—_SSSSSeSeeeeSSSsSSSSSSSSSSssssseses invennueT \\ / (EXTERNAL) fad 2 | (EXTERNAL) ta onrennad) Co iseavice . UNTERNAL) 170102-20 The MPSC's internal INTA is set on the leading (fall- Each of the six interrupt sources has an associated ing) edge of the first external INTA pulse, and reset _—_in-Service latch. After priority has been resolved, the ‘on the trailing (rising) edge of the second external _ highest priority In-Service latch is set. After the In- INTA pulse. After an interrupt is accepted internally, Service latch is set, the INT pin goes inactive (high). and external INT request is generated and TPO goes NOTE: inactive (high). IPO and IPI are used for daisy-chain- {the External INT pin is active and the IP! signal is pulled ing MPSC's together. inactive high, the wT signal will also go inactive. IPI quali- fies the External INT Signal. 2-139

intel. 8274 EO! Command Timing serrce wrennaconrenauey aeerves ee wrennuer / (erro a ~\\S\\/- cexreaa) wren / \\ co / - ‘oma - memes / peony wren Tare torcommane ‘Serena ——— 170102-21 Lower priority interrupts are not accepted internally After the interrupt is serviced, the End-of-Interrupt while the In-Service latch is set. However, higher pri- (EO!) command should be written to the MPSC. This. ority interrupts are accepted internally and a new ex- command will cause an internal pulse that is used to ternal INT request is generated. If the CPU responds reset the In-Service Latch which allows service for with a new INTA sequence, the MPSC will respond —_lower priority interrupts in the daisy-chain to resume, as before, suspending the lower priority interrupt. provided a new INTA sequence does not start for a higher priority interrupt (higher than the highest un- der service). If there is no interrupt pending internal- ly, the IPO follows IPI. 2-140

intel. 8274 Non-Vectored Interrupt Timing ne nue LOWER PRIORITY INTERRUPTS WOT ACCEPTED ————— 7 een y, _ soomurenst senna

7 LOWER PRIORITY INTERAUETE MOT ACCEPTED - 7

a 170102-22 PRIORITY RESOLUTION: nal in the vectored mode. It inhibits acceptance of NON-VECTORED MODE any additional internal interrupts and its leading edge starts the interrupt priority resolution circuit. In non-vectored mode, the MPSC does not respond —_The interrupt priority resolution is ended by the lead- to interrupt acknowledge sequences. The INTA input ing edge of the read signal used by the CPU to re- (pin 27) must be pulled high for proper operation. _trieve the modified vector. The leading edge of read ‘The MPSC should be programmed to the Status-Af- _ sets the In-Service latch and forces the external INT fects-Vector mode, and the CPU should read RR2 —_ output inactive (high). The internal pointer is reset to (Ch. B) in its service routine to determine which in- zero after the trailing edge of the read pulse. terrupt requires service. NOTE: In this case, the internal pointer being set to RR2 That if RR2 is specified but not read, no internal in- provides the same function as the internal INTA sig- _terrupts, regardless of priority, are accepted. 2441

intel. 8274 Vee wt wm cru Ya Ter Ter Lal we ta ci) Lid cd ursc arse wesc WIGHEST PRIORITY Lowest PRIORITY ‘ 170102-23 DAISY CHAINING MPSC It TPl is active (low), the MPSC knows that all higher priority MPSC's have no interrupts pending. The IPI In the vectored interrupt mode, rustle MPSC’'s can pin of the highest priority MPSC is strapped active be daisy-chained on the same INT, INTA signals. (low) to ensure that it always has priority over the These signals, in conjunction with the IPI and IPO. rest. allow a daisy-chain-like interrupt resolution scheme. This scheme can be configured for either 8085 or MPSC’s Daisy-chained on an 8088/86 CPU should 8086/88 based system. be programmed to the 8088/86 Interrupt mode (WR2; D4, D3 Ch. A). MPSC’s Daisy-chained on an In either mode, the same hardware configuration is 8085 CPU should be programmed to 8085 interrupt called for. The INT request lines are wire-OR’ed to- mode 1 if it is the highest priority MPSC. in this gether at the input of a TTL inverter which drives the mode, the highest priority MPSC issues the CALL INT pin of the CPU. The INTA signal from the CPU instruction during the first INTA cycle, and the inter- drives all of the daisy-chained MPSC’s. rupting MPSC provides the interrupt vector during ‘the following INTA cycles. Lower priority MPSC’s ‘The MPSC drives IPO (Interrupt Priority Output) inac- should be programmed to 8085 interrupt mode 2. tive (high) if IPI (Interrupt Priority Input) is inactive (high), or if the MPSC has an interrupt pending. MPSC’s used alone in 8085 systems should be pro- grammed to 8085 mode 1 interrupt operation. The IPO of the highest priority MPSC is connected to the IPI of the next highest priority MPSC, and so on. 2.142

intel. 8274 DMA Acknowledge Circuit oneK, ORCK, ORC, ox cr |) > ucripcexen > CTT CL hs [es] ho ay Ko AY To & {> ° 17010226 DMA Timing 170102-25 DMA OPERATION mutations of interrupt, wait, and DMA modes for channels A and B. Bits Dy, Op of WR2 Ch. A deter- Each MPSC can be programmed to utilize up to four mine these permutations. DMA channels: Transmit Channel A, Receive Chan- nel A, Transmit Channel B, Receive Channel 8. Each DMA Channel has an associated DMA Re- rela quest line. Acknowledgement of a DMA cycle is . done via normal data read or write cycles. This is Dy Do accomplished by encoding the DACK signals to gen- Wait Wait erate Ag, Ai, and CS, and multiplexing them with the Intorupt | Interrupt normal Ag, Ay, and CS signals. Pollen Polloa DMA Interrupt PenMTaiONS aE: Channels A and B can be used with different system DMA DMA interface modes. In all cases it is possible to poll the Poted Polled MPSC. The following table shows the possible per- NOTE: D1, DO = 1, 1 is illegal. 2143

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intel. 8274 PROGRAMMING HINTS Transmit Under-run/EOM Latch This section will describe some useful programming In SDLC/HDLC, bisync and monosync mode, the hints which may be useful in program development. _ transmit under-run/EOM must be reset to enable the CRC check bytes to be appended to the transmit frame or transmit message. The transmit under-run/ Asynchronous Operation EOM latch can be reset only after the first character is loaded into the transmit buffer. When the transmit- At the end of transmission, the CPU must issue “Re- _ter under-runs at the end of the frame, CRC check set Transmit Interrupt/DMA Pending” command in bytes are appended to the frame/message. The WRO to reset the last transmit empty request which _ transmit under-run/EOM latch can be reset at any was not satisfied, Failing to do so will result in the time during the transmission after the first character. MPSC locking up in a transmit empty state forever. However, it should be reset before the transmitter under-runs otherwise, both bytes of the CRC may not be appended to the frame/message. In the re- Non-Vectored Mode ceive mode in bisync operation, the CPU must read the CRC bytes and two more SYNC characters be- In non-vectored mode, the Interrupt Acknowledge fore checking for valid CRC result in RR1. pin (INTA) on the MPSC must be tied high through a 2 pull-up resistor. Failing to do so will result in unpre- dictable response from the 8274. Sync Character Load Inhibit In bisync/monosyne mode only, it is possible to pre- HDLC/SDLC Mode vent loading sync characters into the receive buffers by setting the sync character load inhibit bit (WR3; When receiving data in SDLC mode, the CRC bytes D1 = 1). Caution must be exercised in using this must be read by the CPU (or DMA controller) just option. It may be possible to get a CRC character in like any other data field. Failing to do so will result inthe received message which may match the sync receiver buffer overflow. The CRC bytes are not to character and not get transferred to the receive buff- be used for CRC verification. Residue bits may be er. However, sync character load inhibit should be contained in the first CRC byte. Also, the End of enabled during all pre-frame sync characters so the Frame Interrupt indicates that the entire frame has —_ software routine does not have to read them from been received. At this point, the CRC result (RR1: the MPSC. Dé) and residue code (RR1; D3, D2, 01) may be checked. In SDLC/HDLC mode, sync character load inhibit bit must be reset to zero for proper operation. Status Register RR2 AR2 contains the vector which gets modified to ind. FO! Command cate the source of interrupt (See the section titled EO! command can only be issued through channel A MPSC Modes of Operation). However, the state of irrespective of which channel had generated the in- the vector does not change if no new interrupts are —_terrupt. generated. The contents of RR2 are only changed when a new interrupt is generated. In order to get the correct information, RR2 must be read only after an interrupt is generated, otherwise it will indicate Priority In DMA Mode the previous state. There is no priority in DMA mode between the fol- lowing four signals: TxORQ(CHA), RxDRQ(CHA), TxDRQ(CHB), RxDRQ(CHB). The priority between Initialization Sequence these four signals must be resolved by the DMA controller. At any given time, all four DMA channels The MPSC initialization routine must issue a channel__ from the 8274 are capable of going active. Reset Command at the beginning. WR4 should be defined before other registers. At the end of the ini- tialization sequence, Reset External/Status and Er- ror Reset commands should be issued to clear any spurious interrupts which may have been caused at power up. 2-145

intel. 8274 ABSOLUTE MAXIMUM RATINGS* NOTICE: This is a production data sheet. The specifi- Ambient T cations are subject to change without notice. Undo BIBS cesses OCt0 +706 WARNING: Stressing tho device beyond to “Absolute os Maximum Ratings” may cause permanent damage. Storage Temperature These are stress ratings only. Operation beyond the Voltage on Any Pin with may affect device reliability. D.C. CHARACTERISTICS T, = 0°C to + 70°C; Voc = +5V +10% [_sympo_[ Parameter [Min [Max [unite [Test Concitions Inputtowvottage | -os | +08 | vi fo | InputHighvottage [+20 | Vootos | ov [| OuputLowvorge | | +045 |v | to = 20ma Output High Vottage | +24 | |v ton = 200A InputLeakage Curent [| +10 | wa | Viv = Voctoov Output Leakage Curent | | +10 | wa | Vour = Voc to 0.45V VeoSupply Curent | | 200 | ma NOTE: "1. For Extended Temperature EXPRESS, use MIL8274 electrical Parameters. CAPACITANCE Ta = 25°C; Voc = GND = OV [_sympot_[ Parameter | min | Max [unite [Test Conaitions _| Input Capacitance ee ee |_Cour | Outputcapacitance [18 | pF | Unmeasuredpins Inpur/Output Capacitance | | 20 | pr | retuned to GNO 2-146

intel. 8274 A.C. CHARACTERISTICS Ta = 0°C to + 70°C; Voc = +5V 10% [symbol | Parameter ‘| Min | Max | Units | TestConditions | [ey | GikPees ——SSSC*dt Caso wo] os | Tic, | CuK towtime its | 00 | ns | [en [eux Higntime its | a0 [nsf [wp cuKRisetme it | ots | Cu pekratim ——Ss—~ir if es [CY [um AGATsouptoRBE Po || rs | [inn | AB, At to Data OutputDoay || 200 | ns [| = 160eF | [isa | AAtHoaterOT to || os | [ino | FB to Data OuputDoiay | | 200 | ns | C= 160nr | [Ting | RO Pusewin te || os ST [iow | CSiaoatseuptownd [| 0 | | ns [| [wa | OS. AOAtHoWdaterwAT fo | |= |_| [Ciww | WRusowam oso] | os | [iow | batasouptowiT id; eo | i] re | CS [wo | BataHoderewAT | o | tm | | [in | Pisewpoitad io |] os | [ie PimewanermiTaT SP wo | rs | d uD nTAPusewan ——SS—=d as |) | [ero | FL woo SYS Te P| [ito NTA tobataouptbeay | | 200 | ms |_| [tv | Recovery Time Between Conrois | suo | | ns | id [iow [US AGATTORDYAorROYaDewy [| 0 | ms [| [ocr | DataGockoe Pa] tm | [ioc [Bata Giocktowtime Sit veo || rs | [ooe | Data Gookrigntime if veo] | ms [| [io Tato THO Delay tt ode) | «| eo] we | [on PD HoatermeT | wo | | os | (Cu TSwNTowy SP *# |e |) [| [ino Cw Noy SCP | || [ee | OTS.C0, SYROETLowtime | 200 | | ms | | [ie | GTS,06 SYNDET Hoh Time | 20 [| m= | | Cweo | External NT tomGTS, CO, SvNDET | | 00 | os [| 2-147

intel. 9274 A.C. TESTING INPUT/OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT TRPUT/OUTPUT " 20 20 DEVICE > rarronre Z ae oss 08 oa C= 150 pF s70102-27 I AAC. Teang pu are ven at 2.40 tor 8 Loge“ and 048 = fore ope -0 Tin monsuremonts ar ade a 20 for & sro100-28 Logic "1" and 0.8V for a Logic "0" CL = 100 pF ‘C, Includes Jig Capacitance WAVEFORMS CLOCK CYCLE tey: CuK t tow: ty ter s70100-208 READ CYCLE GS. ao. at an Van tae iy pa,-08, MGM MPCOANCE tao s70102-90 2-148

intel. 8274 WAVEFORMS (Continued) WRITE CYCLE DMA CYCLE anon a Rone 17010293 READ/WRITE CYCLE (SOFTWARE POLLED MODE) noonwn 170102-34 2.149

intel. 8274 INTA CYCLE é 3 is f eee z | - R | - F .

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NOTES: 1. INTA signal as FID signal. 2. IPI signal acts as CS signal. 2-150

intel. 8274 WAVEFORMS (Continued) TRANSMIT DATA CYCLE e vece ocx = ‘ne 170102-38 RECEIVE DATA CYCLE we ten Moen mo wr ' 170102-36 OTHER TIMING 170102-97 2-151