82731

82731 INTEL | Alldatasheet

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Technical content

80 MHz—82731-2 Synchronization and Tab Function

50 MHz—82731 = Single 5V Power Supply

Character and attribute information coming from the character generator and the 82730 Text Coprocessor. system for the 82730 Text Coprocessor and the CRT monitor. Figure 1. 82731 Block Diagram

Table 1. 82731 Pin Description 21 times the period of the internal dot clock. the period of the internal dot clock.

7 Double width attribute input; the internal dot clock

generation and is used for TAB function (active low). nected to a 3.3k resistor to ground if used. a must be 1/8 of the required dot clock frequency. quency of the internal dot clock. twice the dot clock frequency.

serial form for the video terminal. synchronize with the reference clock (RCLK). The dot clock is generated by voltage controlled _the quality of high resolution character displays. crystals even for generating frequencies up to 80 sired attributes. Figure 3. CRT System Block Diagram

reference for the dot data to be shifted serially to the frequency via the T1 pin, as shown in Figure 4b. required by the 82730. DCLK frequency is divided to 1/2 its normal value. oscillator controlled by a crystal attached to the X1, —the loop filter for the PLL. Figure 4. Clock Generation

3 HO} ov Py Cp « S pF

e) Example layout for printed circult . {) U/f-diagram . Figure 5. Designing the Oscillator Circuit

suppress overtone oscillations if the crystal fre- shown in Figure 5d. Table 1. Programming RCLK

tel” 2731 ADVANGE INFORMATION ch = nase SLK hightime is 2 dot clock periods and the CCLK Table 2. Programming CCLK w time is programmable from 1 to 16 dot clock ———— sriods, ROG = 1| 03 | D2 | D1 | DO! Ccik Period then CSYN is active (normally outside the active PROG = 0 | W3 | W2 | W1 | WO | (dot clocks) aaracter field) CCLK is forced to match RCLK. In Oo} o};o0j)0 16 ais case the CCLK high time is 3 dot clock periods o;o}o}1 7 stead of 2. ofo}1}o 18

0 O 1 1 3

order to support proportional spacing, the period ol1itolo 4 CCLK can be reprogrammed at the beginning of olitola 5 ach CCLK cycle (i.e. at the beginning of each olil1to 3 naracter) if PROG is inactive. ofa]a]a 7 2rogramming the character width is done via the 1} oy;o);o 8 slock width inputs WO-W3 according to Table 2. The 1 o|;o 1 9 'NO-W3 input data is clocked into the 82731 at the r1}o}1]o 10 ‘ising edge of CCLK and defines the width of the oe oe "1 currently displayed character (see Figure 7) i1/1]}ol]}o 12 1} 1]o {4 13 4 the width defeat attribute (WDEF) is active, the i+}a]/4]0 14 period of CCLK will be set to the programmed atadada 15 default value ignoring the clock width inputs WO- W3. This value is programmable from 3to 18 times 44. the period of the dot clock via the DO-D3 inputs, pag = 1: Programming the CCLK default clock width when the PROG input is active (see Figure 6) during the initialization phase via DO-D3 at the rising edge of CCLK. The default CCLK width should be programmed PROG = 0. Programming the clock width of the current only once aftera system reset. CLK cycle via WO-W3 at the rising edge of The CCLK clock period will be doubled if the double width attribute (DW) is asserted at the rising edge of CCLK. NOTE If width of CCLK is programmed to 17 or 18, zeros are shifted out from the internal shift register after the 16 data bits and displayed according to the attribute signals. Character Data Signals Clock Initialization Sequence (PROG) The character data signals are normally provided by the character ROM and clocked into the 82731 at the After power on the width of RCLK is a random value rising edge of CCLK. between 6 and 21 and the width of CCLK is a ran- dom value between 3 and 18. The character data signals consist of: the character data lines (D0-D15), The 82731 should be initialized in the following way: *_ the character width information (WO-W3), and * Activate the CSYN signal. CCLK is forced to © the half dot shift signal (HDOT), match RCLK, which has a minimum clock width of 6 dot clock periods Dot Data (D0-D15) * Apply the clock width informations to D0-D3 and D4-D7 according to tables. The dot data signals will be clocked into the 82731 * Activate the PROG signal. The default width of via the DO-D15 inputs at the rising edge of CCLK. CCLK and the width of RCLK are programmed —_The actual character width is defined by the WO-W3 at the naxt rising edge of CCLK (see Figure 6) inputs or the default width information previously © Remove the PROG signal programmed. The dot data will be displayed depen- dent on the control signais and on the correspond- CSYN can be removed at the beginning of the next _ing attribute information. The data bits are serially active data field. shifted out at the video output starting with DO. 7-193 210925-004

Character Width (WO-W3) character only. Half Dot Shift (HDOT) © width defeat WDEF. Figure 8. Function of HDOT on VIDEO

the CRVV attribute will produce the effect of revers- * lock synchronization CSYN. ter attribute, it may change from dot line to dat line @¢tive high signal. Double Width (DW) synchronizing CCLK and RCLK. how many characters are displayed within this part. _ troller with the information of the first character. Figure 9. Function of DW on DCLK and CCLK

Figure 10. Function of WOEF fied tabulator location, which is defined by CHOLD Purl wil be Soriinucully lene TAS. deactivated by the falling edge of RCLK. Figure 12 signal is active the video output signal is inverted.

Figure 11. Function of CSYN

intel 82731 ADVANCE INFORMATION ABSOLUTE MAXIMUM RATINGS “NOTICE: Stresses above those listed under , . 7 “Absolute Maximum Ratings” may cause perma: All Output and Supply or any other conditions above those indicated in not implied. Exposure to absolute maximum rating D.C. CHARACTERISTICS (Voc = 5V # 10%, Ta = 0°C to 70°C) Vor Output Low Voltage CCLK 05 v Io =8 MA RCLK 05 v Ion =4mA VIDEO Veo-1.2V | Vecg-06v | — lo. =0 Von | Output High Voltage CCLK, RCLK 2.4 v low = — 400 wA VIDEO Voc - 0.2V Veo - low =0 7-202 210828-004

intel” 2731 ADVANCE INFORMATION JS OOOO A.C. CHARACTERISTICS Ta= 00 70°C; Voc = SV + 10%. All timings measured at 15V unless otherwise noted | Towon | Deukeyeleperieg | 20 [vas [vs | 15 | ns | - | Tercr | CCLK tow time Tonon [#6Tonon) Toon | 18 Toon =10 10 Touer | CCLK high time 2 Tonon 2 Touon -5 -5 Fig. 17 Trunn | RCLK low time 3TonoH |18 Tonon| 3 Touon | 18 Toxpn =10 ~10 Revenn ine -5 -5 Torcx | Data and attribute input set up time Toupx | Data and attribute . input hold time Ture | CHOLD active before end of TAB-character CHOLD pulse width 25 Thmrn | CHOLD inactive set up before rising edge of RCLK Tian | CHOLD inactive hold time after rising edge of RCLK Tou | Video output valid after 6 ideo output] rising edge of CCLK measured at Veo = 04V 10 Fig. 17 Fig. 18 Video output fall time 7-203 210925-004