8273

Intel Corporation

PROGRAMMABLE HDLC/SDLC PROTOCOL CONTROLLER

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relieves the system CPU of the low level real-time tasks normally associated with controllers. Figure 1. Block Diagram

086 Hie 23D brut

087 C19 2D a

Figure 2. Configuration (PDIP) Figure 3. 8273 Pin Configuration (PLCC)

intel. 8273 A BRIEF DESCRIPTION OF beginning ight bit FLAG (F) consisting of one zero, six ones, and a zero, an eight bit ADDRESS FIELD HOLC/SDLC PROTOCOLS (A), an eight bit CONTROL FIELD (C), a variable (N-bit) INFORMATION FIELD ()), a sixteen bit General FRAME CHECK SEQUENCE (FCS), and an eight bit ‘end FLAG (F), having the same bit pattern as the The High Level Data Link Control (HDLC) is a stan- _ beginning flag. In HDLC the Address (A) and Control dard communication link protocol established by In- __(C) bytes are extendable. The HDLC and the SDLC ternational Standards Organization (ISO). HDLC is _use three types of frames; an Information Frame is the discipline used to implement ISO X.25 packet _used to transfer data, a Supervisory Frame is used switching systems. for control purposes, and a Non-sequenced Frame is used for initialization and control of the secondary The Synchronous Data Link Control (SDLC) is an _ stations. IBM communication link protocol used to implement the System Network Architecture (SNA). Both the protocols are bit oriented, code independent, and § Frame Characteristics ideal for full duplex communication. Some common applications include terminal to terminal, terminal to An important characteristic of a frame is that is con- CPU, CPU to CPU, satellite communication, packet _tents are made code transparent by use of a zero bit switching and other high speed data links. In sys- __ insertion and deletion technique. Thus, the user can tems which require expensive cabling and intercon- adopt any format or code suitable for his system—it nect hardware, any of the two protocols could be ‘May even be a computer word length or a “memory used to simplify interfacing (by going serial), thereby | dump”. The frame is bit oriented that is, bits, not reducing interconnect hardware costs. Since both characters in each field, have specific meanings. the protocols are speed independent, reducing inter- | The Frame Check Sequence (FCS) is an error de- connect hardware could become an important appii- tection scheme similar to the Cyclic Redundancy cation. Checkword (CRC) widely used in magnetic disk stor- age devices. The Command and Response informa- tion frames contain sequence numbers in the control Network fields identifying the sent and received frames. The sequence numbers are used in Error Recovery Pro- In both the HDLC and SDLC line protocols, accord cedures (ERP) and as implicit acknowledgement of ing to a pre-assigned hierarchy, a PRIMARY (Con- _ frame communication, enhancing the true full-duplex trol) STATION controls the overall network (data nature of the HDLC/SDLC protocols. link) and issues commands to the SECONDARY (Slave) STATIONS. The latter comply with instruc- In contrast, BISYNC is basically half-duplex (two way tions and respond by sending appropriate RE- alternate) because of necessity to transmit immedi- SPONSES. Whenever a transmitting station must ate acknowledgement frames. HDLC/SDLC there- fend transmission prematurely it sends an ABORT _fore saves propagation delay times and have a po- character. Upon detecting an abort character, a re- _tential of twice the throughput rate of BISYNC. ceiving station ignores the transmission block called a FRAME. Time fill between frames can be accom- It is possible to use HDLC or SDLC over half duplex plished by transmitting either continuous frame pre- _lines but there is a corresponding loss in throughput ambles called FLAGS or an abort character. A time because both are primarily designed for full-duplex fill within a frame is not permitted. Whenever a sta- © communication. As in any synchronous system, the tion receives a string of more than fifteen consecu- _bit rate is determined by the clock bits supplied by tive ones, the station goes into an IDLE state. the modem, protocols themselves are speed inde- pendent. Frames A byproduct of the use of zero-bit insertion-deletion technique is the non-return-to-zero invert (NRZI) A single communication element is called a FRAME —_data transmission/reception compatibility. The latter which can be used for both Link Control and data _allows HDLC/SDLC protocols to be used with asyn- transfer purposes. The elements of a frame are the chronous data communication hardware in which the clocks are derived from the NRZI encoded data. 2-82

Figure 4. Frame Format Table 1. Pin Description [voc | 40 |_| POWER SUPPLY: +5v Supply. [eno [20 |_| GROUND: Ground. RESET 4 RESET: A high signal on this pin will force the 8273 to an idle state. which interface with the system Data Bus. a command or data from CPU to the 8273. a data byte or a status word from the 8273 to the CPU. indicates that the transmitter logic requires service. the Receiver logic requires service. between memory and the 8273 for a transmit operation. 8273 and memory for a receive operation.

Table 1. Pin Description (Continued)

7 RECEIVER DMA ACKNOWLEDGE: The Receiver DMA acknowledge

signal notifies the 8273 that the RxDMA cycle has been granted. | Ao-Ar__| 21-22 | 1 _| ADDRESS: These two lines are CPU interface Register Select lines.

27 RECEIVER CLOCK: The Receiver Clock is used to synchronize the

received by an active receiver. has started and the 8273 may begin to sample data on RxD line. can be Read by the CPU through the Data Bus Butfer. Louk | 3 | 1 | Lock: Asquare wave TTL clock.

intel. 8273 FUNCTIONAL DESCRIPTION CPU Interface The CPU interface is optimized for the MCS-80/ General 85™ bus with an 8257 DMA controller. However, the intertace is flexible, and allows either DMA or The Intel 8273 HDLC/SDLC controller is a micro- —_non-DMA data transfers, interrupt or non-interrupt computer peripheral device which supports the In- driven. It further allows maximum line utilization by ternational Standards Organization (ISO) High Level __ providing early interrupt mechanism for buttered Data Link Control (HDLC), and IBM Synchronous (only the information field can be transferred to Data Link Control (SDLC) communications proto- memory) Tx command overlapping. It also provides cols. This controller minimizes CPU software by sup- _ separate Rx and Tx interrupt output channels for ef- Porting a comprehensive frame-level instruction set ficient operation. The 8273 keeps the interrupt re- and by hardware implementation of the low level quest active until all the associated interrupt results tasks associated with frame assembly/disassembly _ have been read. and data integrity. The 8273 can be used in either synchronous or asynchronous applications. The CPU utilizes the CPU interface to specify com- mands and transfer data. It consists of seven regis- In asynchronous applications the data can be pro- ters addressed via CIA, Ay, Ao, RD and WR signals 2 grammed to be encoded/decoded in NRZI code. —_and two independent data registers for receive data The clock is derived from the NRZ! data using a digi- and transmit data. A;, Ao are generally derived from tal phase locked loop. The data transparency is two low order bits of the address bus. If an 8080 achieved by using a zero-bit insertion/deletion tech- based CPU is utilized, the RD and WR signals may nique. The frames are automatically checked for er- be driven by the 8228 I7OR and I7OW. The table rors during reception by ering the Frame Check —_shows the seven register select decoding: Sequence (FCS); the FCS is automatically generat- ed and appended before the final flag in transmit. —_[AyAg| TxDACK|RXDACK|CS|RO|WA| Register | The 8273 recognizes and can generate flags (01111110) Abort, Idle, and GA (EOP) characters. ojo 1} 0] 1) 0 |Command ojo 1 0] 0} 1 [Status The 8273 can assume either a primary (contro!) ora || 1 1 |0] 1] 0 [Parameter secondary (slave) role. It can therefore be readily | 0| 1 1 }0]0] 1 Result implemented in an SDLC loop configuration as typ | 1| 0 1 | 0] 1] 0 [Reset fied by the |BM 3650 Retail Store System by pro- [4] 9 1 |o]o] 1 [txiInTResutt gramming the 8273 into a one-bit delay mode. in | 4 | 4 1 lolilo _ such a configuration, a two wire pair can be effec- tively used for data transfer between controllers and x x ' : ° $ PRINT Rosa loop stations. The digital phase locked loop output ‘4 ‘' pin can be used by the loop station without the pres- |X| 0 | 1] 0] 1 [Receive Data ence of an accurate Tx clock. 2-85

Figure 5. 8273 Block Diagram Showing CPU Interface Functions

intel. 8273 Register Description RxDRQ: RECEIVE DMA REQUEST Requests a transfor of data between the 8273 and COMMAND memory for a receive operation. Operations are initiated by writing an appropriate command in the Command Register. RxDACK: RECEIVE DMA ACKNOWLEDGE The AxDACK signal notifies the 8273 that a receive PARAMETER DMA cycle has been granted, It is also used with RD ; Sioa) j to read data from the 8273 in non-DMA mode. Note: Parameters of commands that require additioal in- IS ERDACK to acti formation are written to this register. WA must not be asserted while is active. RESULT RD, WR: READ, WRITE Contains an immediate result describing an outcome 76 RD and WA signals are used to specity the dt ‘of an executed command. ° DMA transfers require the use of a DMA controller (WA TRANSMIT INTERRUPT RESULT such as the Intel 8257. The function of the DMA controller is to provide sequential addresses and Contains the outcome of 8273 transmit operation timing for the transfer, at a starting address deter- (good/bad completion). mined by the CPU. Counting of data blocks lengths is performed by the 8273. RECEIVE INTERRUPT RESULT To request a DMA transfer the 8273 raises the ap- Contains the outcome of 8273 receive operation ProPriate DMA REQUEST. DMA ACKNOWLEDGE i and READ enables DMA data onto the bus (inde- (good/bad completion), followed by additional re- sults which detail the reason for interrupt pendently of CHIP SELECT). DMA ACKNOWLEDGE " and WRITE transfers DMA data to the 8273 (inde- pendent of CHIP SELECT). STATUS It is also possible to configure the 8273 in the non- The status register reflects the state of the 6273 DMA data transfer mode. In this mode the CPU CPU Interface. module must pass data to the 8273 in response to non-DMA data requests indicated by status word. DMA Data Transfers Modem Interface The 8273 CPU interface supports two independent lod fe data interfaces: receive data and transmit data. At_ The 8273 Modem interface provides both dedicated high data transmission speeds the data transfer rate. and user defined modem control functions. Alll the of the 8273 is great enough to justify the use of di- control signals are active low so that EIA RS-232C rect memory access (DMA) for the data transfers. —_ inverting drivers (MC 1488) and inverting receivers When the 8273 is configured in DMA mode, the ele- (MC 1489) may be used to interface to standard mo- ments of the DMA interfaces are: dems. For asynchronous operation, this interface supports programmable NRZI data encode/decode, a digital phase locked loop for efficient clock extrac- ‘TxDRG: TRANSMIT OMA REQUEST tion from NAZI data, and modem control ports with Requests a transfer of data between memory and automatic CTS, CD monitoring and ATS generation. the 8273 for a transmit operation. This interface also allows the 8273 to operate in PRE-FRAME SYNC mode in which the 8273 prefix- es 16 transitions to a frame to synchronize idle lines TXDACK: TRANSMIT DMA ACKNOWLEDGE before transmission of the first flag. The TxDACK signal notifies the 8273 that a transmit _{t should be noted that all the 8273 port operations DMA cycle has been granted. It is also used with —_deal with logical values, for instance, bit DO of Port A WR to transfer data to the 8273 in non-DMA mode. —_will be a one when CTS (Pin 30) is a physical zero Note: RD must not be asserted while TxDACK is (logical one). active. 2.87

intel. 8273 PORT A—INPUT PORT Serial Data Logic During operation, the 8273 interrogates inout pins The Serial data is synehvonized by the user transmit CTS (Clear to Send) and CD (Carrier Detect). CTS is (TxC) and receive (AxC) clocks. The leading edge of used to condition the start of a transmission. If dur- TxC generates new transmit data and the trailing ing transmission CTS is lost the 8273 generates an —_ edge of AxC is used to capture receive data. The interrupt. During reception, if CD is lost, the 8273 NRZI encoding/decoding of the receive and trans- generates an interrupt. mit data is programmable. > 4 4 4 4 BF ao The diagnostic features included in the Serial Data logic are programmable loop back of data and se- . lectable clock for the receiver. In the loop-back [ers bean ro seno mode, the data presented to the TxD pin is internally [cb — CARRIER DETECT routed to the receive data input circuitry in place of [USER DEFINED INPUT PA, PAs, PA: ‘the RxD pin, thus allowing a CPU to send a message 21087520 to itself to verity operation of the 8273. The user defined input bits correspond to the 8273 i, Plectapie Cock clagnostic feature. when the PAs, PAg and PAg pins. The 8273 does not interro- tweet sample tri y DE Pre , " ple timing by the external circuitry. The gate or manipulate these bits. user may select to substitute the TxC pin for the AxC input on-chip so that the clock used to generate the PORT B—OUTPUT PORT loop back data is used to sample it. Since TxD is generated off the leading edge of TxC and AxD is During normal operation, if the CPU sets RTS active, sampled on the trailing edge, the selected clock al- the 8273 will not change this pin; however, if the lows bit synchronism. CPU sets RTS inactive, the 8273 will activate it be- fore each transmission and deactivate it one byte time after transmission. While the receiver is active | ASYNCHRONOUS MODE INTERFACE the flag detect pin is pulsed each time a flag se- i i quence is detected in the receive data stream. Fol. Vmouah the 6273 is fully compatible with the lowing an 8273 reset, all pins of Port B are set toa HOLC/SDLC communication line protocols, which high, active lovel are primarily designed for sychronous communica- , g tion, the 8273 can also be used in asynchronous Paar’ applications by using this interface. The interface employs a digital phase locked loop (DPLL) for clock recovery from a receive data stream and program- tt ncautsr ro xxx mable NRZI encoding and decoding of data. The sen oer weD OUrPUT PB, r,s Poy use of NRZI coding with SDLC transmission guaran- tees that within a frame, data transitions will occur at rag oerect least every five bit times—the longest sequence of 210479-29 ‘ones which may be transmitted without zero-bit in- sertion. The DPLL should be used only when NRZ! The user defined output bits correspond to the state coding is used since the NRZI coding will transmit of PB4-PB, pins. The 8273 does not interrogate or zero Sequence as line transitions. The digital phase manipulate these bits. locked loop also facilitates full-duplex and half-du- plex asynchronous implementation with, or without modems. 2-88

and bit distortion. This is accomplished by making _stant incoming RxD edges. phase error adjustments in discrete increments. or added to the nominal, depending upon which mission. Figure 8. DPLL Sample Timing

intel. 8273 SYNCHRONOUS MODEM—DUPLEX OR HALF DUPLEX OPERATION of oo ro xo a eC ee EC 1 SRC OPT ‘S5xCiK PLL on we. oxo Ne 210470-7 ASYNCHRONOUS MODES—DUPLEX OR HALF DUPLEX OPERATION ws Ti ee at ixt wept | woo KY wooen [fice S2CLK PLL [te | ctock 210479-8 ASYNCHRONOUS—NO MODEMS—DUPLEX OR HALF DUPLEX rer med RxD] L— _ TxD BaxciK Pas sex | eo | 210479-83 2-91

The DPLL simplifies the SDLC loop station imple- _frames are relayed to the next station on the loop. tion to station then, back to the controller. Any sec- _the same clock to implement Tx clock timing. Figure 9. SDLC Loop Application

intel. 8273 ee PRINCIPLES OF OPERATION Bit 7 CBSY (Command Busy) The 8273 is an intelligent peripheral controller which indicates in-progress command, set for CPU poll relieves the CPU of many of the rote tasks associat-__ when Command Register is full, reset upon com- ed with constructing and receiving frames. It is fully | mand phase completion. It is improper to write a ‘compatible with the MCS-80/85™ system bus. Asa command when CBSY is set; it results in incorrect peripheral device, it accepts commands from a CPU, __ operation. executes these commands and provides an Interrupt and Result back to the CPU at the end of the execu- tion. The communication with the CPU is done by activation of CS, RD, WR, pins while the Ay, Ao se- Coun) lect the appropriate registers on the chip as de- scribed in the Hardware Description Section. The 8273 operation is composed of the following sequence of events: [cownnno rnase | S2ra'SouMano anO PARAMETER REGISTERS = [ExecuTion range] "HE 82721800 oN TO CAMRY OUT THE COMMAND. vmeneoranesuinnsaerenen [am | [Cnesuer minst ] GtmaTion OF ONE OR MORE OF THE REGISTERS. 210479-40 The Command Place we C ~_) During the command phase, the software writes a zk (NO.OF COMMAND FLARE command to the command register. The command bytes provide a general description of the type of operation requested. Many commands require more detailed information about the command. In such a case up to four parameters are written into the pa- rameter register. The flowchart of the command S phase indicates that a command may not be issued if the Status Register indicates that the device is Ka busy. Similarly if a parameter is issued when the Pa- rameter Butter shows full, incorrect operation will oc- our. 210479-10 The 8273 is a duplex device and both transmitter and receiver may each be executing a command or Figure 10. Command Phase Flowchart passing results at any given time. For this reason separate interrupt pins are provided. However, the Bit 6 CBF (Command Buffer Full) command register must be used for one command sequence at a time. Indicates that the command register is full, itis reset when the 8273 accepts the command byte but does not imply that execution has begun. STATUS REGISTER The status register contains the status of the 8273 Bit 5 CPBF (Command Parameter Buffer Full) activity. The description is as follows. Dy Ds Ose 5p CPBF is set when the parameter butter is full, and is [easy | car [Per [cree | Rant] tant] [tuna] reset by the 8273 when it accepts the parameter. cesy | cer | ceer | cree | pent | Tent | RxiRA| TxIRA The CPU may poll CPBF to determine when addi. tional parameters may be written. 2-93

when the CPU has read the TxINT register. TxINT and RxiNT pins, for each data byte request.

An error detected during an operation.

after the CPU has read the RxINT register.

2 Oe Os Or Pe Os D4 Pa Oz Dy Op | Receiernervpt Rent Code | x Bite Alter NT

Figure 11. Rx Interrupt Result Byte Format

Figure 12. Tx Interrupt Result Byte Format mands such as Read Port A and Read Port B which _detail the condition. of the Result phase. The immediate results are pro- tains count thal indicates the number of bits ve. sults are available upon device interrupt, through Tx the high order bits of the | ee data byte ara indetor. sult Register RxI/R. The result may consist of a one- . be read during the result phase.

Figure 13. Result Phase Flowchart—interrupt Results

Figure 14. (Rx Interrupt Service) the 8273 to be readily used in full-duplex, half-du- transmission and interrogate them upon reception. In buttered transmit mode, the 8273 transmits a flag _ perfect for a two byte address field. Field is transferred to memory. mode. cal-AND of the specified register with the mask).

intel. 8273 eee When one bit dolayis st, Parecajansmits the re RESET OPERATING MODE (CMD CODE 51) ceive lata stream one ayed. iS le is entered at a receiver character boundary, and Ar Ao 07 Og Ds Ds Dy De Dy Do should only be used by Loop Stations. omo:[oTo[o[s[o[+[o]olo]i] ear-folatitat [TTT [4] RESET ONE-BIT DELAY (CMD CODE 64) Ay Ag D7 Dg Ds Ds D3 Dz Dy Dy — Any mode switches set in CMD code 91 can be re- [1] set using this command by placing zeros in the ap- omo:foTofo[s[iTofoTs [oo] — setusing this come par:Lotfolalatatats[s [5] (D5) HDLC MODE The 8273 stops the one bit delayed retransmission mode. In HDLC mode, a bit sequence of seven ones (01111111) is intorpreted as as an abort character. Otherwise, eight 11111111) signal . SET DATA TRANSFER MODE (CMD CODE 97) wise, eight ones (011111111) signal an abort Ar Ao D7 De Ds Ds Dz Dz Dy Do (D4) EOP INTERRUPT MODE owo-fofoTiTofofs fos [a Ts In EOP interrupt mode, an interrupt is generated PAR: Lo[sfo[ololofofofo]s| whenever an EOP character (01111111) is detected by an active receiver. This mode is useful for the When the data transfer mode is set, the 8273 will implementation of an SDLC loop controller in detect. interrupt when data bytes are required for transmis- ing the end of a message stream after a loop poll sion or are available from a receive. If a transmit interrupt occurs and the status indicates that there is no Transmit Result (TxIRA = 0), the interrupt is a (03) TRANSMITTER EARLY INTERRUPT MODE transmit data request. If a receive interrupt occurs (Tx) and the status indicates that there is no receive re- r . us . The early interrupt mode is specified to indicate Sul (RXIRA = 0), the interrupt is a receive data re- nen‘the 9279 should ganerate an ond of frame re quest. terrupt. When set, an early interrupt is generated when the last data character has been passed to the RESET DATA TRANSFER MODE (CMD CODE 8273. If the user software responds with another 57) transmit command before the final flag is sent, the final flag interrupt will not be generated and a new Ar Ao O7 Dg Os Ds Ds De Di Do frame will immediately begin when the current frame omo:[oToTo[s]o[s]o[1]1] 1] — iscomplete. This permits ames to be separated by . a single flag. If no additional Tx commands are pro- PAR: Lolals{stataf{afs fifo] vided, a final interrupt will follow. If the Data Transfer Mode is reset, the 8273 data NOTE: transfers are performed through the DMA requests —_In buffered mode, if a supervisory frame (no Infor- without interrupting the CPU. mation) Transmit command is sent in response to an early Transmit Interrupt, the 8273 will repeatedly transmit the same supervisory frame with one flag SET OPERATING MODE (CMD CODE 91) in between, until a non-supervisory transmit is is- Ay MeO) Oy OO O} O01 Oy sued. ~ fe[eT+[efefs Tofe Tots] Early transmitter interrupt can be used in butfered Cert t Pty ty mode by waiting for a transmit complete interrupt | 1+ FLAG STREAM MODE instead of early Transmit Interrupt before issuing a 1 mera ve woot transmit frame command for a supervisory frame. « surpeneo moe See Figure 15. | Sstormtennurrmoce ELMORE MODE 210479-34 2-98

intel. 8273 eee suorrennuer noceoune (00) FLAG STREAM MODE If this bit is set to a one, the following table outlines TRANSMIT COMPLETION the operation of the transmitter. omen <i> Rarer cosmo Transmitter State [Acton] Idle Send Flags immediately. Transmit or Transmit} | Send Flags After the Transparent Active | | Transmission Complete Loop Transmit Active | Ignore Command. 1 Bit Delay Active Ignore Command. <a> If this bit is reset to zero the following table outlines the operation of the transmitter <> Tranemiter State [_Aciion | IDLE Sends ales on Nea | (4 EZ [ho Character boundary. Transmit or Transmit: } Send idles after the Transparent Active ieComplote. 1 Bit Delay Active Ignore Command. omen processina SET SERIAL 1/0 MODE (CMD CODE Ao) 210479-18 AL he O_O OO Figure 15 owe foToTs Tots Tote [eo [ole] on CoTsTofofeToloT TT] If this bit is zero, the interrupt will be generated only | Lesmme aoe after the final flag has been transmitted. [remeseme 14008 aA 10 — (02) BUFFERED MODE 21047916 If the buffered mode bit is set to a one, the first two bytes (normally the address (A) and control (c) RESET SERIAL 1/0 MODE (CMD CODE 60) fields) of a framo are buttered by the 8273. If this bit This command allows bits set in CMD code AO to be 5 2 2010 the address and control fields are Passed reset by placing zeros in the appropriate positions. Ai Ao Dy Dg Ds Dy Dg Dp Dy Do (D1) PREFRAME SYNC MODE omo:[oToTo[s[s[oTolfo]o[o] I this bits sotto a one the 2273 wit ranamt wo PAR LOLs [+ [a fatatay | [| characters before the first flag of a frame. To guarantee sixteen line transitions, the 6273 (02) LOOP BACK sends two bytes of data (00)} if NRZI is set or data If this bit is set to a one, the transmit data is internal- (55) if NRZI is not set. ly routed to the receive data circuitry. 2-99

intel. 8273 SS (D1) Txc — Rx Receive Commands If this bit is set to a one, the transmit clock is inter- The 8273 supports three receive commands: Gener- nally routed to the receive clock circuitry. It is nor- —_al Receive, Selective Receive, and Selective Loop mally used with the loop back bit (D2). Receive. (D0) NRZI MODE GENERAL RECEIVE (CMD CODE C0) If this bit is set to a one, NRZI encoding and decod- —_ General receive is a receive mode in which frames ing of transmit and receive data is provided. If this bit are received regardless of the contents of the ad- is a zero, the transmit and receive data is treated as dress field. a normal positive logic bit stream. Ay Ag D7 Dg Ds D4 Dg Dp Dy Do NRZI encoding specifies that a zero causes a CMD: (ofo[s[+[ofofolofo]o| change in the polarity of the transmitted signal and a PAR: LEAST SIGNIFICANT BYTE one causes no polarity change. NRZI is used in all OF THE RECEIVE BUFFER asynchronous operations. Refer to IBM document LENGTH (80) GA27-3093 for details. PAR: 1 | MOST SIGNIFICANT BYTE OF RECEIVE Reset Device Command BUFFER LENGTH (81) Ay Ag D7 Dg Ds D4 Dg Dz Di Do we[sTofoTo[ofoTo[ofo] 1] Nore 1. If buttered mode is specified, the RO, R1 receive twr:[1[o[olofolo[o[olo]o] tame length result) is the number of data bytes re ‘An 8273 reset command is executed by outputting a2. If non-buffered mode is specified, the RO, R1 re- (01) followed by (00), to the reset register (TMR). ceive frame length (result) is the number of data See 8273 AC timing characteristics for Reset pulse _bytes received plus two (the count includes the ad- specifications. dress and control bytes). 3. The frame check sequence (FCS) is not trans- The reset command emulates the action of the reset _ferred to memory. bin. 4. Frames with less than 32 bits between flags are 1) The modem control signals are forced high (inac- ionored on generated) if the buffered tive level). 5. In the non-butfered mode an interrupt is generat- 2) The 8273 status register flags are cleared. ed when a less than 32 bit frame is received, since 3) Any commands in progress are terminated imme- _data transfer requests have occurred. lee Prog 6. The 8273 receive is always disabled when an : Idle is received after a valid frame. The CPU mod- 4) The 8279 enters an idle state until the next com- ie must issue a receive command to re-enable the mand is issued. receiver. 5) The Serial 1/O and Operating Mode registers are 7. The intervening ABORT character between a fi- set to zero and DMA data register transfer mode nal flag and an IDLE does not generate an inter- is selected. rupt. 6) The device assumes a non-loop SDLC terminal _8. If an ABORT Character is not preceded by a flag role. and is followed by an IDLE, an interrupt will be gen- erated for the ABORT followed by an IDLE interrupt ‘one character time later. The reception of an ABORT will disable the receiver. 2-100

intel. 8273 SSeS SELECTIVE RECEIVE (CMD CODE C1) RECEIVE DISABLE (CMD CODE 5) Ar Ao 07 Dg Ds D4 Ds Dz Di Do — Terminates an active receive command immediately. owo:[ofo[+]+foTo[ololfo]s] Ar Ao D7 Dg Ds D4 Da De Di Dp PAR: LEAST SIGNIFICANT BYTE emo:[olo[+[+fo[olo]ijo]s] OF THE RECEIVE PAR: NONE BUFFER LENGTH (80) PAR: 1 | MOST SIGNIFICANT BYTE ail OF RECEIVE Transmit Commands BUFFER LENGTH (81) The 6273 supports three transmit commands: PAR: 1 | RECEIVE FRAME ADDRESS Transmit Frame, Loop Transmit, Transmit Transpar- MATCH FIELD ONE (A1) ent. PAR: 1 | RECEIVE FRAME ADDRESS MATCH FIELD TWO (A2) TRANSMIT FRAME (CMD CODE C8) Ay Ao D7 Dg Ds Dg Dg Dz Dy Do 2 ‘Selective receive is a receive mode in which frames MD: are noted ones ho aadros Nol matches ary fofetsT:fofo[sfofofo] ‘one of two address fields given to the 8273 as pa- PAR: LEAST SIGNIFICANT BYTE OF rameters. FRAME LENGTH (LO) , PAR: MOST SIGNIFICANT BYTE OF Won min nn oxen nra PA] [GT ETE looks at the first character, it extended, software FRAME LENGTH (L1) must then decide if the message is for this unit. PAR: ADDRESS FIELD OF TRANSMIT ; FRAME (A) SELECTIVE LOOP RECEIVE (CMD CODE C2) PAR: fot CONTROL FIELD OF TRANSMIT As Ao D7 Dg Ds D4 D3 Do Dy Do FRAME (C) CMD: [ofo[s]+Jofofo[o]s fo] Transmits one frame including: initial flag, frame PAR: LEAST SIGNIFICANT BYTE check sequence, and the final flag. OF THE RECEIVE BUFFER LENGTH (80) If the buffered mode is specified, the LO, L1, frame . length provides as a parameter is the length of the PAR: MOST SIGNIFICANT BYTE information field and the address and control fields OF RECEIVE must be input. BUFFER LENGTH (81) . In unbuffered mode the frame length provided must Par:| @| 1 | RECEVE FRAME ADDRESS be the long ofthe Information fed pls two and (At) the address and control fields must be the first two PAR: RECEIVE FRAME ADDRESS. bytes of data. Thus only the frame length bytes are MATCH FIELD TWO (A2) required as parameters. Selective loop receive operates like selective re- ceive except that the transmitter is placed in flag stream mode automatically after detecting an EOP (01111111) following a valid received frame. The one bit delay mode is also reset at the end of a selective loop receive. 2-101

intel. 8273 LOOP TRANSMIT (CMD CODE CA) After an abort character (eight contiguous ones) is transmitted, the transmitter reverts to sending flags Ai Ag D7 De Ds D4 Dg Dz Di Do or idies as a function of the flag stream mode speci- omo:(oTo[s[+ToTo[sfo]+]o] tea PAR: LEAST SIGNIFICANT BYTE OF FRAME LENGTH (LO) ABORT LOOP TRANSMIT (CMD CODE CE) PAR: et MOST SIGNIFICANT BYTE OF Ay Ag D7 Dg Ds D4 Dg Dz Di Do FRAME LENGTH (L1) omo:[oTo[s]+fofo[+][+]1 Jo] PAR: ADDRESS FIELD OF TRANSMIT PAR: NONE FRAME (A) . Atter a flag is transmitted the transmitter reverts to PAR: et CONTROL FIELD OF TRANSMIT | One bit delay mode. Transmits one frame in the same manner as the ABORT TRANSMIT TRANSPARENT (CMD CODE transmit frame command except: » 4) Ifthe flag stream mode is not active transmission Ar Ao D7 Dg Ds O4 Dg Dz Dy Do wil begin after a received EOP has been convert- CMD: fofo[+[1fofof+]1fo]1] 2) Ifthe flag stream mode is active transmission will PAR: NONE begin at the next flag boundary for buffered mode The transmitter reverts to sendin fs ig flags or idles as a oF at the third flag Boundary for non-butfered function of the flag stream mode specified. 3) At the end of a loop transmit the one-bit delay mode is entred and the flag stream mode ise: Modiem Gontrol Commands set. The modem control commands are used to manipu- late the mod . ‘TRANSMIT TRANSPARENT (CMD CODED C9) ate the modem control ports. Ay Ag Dy Dg Ds Dg Dg Dz Dy Dy — Whenread Port A or Port B commands are executed the result of the command is returned in the result omo:[oTo]+[+ToTo[s[o]o[ +] register. the sit Set Port 8 command requires a pa- PAR: LEAST SIGNIFICANT BYTE OF rameter that is a mask that corresponds to the bits FRAME LENGTH (LO) to be set. The Bit Reset Port B command requires a mask that has a zero in the bit positions that are to PAR: MOST SIGNIFICANT BYTE OF be reset. FRAME LENGTH (L1) The 8273 will t it a block of data without READ PORT A (CMD CODE 22) will transmit a block of raw data without protocol, i.e., no zero bit insertion, flags, or frame Ay Ao D7 Dg Ds Dy Dg Dz Dy Do check sequences. omo:Lo[ofolo]+{o]ofo]s]o] PAR: NONE Abort Transmit Commands ‘An abort command is supported for each type of READ PORT B (CMD CODE 23) transmit command. The abort commands are ig- As Ao D7 De Ds D4 Dg Dz Dy Do nored if transmit command 's notin Progress ‘CoToToTo[sfofolo[s[s] 9 owo:[oToToTo[sfofofo]:]1 ABORT TRANSMIT FRAME (CMD CODE CC) PAR: NONE Ay Ao D7 Dg Ds D4 Dg Dz Dy Do omo:[oTo[+]+Jolo]s [1 JoJo] PAR: NONE 2-102

intel. 8273 ee SET PORT B BITS (CMD CODE A3) (Do) REQUEST TO SEND This command allows user defined Port B pins tobe This is a dedicted 8273 modem control signal, and set. reflects the same logical state of RTS pin. Ay A 2) O% De Oy 0; 0, 0% ow:[oToTs [els |e] ole] fs] RESET PORT B BITS (CMD CODE 63) ee Te T TT TTT cumwane Th command allows Port 8 user defined bits to be Unrencouesrrostne rset, sen oerineo reagoerect Ay Ae 2) Dy Oy Oy 0) Dy 0) OW 210479-35 ow foToToTs Ts Tofofo[ Ts] oe PTET TTT Ty) sen ogFmED This bit can be used to set the flag detect pin. How- susaoereer ever, it will be reset when the next flag is detected. rag oereet —_____ 2 nome WY (D4-D1) USER DEFINED OUTPUTS This command allows Port B (D4-D;) user defined bits to be reset. These bits correspond to Output These bits correspond to the state of the PB4-PB; —_Port pins (PB,—PBy). output pins.

8273 Command Summary

Result | Completion | comanaoneiton | GE | ramen [meme | rt | So Set One Bit Delay [as [setmask [none | = to | ResetOnepitDelay | 64 __| ResetMask_| None | No Set ata TranstorMade | 97 | Setaask | None | — | no] Reset ata TarserMode | 87 | Resetuask | none | _— | no] SetOperating Modo | e1__| Setmask | None || No _| ResetOperating Mode | s1__| ResetMask | None | — | NO _| Set Serial VO Mode SetMask [None | [No | Reset Seri /OMode | 60 | ResetMask | None | — | No | Generaireceve [| co | eo.8t | RIG RO.ATAG® | AXVA B0,B1,A1,A2 | ICRO,RT (A.C) Selective Loop Receive RIC,RO,R1(A,C)2) Receive Disable [cs [one [None | |e | | TransmitFreme | ca ost acon THUR LO,L1A,C) THUR Lot AvortTransmitFrame | oc | None | ic | TA [Ves 2-103

8273 Command Summary (Continued)

1, Issued only when in buffered mode.

Read as results only in buttered mode.

B1— Most significant byte of the receive butter --AXI/R— Receive interrupt result register. length. ‘TXI/R— Transmit interrupt result register. A1— Receive frame address match field one. RIC— Receiver interrupt result code. A2— Receive frame address match field two. TIC— Transmitter interrupt result code. Figure 16. Typical Frame Reception full Duplex (active transmitter or receiver) with commands, the maximum data rate decreases to 49K Baud.

Figure 18. 8273 System Diagram

13 Command Parameter Buffer Full Bit 10 705 tey

14 Command Busy Bit Reset after Last 702 128 toy

Table 3. Receiver Interrupt Result Timing Table 4. Transmit interrupt Result

intel . 8273 A.C. CHARACTERISTICS 8273 (Ta = 0°C to 70°C, Voc = +5.0V + 5%) (Continued) OTHER TIMING (Continued) [_symbor_ [Parameter [| Min_—|_ Max | unit | Test Conattione Data Clock Low [txtey-so [fs PO toon [Data Gockiign | extey | | oe | _—i Data Clock easxtcy | | ne [Woes | TransmitDatadelay | | 200 | ons [| [ios | batasouptine [am | | | it Datariodtine | 00 | | w= | + FIAGDETowwuiiow | exes | | = |_| NOTES: 1. All timing measurements are made at the reference voltages unless otherwise ‘specified: Input ““1" at 2.0V, “O" at 0.8V; Output “1” at 2.0V, "0" at 0.8V. 2. tap. tap, tac and tc, are not concurrent specs. 3. If receive commands or Read/Write Port commands are issued while both the transmitter and receiver are active, this ‘specification will be 81.5 Toy min. A.C. TESTING INPUT, OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT pay 70 Ey ous os os c= 180 pF 21047824 T ‘AC. Testing: Inputs are driven at 2.4V fora logic "1" and 0.45V = {ora logic "0". Timing measurements are made at 20V for logic 210479-25 "1" and O.8V for @ loge “0”. Cy = 150 pF ’ C; Includes Jig Capacitance WAVEFORMS READ Dacx ‘cD Ao Ay 08 are 6 rT (210479-26 2-110

intel. 8273 WAVEFORMS (Continued) WRITE tae oy "ea ‘on —— wo 210479-27 oa DMA a a. seo oaCK ‘AB on WA ter CHIP CLOCK q sax c100K — i _ cua: tenga: 210479-28 TRANSMIT Tet $$ tgey = eto 210479-20 2411

intel. 8273 WAVEFORMS (Continued) RECEIVE at a Se tee | | ‘oa — 210479-20 DPLL OUTPUT Ort *& _— 210479-91 FLAG DETECT OUTPUT FLAG DET +-—mo 210470-1 2-112

Product Information

8273 specifications and overview.

Summary

PROGRAMMABLE HDLC/SDLC PROTOCOL CONTROLLER

Description

PROGRAMMABLE HDLC/SDLC PROTOCOL CONTROLLER

Source title 8273 Datasheet(PDF) - Intel Corporation

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