82595FX

82595FX INTEL | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 54

Technical content

Datasheet sections

• 10.5 Layout Guidelines ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
• 10.5.1 General ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
• 10.5.2 Crystal ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
• 10.5.4 Decoupling
• 11.0 ELECTRICAL SPECIFICATIONS
• 11.1 Absolute Maximum Ratings ÀÀÀÀÀÀÀÀ
• 11.1.1 Package Thermal
• 11.2 AC Timing Characteristics ÀÀÀÀÀÀÀÀÀ
• 11.3 AC Measurement Conditions ÀÀÀÀÀÀ
• 11.4 ISA Interface Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
• 11.6 Local Memory Timings ÀÀÀÀÀÀÀÀÀÀÀÀ
• 11.6.1 SRAM Timings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
• 11.6.2 FLASH/EPROM Timings ÀÀÀÀÀ
• 11.7 Interrupt Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
• 11.8 RESET and SMOUT Timing ÀÀÀÀÀÀÀ
• 11.9 JTAG Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
• 11.10 Serial Timings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ

*Other brands and names are the property of their respective owners. changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.

1 Mbyte for Diskless Workstations

Figure 1. 82595FX Block Diagram

ISA Bus High Integration ETHERNET Controller CONTENTS PAGE

1.0 INTRODUCTION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5

1.1 82595FX Overview ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5

1.2 Power Management ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5

1.3 Auto-Negotiation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5

1.4 Compliance to Industry

Standards ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6

1.4.1 Bus InterfaceÐISA IEEE

P996 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6

1.4.2 ETHERNET/Twisted Pair

Ethernet InterfaceÐIEEE 802.3 Specification ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6 2.0 82595FX PIN DEFINITIONS ÀÀÀÀÀÀÀÀÀÀÀ 6

2.1 ISA Bus Interface ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6

2.2 Local Memory Interface ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8

2.3 Miscellaneous Control ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 9

2.4 JTAG Control ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 9

2.5 Serial Interface ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 9

2.6 Serial Interface LEDs ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 10

2.7 Power and Ground ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 11

2.8 Reserved Pins ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 11

2.9 82595FX Pin Summary ÀÀÀÀÀÀÀÀÀÀÀÀÀ 12 3.0 82595FX INTERNAL ARCHITECTURE OVERVIEW ÀÀÀÀÀÀÀÀÀÀ 13

3.1 System Interface Overview ÀÀÀÀÀÀÀÀÀ 13

3.1.1 Concurrent Processing

Functionality ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 13

3.2 Local Memory Interface ÀÀÀÀÀÀÀÀÀÀÀÀ 13

3.3 CSMA/CD Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 14

3.4 Serial Interface ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 14

4.0 ACCESSING THE 82595FX ÀÀÀÀÀÀÀÀÀÀÀ 14

4.1 82595FX Register Map ÀÀÀÀÀÀÀÀÀÀÀÀÀ 14

4.1.1 IO Bank 0 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 15

4.1.2 IO Bank 1 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 16

4.1.3 IO Bank 2 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 17

4.2 Writing to the 82595FX ÀÀÀÀÀÀÀÀÀÀÀÀÀ 17

4.3 Reading from the 82595FX ÀÀÀÀÀÀÀÀÀ 18

4.4 Local SRAM Accesses ÀÀÀÀÀÀÀÀÀÀÀÀÀ 18

4.4.1 Writing to Local Memory ÀÀÀÀÀÀÀ 18

4.4.2 Reading from Local

Memory ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 18

4.5 Serial EEPROM Interface ÀÀÀÀÀÀÀÀÀÀÀ 19

4.6 Boot EPROM/FLASH Interface ÀÀÀÀÀ 20

5.0 COMMAND AND STATUS

INTERFACE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 20

5.1 Command OP Code Field ÀÀÀÀÀÀÀÀÀÀÀ 20

5.2 ABORT (Bit 5) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 20

5.3 Pointer Field (Bits 6 and 7) ÀÀÀÀÀÀÀÀÀÀ 20

5.4 82595FX Status Interface ÀÀÀÀÀÀÀÀÀÀÀ 22

6.0 INITIALIZATION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22

7.0 FRAME TRANSMISSION ÀÀÀÀÀÀÀÀÀÀÀÀÀ 23

7.1 82595FX XMT Block Memory Format ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 23

7.2 XMT Chaining ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 25

7.3 Automatic Retransmission on

Collision ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 28

8.0 FRAME RECEPTION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 28

8.1 82595FX RCV Memory Structure ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 28

8.2 RCV Ring Buffer Operation ÀÀÀÀÀÀÀÀÀ 31

9.0 SERIAL INTERFACE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 32

10.0 APPLICATION NOTES ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 33

10.1 Bus Interface ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 33

10.2 Local Memory Interface ÀÀÀÀÀÀÀÀÀÀÀ 33

10.3 EEPROM Interface (ISA Only) ÀÀÀÀÀ 33

10.4 Serial Interface ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 33

10.4.1 AUI Circuit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 33

10.4.2 TPE Circuit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 34

10.4.3 LED Circuit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 34

Figure 2. 82595FX Pinout

1.0 INTRODUCTION

1.1 82595FX Overview The 82595FX is a highly integrated, high perform- ance LAN controller which provides a cost effective LAN solution for ISA compatible Personal Computer (PC) motherboards (both desktop and portable), and add-on ISA adapter boards. The 82595FX integrates all of the major functions of a buffered LAN solution into one chip with the exception of the local buffer memory, which is implemented by adding one SRAM component to the LAN solution. The 82595FX’s Concurrent Processing feature significantly enhanc- es throughput performance. Both system bus and serial link activities occur concurrently, allowing the 82595FX to maximize network bandwidth by mini- mizing delays associated with transmit or receiving frames. The 82595FX’s bus interface is a glueless attachment to an ISA bus. Its serial interface pro- vides a Twisted Pair Ethernet (TPE) and an Attach- ment Unit Interface (AUI) connection. By integrating the majority of the LAN solution functions into one cost effective component, production cost saving can be achieved as well as significantly decreasing the design time for a solution. This level of integra- tion also allows an 82595FX solution to be ported between different applications (PC motherboards, and adapters, while maintaining a compatible hard- ware and software base. The 82595FX’s software interface is optimized to re- duce the number of processing steps that are re- quired to interface to the 82595FX solution. The 82595FX’s initialization and control registers are di- rectly addressable within one 16-byte IO address block. The 82595FX can automatically resolve any conflicts to an IO block by moving its IO offset to an unused location in the case that a conflict occurs. The 82595FX’s local memory is arranged in a simple ring buffer structure for efficient transfer of transmit and receive packets. The local memory, up to

64 Kbytes of SRAM, resides as either a 16-bit or 32-

bit IO port in the host systems IO map programma- ble through configuration. The 82595FX provides di- rect control over the local SRAM. The 82595FX per- forms a prefetch to the SRAM memory allowing CPU IO cycles to this data with no added wait-states. The 82595FX also provides an interface to up to 1 Mbyte of FLASH or EPROM memory. An interface to an EEPROM, which holds solution configuration values and can also contain the Node ID, allows for the implementation of a ‘‘jumperless’’ design. In addi- tion, the 82595FX contains full hardware support for the implementation of the ISA Plug N’ Play specifica- tion. Plug N’ Play eliminates jumpers and complicat- ed setup utilities by allowing peripheral functions to be added to a PC automatically (such as adapter cards) without the need to individually configure each parameter (e.g. Interrupt, IO Address, etc). This allows for configuration ease-of-use, which re- sults in minimal time associated with installation. The 82595FX’s packaging and power management features are designed to consume minimal board real estate and system power. This is required for applications such as portable PC motherboard de- signs which require a solution with very low real es- tate and power consumption. The 82595FX package is a 160-lead PQFP (Plastic Quad Flat Pack). Its di- mensions are 28 mm by 28 mm, and 3.5 mm in height. The 82595FX contains two power down modes; an SL compatible power down mode which utilizes the SL SMOUT input, and a POWER DOWN command for non-SL systems.

1.2 Power Management

Power management and low power consumption are two items that will allow any design using the 82595FX to be suitable for green PC use. Low pow- er operation is initiated when software issues a SLEEP command to the device. After a short wait, it will shut off the system clock, some parts of the Backoff Randomizer, several input buffers and the two LED drivers. The 82595FX will subsequently wake up from sleep mode when software initiates an ISA cycle in the application, as well as when it re- ceives a frame addressed to it. The total power con- sumption when in sleep mode can be as low as ap- proximately 175 mW. Normal idle power consump- tion is 300 mW. The software POWER DOWN command, along with its companion hardware implementationÐthe SMOUT I/O pin, provide additional power manage- ment capabilities. This feature allows the 82595FX to be powered down, and then at some time in the future be selectively reset without having lost the current configuration. See the 82595FX User’s Guide for further details on these features.

1.3 Auto-Negotiation

Auto-negotiation functionality is a method of auto- matically determining the highest common operating mode (i.e., 10BaseT half duplex, 10BaseT full du- plex, etc.) between two network devices. Using this functionality, two stations, each having a varying number of different operating modes, negotiate the highest possible common operating mode between them. During the power up sequence, the auto-ne- gotiation functionality will automatically establish a link with which it can take advantage of any auto-ne- gotiation-capable device it is connected to. An auto- negotiation capable hub can detect and automatical- ly configure its ports to take maximum advantage of

common modes of operation without any user inter- vention or prior knowledge by connected stations. See the 82595FX User’s Guide for details on this function. For further information on these enhancements and a description of all the differences between the 82595TX and 82595FX, please consult the 82595FX User’s Manual, available through your local sales representative.

1.4 Compliance to Industry Standards

The 82595FX has two interfaces; the host system interface, which is an ISA bus interface, and the seri- al, or network interface. This interface has been standardized by the IEEE.

1.4.1 BUS INTERFACEÐ

The 82595FX implements the full ISA bus interface. It is compatible with the IEEE spec P996.

1.4.2 ETHERNET/TWISTED PAIR ETHERNET

INTERFACEÐIEEE 802.3 SPECIFICATION The 82595FX’s serial interface provides either an AUI port interface or a Twisted Pair Ethernet (TPE) interface. The AUI port can be connected to an Ethernet Transceiver cable drop, providing a fully compliant IEEE 802.3 AUI interface. The TPE port provides a fully compliant IEEE 10BASE-T interface. The 82595FX can automatically switch to whichever port (TPE or AUI) is active. 2.0 82595FX PIN DEFINITIONS

2.1 ISA Bus Interface

Symbol Pin Type Name and FunctionNo. SA0 61 I ADDRESS BUS: These pins provide address decoding for up to 1 Kbyte of address. These pins also provide 4 Kbytes of IO addressing to support theSA1 62 Plug N’ Play Standard.SA2 63 SA3 64 SA4 65 SA5 66 SA6 67 SA7 68 SA8 69 SA9 70 SA10 71 SA11 72 SA14 73 I ADDRESS BUS: These pins provide address decoding between the 16 Kbyte and 1 Mbyte memory space. This allows for decoding of a Boot EPROM or aSA15 74 FLASH in 16K increments.SA16 75 SA17 76 SA18 77 SA19 78

2.1 ISA Bus Interface (Continued)

Symbol Pin Type Name and FunctionNo. SD0 81 I/O DATA BUS: This is the data interface between the 82595FX and the host system. This data is buffered by one (8-bit design) or two (16-bit design)SD1 83 internal transceivers.SD2 85 SD3 87 SD4 88 SD5 90 SD6 92 SD7 94 SD8 60 SD9 58 SD10 56 SD11 54 SD12 53 SD13 51 SD14 49 SD15 47 AEN 24 I ADDRESS ENABLE: Active high signal indicates a DMA cycle is active. SMEMR 20 I MEMORY READ for system memory accesses below 1 Mbyte. Active low. SMEMW 21 I MEMORY WRITE for system memory accesses below 1 Mbyte. Active low. IOR 22 I IO READ: Active low. IOW 23 I IO WRITE: Active low. IOCS16 45 O IO CHIP SELECT 16: Active low, open drain output which indicates that an IO cycle access to the 82595FX solution is 16-bit wide. Driven for IO cycles to the local memory or to the 82595FX. IOCHRDY 42 O IO CHANNEL READY: Active high, open drain output. When driven low, it extends host cycles to the 82595FX solution. SBHE 37 I SYSTEM BUS HIGH ENABLE: Active low input indicates a data transfer on the high-byte (D8–D15) of the system bus (a 16-bit transfer). This pin also determines if the 82595FX is operating in an 8- or 16-bit system upon initialization. INT0 29 O 82595FX INTERRUPT 0–7: One of these 8 pins is selected to be active one at a time (the other seven are in Hi-Z state) by configuration. TheseINT1 30 active high outputs serve as interrupts to the host system.INT2 31 INT3 32 INT4 33 INT5 34 INT6 35 INT7 36 RESET DRV 19 I RESET DRIVE: Active high reset signal.

2.2 Local Memory Interface

Symbol Pin Type Name and FunctionNo. LADDR0 143 O LOCAL MEMORY ADDRESS (LADDR0–LADDR15): These outputs contain the multiplexed address for the local SRAM.LADDR1 144 LADDR2 145 FLASH ADDRESS 14–17 (LADDR0–LADDR5): These pins control the LADDR3 146 FLASH addressing from 16K to 1M to allow paging of the FLASH in 16K LADDR4 147 spaces. These addresses are under direct control of the FLASH PAGING configuration register.LADDR5 148 LADDR6 149 LADDR7 150 LADDR8 153 LADDR9 154 LADDR10 155 LADDR11 156 LADDR12 157 LADDR13 158 LADDR14 159 LADDR15 2 LDATA0 132 I/O LOCAL MEMORY DATA BUS (LDATA0–LDATA7): The eight I/O signals, comprising the local data bus, are used to read or write data to orLDATA1 133 from the 8-bit wide SRAM.LDATA2 134 LDATA3 135 FLASH MEMORY DATA BUS (LDATA0–LDATA7): These signals also LDATA4 137 provide eight bits of data for accesses to an 8-bit FLASH/EPROM if these components are used.LDATA5 138 LDATA6 139 LDATA7 140 SRAMCS 13 O SRAM CHIP SELECT: This active low output is the chip select to the SRAM. LWE 12 O This active low output is the Write Enable to the SRAM. This pin also provides the active low Write Enable to the FLASH. LOE 16 O This active low output is the Output Enable to the SRAM. This pin also provides the active low Output Enable control to the FLASH. BOOTCS 10 O BOOT EPROM/FLASH CHIP SELECT: Active low output. EEPROMCS 8 I/O EEPROM CS: Active high signal. If no EEPROM is connected, this pin should be connected to V CC. In this case it will function as an input to the 82595FX to indicate no EEPROM is connected. EEPROMSK 117 O EEPROM SHIFT CLOCK: This output is used to shift data into and out of the serial EEPROM. EEPROMDO 119 O EEPROM DATA OUT EEPROMDI 118 O EEPROM DATA IN

2.4 Miscellaneous Control

Symbol Pin Type Name and FunctionNo. SMOUT 18 I/O This active LOW signal, when asserted, places the 82595FX into a Power Down mode. The 82595FX will remain in power down mode until SMOUT is unasserted. If this line is unconnected to SMOUT from the system bus, it can be used as an active low output which, when a POWER DOWN command is issued to the 82595FX, can be used to power down other external components (this output function is enabled by configuration). J0 119 I JUMPER: Input for selecting between 7 ISA IO spaces. These pins should be connected to either V CC or GND or the EEPROM. The 82595FX reads theJ1 118 I Jumper block during its initialization sequence.J2 117 I J0 J1 J2 IO Address Connected to EEPROM Configuration contained in EEPROM GND GND GND I/O Window Disabled V CC GND GND 2A0h GND V CC GND 280h VCC VCC GND 340h GND GND V CC 300h VCC GND V CC 360h GND V CC VCC 350h VCC VCC VCC 330h

2.4 JTAG Control

Symbol Pin Type Name and FunctionNo. TDO 109 O JTAG TEST DATA OUT TMS 110 I JTAG TEST MODE SELECT TCK 111 I JTAG TEST CLOCK TDI 112 I JTAG TEST DATA IN

2.5 Serial Interface

Symbol Pin Type Name and FunctionNo. TRMT 122 O Positive side of the differential output driver pair that drives 10 Mb/s Manchester Encoded data on the TRMT pair of the AUI cable (Data Out A). TRMT 123 O Negative side of the differential output driver pair that drives 10 Mb/s Manchester Encoded data on the TRMT pair of the AUI cable (Data Out B). RCV 115 I The positive input to a differential amplifier connected to the RCV pair of the AUI cable (Data In A). It is driven with 10 Mb/s Manchester Encoded data.

2.5 Serial Interface (Continued)

Symbol Pin Type Name and FunctionNo. RCV 116 I The negative input to a differential amplifier connected to the RCV pair of the AUI cable (Data In B). It is driven with 10 Mb/s Manchester Encoded data. CLSN 124 I The positive input to a differential amplifier connected to the CLSN pair of the AUI cable (Collision In A). CLSN 125 I The negative input to a differential amplifier connected to the CLSN pair of the AUI cable (Collision In B). TDH 105 O TRANSMIT DATA HIGH: Active high Manchester Encoded data to be transmitted onto the twisted pair. This signal is used in conjunction with TDL, TDH , and TDL to generate the pre-conditioned twisted pair output waveform. TDL 106 O TRANSMIT DATA LOW: Twisted Pair Output Driver. Active high Manchester Encoded data with embedded pre-distortion information to be transmitted onto the twisted pair. This signal is used in conjunction with TDH, TDH , and TDL to generate the pre-conditioned twisted pair output waveform. TDH 103 O TRANSMIT DATA HIGH INVERT: Active low Manchester Encoded data to be transmitted onto the twisted pair. This signal is used in conjunction with TDL, TDH, and TDL to generate the pre-conditioned twisted pair output waveform. TDL 104 O TRANSMIT DATA LOW INVERT: Twisted Pair Output Driver. Active low Manchester Encoded data with embedded pre-distortion information to be transmitted onto the twisted pair. This signal is used in conjunction with TDL, TDH, and TDH to generate the pre-conditioned twisted pair output waveform. RD 114 I Active high Manchester Encoded data received from the twisted pair. RD 113 I Active low Manchester Encoded data received from the twisted pair. X1 127 I 20 MHz CRYSTAL INPUT: This pin can be driven with an external MOS level clock when X2 is left floating. This input provides the timing for all of the 82595FX functional blocks. X2 128 O 20 MHz CRYSTAL OUTPUT: If X1 is driven with an external MOS level clock, X2 should be left floating.

2.6 Serial Interface LEDs

Symbol Pin Type Name and FunctionNo. AUI LED/BNC DIS 95 O AUI LED INDICATOR: This output, when the 82595FX is used as a TPE/AUI solution, will turn on an LED when the 82595FX is actively interfaced to its AUI serial port. When the 82595FX is used as a BNC/AUI solution, this output becomes the BNC DIS output, which can be used to power down the BNC Transceiver section (the Transceiver and the DC to DC Converter) of the solution when the BNC port is unconnected. LILED 98 O LINK INTEGRITY LED: Normally on (low) ouput which indicates a good link integrity status when the 82595FX is connected to an active TPE port. This output will remain on when the Link Integrity function has been disabled. It turns off (driven high) when Link Integrity fails, or when the 82595FX is actively interfaced to an AUI port. The minimum off time is 100 ms.

2.6 Serial Interface LEDs (Continued)

Symbol Pin Type Name and FunctionNo. ACTLED 97 O LINK ACTIVITY LED: Normally off (high) output turns on to indicate activity for transmission, reception, or collision. Flashes at a rate dependent on the level of activity on the link. POLED 96 O POLARITY LED: If the 82595FX detects that the receive TPE wires are reversed, the POLED will turn on (low) to indicate the fault. POLED remains on even if automatic polarity correction is enabled, and the 82595FX has automatically corrected for the reversed wires.

2.7 Power and Ground

Symbol Pin Type Name and FunctionNo. VCC 1, 3, 7, 15, I POWER: a5V g5%. 26, 28, 40, 43, 46, 50, 57, 80, 84, 91, 99, 101, 107, 121, 129, 131, 141, 152 VSS 4, 6, 9, 11, I GROUND: 0V. 14, 17, 25, 27, 38, 39, 41, 44, 48, 52, 55, 59, 79, 82, 86, 89, 93, 100, 102, 108, 120, 126, 130, 136, 142, 151

2.8 Reserved Pins

Symbol Pin Type Name and FunctionNo. N/C 5, 160 Reserved. Do not connect.

2.9 82595FX Pin Summary ISA Bus Interface ISA Pin P-Down Pin Name Type State SA0–SA3 (In) Inactive SA4–SA11 Inactive/Act (1) SA14–19 (In) Inactive SD0–SD15 (I/O) TS TS SMEMR (In) Inactive SMEMW (In) Inactive IOR (In) Inactive IOW (In) Inactive/Act (1) INT0–7 (Out) TS TS RESET DRV (In) Act IOCS16 (Out) OD TS IOCHRDY (Out) OD TS SBHE (In) Inactive AEN (In) Inactive/Act (1) NOTE: 1. For hardware powerdown using SMOUT , these pins will be inactive. For software powerdown, these pins remain active. Local Memory Interface Pin MUXed Pin P-DownName Name Type LADDR[5:0] (Out) FADDR [14:19] 2S TS LADDR[6:15] (Out) 2S TS LDATA[0:7] (I/O) TS TS LWE (Out) 2S TS LOE (Out) 2S TS BOOTCS (Out) 2S PU SRAMCS (Out) 2S PU EEPROMCS (I/O) TS PD Miscellaneous Control MUXed Pin P-Down DualPin Name Pin Type State Pin NameName J0(In) ACT EEPROM2D0 (In) J1 (I/O) TS TS EEPROM2DI (Out) J2 (I/O) TS TS EEPROM2SK (Out) SMOUT (I/O) TS ACT/TS JTAG Control Pin Name MUXed Pin P-Down Pin Name Type State TMS (In) In Act TCK (In) In Act TDI (In) In Act TDO (Out) TS Serial Interface Pin Name MUXed Pin P-Down Pin Name Type State TRMT (Out) Ana TS TRMT (Out) Ana TS RCV (In) Ana In Act RCV (In) Ana In Act CLSN (In) Ana In Act CLSN (In) Ana In Act TDH (Out) Ana TS TDL (Out) Ana TS TDH (Out) Ana TS TDL (Out) Ana TS RD (In) Ana In Act RD (In) Ana In Act X1 (In) In Act X2 (Out) 2S TS LILED (Out) 2S TS * POLED (Out) 2S TS * ACTLED (Out) 2S TS * AUILED (Out) BNC DIS (Out) 2S TS * *Assuming auto-negotiation disabled. Legend: TSÐTriState. ODÐOpen Drain. 2SÐTwo State, will be found in eithe ra1o r0 logic level. AnaÐAnalog pin (all serial interface signals). ActÐInput buffer is active during Power Down. In ActÐInput buffer is inactive during Power Down. PUÐOutput in inactive state with weak internal Pull-up during Power Down. PDÐOutput in inactive state with weak internal Pull-down during Power Down. DualÐDual function pin.

3.0 82595FX INTERNAL ARCHITECTURE OVERVIEW Figure 1 shows a high level block diagram of the 82595FX. The 82595FX is divided into four main subsections; a system interface, a local memory sub-system interface, a CSMA/CD unit, and a serial interface.

3.1 System Interface Overview

The 82595FX’s system interface subsection in- cludes a glueless ISA bus interface, and the 82595FX’s IO registers (including the 82595FX’s command, status, and Data In/Out registers). The system interface block also interfaces with the 82595FX’s local memory interface subsystem and CSMA/CD subsystem. The bus interface logic provides the control, ad- dress, and data interface to an ISA compatible bus. The 82595FX decodes up to 1M of total memory address space. Address decoding within 16K block increments (A14–A19) are used for Flash or Boot EPROM. IO accesses are decoded throughout the 1 Kbyte PC IO address range (A10 and A11 provide up to 4K of IO addressing and are used for Plug N’ Play). The 82595FX data bus interface provides ei- ther an 8- or 16-bit interface to the host system’s data bus. The control interface provides complete handshaking interface with the system bus to enable transfer of data between the 82595FX solution and the host system. The 82595FX’s IO registers provide 3 banks of di- rectly addressable registers which are used as the control and data interface to the 82595FX. There are 16 IO registers per bank, with only one bank enabled at a time. This allows the complete 82595FX software interface to be contained in one 16-byte IO space. The base address of this IO space is selectable via either software (which can be stored in a serial EEPROM), or by strapping the 82595FX IO Jumper block (J0–J2). The 82595FX can also detect conflicts to its base IO space, and automatically resolve these conflicts either by allow- ing the selection of one Plug N’ Play card from multi- ple cards (using Plug N’ Play software), or by map- ping itself into an un-used IO space (Automatic IO Resolution). Included in the 82595FX IO registers are the Command Register, the Status Register, and the Local Memory IO Port register, which provides the data interface to the local SRAM buffer con- tained in an 82595FX solution. Functions such as IO window mapping, Interrupt enable, RCV and XMT buffer initialization, etc. are also configured and con- trolled through the IO registers. The 82595FX’s Concurrent Processing feature sig- nificantly enchances data throughput performance by performing both system bus and serial link activi- ties concurrently. Transmission of a frame is started by the 82595FX before that frame is completely cop- ied into local memory. During reception, a frame is processed by the host CPU before that frame is en- tirely copied to local memory. Transmit Concurrent Processing feature is enabled by writing to BANK 2, Register 1, Bit 0 . A 1 written to this bit enables this functionality, a 0 (default) disables it. To enable Re- ceive Concurrent Processing, BANK 1, Register 7 must be programmed to value other than 00h (00h disables RCV Concurrent Processing, and is de- fault). (See Section 4.1 for the format of IO BANK 1 and 2.) Improvements in concurrent processing functionality have allowed the 82595FX to include enhancements to the throughput efficiency of the 82595TX. For details, refer to the 82595FX User’s Guide. Concurrent Processing is not recommended for 8-bit interfaces. For more information on Trans- mit and Receive Concurrent Processing, refer to Section 7.0 and Section 8.0.

3.2 Local Memory Interface

The 82595FX’s local memory interface includes a DMA unit which controls data transfers to or from the 82595FX’s local SRAM, control for access to a Boot EPROM/FLASH, and two interfaces to a serial EEPROM. The local memory interface subsection also arbitrates accesses to the local memory by the host CPU and the 82595FX. Data transfers between the 82595FX and the local SRAM are always through the 82595FX’s Local Memory 16-bit/32-bit IO Port. This allows the entire SRAM memory (up to 64 Kbytes) to be mapped into one IO location in the host systems IO map. By setting a configuration bit in the 82595FX’s IO Registers (32IO/HAR Ý), the local memory can be extended from 16 bits to a full 32 bits. During 32-bit accesses, the CPU would perform a doubleword ac- cess addressed to register 12 of BANK0. The ISA bus will break this access up into two 16-bit access- es to Registers 12/13 followed by Registers 14/15, (or 4 sequential 8-bit accesses in an 8-bit interface). The CPU always accesses the 82595FX IO Port for Receive or Transmit data transfers, while the 82595FX automatically increments the address to the SRAM after each CPU access. The SRAMs data path is an 8-bit interface (typically 64K by 8-bits wide, or 256K by 8-bits wide) to allow for the lowest possible solution cost. The 82595FX implements a

prefetch mechanism to the local SRAM so that the data is always available to the CPU as either an 8- or 16-bit word. In the case of the CPU reading from the SRAM, the 82595FX reads the next two bytes from the SRAM, the 82595FX between CPU cycles so that the data is always available as a word in the 82595FX’s Local Memory IO Port register. In the case of the CPU writing to the SRAM, the data is written into the 82595FX’s Local Memory IO Port then transferred to the SRAM by the 82595FX be- tween CPU cycles. This prefetch mechanism of the 82595FX allows for IO read and writes to the local memory to be performed with no additional wait- states (3 clocks per data transfer cycle). The DMA unit provides addressing and control to move RCV or XMT data between the 82595FX and the local SRAM. For transmission, the CPU is re- quired only to copy the data to the local memory, initialize the 82595FX’s DMA Current Address Reg- ister (CAR) to point to the beginning of the frame, and issue a Transmit Command to the 82595FX. The DMA unit facilitates the transfers from the local memory to the 82595FX as transmission takes place. The DMA unit will reset upon collision during a transmission, enabling automatic re-transmission of the transmit frame. During reception, the DMA unit implements a recyclable ring buffer structure which can receive continuous back to back frames without CPU intervention on a per frame basis (see Section 8.2 for details). The 82595FX provides address decoding and con- trol to allow access to an external Boot EPROM/ FLASH if these components are utilized in an 82595FX design. The 82595FX also provides an in- terface to a serial EEPROM to replace jumper blocks used to contain configuration information. This port is used to store configuration information and in addition, it is used to store Plug N’ Play infor- mation as defined in the Plug N’ Play Specification. The 82595FX arbitrates accesses to the local mem- ory sub-system by the CPU and the 82595FX. The arbitration unit will hold off an 82595FX DMA cycle to the local memory if a CPU cycle is already in prog- ress. Likewise, it will hold off the CPU if an 82595FX cycle is already in progress. The cycle which is held off will be completed on termination of the preceding cycle.

3.3 CSMA/CD Unit

The CSMA/CD unit implements the IEEE 802.3 CSMA/CD protocol. It performs such functions as transmission deferral to link traffic, interframe spac- ing, exponential backoff for collision handling, ad- dress recognition, etc. The CSMA/CD unit serves as the interface between the local memory and the se- rial interface. It serializes data transferred from the local memory before it is passed to the serial inter- face unit for transmission. During frame reception, it converts the serial data received from the serial in- terface to a byte format before it is transferred to local memory. The CSMA/CD unit strips framing pa- rameters such as the Preamble and SFD fields be- fore the frame is passes to memory for reception. For transmission, the CSMA/CD unit builds the frame format before the frame is passed to the serial interface for transmission.

3.4 Serial Interface

The 82595FX’s serial interface provides either an AUI port interface or a Twisted Pair Ethernet (TPE) interface. The AUI port can be connected to an Ethernet Transceiver cable drop to provide a fully compliant IEEE 802.3 AUI interface. The AUI port can also interface to a transceiver device to provide a fully compliant IEEE 802.3 10BASE2 (Cheapernet) interface. The TPE port provides a ful- ly compliant 10BASE-T interface. The 82595FX au- tomatically enables either to the AUI or TPE inter- face depending on which medium is connected to the chip. Software configuration can override this automatic selection.

4.0 ACCESSING THE 82595FX

All access to the 82595FX is made through one of three banks of IO registers. Each bank contains 16 registers. Each register in a bank is directly accessi- ble via addressing. Through the use of bank switch- ing, the 82595FX utilizes only 16 IO locations in the host system’s IO map to access each of its regis- ters. The different banks are accessed by setting the POINTER field in the 82595FX Command Register to select each bank. The Command Register is Reg- ister for each bank. 4.1 82595FX Register Map The 82595FX registers are contained in three banks of 16 IO registers per bank. These three banks are shown in the following three pages.

4.1.1 IO BANK 0

The format for IO Bank 0 is shown below. 76543210 Reg 0 POINTER ABORT COMMAND OP CODE (CMD Reg) RCV EXEC EXEC TX RX RX STP States States INT INT INT INT Reg 1 ID REGISTER 0 0 (Counter) 1 (Auto En) 0 1 RESERVED Reg 2 0 0 Cur/ 32 IO/ EXEC TX RX RX STP Resvrd Resvrd Base HAR Mask Mask Mask Mask Reg 3 RCV CAR/BAR (Low) Reg 4 RCV CAR/BAR (High) Reg 5 RCV STOP REG (Low) Reg 6 RCV STOP REG (High) Reg 7 RCV Copy Threshold REG Reg 8 EARLY XMT THRESHOLD REGISTER (XTR) Reg 9 XMT CAR/BAR (Low) Reg 10 XMT CAR/BAR (High) Reg 11 Host Address Reg (Low) /32-Bit I/O (Byte 0) Reg 12 Host Address Reg (High) /32-Bit I/O (Byte 1) Reg 13 Local Memory I/O Port (Low) /32-Bit I/O (Byte 2) Reg 14 Local Memory I/O Port (High) /32-Bit I/O (Byte 3) Reg 15

4.1.2 IO BANK 1

The format for IO Bank 1 is shown below. 76543210 Reg 0 POINTER ABORT COMMAND OP CODE (CMD Reg) Tri-ST 00000 Host 0 INT Resvrd Resvrd Resvrd Resvrd Resvrd Bus Wd Resvrd Reg 1 FL/BT Boot EPROM/FLASH Bad INT SelectPresent Decode Window IRQ Reg 2 0 0 I/O Mapping Window Reg 3 00000000 (Reserved) Reg 4 00000000 (Reserved) Reg 5 BACK TO BACK TRANSMIT IFS Reg 6 RCV BOF Threshold REG Reg 7 RCV LOWER LIMIT REG (High Byte) Reg 8 RCV UPPER LIMIT REG (High Byte) Reg 9 XMT LOWER LIMIT REG (High Byte) Reg 10 XMT UPPER LIMIT REG (High Byte) Reg 11 FLASH PAGE FLASH WRITE FLASH PAGE SELECT HIGH ENABLE SELECT Reg 12

00000 SMOUT 00

(Reserved) OUT EN Resvrd Resvrd Reg 13 00000000 (Reserved) Reg 14 00000000 (Reserved) Reg 15

4.1.3 IO BANK 2

The format for IO Bank 2 is shown below. 76543210 Reg 0 POINTER ABORT COMMAND OP CODE (CMD Reg) Disc Tx Chn Tx Chn Res 0 0 0 TX Con Bad Fr ErStp Int Md 0 (Reserved) Proc En Reg 1 LoopBack Multi No SA Length RX CRC BC PRMSC IA Ins Enable In MEM DIS Mode Reg 2 Test 1 Test 2 BNC/ APORT Jabber TPE/ Pol Link In TPE Disable AUI Corr Dis Reg 3 INDIVIDUAL ADDRESS REGISTER 0 Reg 4 INDIVIDUAL ADDRESS REGISTER 1 Reg 5 INDIVIDUAL ADDRESS REGISTER 2 Reg 6 INDIVIDUAL ADDRESS REGISTER 3 Reg 7 INDIVIDUAL ADDRESS REGISTER 4 Reg 8 INDIVIDUAL ADDRESS REGISTER 5 Reg 9 STEPPING Turnoff EEDO EEDI EECS EESKEnable Reg 10 RCV NO RESOURCE COUNTER Reg 11 Reserved

0 Reg 12

Polarity Link Activity 0 Auto-Negotiation A-N FDX/ LED LED LED (Resvrd) Status Enable HDX Reg 13 00000000 (Reserved) Reg 14 00000000 (Reserved) Reg 15

4.2 Writing to the 82595FX

Writing to the 82595FX is accomplished by an IO Write instruction (such as an OUT instruction) from the host processor to one of the 82595FX registers. The 82595FX registers reside in a block of 16 con- tiguous addresses contained within the PC IO ad- dress space. The mapping of this address block is programmable throughout the 1 Kbyte PC IO ad- dress map. The 82595FX registers are contained within three banks of IO registers. When writing to a particular register, the processor must first select the correct bank (Bank 0, 1 or 2) in which the register resides. Once a bank is selected, all register accesses are made in that bank until a switch to another bank is performed. Switching banks is accomplished by writ- ing to the PTR field of Reg 0 in any bank. Reg 0 is the command register of the 82595FX and its func- tionality is identical in each bank. Once in the appro-

priate bank, the processor can write directly to any of the 82595FX registers by simply issuing an OUT instruction to the IO address of the register.

4.3 Reading from the 82595FX

Reading from the 82595FX is accomplished by an IO Read instruction (such as an IN instruction) from the host processor to one of the 82595FX registers. When reading from a particular register, the proces- sor must first select the correct bank (Bank 0, 1 or 2) in which the register resides. Once in the appropri- ate bank, the processor can read directly from any of the 82595FX registers by simply issuing an IN in- struction to the IO address of the register.

4.4 Local SRAM Accesses

IO mapping the local SRAM memory of an 82595FX solution allows it to appear as simply an IO Port to the host system. This allows an 82595FX solution to work in PCs which do not have enough space in their system memory map to accommodate the ad- dition of LAN buffer memory (typically 16 Kbytes to 64 Kbytes) into the map. The entire local memory (up to 64 Kbytes) is mapped into one 16-bit IO Port location. For all IO-mapped accesses to the local memory of a 82595FX solution, the 82595FX per- forms the IO address decoding and the ISA Bus in- terface handshake and asserts the address and control signals to the local memory.

4.4.1 WRITING TO LOCAL MEMORY

The local memory of an 82595FX solution is written to whenever the host CPU performs a Write opera- tion to the 82595FX Local Memory IO Port. Prior to writing a block of data to the local memory, the CPU should update the 82595FX Host Address Register with the first address to be written. The CPU then copies the data to the local memory by writing it to the 82595FX Local Memory IO Port. The addressing to the local memory is provided by the Host Address Register which is automatically incremented by the 82595FX upon completion of each write cycle. This allows sequential accesses to the local memory, even though the IO port address accessed does not change.

4.4.2 READING FROM LOCAL MEMORY

The local memory of an 82595FX solution is read from whenever the host CPU performs a Read oper- ation from the 82595FX Local Memory IO Port. Prior to reading a block of data from the local memory, the CPU should utilize the 82595FX Host Address Register to point to first address to be read. The CPU then reads the data from the local memory through the 82595FX Local Memory IO Port. The addressing to the local memory is provided by the Host Address Register which is automatically incre- mented by the 82595FX upon completion of each read cycle.

4.5 Serial EEPROM Interface

A Serial EEPROM, a Hyundai HY93C46 or equiva- lent IC, stores configuration data for the 82595FX. The use of an EEPROM enables 82595FX designs to be implemented without jumpers (the use of jump- ers to select IO windows is optional.) The port inter- face to the serial EEPROM provides both configura- tion and Plug N’ Play information access. Plug N’ Play allows peripheral functions to be added to a PC (such as adapter cards) without the need to individu- ally configure each parameter (e.g. Interrupt, IO Ad- dress, etc). Information describing system resources are contained within the 82595FX configuration reg- isters. This allows Auto-configuration software, which is usually contained in the BIOS or O/S, to identify system resource usage, identify conflicts and automatically re-configure the 82595FX. The 82595FX automatically accesses Register 0 of the EEPROM upon a RESET in ISA Bus Interface mode. Register 0 contains the information that the 82595FX must be configured to allow CPU accesses to it (IO Mapping Window, FLASH Detect Enable, Auto I/O Enable, Boot EPROM/FLASH Window, Host Bus Width, and Plug N’ Play Enable) following a system boot. The format for EEPROM Register 0 is shown in Figure 4-1. Note that all 0’s are assumed to be reserved. In the case where an EEPROM is either unprogrammed (each bit defaults to a 1) or completely erased (all 0’s), the 82595FX will default to IO Address 300h. Word0, Bit 1, the Word 1 Enable bit, is asserted to enable the read of EEPROM Word 1 during reset. This bit is active high. NOTE: If Word 1 of the EEPROM is not to be read during a reset, software must wait 200 ms af- ter the reset is issued before accessing the 82595FX, as was the case on all versions of the 82595. If Word 1 is to be read during a reset, software must wait 400 ms after reset before accessing the part. During this ‘‘blackout’’ period, the part will not respond to accesses on the ISA bus. Word 0, Bit 8, is the Flash Present bit. This bit is active low to indicate the presence of flash memory, as in the 82595FX B-3. The functionality of the bit is changed from the 82595FX B-2 and prior versions. Word 0, Bit 9 is the Auto-Negotiation, or A-N, Enable bit for the negotiation process at boot time. The bit is active high. Word 1 of the EEPROM is used to store the INT Select value to which the part will default on reset. The mapping from INT Select to IRQ is explained later in this document. The value stored in bits 0 through 2 of word 1 of the EEPROM is loaded into the INT Select register of the 82595FX, bank 1, reg- ister 2, bits 0 through 2 on any hardware or software reset. The reading of Word 1 on reset is enabled when bit 1 of word 0 of the EEPROM is set. If this bit is not set on reset, word 1 will not be read and the INT select register and Bad IRQ bit in bank 1 will be initialized to zero. For additional information regarding a Plug N’ Play implementation for the 82595FX, please consult the 82595FX User’s Guide and LAN595TX Specification, available through your local sales representative. The latest Plug N’ Play Specification is available by Microsoft. D15 D3 D2 D1 D0 Software Reserved INT Select Figure 4-1. EEPROM Register 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 I/O Mapping Window A-N Flash 0 Auto- BT/FLASH Host Word PnP En Pres. En Window Wdth 1 En En Figure 4-2. EEPROM Register 1

4.6 Boot EPROM/FLASH Interface

The Boot EPROM/FLASH of an 82595FX solution is read from or written to (FLASH only) whenever the host CPU performs a Read or a Write operation to a memory location that is within the Boot EPROM/ FLASH mapping window. This window is program- mable throughout the ISA PROM address range (C8000–DFFFF) by configuring the 82595FX Boot EPROM Decode Window register (Bank 1, Register 2, bits 4–6). The 82595FX asserts the BOOTCS Ý signal when it decodes a valid access. Up to 1 MBytes of FLASH can be addressed by the 82595FX. The format for the 82595FX Command Register is shown in Figure 5-1. The Command Register resides in Register 0 of each of the three IO Banks of the 82595FX, and can be accessed in any of these banks. The Command Register is accessed by writ- ing to or reading from the IO address for Register 0.

5.1 Command OP Code Field

Bits 0 through 4 of the Command Register comprise the Command OP Code field. A command is issued to the 82595FX by writing it into the Command OP Code field. A command can be issued to the 82595FX at any time; however in certain cases the command may be ignored (for example, issuing a Transmit command while a Transmit is already in progress). In these cases the command is not per- formed, and no interrupt will result from it. The Command OP Code field can also be read. In this case it will indicate an execution status event other than TRANSMIT DONE (TDR Done, DIAG- NOSE Done, MC-SETUP Done, DUMP Done, INIT Done, and POWER-UP) has been completed. This field is valid only when the EXEC INT bit (Bank 0, Reg 1, Bit 3) is set.

5.2 ABORT (Bit 5)

This bit indicates if an execution command other than TRANSMIT was aborted while in progress. This bit provides status information only. It should be writ- ten to a 0 whenever the Command Register is writ- ten to.

5.3 Pointer Field (Bits 6 and 7)

The Pointer field controls which 82595FX IO register bank is currently to be accessed (Bank 0, Bank 1, or Bank 2). Writing a 00:b to the Pointer field selects Bank 0, 01:b for Bank 1, and 10:b for Bank 2. The Pointer field is valid only when the SWITCH BANK (0h) command is issued. This field will be ignored for any other command. The 82595FX will continue to operate in a current bank until a different bank is selected. Upon power up of the device or Reset, the 82595FX will default to Bank 0.

5.4 82595FX Status Interface The Status of the 82595FX can be read from Regis- ter 1 of Bank 0, with additional status information contained in Register 0 (the Command Register). Figure 5-3 shows these registers. Other information concerning the configuration and initialization of the 82595FX and its registers can be obtained by direct- ly reading the 82595FX registers. When read, the Command OP Code field indicates which event (MC Done, Init Done, TDR Done, or DIAG Done) has been completed. This field is valid only when the EXEC INT Bit (Bank 0, Reg 1, Bit 3) is set to a 1. Reading the Pointer field indicates which bank the 82595FX is currently operating in. Register 1 in Bank 0 contains the 82595FX interrupts status as well as the current states of the RCV and Execu- tion units of the 82595FX. Resultant status from events such as the completion of a transmission or the reception of an incoming frame is contained in the status field of the memory structures for these particular events.

6.0 INITIALIZATION

Upon either a software or hardware RESET, the 82595FX enters into its initialization sequence. When the 82595FX is interfaced to an ISA bus, the 82595FX reads information from its EEPROM and Jumper block (if utilized) which configures critical pa- rameters (IO Address mapping, etc.) to allow initial accesses to the 82595FX during the host system’s initialization sequence and also access by the soft- ware device driver. The 82595FX can also be config- ured (via the EEPROM) to automatically resolve any conflicts to its IO address location either by moving its IO address offset to an unused location in the case that a conflict occurs, or by using the Plug N’ Play Software to the I/O address location. This pro- cess eliminates a large majority of LAN end-user setup problems. The 82595FX can be configured to operate with ISA systems that require early deassertion of the IOCHRDY signal to its low (not ready) state. The 82595FX, along with its software driver, can perform a test at initialization to determine if early IOCHRDY deassertion is required. 76543210 Pointer ABORT EXECUTION EVENT Reg 0 (CMD Reg) RCV EXEC EXEC TX RX RX STP States States INT INT INT INT Reg 1 (Bank 0) Figure 5-3. 82595FX Status Information

7.0 FRAME TRANSMISSION

The 82595FX performs all of the necessary func- tions needed to transmit frames from its local mem- ory. If Transmit Concurrent Processing is enabled, the CPU must only program the Base and Host Ad- dress Register with the starting address to be trans- mitted, copy a portion of the frame into the 82595FX’s transmit buffer located in local memory (the number of bytes for this first portion is deter- mined by the software driver without causing an Un- derrun), issue a XMT command to the 82595FX, and complete the data copies for this frame to local memory. If Transmit Concurrent Processing is dis- abled, the CPU must copy an entire frame into the 82595FX’s transmit buffer located in local memory, set up the 82595FX’s Current Address Registers to point to that frame, and issue a XMT command to the 82559TX. The 82595FX performs all the link management functions, DMA operations, and statis- tics keeping to handle transmission onto the link and communicate the status of the transmission to the CPU. The 82595FX performs automatic retransmis- sion on collision with no CPU interaction. 7.1 82595FX XMT Block Memory Format The format in which a XMT block is written to memo- ry by the CPU is shown in Figure 7-1 for a 16-bit interface. Figure 7-2 shows this structure for an 8-bit interface. 281732–4 Figure 7-1. XMT Block Memory Structure (16-Bit)

281732–5 Figure 7-2. XMT Block Memory Structure (8-Bit)

The two bytes of the Status Field (Status 0 and Status 1) are shown in detail in Figure 7-3. In a 16-bit wide interface, these two bytes will combine to form one word. This field is originally set to all 0’s by the CPU as the XMT block is copied to memory. It is updated by the 82595FX upon completion of the transmission.

7.2 XMT Chaining

The 82595FX can transmit consecutive frames with- out the CPU having issued a separate Transmit command for each frame. This is called Transmit Chaining. The 82595FX Transmit Chaining memory structure for a 16-bit interface is shown in Figure 7-4, with an 8-bit interface shown in Figure 7-5. The 82595FX registers which control the memory struc- ture are also shown. The CPU places multiple XMT blocks in the Transmit buffer. The 82595FX will transmit each frame in the chain, reporting the status for each frame in its status field. If Concurrent Processing is enabled, the copy of additional frames in a chain will take place while the first portion of the chain (one or more frames) is being transmitted by the 82595FX. This chain can be dynamically updat- ed by the CPU to add more frames to the chain. The transmit chain can be configured to terminate upon an errored frame (maximum collisions, underrun, lost CRS, etc.) or it can continue to the next frame in the chain. The 82595FX can be configured to interrupt upon completion of each transmission or to interrupt at the end of the transmit chain only (it always inter- rupts upon an errored condition). 76 54 32 1 0 TX DEF HRT BET MAX COL X No OF COLLISIONS Status 0 COLL X TX OK 0 LTCOL LST CRS X/JERR (1) UND RUN Status 1 NOTE: 1. Only functional in full duplex operations. Figure 7-3. Transmit Result

281732–6 Figure 7-4. 82595FX XMT Chaining Memory Structure

281732–7 Figure 7-5. XMT Block Memory Structure (8-Bit)

The 82595FX performs automatic retransmission when a collision is experienced within the first slot time of the transmission with no intervention by the CPU. The 82595FX performs jamming, exponential backoff, and retransmission attempts as specified by the IEEE 802.3 spec. The 82595FX reaccesses its local memory automatically on collision. This allows the 82595FX to retransmit up to 15 times after the initial collision with no CPU interaction. The 82595FX reaccesses the data in its transmit buffer by simply resetting the value of its Current Address Register back to the value of the Base Ad- dress Register (the beginning of the XMT block) and repeating the DMA process to access the data in the transmit buffer again. Once it regains access to the link, retransmission is attempted. When Transmit Chaining is utilized, the process for retransmission is exactly the same. Only the current frame in the chain will be retransmitted, since the Base Address Register is updated upon transmission of each frame.

8.0 FRAME RECEPTION

The 82595FX implements a recyclable ring buffer DMA structure to support the reception of back to back incoming RCV frames with minimal CPU over- head. The structure of the RCV frames in memory is optimized to allow the CPU to process each frame with as few software processing steps as pos- sible. The frame format is arranged so that all of the required infomation for each frame (status, size, etc.) is located at the beginning of the frame. 8.1 82595FX RCV Memory Structure The 82595FX RCV memory structure for a 16-bit in- terface is shown in Figure 8-1. Figure 8-2 shows this structure for the 8-bit interface. Once an incoming frame passes the 82595FX’s address filtering, the 82595FX deposits the frame into the RCV Data field of the RCV Memory Structure. The fields which pre- cede the RCV Data field, Event, Status, Byte Count, Next Frame Pointer, and the Event field of the fol- lowing frame, are updated upon the end of the frame after all of the incoming data has been deposited in the RCV Data field. If Receive Concurrent Process- ing is enabled, the CPU processes the receive frame without the entire frame being deposited by the 82595FX to the RCV Data Field. The 85295FX, along with the software driver, determines the por- tion of the frame being copied to host memory be- fore the rest of that frame is copied to local memory. An interrrupt is asserted by the 82595FX (EOF) after frame reception has been completed. If the 82595FX is configured to Discard Bad Frames, it will discard all incoming errored frames by reset- ting its DMA Current Address Register back to the value of the Base Address Register and not updat- ing any of the fields in the RCV frame structure. This area will now be reused to store the next incoming frame.

281732–8 Figure 8-1. 82595FX RCV Memory Structure (16-Bit)

281732–9 Figure 8-2. 82595FX RCV Memory Structure (8-Bit)

The two bytes of the Status Field (Status 0 and Status 1) are shown in detail in Figure 8-3. In a 16-bit wide interface, these two bytes will combine to form one word. The 82595FX provides this field for each incoming frame.

8.2 RCV Ring Buffer Operation

The 82595FX RCV Ring Buffer operation is illustrat- ed in Figure 8-4. The 82595FX copies received frames sequentially into the RCV Buffer area of the local memory. The CPU processes these frames by copying the frames from the local memory. After a frame is processed, the CPU updates the 82595FX’s Stop Register to point to the last location processed. This indicates that the RCV Buffer memory which precedes the value programmed in the Stop Regis- ter is now free area (it has been processed by the CPU). When the 82595FX reaches the end of the RCV Buffer (the Upper Limit Register value) it will now wrap around back to the beginning of the buff- er, and continue to copy RCV frames into the buffer, beginning at the value pointed to by the Lower Limit Register. The 82595FX will continue to copy frames into the RCV Buffer area as long as it does not reach the address pointed to by the Stop Register (if this does occur, the 82595FX stops copying the frames into memory and issues an Interrupt to the CPU). As the CPU processes additional incoming frames, the Stop Register value continues to be moved. This ac- tion allows the CPU to keep ahead of the incoming frames and allows the Ring Buffer to be continually recycled as the memory space consumed by an in- coming frame is reused as that frame is processed. 7 6 54 3 210 SRT FRM X X 1 X X IA MCH RCLD Status 0 TYP/LEN 0 RCV OK LEN ERR CRC ERR ALG ERR 0 OVR RN Status 1 Figure 8-3. RCV Status Field 281732–10 Figure 8-4. 82595FX RCV Ring Buffer Operation

9.0 SERIAL INTERFACE

The 82595FX’s serial interface subsystem incorpo- rates all the active circuitry required to interface the 82595FX to 10BASE-T networks or to the attach- ment unit (AUI) interface. It includes on-chip AUI and TPE drivers and receivers as well as Manchester Encoder/Decoder and Clock Recovery circuitry. The AUI port can be connected to an Ethernet Trans- ceiver cable drop to provide a fully compliant IEEE 802.3 AUI interface. The AUI port can also be inter- faced to a transceiver to provide a fully compliant IEEE 802.3 10BASE2 (Cheapernet) interface. The TPE port provides a fully compliant 10BASE-T inter- face. The 82595FX automatically enables either the AUI or TPE interface, depending on which medium is active. This automatic selection can be overridden by software configuration. The TPE interface also features a polarity fault detection and correction cir- cuit which will detect and correct a polarity error on the twisted pair wire, the most common wiring fault in twisted pair networks. A 20 MHz parallel resonant crystal is used to control the clock generation oscillator, which provides the basic 20 MHz clock source. An internal divide-by- two counter generates the 10 MHz g0.01% clock required by the IEEE 802.3 specification. The 82595FX supports 802.3 Half Duplex Ethernet functionality, as did previous versions of the 82595. It also supports a Full Duplex Ethernet mode that complies with Specifications for Full Duplex Ether- net , Rev. 1.0, Sept. 9th, 1993, from Kalpana, when connected to a Full Duplex hub through the TPE port. Full-duplex provides increased network throughput (using full duplex network components) by providing dedicated channels for both Transmit and Receive data at the same time. Full Duplex op- eration is transparent to existing software drivers. More details on Full Duplex functionality can be found in the 82595FX User’s Guide. Auto-Negotiation (or N-Way) is a method of maximiz- ing network operational efficiency. Auto-Negotiation works by interrogating Auto-Negotiation compliant equipment to determine the highest common mode of operation shared by all connected devices. When Auto-Negotiation is enabled, the 82595FX will nego- tiate the Highest Common Denominator (HCD) transmission mode with the hub to which it is at- tached, on a hardware reset. If the hub does not support Auto-Negotiation and Auto-Negotiation is enabled on the 82595FX, the 82595FX will revert to Half Duplex. The 82595FX is in Auto-Negotiation mode only when the A-N Enable bit, bit 1 in register 13 of bank 2, is set. On hardware reset, the state of this bit is copied from the EEPROM A-N Enable bit, bit 9 of Word 0 of the EEPROM. We recommend that a crystal that meets the follow- ing specifications be used: # Quartz Crystal # 20.00 MHz g0.002% at 25 §C # Accuracy g0.005% over Full Operating Temper- ature, 0 §Ct o a70§C # Parallel resonant with 20 pF Load Fundamental Mode Several vendors have such crystals; either off-the- shelf or custom-made. Two possible vendors are: 1. M-Tron Industries, Inc. Yankton, SD 57078 Specifications: Part No. HC49 with 20 MHz, 50 PPM over 0 §Ct o a70§C, and 20 pF fundamental load. 2. Crystek Corporation

100 Crystal Drive

Ft. Myers, FL 33907 Part No. 013212 The accuracy of the Crystal Oscillator frequency de- pends on the PC board characteristics; therefore, it is advisable to keep the X1 and X2 traces as short as possible. The optimum value of C1 and C2 should be determined experimentally under nominal operat- ing conditions. The typical value of C1 and C2 is between 22 pF and 35 pF. An external 20 MHz MOS-level clock may be applied to pin X1, if pin X2 is left floating. A summary of the 82595FX’s serial interface sub- sections functions is shown below: # Manchester Encoder/Decoder and Clock Recovery # Diagnostic Loopback # Reset-Low-Power Mode # Network Status Indicators # Defeatable Jabber Timer # User Test Modes

# Complies with IEEE 802.3 AUI Standard Ð Direct Interface to AUI Transformers Ð On-Chip AUI Squelch # Complies with IEEE 802.3 10BASE-T for Twisted Pair Ethernet Ð Selectable Polarity Detection and Correction Ð Direct Interface to TPE Analog Filters Ð On-Chip TPE Squelch Ð Defeatable Link Integrity for Pre-Standard Networks Ð Supports 4 LEDs (Link Integrity, Activity, AUI/BNC DIS and Polarity Correction) Ð Auto-Negotiation of Full Duplex Functionality

10.0 APPLICATION NOTES

This section is intended to provide Ethernet LAN de- signers with a basic understanding of how the 82595FX is used in a buffered LAN design.

10.1 Bus Interface

The 82595FX Bus Interface unit integrates ISA Bus data transceivers, providing an even more cost effi- cient and seamless integration than that of the 82595TX. The 82595FX provides the complete con- trol and address interface to the host system busÐ implementing a complete ISA bus protocol.

10.2 Local Memory Interface

The 82595FX’s local memory interface includes a DMA unit which controls data transfers between the 82595FX and the local memory SRAM. The 82595FX can support up to 64 Kbytes of local SRAM. The 82595FX provides address decoding and con- trol to allow access to an external Boot EPROM or a FLASH. Addition of a Boot EPROM or FLASH to an ISA solution is optional. The IA is assumed to be stored in the serial EEPROM for the ISA solution.

10.3 EEPROM Interface

The 82595FX provides a complete interface to a se- rial EEPROM for ISA adapter designs. For ISA moth- erboard designs, the EEPROM is not required. The EEPROM is used to store configuration information such as Memory and IO Mapping Window, Interrupt line selection, Plug N’ Play resource data local bus width, etc. The EEPROM is used to replace jumper blocks which previously contained this type of infor- mation.

10.4 Serial Interface

The 82595FX’s serial interface provides either an AUI port interface or a Twisted Pair Ethernet (TPE) interface. The AUI port can be connected to an Ethernet Transceiver cable drop to provide a fully compliant IEEE 802.3 10BASE5 interface. The AUI port can also be interfaced to a transceiver device on the adapter to provide a fully compliant IEEE 802.3 10BASE2 (Cheapernet) interface. The TPE port provides a fully compliant 10BASE-T interface. The 82595FX automatically enables either the AUI or TPE interface, depending on which medium is connected to the chip. This automatic selection can be overridden by software configuration.

10.4.1 AUI CIRCUIT

When used in conjunction with pulse transformers, the 82595FX provides a complete IEEE 802.3 AUI interface. In order to meet the 16V fault tolerance specification of IEEE 802.3, a pulse transformer is recommended. The transformer should be placed between the TRMT, RCV, and CLSN pairs of the 82595FX and the DO, DI, and CI pairs of the AUI (DB-15) connector. The pulse transformer should have the following characteristics: # 75 mH minimum inductance (100 mH recom- mended) # 2000V isolation between the primary and second- ary windings # 2000V isolation between the primaries of sepa- rate transformers # 1:1 Turns ratio The RCV and CLSN input pairs should each be ter- minated by 78.7 X g1% resistors.

10.4.2 TPE CIRCUIT

The 82595FX provides the line drivers and receivers needed to directly Fabinterface to the TPE analog filter network. The TPE receive section requires a 100X termination resistor, a filter section (filter, iso- lation transformer, and a common mode choke) as described by the 10BASE-T 802.3i-1990 specifica- tion. The TPE transmit section is implemented by con- necting the 82595FX’s four TPE outputs (TDH, TDH TDL, TDL ) to a resistor summing network to form the differential output signal. The parallel resistance of R5 and R6 sets the transmitters maximum output voltage, while the difference (R5 bR6)/R5aR6), is used to reduce the amplitude of the second half of the fat bit (100 ns) to a predetermined level. This predistortion reduces line overcharging, a major source of jitter in the TPE environment. The output of the summing network is then fed into the above mentioned filter and then to the 10BASE-T connec- tor (RJ-45). Analog Front End solutions can be pur- chased in a single-chip solution from several manu- facturers. The solution described in this data sheet uses the Pulse Engineering (PE65434) AFE.

10.4.3 LED CIRCUIT

The 82595FX’s internal LED drivers support four LED indicators displaying node status and activity (i.e., Transmit data, receive data, collisions, link in- tegrity, polarity correction, and port (TPE/AUI). To implement the LED indicators, connect the LED driv- er output to an LED in series with a 510 X resistor tied to V CC. Each driver can sink up to 10 mA of current with an output impedance of less than 50 X.

10.5 Layout Guidelines

10.5.1 GENERAL

The analog section, as well as the entire board itself, should conform to good high-frequency practices and standards to minimize switching transients and parasitic interaction between various circuits. To achieve this, follow these guidelines: Make power supply and ground traces as thick and as short as possible. This will reduce high-frequency cross coupling caused by the inductance of thin traces. Connect logic and chassis ground together, only at one point on the fabÐnear the connection to system ground. You must connect all V CC pins to the same power supply and all V SS pins to the same ground plane. Use separate decoupling per power-supply/ground pin. Close signal paths to ground as close as possible to their sources to avoid ground loops and noise cross coupling.

10.5.2 CRYSTAL

The crystal should be adjacent to the 82595FX and trace lengths should be as short as possible. the X1 and X2 traces should be as symmetrical as possible. 10.5.3 82595FX ANALOG DIFFERENTIAL SIGNALS The differential signals from the 82595FX to the transformers, analog front end, and the connectors should be symmetrical for each pair and as short as possible. The differential signals should also be isolated from the high speed logic signals on the same layer as well as on any sublayers of the PCB. Group each of the circuits together, but keep them separate from each other. Separate their grounds. In layout, the circuitry from the connectors to the filter network should have the ground and power planes removed from beneath it. This will prevent ground noise from being induced into the analog front end. All trace bends should not exceed 45 degrees.

10.5.4 DECOUPLING CONSIDERATIONS

Four 0.1 mF ceramic capacitors should be used. Place one on each side in the center of the I.C. adja- cent to the 82595FX. Connect the capacitors direct- ly to the V CC pins and ground planes of the 82595FX.

11.0 ELECTRICAL SPECIFICATIONS

11.1 Absolute Maximum Ratings

Case Temperature under Bias ÀÀÀÀÀÀÀ0 §Ct o a85§C Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b65§Ct o a140§C All Output and Supply Voltages ÀÀÀÀÀ b0.5V to a7V All Input Voltages ÀÀÀÀÀÀÀÀÀÀÀÀÀ b1.0V to a6.0V(1) Further information on the quality and reliability of the 82595FX may be found in the Components Quality and Reliability Handbook , Order Number 210997. NOTICE: This data sheet contains information on products in the sampling and initial production phases of development. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest data sheet be- fore finalizing a design. *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability. Table 11-1. DC Characteristics (TC e 0§Ct o a85§C, V CC e 5V g5%) Symbol Parameter Min Max Units Test Conditions VIL Input LOW Voltage (TTL) b0.3 a0.8 V VIH Input HIGH Voltage (TTL) 2.0 V CC a 0.3 V VIH(JUMPR) Input HIGH Voltage (Jumpers) 3.0 V CC a 0.3 V VOL1(2) Output LOW Voltage 0.45 V I OL e 17 mA VOL2(3) Output LOW Voltage 0.45 V I OL e 12 mA VOL4(4) Output LOW Voltage 0.45 V I OL e 2m A VOH Output HIGH Voltage 2.4 V I OH eb 1m A VOL (LED)(5) Output Low Voltage 0.45 V I OL e 10 mA VOH (LED) Output High Voltage 3.9 V I OH eb 500 mA ILP(6) Leakage Current g10 mA0 s VI s VCC RDIFF(7) Input Differential-Resistance 10 K X DC VIDF (TPE)(8) Input Differential Accept g0.5 g3.1 V P 5 MHz s f s 10 MHz Input Differential Reject g0.3 V P RS (TPE)(9) Output Source Resistance 5 13 X lILOADl e 25 mA VIDF (AUI)(10) Input Differential Accept g0.3 g1.5 V P Input Differential Reject g0.16 V P VICM (AUI)(11) AC Input Common Mode g0.5 V P f s 40 KHz g0.1 V P 40 KHz s f s 10 MHz VODF (AUI) Output Differential Voltage g0.45 g1.2 V IOSC (AUI) AUI Output Short Circuit Current g150 mA Short Circuit to V CC or GND VU (AUI) Output Differential Undershoot b100 mV VODI (AUI)(12) Differential Idle Voltage 40 mV ICC Power Supply Current 90 mA ICCHWPD Hardware Power Down 400 mA ICCSWPD Software Power Down 2 mA ICCSLEEP Sleep Mode 35 mA CIN(13) Input Capacitance 10 pF @ f e 1 MHz NOTES: 1. The voltage level for RCV and CLSN pairs are b0.75V to a8.5V. 2. SDx, IOCS16 . 3. IOCHRDY, IRQx. 4. LDATAx, LADDRx, LOE , LWE , BOOTCS , SRAMCS , EEPROMCS, SMOUT , TSTCLK, TDO, J1, J2. 5. LILED, ACTLED, POLED and TPE ÐBNCÐAUI. 6. Pins: ACTLED, LILED, POLED, TPE ÐBNCÐAUI. 7. RD to RD , RCV to RCV and CLSN to CLSN . 8. TPE input pins: RD and RD . 9. TPE output pins: TDH, TDH , TDL and TDL ,R S measure V CC or V SS to pin. 10. AUI input pins: RCV and CLSN pairs. 11. AUI output pins: TPMT pair. 12. Measured 8.0 ms after last positive transition of data packet. 13. Characterized, not tested.

11.1.1 PACKAGE THERMAL SPECIFICATIONS

The 82595FX is specified for operation when case temperature is within the range of 0 §Ct o8 5 §C. The case temperature may be measured in any environ- ment to determine whether the 82595FX is within the specified operating range. The case temperature should be measured at the center of the top surface opposite the pins. The ambient temperature is guaranteed as long as T C is not violated. The ambient temperature can be calculated from the iJA and the iJC from the follow- ing equations: TJ e TC a P*iJC TA e TJ b P*iJA TC e TA a P*ÀiJA b iJCÓ iJA and iJC values for the 160 QFP package are as follows: Thermal Resistance ( §C/Watt) iJC iJA b VS b Airflow ft/min (m/Sec) 0 (0) 4.9 34.4

11.2 AC Timing Characteristics

281732–11 Figure 11-1. Voltage Levels for Differential Input Timing Measurements (RCV and CLSN Pairs) 281732–12 Figure 11-2. Voltage Levels for TDH, TDL, TDH and TDL 281732–13 Figure 11-3. Voltage Levels for TRMT Pair Output Timing Measurements 281732–14 Figure 11-4. Voltage Levels for Differential Input Timing Measurements (RD Pair)

11.3 AC Measurement Conditions

1. T C e 0§Ct o a85§C, V CC e 5V g5% 2. The signal levels are referred to in Figures 1, 2, 3 and 4. 3. AC Loads: a) AUI Differential: a 10 pF total capacitance from each terminal to ground and a load resis- tor of 78 X g1% in parallel with a 27 mH g5% inductor between terminals. b) TPE: 20 pF total capacitance to ground. 281732–15 Figure 11-5. X1 Input Voltage Levels for Timing Measurements

Table 11-2. Clock Timing Symbol Parameter Min Max Unit t1 X1 Cycle Time 49.995 50.005 ns t2 X1 Fall Time 5 ns t3 X1 Rise Time 5 ns t4 X1 Low Time 15 ns t5 X1 High Time 15 ns

11.4 ISA Interface Timing

Table 11-3. 16-Bit I/O Access Parameter Description Min Max Units Comments T1a AEN Valid to I/O Command Active 100 ns T2a AEN Valid from I/O Command Inactive 30 ns T3a SA to CMD Active 63 ns T4a SA Valid Hold from CMD Inactive 42 ns T5a Valid SA to IOCS16 Active 100 ns T6a IOCS16 Valid Hold from Valid SA 0 ns T7a CMD Active to Inactive 125 ns T8a CMD Inactive to Active 92 ns Before I/O Command T9a Active CMD to Valid IOCHRDY 30 ns Applies to Ready Cycles T10a CMD Active Hold from IOCHRDY Active 80 ns Applies to Ready Cycles T11a DATA Driven from READ CMD Active 0 ns T12a Valid READ Data from CMD Active 64 ns Applies to Standard Cycles Only T13a Valid READ Data from IOCHRDY Active 52 ns Applies to Ready Cycles Only T14a READ Data Hold from CMD Inactive 0 ns T15a READ CMD Inactive to Data Tristate 30 ns T16a CMD to WRITE Data Active 62 ns T17a WRITE Data Hold from CMD Inactive 15 ns T18a WRITE CMD Inactive to Data Tristate 30 ns

Table 11-4. 8-Bit I/O Access Parameter Description Min Max Units Comments T1b AEN Valid to I/O Command Active 100 ns T2b AEN Valid from I/O Command Inactive 30 ns T3b SA to CMD Active 63 ns T4b SA Valid Hold from CMD Inactive 42 ns T5b Valid SA to IOCS16 Inactive 100 ns T6b IOCS16 Valid Hold from Valid SA 0 ns T7b CMD Active to Inactive 125 ns T8b CMD Inactive to Active 92 ns Before I/O Command T9b Active CMD to Valid IOCHRDY 226 ns Applies to Ready Cycles T10b CMD Active Hold from IOCHRDY Active 80 ns Applies to Ready Cycles T11b DATA Driven from READ CMD Active 0 ns T12b Valid READ Data from CMD Active 64 ns Applies to Standard Cycles T13b Valid READ Data from IOCHRDY Active 52 ns Applies to Ready Cycles Only T14b READ Data Hold from CMD Inactive 0 ns T15b READ CMD Inactive to Data Tristate 30 ns T16b CMD to WRITE Data Active 62 ns T17b WRITE Data Hold from CMD Inactive 15 ns T18b WRITE CMD Inactive to Data Tristate ns

Table 11-5. 8-Bit Memory Access Parameter Description Min Max Units Comments T1c AEN Valid to Command Active 100 ns T2c AEN Valid from Command Inactive 30 ns T3c SA to CMD Active 63 ns T4c SA Valid Hold from CMD Inactive 42 ns T5c CMD Active to Inactive 125 ns T6c CMD Inactive to Active 60 ns Before Memory Command T7c Active CMD to Valid IOCHRDY 226 ns Applies to Ready Cycles T8c CMD Active Hold from IOCHRDY Active 80 ns Applies to Ready Cycles T9c DATA Driven from READ CMD Active 0 ns T10c Valid READ Data from IOCHRDY Active 52 ns T11c READ Data Hold from CMD Inactive 0 ns T12c READ CMD Inactive to Data Tristate 30 ns T13c CMD to WRITE Data Active 62 ns T14c WRITE CMD Inactive to Data Tristate 30 ns

281732–16 Figure 11-6. ISA Read/Write Cycle

11.6 Local Memory Timings

11.6.1 SRAM TIMINGS

# The 82595FX any SRAM up to 25 ns access time. # SRAM type supported are 4K, 8K, 16K, 32K, 64K x 8. Table 11-6. 82595FX SRAMÐAC Characteristics Parameter Description Min Max Units Comments T1w LADDR Valid to SRAMCS Active 0 ns T2w LADDR Valid to LWE Active 0 ns T3w SRAMCS Active Time 25 ns T4w LWE Active Time 25 ns T5w Data Valid to SRAMCS Inactive 15 ns T6w Data Valid to LWE Inactive 15 ns T7w SRAMCS Inactive to Data Invalid 0 ns T8w LWE Inactive to Data Invalid 0 ns T9w SRAMCS Inactive to LADDR Invalid 0 ns T10w LWE Inactive to LADDR Invalid 0 ns T1r LADDR Valid to SRAMCS Active 0 ns T2r LADDR Valid to LOE Active 0 ns T3r SRAMCS Active Time 25 ns T4r LOE Active Time 25 ns T5r Data Valid to SRAMCS Active 25 ns T6r Data Valid to LOE Inactive 25 ns T7r Data Read Hold Time from SRAMCS Inactive 0 25 ns T8r Read Data Hold Time from LOE Inactive 0 25 ns

11.6.2 FLASH/EPROM TIMINGS

# The 82595FX is designed to support a FLASH or EPROM up to 200 ns access time. # Flash/EPROM types supported are 16K, 32K, 64K, 128K, 256K, 512K, 1024K x 8. Table 11-7. FLASHÐAC Characteristics Parameter Description Min Max Units Comments T1w LADDR Setup Time to LWE Active 0 ns T2w LADDR Hold Time from LWE Active 75 ns T3w LWE Active Time 60 ns T4w BOOTCS Setup Time before LWE Active 20 ns T5w BOOTCS Hold Time from LWE Inactive 0 ns T6w Data Setup Time before LWE Inactive 50 ns T7w Data Hold Time from LWE Inactive 10 ns T1r LADDR Setup Time to BOOTCS Active 0 ns T2r LADDR Setup Time to LOE 0n s T3r BOOTCS Active Time 225 ns T4r LOE Active Time 225 ns T5r BOOTCS Active to Data Valid 200 ns T6r LOE Active to Data Valid 200 ns T7r Data Hold Time from BOOTCS Inactive 0 40 ns T8r Data Hold Time from LOE Inactive 0 40 ns 281732–22 Figure 11-10. FLASH TimingsÐWrite Cycle

11.7 Interrupt Timing

Table 11-9. Interrupt Timing Parameter Description Min Max Units Notes T177 Interrupt Ack CMD Inactive to IRQ [0–7 ] Inactive 500 ns T178 IRQ [0–7 ] Inactive to IRQ [0–7 ] Active 100 ns T179 Tri-state CMD Inactive to IRQ [0–7 ] Tri-State 500 ns 281732–26 Figure 11-13. Interrupt Timing

11.8 RESET and SMOUT Timing

# Both signals are asynchronous signals and have minimum pulse duration specification only. # SMOUT during Hardware power down activation. Table 11-10. RESET and SMOUT Timing Parameter Description Min Max Units Notes T180 RESET Minimum Duration 32 ms 1 T181 SMOUT Minimum Duration 100 ns 2 T182 SMOUT Activation by Power Down Command 150 ns 3 T183 SMOUT Deactivation 25 ns 3 NOTES: 1. Noise spikes of maximum TBD ns are allowed on Reset. 2. SMOUT is input. 3. SMOUT is output after configuration. 281732–27 Figure 11-14. SMOUT Timing

11.9 JTAG Timing

Table 11-11. 82595FX JTAG Timing Symbol Parameter Min Max Unit Notes T184 TMS Set-Up Time 30 ns T185 TMS Hold Time 30 ns T186 TDI Set-Up Time 30 ns T187 TDI Hold Time 30 ns T188 Input Signals Set-Up Time 30 ns T189 Input Signals Hold Time 30 ns T190 Outputs Valid Delay 200 ns T191 TDO Valid Delay 40 ns T192 TCK Cycle Time (Period) 100 ns 50% Duty Cycle 281732–28 Figure 11-15. 82595FX JTAG Timing

11.10 Serial Timings

Table 11-12. TPE Timings Symbol Parameter Min Typ Max Unit t90 Number of TxD Bit Loss at Start of Packet 2 bits t91 Internal Steady State Propagation Delay 400 ns t92 Internal Start UP Delay 600 ns t93 TDH and TDL Pairs Edge Skew ( @ VCC/2) 1.5 3 ns t94 TDH and TDL Pairs Rise/Fall Times 2 5 ns (@ 0.5V to V CC b 0.5V) t95 TDH and TDL Pairs Bit Cell Center to Center 99 100 101 ns t96 TDH and TDL Pairs Bit Cell Center to Boundary 49 50 51 ns t97 TDH and TDL Pairs Return to Zero from Last TDH 250 400 ns t98 Link Test Pulse Width 98 100 100 ns t99 Last TD Activity to Link Test Pulse 8 13 24 ms t100 Link Test Pulse to Data Separation 190 200 ns 281732–29 281732–30 Figure 11-16. TPE Transmit Timings (Link Test Pulse)

Table 11-13. TPE Receive Timings Symbol Parameter Min Typ Max Unit t105 RD to RxD Bit Loss at Start of Packet 4 19 bits t106 RD Invalid Bits Allowed at Start of Packet 1 bits t107 RD to Internal Steady State Propagation Delay 400 ns t108 RD to Internal Start Up Delay 2.4 ms t109 RD Pair Bit Cell Center Jitter g13.5 ns t110 RD Pair Bit Cell Boundry Jitter g13.5 ns t111 RD Pair Held High from Last Valid 230 400 ns Position Transition 281732–31 Figure 11-17. TPE Receive Timings (End of Frame) Table 11-14. TPE Link Integrity Timings Symbol Parameter Min Typ Max Unit t120 Last RD Activity to Link Fault 50 100 150 ms (Link Loss Timer) t121 Minimum Received Linkbeat Separation (1) 25 7 m s t122 Maximum Received Linkbeat Separation (2) 25 50 150 ms NOTES: 1. Linkbeats closer in time to this value are considered noise and rejected. 2. Linkbeats further apart in time than this value are not considered consecutive and are rejected.

Additional 82595FX Documentation This datasheet provides complete pinout and pin definitions, and electrical specifications and timings. It also includes an overview of the various subsec- tions listed in Figure 1. For more complete informa- tion on the 82595FX, please ask your local sales representative for the 82595FX User’s Guide. The 82595FX User’s Guide contains detailed information on the 82595FX feature set, including register de- scriptions and implementation steps for various 82595FX functions (initialization, transmission, re- ception). Design Example The schematic on the next page shows a typical 82595FX design.

281732–39