8255A-5

8255A INTEL | Alldatasheet

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8255A FU ONAL DE SPTION commands to both of the Control Groups. systems. Its function is that of a general purpose I/O communication between the 8255A and the CPU. microcomputer system bus. The functional configu- . software so that normally no extemal logic is neces- . Data Bus Buffer from" the 8255A. words and status information are also transferred Write data or control words into the 8255A. through the data bus buffer. Figure 3. 8255A Block Diagram Showing Data Bus Buffer and Read/Write Control Logic Functions

intel. 8255A/8255A-5 Each of the Control blocks (Group A and Group B)

82654 BASIC OPERATION accepts “commands” from the Read/Write Control

[As| Ao| RD] WA|CS| input Operation (READ)| Logic, receives “control words" from the internal [Por —> Data Bus | ata bus and issues the proper commands to its as- lofolo] + [o [Porta — Data Bus soolatod pots pro lo[+[o] + [o [rors — datasus | [1folo|1]|o| PortG —> Data Bus Control Group A—Port A and Port C upper (C7-C4) Control Group B—Port 8 and Port C lower (C3-C0) Output Operation (WRITE) The Contro! Word Register can Only be written into. Folo|1| 0 | 0 |dataBus > Pona No Read operation of the Control Word Register is allowed. Lo] +] +] 0 [6 [oatagus > Pots [1 [0] 4] 0 | 0 |atabus > Porte Ports A, B, and C [1] 1] 4 ]°o | 0 | DataBus —> Control ; The 8255A contains three 8-bit ports (A, B, and C). [| [Tt { Disable Function All can be configured in a wide variety of functional characteristics by the system software but each has |x| x] x | 1 [oatabus — 3-state its own special features or “personality” to further [4 [4 [| 4 [0 | tegai Condition enhance the power and flexibility of the 8255A. Lx] x[1 [1 [o [oatabus > a-state Port A. One 8-bit data output latch/butfer and one 8-bit data input latch. (RESET) Port B. One 8-bit data input/output latch/butfer and a one 8-bit data input butter. Reset. A “high” on this input clears the control reg- ister and all ports (A, B, C) are set to the input mode. Port C, One &-bit data output latch/butfer and one 8-bit data input buffer (no latch for input). This port can be divided into two 4-bit ports under the mode Group A and Group B Controls control. Each 4-bit port contains a 4-bit latch and it . - can be used for the control signal outputs and status The functional configuration of each port is pro- Signal i tion with ports A and B. grammed by the systems software. In essence, the “1974! inputs in conjunction with ports A and CPU “outputs” a contro! word to the 8255A. The control word contains information such as “mode”, “bit set”, “bit reset”, etc., that initializes the func- tional configuration of the 8255A. 3-102

Figure 4. 8225A Block Diagram Showing Group A and Group B Control Functions

devices with a simple software maintenance routine. instance; Group B can be programmed in Mode 0 to. iio | io almost any peripheral device with no external logic. Figure 5. Basic Mode Definitions and Bus duces software requirements in Control-based appli-

Figure 7. Bit Set/Reset Format figuration provides simple input and output opera-

• Two 8-bit ports and two 4-bit ports.

Interrupt Control Functions * Any port can be input or output. terrupt request signals, generated from port C, can sible in this Mode.

intel. 8255A/8255A-5 MODE 0 (BASIC OUTPUT) ae 4 [ee aw Seq +} masa a toot . zava00-10 MODE 0 PORT DEFINITION (oa Troup TT Grow [me fm fm | om | ree | ome | + | rowe | ome (Upper) (Lower) | o [ o | o | o | oureur | oureur | o | oureut | outeur | Lo [oo | o | a | oureur [ ourput | 1 | oureur | inpur_| po | o | a [ o | oureur [ output | 2 | inpur | oureur | po foo [os fs | oureur [ ourpur [3 | inpur_ [input po {1 [o | o | oureur [ ineur_ | 4 | oureur_ [| ourpur | jo | + [ o | 4 | oureur [eur | s | oureur [input | fo | 1 {1 {| o | oureur [ ineur_ | 6 | ineur_[ ourpur | fo fos fos [os [ ourpur [wpur [7 [input | npur_| [+ [ o | o [ o [ weur 7 oureur [es [| oureur_| output _| [La [of o | + | weer [ output | se | oureur [eur _| La fo [is [ o | weur | ourpur | to | pur | ourpur | [a foo [a fos | eur | ourpur [os [input [input _| pa [+ [oo To | ineur | meut [te | oureur | ourrur | fa fia foo fot J eur | npur_ | ta | oureur | ineur_| pa fia fos foo J eur | eur { t¢ [pur | ourpur_| Laat Po Ta inp neu ts input inpur _| 3-106

intel . 8255A/8255A-5 MODE CONFIGURATIONS CONTROL WORD #0 CONTROL WORD #2 Dy Oy Oy 05 Oy 0% Oy Dy Dy 05 % Oy 0; 0, Oy BEEEoooo Eooooono A 8. easeny A 8. pa, pay 22554 255A 4. 9,70, $e pcre 291908-11 29190812 CONTROL WORD #1 CONTROL WORD #2 Dy Oe O% % 05 0; Oy Op Dy Oy Py % Oy 0; % 0% BEORDooo CeEEEEE TE] a 8. oa, pay a 2m oa, pay 255A 255A O70 f P70, { [>A — rey rg 4 — re,ee, 231908-13 291908-14 CONTROL WORD #4 ‘CONTROL WORD ## 2, Oy Dy 0% 0; Oy D, 0 ©) Dy DB, Dy 0; Oy 0) dy UteTe [et ted oTs] LieDei delet ete] a 8 nen, af 2 ray ny

82550 E2554

. 4. rey) 4+ roy, 8 8 a, 70, 0 231908—15 231908-16 3-107

intel. 8255A/8255A-5 CONTROL WORD #5 ‘CONTROL WORD #9 Dy Og Dy Dy 0; D, Oy Oy Dy Dy Op Dy 0; 0; Dy 0% Beacon EROanooo a Se ony Phy a 5 papa, sas8a ezasa 4 — rey, 4s bc, Pc, 4— vey Pey 4 ve,0c 231308-17 23190018 CONTROL WORD 68 CONTROL WORD =10 Dy Og Oy D% Ds 0; Dy DO 0) % Oy O% Dy 0, 0 O UTeTedel ToT Te] delet det TT] A 8. on, Pay a 5 paeny (255A ‘82550 — Pe 00, 4 pc, 9¢, 4 rey - + rey ecy 8 8 op, oa, 8 |-—> — pa, ra, 291908-19 231908-20 contRot woRD #7 conTROL woo #11 Dy Dy Os % D5 0; 0, O% Dy Oy Oy Oy Dy 0 0; Op BEoononn SROSnono a Se on,pay a + pa, pay e250 coy 4 pe, pc, +. r,70, 2,2, of 0,-2y { 4 vey rey ” A reytey * 5 ra,.P0, 8 5 re, 65 231908-21 23190822 3-108

intel. 8255A/8255A-5 CONTROL WORD #12 CONTROL WoRD #14 Dy Dy Os O_O; Oy O_O Br Pe Oy Oy Oy yO a 2 pa,pa, a 8 opens 82558 ‘B255A ‘ ‘ Poy Pey Poy PCy + rere 4 0574 231908-23 231908-24 CONTROL WoRD #12, CONTROL WORD #15 Dy Dy Ds O% Dy 0; 0, Op Dy Dy Os Oy 0; 0, 0, O 3 | A $ pn, Pay A £ op, eay 22554 2564 4 ‘ Foye Fore 2,0 ef ‘ 2,Dg ef Py Py 4 ve, 00 ® P+ pa, Poy 5 5 ra, 78, 231908-25 291908-26 Operating Modes Input Control Signal Definition MODE 1 (Strobed Input/Output). This functional © STB (Strobe Input). A “low” on this input loads configuration provides a means for transferring I/O _data into the input latch. data to or from a specified port in conjunction with strobes or “handshaking” signals. In mode 1, port A and port B use the lines on port C to generate or IBF (Input Buffer Full F/F) accept these “handshaking” signals. A “high” on this output indicates that the data has Mode 1 Basic Functional Definitions: been loaded into the input latch: in essence, an ac- knowledgement. IBF is set by STB input being low * Two Groups (Group A and Group B) and is reset by the rising edge of the RD input. * Each group contains one 8-bit data port and one 4-bit control/data port. * The 8-bit data port can be either input or output. + INTR (Interrupt Request) Both inputs and outputs are latched. A“high" on this output can be used to interrupt th “high” output can be used rupt the . Tre 4s Ports used for control and status of the Cpu when an input device is requesting. service, 'a port. INTR is set by the STB is a “one”, IBF is a “one” and INTE is a “one”. It is reset by the falling edge of RD. This procedure allows an input device to re- quest service from the CPU by simply strobing its data into the port. 3-109

Figure 12. Combinations of MODE 1 single 8-bit bus for both transmitting and receiving _to port A. © One 8-bit, bi-directional bus Port (Port A) anda 5- BF). Controlled by bit set/reset of PCs.

Figure 16. MODE 1/, Combinations

intel. 8255A/8255A-5 Mode Definition Summary [wT our | [wT our | — [erouraonty PAg OUT ouT - PAY ouT ouT cans PA2 OUT ouT pane PA3 OuT ouT pane PAg OuT OUT pane PAs OUT ouT pas PAs OuT ouT - PA? OuT out << PBo OUT ouT PB, OuT OUT PB2 OuT ~ OUT PBs ouT OUT MODE 0 PBs out out OR MODE 1 PBs OuT out ONLY PBs OuT OUT PB7 OuT out PCo | IN | OUT INTRa | INTRe 7) 3 Pc, | IN | OUT IBF; OBFg vo PC IN OUT STB, ACKg vo PCy | IN | OUT INTRA | INTRA INTRA PC, | IN | OUT STB, vo STB, PCs | IN | OUT IBF 4 vo IBF, PCs | IN | OUT vo ACKa ACK, PC; | IN | OUT vo OBF a OBF A Special Mode Combination This feature allows the 8255 to directly drive Darling- ton type drivers and high-voltage displays that re- Considerations quire such source current. There are several combinations of modes when not all of the bits in Port C are used for control or status. The remaining bits can be used as follows: Reading Port C Status WP Inputs— In Mode 0, Port C transfers data to or from the pe- rogrammed as Inputs ripheral device. When the 8255 is programmed to Al rt li s 1 Pe function in Modes 1 or 2, Port C generates or ac- Air input lines can be accessed during anormal Port °F. nand-shaking” signals with the peripheral de- vice. Reading the contents of Port C allows the pro- "P ed as Output grammer to test or verify the “status” of each pe- Togrammned a3 Quiputs— ripheral device and change the program flow ac- Bits in C upper (PC7-PC,) must be individually ac- 0rdingly. the bit set/reset function. cessed using the bit set/resel There is no special instruction to read the status in- Bits in C lower (PCg-PCo) can be accessed using formation from Port C. A normal read operation of the bit set/reset function or accessed as a three- Port Cis executed to perform this function. some by writing into Port C. Source Current Capability on Port B and Port C Any set of elght output buffers, selected randomly from Ports B and C can source 1 mA at 1.5 volts. 3-115

Figure 25. Machine Tool Controller interface Ambient ; cations are subject to change without notice. 1, Available on any 8 pins from Port B and C.

intel. 8255A/8255A-5 ee CAPACITANCE Tj = 25°C, Vcc = GND = OV [Symbol [Parameter [ win | Typ | Max | Unit | Test Gonditons ] [Cw | InputCapacitance | [| 10 | pr | = iMH Cd [eve [vo Cepactance [|_| 20 | pF | _Unmeasured pins returned to GND | A.C. CHARACTERISTICS Ta = 0°C to 70°C, Voc = +5V +10%, GND = OV" Bus Parameters : READ [ee PET] | Min | Max | Min [Max | | tan | Address StablebeforeREAD [oo [To || ns _| | tra | Address Stable afterREAD | 0 | | co | Sirs [tan | READPulsewiath 00 | a00 | dos _| | tao | Data ValidtromRean®y Taso | 200 | ns _| | top | DataFioatafterREAD | 10 | 150 | 10 | 100 | ns _| [tay | Time between READs and/orwaires | eso [| a50_] | ns] WRITE [__e2ssa_ | e2ssas | Min [Max |" Min [Max _| | tw [Address Stablebeforewnire [ o [| o [| ns _| [| twa | Address Stable atterwrire [20 [7 | 20 | ons _| [ ww | WAITEPulsewiath [400 | | 300 | S| os | | tow | OataVaidiownrre re) | 100 [| 100 [| «| ns _| L_two | Oatavaidaterwarre [90 [Tg S| |r| OTHER TIMINGS pee |e ee [Min [Max | Min [Max _| | we [WA tt0Ouputy TT as0 [50 Tn | ta | Peripheral DatabeforeRD | o | ||| | | wa | Peripheral DataaterRO | oo | | | Ts | tsr | stePusewiatn [500 | | 500 | Ts _—| | tes | Per. DatabeforeTeofsta | oo | | oo | ons | | toy | Per. Dataafterteorsts [eo [| eo [| ons | [to [ACK =otooutputy TT a0 [300s | Limo [ACK = ttoOutputFloat | 20 [250 [20 | 250 | ns | 3-119

intel. 8255A/8255A-5 A.C. CHARACTERISTICS (Continued) OTHER TIMINGS (Continued) tee a a [min [Mex | win | Max | [ince | waa woer=am [| eso [oo | | [Cisos | ASK = owoar= x | | a0 [ [a0 [ow | [tse [| sta=orowr=1) | | s00 | | 300 | ns | [tae [| Ro=ttowr=o0 | | a0 | | s00 ns [tar | RO=owmnta=o | Tao | a00 ns | [ier fst wemrn= noo | | 0 [| 200 | me | [ur] Aak= tonne = 1] | aso [ao |e | [wr | wa=owmme=or9 | [eso [| aso | ns | NOTES: 1. Test Conditions: CL = 150 pF. 2. Period of Reset pulse must be at least 50 4s during or after power on. Subsequent Reset pulse can be 500 ns min. 3. INTRT may occur as early as WAL. 4. Sampled, not 100% tested. *For Extended Temperature EXPRESS, use M8255A electrical parameters. A.C. TESTING INPUT, OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT Input/Output " L# Few ory Er Oe 231308-50 = AG. Testing: Inputs aro driven at 2.4V for @ Logic “1” and 045 731908-81 fora Loge'“O" Timing measurements aro made at 20V ora | | *Vexq is sot at various voltages during testing to quarantoe the Logic “1” and 0.8V for 8 Logic “0”. ‘specification. Cy, includes jig capacitance. 3-120

intel. 8255A/8255A-5 a WAVEFORMS MODE 0 (BASIC INPUT) ——— anne zoro08-52 MODE 0 (BASIC OUTPUT) oe ae o——— BA A0 cow cose 2308-53 3-121

intel. 8255A/8255A-5 WAVEFORMS (Continued) MODE 1 (STROBED INPUT) " a , Va mamma —— {nono nn nnn n nnn ---- zoro0e-se MODE 1 (STROBED OUTPUT) = a : Wo _ a ZL? “ nel a ales zstaoe-38 3-122

intel. 8255A/8255A-5 WAVEFORMS (Continued) MODE 2 (BIDIRECTIONAL) sas ow AK) py atk | py | | BS ‘sale pe afteofe- ww = 3 = 7 ara from ara prow . 80 um NOTE: (231308-56 ‘Any sequence where WA occurs before ACK and STB occurs before AD is permissible. (NTR = IBF» MASK » STB * RD + OBF » MASK » ACK « WR) WRITE TIMING READ TIMING neve we a ‘ae tio a fay DATA RUS 0 rc ee heb - { DATA BUS: HIGH IMPEDANCE VALI | HIGH IMPEDANCE folie , ar008-se 2o1008-57 3-123