82551IT

DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 102

Technical content

Datasheet sections

• 1.0 Introduction
• 1.1 Overview
• 1.2 Byte Ordering
• 1.3 References
• 1.4 Product Ordering Codes
• 2.0 Architectural Overview
• 2.1 Parallel Subsystem Overview
• 2.2 FIFO Subsystem Overview
• 3.0 Performance Enhancements
• 3.1 Multiple Priority Transmit Queues
• 3.2 Early Release
• 3.3 Hardware Integrity Support
• 3.4 Management Data Interfac e MDI/MDI-X Feature
• 4.0 Signal Descriptions
• 4.1 Signal Type Definitions
• 4.2 PCI Bus Interface Signals
• 4.2.1 Address and Data Signals
• 4.2.2 Interface Control Signals
• 4.2.3 System and Power Management Signals
• 4.3 Local Memory Interface Signals
• 4.4 Test Port Signals
• 4.5 PHY Signals
• 4.6 Power and Ground Signals
• 5.0 Media Access Control Functional Description
• 5.1 Device Initialization
• 5.1.1 Initialization Effects
• 5.2 PCI Interface
• 5.2.1 Bus Operations
• 5.2.2 Clock Run Signal
• 5.2.3 Power Management Event
• 5.3 PCI Power Management
• 5.3.1 Power States
• 5.3.2 Wake-up Events
• 5.4 Parallel Flash
• 5.5 Serial EEPROM Interface
• 5.5.1 EEPROM Address Map
• 5.6.1 Full Duplex
• 5.6.2 Flow Control
• 5.6.3 Address Filtering Modifications
• 5.6.4 VLAN Support

Networking Silicon - 82551IT Datasheet Product Features 1 This device is lead-free. That is, lead has not been intentionally added, but lead may still exist as an impurity at <1000 ppm. The Material Declaration Data Sheet, which includes lead impurity levels and the concentration of other Restriction on Hazardous Substances (RoHS)-banned materials, is available at: ftp://download.intel.com/design/packtech/material_content_IC_Package.pdf#pagemode=bookmarks In addition, this device has been tested and conforms to the same parametric specifications as previous versions of the device. For more information regarding lead-free products from Intel Corporation, contact your Intel Field Sales representative.  Enhanced IP Protocol Support — TCP, UDP, IPv4 checksum offload — Received checks um verification  Quality of Service (QoS) — Multiple priority transmit queues  Optimum Integration for Lowest Cost Solution — Integrated IEEE 802.3 10BASE-T and 100BASE-TX compatible PHY — 32-bit PCI master interface — Thin BGA 15mm 2 package  Integrated power management functions — ACPI and PCI power management standards compliance — Wake on “interesting” pa ckets and link status change support  PHY detects polarity, MDI-X, and cable lengths. Auto MDI, MDI-X crossover at all speeds  XOR tree mode support  High Performance Networking Functions — Early release — 8255x controller family chained memory structure — Improved dynamic tran smit chaining with multiple priorities transmit queues — Full pin compatibility with the 82559 and 82559ER controllers — Backward compatible software to 8255xER controllers — Full duplex support at 10 and 100 Mbps — IEEE 802.3u auto-negotiation support — 3 KB transmit and receive FIFOs — Fast back-to-back transmission support with minimum interframe spacing — IEEE 802.3x 100BASE-TX flow control support — Adaptive Technology  Low Power Features — Advanced Power Management (APM) capabilities — Low power 3.3 V device — Efficient dynami c standby mode — Deep power-down support — Clockrun protocol support  82551IT Enhancements — Wider operating temperature range — Improved bit error rate performance — HWI support — Deep power-down state power reduction  Lead-free1 196-pin Ball Grid Array (BGA). Devices that are lead-free are marked with a circled “e1” and have the product code: LUxxxxxx. 317801-004 Revision 4.1

Revision History

Revision Date Revision Description Oct 2003 3.0 • Initial draft for release (non-classified). Sep 2004 3.1 • Added references to the MDI/MDI-X feature.

• Added lead-free information.
• Removed EEPROM Map bit descriptions. These descriptions can now be found in the 82551QM/ER/IT EEPROM Map and Programming Information.
• Added 82551IT Test Port Functionality (Chapter 10).
• Added new values for RBIAS100 and RBIAS10. RBIAS100 = 649 and RBIAS10 = 619 .
• Removed all references to the 82551ER and 82551QM controllers. 82551ER and 82551QM information can now be found in their respective datasheets. Nov 2004 3.2 • Updated the section describing “Multiple Priority Transmit Queues”.
• Updated the section describing “VLAN Support”.
• Added information about migrating from a 2-layer 0.36 mm wide-trace substrate to a 2-layer 0.32 mm wide-trace substrate. Refer to the section on Package and Pin- out Information.
• Added statement that no changes to existing soldering processes are needed for the 2-layer 0.32 mm wide-trace substrate change in the section describing “Pack- age Information”. Jan 2005 3.3 • Added a note for PHY signals RBIAS100 and RBIAS10 to Table 8. April 2005 3.4 • Corrected the note in section 11stating that the maximum rating for the Case Tem- perature under Stress for the 82551QM/ER is 70° C instead of 85° C. July 2005 3.5 • Corrected the X1 Clock Specific ations for symbol Tx1_pr from ±50 ppm to ±30 ppm. Oct 2006 3.6 • Added Figure 28 “196 PBGA Package Pad Detail”. The figure shows solder resist opening and metal diameter dimensions. Feb 2007 3.7 • Updated section 11.1 “Absolute Maximum Ratings”. Sept 2007 3.8 • Added Section 13 “Reference Schematics”, updated Section 11.1 (changed Tcase to ambient) and added ordering information to Section 1.4. Sept 2007 3.9 • Updated Figures 31 and 32. Added Digital I/O and Crystal Input One (X1) Charac- teristics (Tables 52 and 53). Updated Section 5.6.4. March 2008 4.0 • Updated Figure 32: changed TEST pull down resistor value (62 K  to 1 K). Nov 2008 4.1 • Updated Table 12 (changed words 30h:33h to reserved).
• Updated Table 8 (X1 and X2 pin descriptions).
• Updated Tables 52 and 53 (Digital I/O and crystal input one (X1) characteristics). Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 82551IT may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtain ed from: Intel Corporation P .O. Box 5937 Denver, CO 80217-9808 or call in North America 1-800-548-4725, Europe 44-0-1793-431-155, France 44-0-1793-421-777, Germany 44-0-1793-421-333, other Countries 708- 296-9333 Intel® is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries. Copyright © 2008, Intel Corporation. * Other product and corporate names may be trademarks of other companies and are used only for explanation and to the owners’ benefit, without intent to infringe.

82551IT — Networking Silicon iv Datasheet

Networking Silicon — 82551IT

9.3.8 Register 23: 100BASE-TX Receive Premature End of Frame Error Coun-

82551IT — Networking Silicon vi Datasheet

Networking Silicon — 82551IT Datasheet 1

1.0 Introduction

This datasheet is applicable to the Intel® 82551IT Fast Ethernet PCI Controller, a member of the 8255x Fast Ethernet Controller family.

1.1 Overview

The 82551IT is an evolutionary addition to Intel’s family of 8255x controllers. It provides excellent performance by offloading TCP, UDP and IP checksums and supports TCP segmentation off-load for operations such as Large Send. The 82551IT provides an extended operating temperature in addition to all of the same capabilities and features as the 82551ER to address applications requiring a wider operating temperature range. Its optimized 32-bit interface and efficient scatter-gather bus mastering capabilities enable the 82551IT to perform high speed data transfers over the PCI bus. This capability accelerates the processing of high level commands and operations, which lowers CPU utilization. Its architecture enables data to flow efficiently from the bus interface unit to the 3 KB Transmit and Receive FIFOs, providing the perfect balance between the wire and system bus. In addition, multiple priority queues are provided to prevent data underruns and overruns. The 82551IT includes both a MAC and PHY . In also has a simple interface to the analog front end, which allows cost effective designs requiring minimal board real estate. The 82551IT is pin compatible with the 82559 family of controllers and is offered with software that provides backwards compatibility with previous 8255xER controllers.

1.2 Byte Ordering

TCP and IP Internet Engineering Task Force (IETF) Request for Comments (RFCs) and literature use big endian (BE) byte ordering. This document uses big endian ordering for all IP and TCP frame formats. However, little endian byte ordering is used for referencing 82551IT memory resident structures and internal structures.

1.3 References

The following documents may provide further information on topics discussed in this document.

• 10/100 Mbit Ethernet Controller Family Software Developer’s Manual. Intel Corporation.
• Advanced Configuration and Power Interface Specification, Revision 1.0. Intel Corporation, Microsoft Corporation, and Toshiba.
• IEEE 802.3x and 802.1y Standards.
• Network Device Class Power Management Reference Specification, Revision 1.0a. AMD, Inc. and Microsoft Corporation.

2 Datasheet

1.4 Product Ordering Codes

• GD82551IT (Leaded)
• LU82551IT (Lead Free)

Figure 1. 82551IT Component Markings

Networking Silicon — 82551IT Datasheet 3

2.0 Architectural Overview

The Intel® 82551IT is divided into four main subsystems: a parallel subsystem, a FIFO subsystem, a 10/100 Mbps Carrier Sense Multiple Access with Collision Detect (CSMA/CD) unit, and a 10/ 100 Mbps physical layer (PHY) unit.

2.1 Parallel Subsystem Overview

The parallel subsystem is comprised of several functional blocks: a PCI bus master interface, a micromachine processing unit and its corresponding microcode ROM, and a PCI Target Control/ Flash/EEPROM interface. The parallel subsystem also interfaces to the FIFO subsystem, passing data (such as transmit, receive, and configuration data) and command and status parameters between these two blocks. The PCI bus master interface provides a complete glueless interface to a PCI bus and is compliant with the PCI Bus Specification, Revision 2.2. The 82551IT provides 32 bits of addressing and data, as well as the PCI control interface. As a PCI target, it conforms to the PCI configuration scheme, which allows all accesses to the 82551IT to be automatically mapped into free memory and I/O space upon initialization of a PCI system. When transmit and receive data is processed, the 82551IT operates as a master on the PCI bus, initiating zero wait state transfers. The 82551IT Control/Status Register Block is part of the PCI target element. The Control/Status Register block consists of the following 82551IT internal control registers: System Control Block (SCB), PORT, Flash Control, EEPROM Control, and Management Data Interface (MDI) Control. An embedded micromachine consisting of independent transmit and receive processing units allow the 82551IT to execute commands and receive incoming frames with no real time CPU intervention. The 82551IT contains a multiplexed interface to connect an external serial EEPROM and Flash memory. The Flash interface, which can also be used to connect to any standard 8-bit device, provides up to 128 KB of addressing to the Flash. Both read and write accesses are supported. The Flash can be used for remote boot functions, network statistical and diagnostics functions, and management functions. The Flash is mapped into host system memory (anywhere within the 32-bit memory address space) for software accesses. It is also mapped into an available boot expansion ROM location during boot time of the system. More information on the Flash interface is detailed in Section 5.4, “Parallel Flash”. The serial EEPROM is used to store relevant information for a LAN connection such as node address, as well as board manufacturing and configuration information. Both read and write accesses to the EEPROM are supported by the 82551IT. Information on the EEPROM interface is detailed in Section 5.5, “Serial EEPROM Interface”.

2.2 FIFO Subsystem Overview

The 82551IT FIFO subsystem consists of independent 3 KB transmit and receive FIFOs. Each FIFO provides a temporary buffer for frames as they are transmitted or received. Transmit frames queued within the transmit FIFO allow back-to-back transmission within the minimum Interframe Spacing (IFS). The FIFOs allow the 82551IT to withstand long PCI bus latencies without losing incoming data. Additional attributes of the FIFOs that enhance performance and functionality are:

82551IT — Networking Silicon

4 Datasheet

• Tunable transmit FIFO threshold allows elimination of underruns while concurrent transmits are being performed.
• Extended PCI zero wait state burst accesses to and from the 82551IT for both transmit and receive FIFOs
• Efficient re-transmission of data directly from the transmit FIFO when physical or data link errors (collision detection or data underrun) are encountered, increasing performance by eliminating the need to re-access the data from host memory
• Automatic discard of incoming runt receive frames 2.3 10/100 Mbps Serial CSMA/CD Unit Overview The 82551IT’s CSMA/CD unit allows it to be connected to a 10 or 100 Mbps Ethernet network at half or full duplex. The CSMA/CD unit performs all of the functions of the 802.3 protocol such as frame formatting, frame stripping, collision handling, deferral to link traffic, etc. 2.4 10/100 Mbps Physical Layer Unit The integrated Physical Layer (PHY) unit of the 82551IT allows connection to either a 10 or 100 Mbps Ethernet network. The PHY supports Auto-Negotiation for 100BASE-TX Full Duplex, 100BASE-TX Half Duplex, 10BASE-T Full Duplex, and 10BASE-T Half Duplex. Three LED pins indicate link status, network activity, and speed.

Networking Silicon — 82551IT Datasheet 5

3.0 Performance Enhancements

All of Intel’s Fast Ethernet controllers have the ability to support full wire speeds. The 82551IT has been designed to provide improved networking throughput. Performance is limited to the system’s ability to feed data to the network controller. As networks grow, the task of servicing the network becomes a large burden on the platform. System bottlenecks prevent optimal performance in typical operating conditions. Thus, to help alleviate these issues, Network Operating System (NOS) vendors are establishing normalized off- load specifications. These specifications define the types of off-load support required by the OS and interface between the network drivers. The 82551IT provides support for these initiatives and enables an improvement in platform network efficiency. With the pervasiveness of Internet Protocols, the off-load capabilities have focused on improving IP efficiency. As part of this effort, the 82551IT includes support for Multiple Priority Transmit Queues.

3.1 Multiple Priority Transmit Queues

The 82551IT supports two queues: High Priority Queue (HPQ) and Low Priority Queue (LPQ). The 82551IT provides a method for the driver to modify the HPQ while processing data. A new read only register is defined in the Control/Status Register (CSR) that enables the driver to change the transmit priority of elements within the HPQ. When software reads this register, the address of the next Command Block to be processed by the 82551IT on the HPQ is returned. After reading this register, software can freely modify the next Command Block (for example, overwrite it with a different Command Block) and any subsequent Command Block, without any conflict with the 82551IT. Note: The 82551IT Windows* driver supports the Command Block Pointer register (in the CSR).

3.2 Early Release

Like the 82558, 82559 and 82550, the 82551IT supports a 3 KB transmit FIFO. The 82551IT provides a transmit FIFO enhancement called “early release” that effectively increases the amount of free capacity in the transmit FIFO. The enabling of early release is controlled through configuration space and occurs when the following conditions are met: 1. The transmitted frame is the olde st one in the queue (in other words, it is located at the head of the queue). 2. The transmitted frame has been completely tr ansferred to the XMT-SRAM and processed (for example, XSUM). Large frames (greater than 3 KB) are never candidates for an early release. 3. When the preemptive queue mechanism is on, a frame which satisfies condition 2 may not satisfy condition 1 and therefore will not benefit from an early release. 4. More than 128 bytes have al ready been transferred to the XMT-SYNC-FIFO. This condition guarantees that at least one slot time elapsed (collision window).

6 Datasheet

3.3 Hardware Integrity Support

can be located along the wire.

3.4 Management Data Inter face MDI/MDI-X Feature

connected to the 82551IT without any additional external logic. to the start of the hardware auto negotiation algorithm. Table 1 lists the connections for both straight-through and cross-over RJ-45 ports for comparison. Table 1. RJ-45 Connections a. Straight-through connections used on DTE applications. b. Cross-over connecti ons used on Hub and Switch applications.

1 TD+ RD+

2 TD- RD-

4 Not Used Not Used

5 Not Used Not Used

7 Not Used Not Used

8 Not Used Not Used

4.0 Signal Descriptions

4.1 Signal Type Definitions

Table 2. Signal Type Descriptions IN Input The input pin is a standard input only signal. TS Tri-State The tri-state pin is a bidirectional, input/output pin. clock cycle after it has been tri-stated by the previous owner. AI Analog Input The analog input pin is used for analog input signals. AO Analog Output The analog output pi n is used for analog output signals. B Bias The bias pin is an input bias. Supply Digital power or ground for the device. Supply Analog power or ground for the device.

8 Datasheet

4.2 PCI Bus Interface Signals

4.2.1 Address and Data Signals

4.2.2 Interface Control Signals

Table 3. Address and Data Signals phases; and the target, for read data phases. Table 4. Interface Control Signals stop the current transaction.

4.2.3 System and Power Management Signals

every bus master has its own REQ#. to-point signal and every master has its own GNT#. the 82551IT. This is an active low, level-triggered interrupt signal. Table 5. System and Power Management Signals disable suspension of the PCI Clock signal or restart of the PCI clock. to an external pull-down resistor.

10 Datasheet

4.3 Local Memory Interface Signals

unnecessarily connected to a pull-up or pull-down resistor. should be driven by the PCI Reset signal. 3.3 V supply in 3.3 V signaling environment. Table 6. Local Memory Interface Signals interface. These pins should be left floating if the Flash is not used. left floating if the Flash and the CLK25 functionality are not used. should be left floating if Flash is not used. this pin should be left floating.

4.4 Test Port Signals

Note: These test port signals are not JTAG compatible. As a result, a BSDL file is not required. FLA6:2 OUT Flash Address 6:2. These pins are used as Flash address outputs. These pins should be left floating if the Flash is not used. pin should be left floating. reset of the 82551IT is active (low), it acts as the input system type. For PCI systems that do not use Flash, this pin should be left floating. assert chip select to the serial EEPROM. Table 7. Test Port Signals Test Port. If this input pin is high, the 82551IT will enable the test port. TCK IN Test Port Clock. This pin is used for the Test Port Clock signal.

12 Datasheet

4.5 PHY Signals

Table 8. PHY Signals semiconductor (MOS) level 25 MHz oscillator when X2 is left floating. 25 MHz oscillator when X2 is left floating. signals depending on the mode of operation. active low); when no activity is present, the activity LED is off. Link Integrity LED. The Link Integrity LED pin indicates link integrity. active low); if link is invalid, the LED is off. will be on at 100 Mbps (SPDLED# active low) and off at 10 Mbps. print LOM Design Guide for more information.

4.6 Power and Ground Signals

Table 9. Power and Ground Signals VCCR APS Analog Power. These pins should be connected directly to VCC. up or pull-down resistors should not be used.

82551IT — Networking Silicon

14 Datasheet

Note: This page is intentionally left blank.

5.0 Media Access Control Functional Description

5.1 Device Initialization

1. Internal Power-on Reset (POR)
2. Software Reset (Software Command)
3. Selective Reset (Software Command)

5.1.1 Initialization Effects

ALTRST# and PCI RST# but not necessarily by the selective reset. Table 10. Initialization Effects

16 Datasheet

5.2 PCI Interface

5.2.1 Bus Operations

82551IT, as a bus master device, will initiate memory cycles by way of the PCI bus. 82551IT operation as a bus master (initiator) in Section 5.2.1.2.

5.2.1.1 Bus Slave Operation

• CPU accesses to the 82551IT System Control Block (SCB) Control/Status Registers (CSR)
• CPU accesses to the EEPROM through its CSR
• CPU accesses to the 82551IT PORT address through the CSR
• CPU accesses to the MDI control register in the CSR
• CPU accesses to the Flash control register in the CSR
• CPU accesses to the 128 KB Flash The CSR and the 1 MB Flash buffer are considered by the 82551IT as totally separated memory spaces. The 82551IT provides separate Base Address Registers (BARs) in the configuration space to distinguish between them. The size of the CSR memory space is 4 KB in the memory space and 64 bytes in the I/O space. The 82551IT treats accesses to these memory spaces differently. Power management event reset Clear only if no auxiliary power present Clear only if no auxiliary power present -- -- -- Statistic Sampling of configuration input pins ??? -- -- -- --

5.2.1.1.1 Control/Status Register (CSR) Accesses

• System Control Block (SCB) registers
• PORT register
• Flash control register
• EEPROM control register
• MDI control register
• Flow control registers The following figures show CSR zero wait state I/O read and write cycles. In the case of accessing the Control/Status Registers, the CPU is the initiator and the 82551IT is the target of the transaction. Read Accesses: The CPU, as the initiator, drives address lines AD[31:0], the command and byte enable lines C/BE#[3:0] and the control lines IRDY# and FRAME#. As a slave, the 82551IT controls the TRDY# signal and provides valid data on each data access. The 82551IT allows the CPU to issue only one read cycle when it accesses the Control/Status Registers, generating a disconnect by asserting the STOP# signal. The CPU can insert wait states by de-asserting IRDY# when it is not ready.

Figure 2. CSR I/O Read Cycle

18 Datasheet

the STOP# signal. This is true for both memory mapped and I/O mapped accesses. Figure 3. CSR I/O Write Cycle

5.2.1.1.2 Flash Buffer Accesses

longest burst cycle to the Flash buffer contains one data access only. Figure 4. Flash Buffer Read Cycle

20 Datasheet

accesses can be byte length only. Figure 5. Flash Buffer Write Cycle

5.2.1.1.3 Retry Premature Accesses

honored. Figure 6 below shows how a Retry looks when it occurs. Note: The 82551IT is considered the target in the above diagram; thus, TRDY# is not asserted.

5.2.1.1.4 Error Handling

• After accesses to the Flash buffer
• After accesses to its CSR
• After accesses to the configuration space System Error: The 82551IT reports parity error during the address phase using the SERR# pin. If the SERR# Enable bit in the PCI Configuration Command register or the Parity Error Response bit is not set, the 82551IT only sets the Detected Parity Error bit (PCI Configuration Status register, bit 15). If SERR# Enable and Parity Error Response bits are both set, the 82551IT sets the Signaled System Error bit (PCI Configuration Status register, bit 14) as well as the Detected Parity Error bit and asserts SERR# for one clock.

Figure 6. PCI Retry Cycle

22 Datasheet

involved in the current transaction.

5.2.1.2 Bus Master Operation

main memory (or the PCI host bridge, depending on the configuration of the system) is the target. Figure 7. Memory Read Burst Cycle Figure 8. Memory Write Burst Cycle

Networking Silicon — 82551IT Datasheet 23 command for burst accesses to control structures. For all write accesses to the control structure, the 82551IT uses the Memory Write (MW) command. For write accesses to data structure, the 82551IT may use either the Memory Write or Memory Write and Invalidate (MWI) commands. Read Accesses: The 82551IT performs block transfers from host system memory to perform frame transmission on the serial link. In this case, the 82551IT initiates zero wait state memory read burst cycles for these accesses. The length of a burst is bounded by the system and the 82551IT’s internal FIFO. The length of a read burst may also be bounded by the value of the Transmit DMA Maximum Byte Count in the Configure command. The Transmit DMA Maximum Byte Count value indicates the maximum number of transmit DMA PCI cycles that will be completed after an 82551IT internal arbitration. The 82551IT, as the initiator, drives the address lines AD[31:0], the command and byte enable lines C/BE#[3:0] and the control lines IRDY# and FRAME#. The 82551IT asserts IRDY# to support zero wait state burst cycles. The target signals the 82551IT that valid data is ready to be read by asserting the TRDY# signal. Write Accesses: The 82551IT performs block transfers to host system memory during frame reception. In this case, the 82551IT initiates memory write burst cycles to deposit the data, usually without wait states. The length of a burst is bounded by the system and the 82551IT’s internal FIFO threshold. The length of a write burst may also be bounded by the value of the Receive DMA Maximum Byte Count in the Configure command. The Receive DMA Maximum Byte Count value indicates the maximum number of receive DMA PCI transfers that will be completed before the 82551IT internal arbitration. The 82551IT, as the initiator, drives the address lines AD[31:0], the command and byte enable lines C/BE#[3:0] and the control lines IRDY# and FRAME#. The 82551IT asserts IRDY# to support zero wait state burst cycles. The 82551IT also drives valid data on AD[31:0] lines during each data phase (from the first clock and on). The target controls the length and signals completion of a data phase by de-assertion and assertion of TRDY#.

5.2.1.2.1 Memory Write and Invalidate

The 82551IT has four Direct Memory Access (DMA) channels. Of these four channels, the Receive DMA is used to deposit the large number of data bytes received from the link into system memory. The Receive DMA uses both the Memory Write (MW) and the Memory Write and Invalidate (MWI) commands. To use MWI, the 82551IT must guarantee the following: 1. Minimum transfer of one cache line 2. Active byte enable bits (or BE[3 :0]# are all low) during MWI access 3. The 82551IT may cross the cache line boundary on ly if it intends to transfer the next cache line too. To ensure the above conditions, the 82551IT may use the MWI command only if the following conditions are true: 1. The Cache Line Size (CLS) written in the CLS register during PCI configuration is 8 or 16 Dwords. 2. The accessed address is cache line aligned. 3. The 82551IT has at leas t 8 or 16 Dwords of data in its receive FIFO. 4. There are at least 8 or 16 Dwords of data space left in the system memory buffer. 5. The MWI Enable bit in the PCI Configuration Command register, bit 4, must be set to 1b.

82551IT — Networking Silicon

24 Datasheet

1. The MWI Enable bit in the 82551IT Configure command must be set to 1b. If any one of the above conditions is not true, the 82551IT uses the MW command. If an MWI cycle has started and one of the conditions is no longer valid (for example, the data space in the memory buffer is now less than CLS), then the 82551IT terminates the MWI cycle at the end of the cache line. The next cycle is either an MW or MWI cycle depending on the conditions listed above. If the 82551IT started a MW cycle and reached a cache line boundary, it either continues or terminates the cycle depending on the Terminate Write on Cache Line configuration bit of the 82551IT Configure command (byte 3, bit 3). If this bit is set, the 82551IT terminates the MW cycle and attempts to start a new cycle. The new cycle is an MWI cycle if this bit is set and all of the above conditions are met. If the bit is not set, the 82551IT continues the MW cycle across the cache line boundary if required.

5.2.1.2.2 Read Align

The Read Align feature enhances the 82551IT’s performance in cache line oriented systems. In these particular systems, starting a PCI transaction on a non-cache line aligned address may cause low performance. To resolve this performance anomaly, the 82551IT attempts to terminate transmit DMA cycles on a cache line boundary and start the next transaction on a cache line aligned address. This feature is enabled when the Read Align Enable bit is set in the 82551IT Configure command (byte 3, bit 2). If this bit is set, the 82551IT operates as follows:

• When the 82551IT is almost out of resources on the transmit DMA (that is, the transmit FIFO is almost full), it attempts to terminate the read transaction on the nearest cache line boundary.
• When the arbitration counter’s feature is enabled (in other words, the Transmit DMA Maximum Byte Count value is set in the Configure command), the 82551IT switches to other pending DMAs on cache line boundary only. This feature is not recommended for use in non-cache line oriented systems since it may cause shorter bursts and lower performance. If this feature is used, it is recommended that the CLS register in PCI Configuration space is set to 8 or 16.

5.2.1.2.3 Error Handling

Data Parity Errors: As an initiator, the 82551IT checks and detects data parity errors that occur during a transaction. If the Parity Error Response bit is set (PCI Configuration Command register, bit 6), the 82551IT also asserts PERR# and sets the Data Parity Detected bit (PCI Configuration Status register, bit 8). In addition, if the error was detected by the 82551IT during read cycles, it sets the Detected Parity Error bit (PCI Configuration Status register, bit 15).

5.2.2 Clock Run Signal

This signal is active in PCI bus operating modes. The Clock Run signal is an open drain I/O signal. It is used as a bi-directional channel between the host and the devices.

• The host de-asserts the CLK_RUN# signal to indicate that the clock is about to be stopped or slowed down to a non-operational frequency.
• The host asserts the CLK_RUN# signal when the clock is either running at a normal operating frequency or about to be started.

Networking Silicon — 82551IT Datasheet 25

• The 82551IT asserts the CLK_RUN# signal to indicate that the PCI clock must prevent the host from stopping or to request that the host restore the clock if it was previously stopped. Proper operation requires that the system latency from the nominal PCI CLK to CLK_RUN# assertion should be less than 0.5 µs. If the system latency is longer than 0.5 µs, there is an increase in receive overruns. In these types of systems, the Clock Run functionality should be disabled. In this case, the 82551IT will claim the PCI clock even during idle time. If the CLK_RUN# signal is not used, it must be connected to a pull-down resistor.

5.2.3 Power Management Event

The 82551IT supports power management indications in the PCI mode. The PME# output pin provides an indication of a power management event in PCI systems.

5.3 PCI Power Management

The 82551IT supports interesting packet wake-up and the capability to wake the system on a link status change from a low power state. The 82551IT enables the host system to be in a sleep state and remain virtually connected to the network. After a power management event or link status change is detected, the 82551IT will wake the host system. The sections below describe these events, the 82551IT power states, and estimated power consumption at each power state.

5.3.1 Power States

The 82551IT has one set of PCI power management registers and implements all four power states as defined in the Power Management Network Device Class Reference Specification, Revision 1.0. The four device power states, D0 through D3, vary from maximum power consumption at D0 to the minimum power consumption at D3. PCI transactions are only allowed in the D0 state, except for host accesses to the 82551IT’s PCI configuration registers. The D1 and D2 power management states enable intermediate power savings while providing the system wake-up capabilities. In the D3 cold state, the 82551IT can provide wake-up capabilities only if auxiliary power is supplied. Wake-up indications from the 82551IT are provided by the Power Management Event (PME#) signal in PCI implementations.

5.3.1.1 D0 Power State

As defined in the Network Device Class Reference Specification, the device is fully functional in the D0 power state. In this state, the 82551IT receives full power and should be providing full functionality. In the 82551IT the D0 state is partitioned into two substates, D0 Uninitialized (D0u) and D0 Active (D0a). D0u is the 82551IT’s initial power state following a Power-on Reset (POR) event and before the Base Address Registers (BARs) are accessed. Initialization of the CSR, Memory, or I/O Base Address Registers in the PCI Configuration space switches the 82551IT from the D0u state to the D0a state. In the D0a state, the 82551IT provides its full functionality and consumes nominal power. In addition, the 82551IT supports wake on link status change (Section 5.3.2, “Wake-up Events”). While it is active, the 82551IT requires a nominal PCI clock signal (in other words, a clock frequency greater than 16 MHz) for proper operation. During idle time, the 82551IT supports a PCI

82551IT — Networking Silicon

26 Datasheet

clock signal suspension using the Clockrun signal mechanism. The 82551IT supports a dynamic standby mode. In this mode, the 82551IT is able to save almost as much power as it does in the static power-down states. The transition to or from standby is done dynamically by the 82551IT and is transparent to the software.

5.3.1.2 D1 Power State

For a device to meet the D1 power state requirements, as specified in the Advanced Configuration and Power Interface (ACPI) Specification, Revision 1.0, it must not allow bus transmission or interrupts; however, bus reception is allowed. Therefore, device context may be lost and the 82551IT does not initiate any PCI activity. In this state, the 82551IT responds only to PCI accesses to its configuration space and system wake-up events. The 82551IT retains link integrity and monitors the link for any wake-up events such as wake-up packets or link status change. Following a wake-up event, the 82551IT asserts the PME# signal to alert the PCI system.

5.3.1.3 D2 Power State

The ACPI D2 power state is similar in functionality to the D1 power state. If the bus is in the B2 bus power state, the 82551IT will consume less current than it does in the D1 state. In addition to D1 functionality, the 82551IT can provide a lower power mode with wake-on-link status change capability. The 82551IT may enter this mode if the link is down while the 82551IT is in the D2 state. In this state, the 82551IT monitors the link for a transition from an invalid link to a valid link. The 82551IT will not attempt to keep the link alive by transmitting idle symbols or link integrity pulses.

1 The sub-10 mA state due to an invalid link can be enabled or disabled by a configuration

bit in the Power Management Driver Register (PMDR).

5.3.1.4 D3 Power State

In the D3 power state, the 82551IT has the same capabilities and consumes the same amount of power as it does in the D2 state. However, it enables the PCI system to be in the Bus Power 3 (B3) state. If the PCI system is in the B3 state (in other words, no PCI power is present), the 82551IT provides wake-up capabilities if it is connected to an auxiliary power source in the system. If PME# is disabled, the 82551IT does not provide wake-up capability or maintain link integrity. In this mode, the 82551IT consumes minimal power. The 82551IT enables a system to be in a sub-5 watt state (low power state) and still be virtually connected. More specifically, the 82551IT supports full wake-up capabilities while it is in the D3 cold state. The 82551IT can be connected to an auxiliary power source (V AUX), which enables it to provide wake-up functionality while the PCI power is off. The typical current consumption of the 82551IT is 125 mA at 3.3 V and a dual power plane is not required. If connected to an auxiliary power source, the 82551IT receives all of its power from the auxiliary source in all power states. When connected to an auxiliary power supply, the 82551IT must have a status indicator of whether the power supply is valid (in other words, auxiliary power is stable). The indication is received at the AUXPWR pin, as described next. 1. For a topology of two 82551IT devices connected by a crossed tw isted-pair Ethernet cable, the deep power-down mode should be disabled. If it is enabled, the two devices may not detect each other if the operating system places them into a low power state before both nodes become active.

Networking Silicon — 82551IT Datasheet 27

5.3.1.4.1 Auxiliary Power Signal

The 82551IT senses whether it is connected to the PCI power supply or to an auxiliary power supply (VAUX) through the FLA1/AUXPWR pin. The auxiliary power detection pin (multiplexed with FLA1) is sampled when the 82551IT power-on reset is active. An external pull-up resistor should be connected to the 82551IT if it is fed by VAUX; otherwise, the FLA1/AUXPWR pin should be left floating. The presence of AUXPWR affects the value reported in the Power Management Capability Register (PCI Configuration Space, offset DEh). The Power Management Capability Register is described in more detail in Section 7.1.19, “Power Management Capabilities Register”.

5.3.1.4.2 Alternate Reset Signal

The 82551IT’s ALTRST# input pin functions as a power-on reset input. Following ALTRST# being driven low, the 82551IT is initialized to a known state. While this function is required, this pin is not needed for it. Since this functionality is provided by the 82551IT’s internal power-on reset signal, this pin should be pulled high to the main digital power supply. Note: A separate internal power-on reset signal is generated when power is applied to the device. This signal is active while it provides the 82551IT power-on reset function and is also used for sampling configuration inputs.

5.3.1.4.3 Isolate Signal

When the 82551IT is connected to VAUX, it can be powered on while the PCI bus is powered off. In this case, the 82551IT isolates itself from the PCI bus. The 82551IT has a dedicated ISOLATE# pin that must be connected to the PCI Reset signal. Whenever the PCI Bus is in the B3 state, the PCI Reset signal becomes active and the 82551IT isolates itself from the PCI bus. During this state, the 82551IT ignores all PCI signals including the RST# and CLK input signals. It also tristates all PCI outputs, except the PME# signal. In the transition to an active PCI power state (in other words, from B3 bus power state to B0 bus power state), the PCI Reset signal shifts high. This generates an internal hardware reset, which initializes the device (described in Section 5.1.1, “Initialization Effects”). Some designs in existence may implement the previous recommendations for the RST#, ISOLATE# and ALTRST# input pins. In these cases, the PCI Reset signal is connected to the RST# pin, the PCI power source’s stable power (power good) to the ISOLATE# pin, and the auxiliary power source’s stable power (auxiliary power good) to the ALTRST# pin. It is not necessary for existing working designs to make changes for these signals; however, it is recommended that the changes contained in this document should be included when possible. New designs should implement the recommendations contained in this document.

5.3.1.4.4 PCI Reset Signal

The PCI RST# signal can be activated in one of the following cases:

• Power-up
• Warm boot
• Wake-up (B3 to B0 transition)
• Set to power-down (B0 to B3 transition)

28 Datasheet

packet would not be affected).

• Active RST# signal while the 82551IT is the D0, D1, or D2 power state
• RST# trailing edge while the 82551IT is in the D3 power state
• ISOLATE# trailing edge The internal initialization signal resets the PCI Configuration Space, MAC configuration, and memory structure. The behavior of the RST# and ISOLATE# pins and the internal 82551IT initialization signal are shown in the following figure.

Figure 9. Initialization upon RST# and ISOLATE#

The following tables list the functionality at the different power states for the 82551IT.

5.3.2 Wake-up Events

Status (PMCSR) register is set.

• Address Resolution Protocol (ARP) Packets (with Multiple IP addresses)
• Direct Packets (with or without type qualification)
• Neighbor Discovery Multicast Address Packet (“ARP” in IPv6 environment)
• NetBIOS over TCP/IP (NBT) Query Packet (under IPv4)
• Internetwork Package Exchange* (IPX*) Diagnostic Packet This allows the 82551IT to handle various packet types. In general, the 82551IT supports programmable filtering of any packet in the first 128 bytes.

Table 11. Functionality at the Different Power States

• PCI slave access D0a Valid Full functionality at full power and wake on an invalid link Invalid Full functionality at full power and wake on a valid link Valid
• Wake-up on “interesting” packets and link invalid
• PCI configuration access Invalid • Wake on link valid
• PCI configuration access Valid Same functionality as D1 (link valid) Invalid Detection for valid link and no link integrity D3 (with power) Valid Same functionality as D1 (link valid) Invalid Detection for valid link and no link integrity Dx (x>0 without PME#) Don’t care No wake-up functionality.

82551IT — Networking Silicon

30 Datasheet

5.3.2.2 Link Status Change Event

The 82551IT link status indication circuit is capable of issuing a PME on a link status change from a valid link to an invalid link condition or vice versa. The 82551IT reports a PME link status event in all power states. The PME# signal is gated by the PME Enable bit in the PMCSR and the CSMA Configure command.

5.4 Parallel Flash

The 82551IT’s parallel interface is used for a Flash interface. The 82551IT supports a glueless interface to an 8-bit wide, 128 KB, parallel memory device. The Flash (or boot PROM) is read from or written to whenever the host CPU performs a read or a write operation to a memory location that is within the Flash mapping window. All accesses to the Flash, except read accesses, require the appropriate command sequence for the device used. (Refer to the specific Flash data sheet for more details on reading from or writing to the Flash device.) The accesses to the Flash are based on a direct decode of CPU accesses to a memory window defined in either the 82551IT Flash Base Address Register (PCI Configuration space at offset 18h) or the Expansion ROM Base Address Register (PCI Configuration space at offset 30h). The 82551IT asserts control to the Flash when it decodes a valid access. The 82551IT supports an external Flash memory (or boot PROM) of up to 128 KB. The Expansion ROM address can be separately disabled by setting the corresponding bit in the EEPROM, word Ah. Note: Flash accesses must always be assembled or disassembled by the 82551IT whenever the access is greater than a byte-wide access. Due to slow access times to a typical Flash and to avoid violating PCI bus holding specifications (no more than 16 wait states inserted for any cycles that are not system initiation cycles), the maximum data size is either one word or one byte for a read operation and one byte only for a write operation.

5.5 Serial EEPROM Interface

The serial EEPROM stores configuration data for the 82551IT and is a serial in/serial out device. The 82551IT supports either a 64-register or 256-register size EEPROM and automatically detects the EEPROM’s size. The EEPROM should also operate at a frequency of at least 1 MHz.

Information for more details. Figure 10. 64-Word EEPROM Read Instruction Waveform

32 Datasheet

5.5.1 EEPROM Address Map

Table 12 lists the EEPROM address map for the 82551IT Fast Ethernet Controller. Note: Refer to the 82551QM/ER/IT EEPROM Map and Programming Information for more details. serial clocks run at either 25 or 2.5 MHz. Table 12. 82551IT EEPROM Address Map

Networking Silicon — 82551IT Datasheet 33

5.6.1 Full Duplex

When operating in full duplex mode the 82551IT can transmit and receive frames simultaneously. Transmission starts regardless of the state of the internal receive path. Reception starts when the internal PHY detects a valid frame on the receive differential pair of the PHY . The 82551IT operates in either half duplex mode or full duplex mode. For proper operation, both the 82551IT CSMA/CD module and the PHY unit must be set to the same duplex mode. The CSMA duplex mode is set by the 82551IT Configure command or forced by the settings in the PHY unit’s registers. The PHY duplex mode is set either by Auto-Negotiation or, if Auto-Negotiation is disabled, by setting the full duplex bit in the Management Data Interface (MDI) Register 0, bit 8. By default, the internal PHY unit advertises full duplex ability in the Auto-Negotiation process regardless of the duplex setting of the CSMA unit. The CSMA configuration should match the result of the Auto- Negotiation. The selection of duplex operation (full or half) and flow control is done in two levels: MAC and PHY . The MAC duplex selection is done only through the CSMA configuration mechanism (in other words, the Configure command in software).

5.6.2 Flow Control

The 82551IT supports IEEE 802.3x frame-based flow control frames in both full duplex and half duplex switched environments. The 82551IT flow control feature is not intended to be used in shared media environments. The PHY unit’s duplex and flow control enable can be selected using the NWay* Auto-Negotiation algorithm or through the Management Data Interface.

5.6.3 Address Filter ing Modifications

The 82551IT can be configured to ignore one bit when checking for its Individual Address (IA) on incoming receive frames. The address bit, known as the Upper/Lower (U/L) bit, is the second least significant bit of the first byte of the IA. This bit may be used, in some cases, as a priority indication bit. When configured to do so, the 82551IT passes any frame that matches all other 47 address bits of its IA, regardless of the U/L bit value. This configuration only affects the 82551IT specific IA and not multicast, multi-IA or broadcast address filtering. The 82551IT does not attribute any priority to frames with this bit set, it simply passes them to memory regardless of this bit.

5.6.4 VLAN Support

The 82551IT controller supports the VLAN standard as currently defined by the IEEE 802.1 committee. All VLAN receive flows will be implemented by software. The 82551IT supports the reception of long frames, specifically frames longer than 1518 bytes, including CRC, if software sets the Long Receive OK bit in the Configuration command. Otherwise, “long” frames are discarded.

82551IT — Networking Silicon

34 Datasheet

5.7 Media Independent Interface (MII) Management Interface

The MII management interface allows the CPU to control the PHY unit through a control register in the 82551IT. This allows the software driver to place the PHY in specific modes such as full duplex, loopback, power down, etc., without the need for specific hardware pins to select the desired mode. This structure allows the 82551IT to query the PHY unit for status of the link. This register is the MDI Control Register and resides at offset 10h in the 82551IT CSR. (The MDI registers are described in detail in Section 9.0, “PHY Unit Registers”.) The CPU writes commands to this register and the 82551IT reads or writes the control/status parameters to the PHY unit through the MDI register. Although the 82551IT follows the MII format, the MI bus is not accessible on external pins.

Networking Silicon — 82551IT Datasheet 35

6.0 Physical Layer Functional Description

6.1 100BASE-TX PHY Unit 6.1.1 100BASE-TX Transmit Clock Generation A 25 MHz crystal or a 25 MHz oscillator is used to drive the PHY unit’s X1 and X2 pins. The PHY unit derives its internal transmit digital clocks from this crystal or oscillator input. The internal Transmit Clock signal is a derivative of the 25 MHz internal clock. The accuracy of the external crystal or oscillator must be ± 0.005% (30 ppm). 6.1.2 100BASE-TX Transmit Blocks The transmit subsection of the PHY unit accepts nibble-wide data from the CSMA/CD unit. The transmit subsection passes data unconditionally to a 4B/5B encoder. The 4B/5B encoder accepts nibble-wide data (4 bits) from the CSMA unit and compiles it into 5- bit-wide parallel symbols according to the IEEE 802.3u 100BASE_TX standard. Next, the symbols are scrambled to reduce electromagnetic emissions during long sequences of high-frequency data codes. The MLT-3 (multi-level signal) encoder receives the scrambled Non-Return to Zero (NRZ) data stream from the scrambler and encodes the stream into MLT-3 for presentation to the driver. MLT- 3 is similar to NRZ1 coding, but three levels are output instead of two. The three output levels are positive, negative and zero. The transmit differential pair line drivers are implemented with digital slope controlled current buffers that meet the TP-PMD specifications. Current is sinked from an isolation transformer by the TDP and TDN pins. The 125 Mbps bit stream is typically driven onto Unshielded Twisted Pair (UTP) cable. 6.1.3 100BASE-TX Receive Blocks The receive subsection of the PHY unit accepts 100BASE-TX MLT-3 data on the receive differential pair. Due to the advanced digital signal processing design techniques employed, the PHY unit will accurately receive valid data from Category 5 (CAT5) UTP cables of lengths well in excess of 100 meters. The distorted MLT-3 signal at the end of the wire is restored by the equalizer. The equalizer performs adaptation based on the shape of the received signal. The clock recovery circuit uses digital signal processing to compensate for various signal jitter causes. The circuit recovers the 125 MHz clock and data and presents the data to the MLT-3 decoder. The PHY unit first decodes the MLT-3 data; afterwards, the descrambler reproduces the 5B symbols originated in the transmitter. The data is decoded at the 4B/5B decoder. After the 4B symbols are obtained, the PHY unit outputs the receive data to the CSMA unit. In 100BASE-TX mode, the PHY unit can detect errors in receive data in a number of ways, including link integrity failures, undetected start of stream delimiters, invalid symbols, or idles in the middle of a frame.

82551IT — Networking Silicon

36 Datasheet

6.1.4 100BASE-TX Link In tegrity Auto-Negotiation The 82551IT Auto-Negotiation function automatically configures the device to the technology, media, and speed to operate with its link partner. Auto-Negotiation is described in IEEE specification 802.3u, clause 28. The PHY unit supports 10BASE-T half duplex, 10BASE-T full duplex, 100BASE-TX half duplex, and 100BASE-TX full duplex. Speed and duplex auto-select are functions of Auto-Negotiation. However, these parameters may be manually configured through the MII management interface (MDI registers). Manual configurations override the auto-select. 6.2 10BASE-T PHY Functions 6.2.1 10BASE-T Transmit Clock Generation The 20 MHz and 10 MHz clocks needed for 10BASE-T are synthesized from the external 25 MHz crystal or oscillator. The PHY unit provides the transmit clock and receive clock to the internal MAC at 2.5 MHz. 6.2.2 10BASE-T Transmit Blocks After the 2.5 MHz clocked data is serialized in a 10 Mbps serial stream, the 20 MHz clock performs Manchester encoding. Since 10BASE-T and 100BASE-TX have different filtration needs, both filters are implemented inside the chip. The PHY unit supports both technologies through one pair of TD pins and by externally sharing the same magnetics. In 10 Mbps mode, the line drivers use a pre-distortion algorithm to improve jitter tolerance. The line drivers reduce their drive level during the second half of “wide” Manchester pulses and maintain a full drive level during narrow pulses and the first half of the wide pulses. This reduces jitter caused by overcharging the line. 6.2.3 10BASE-T Receive Blocks The PHY unit performs Manchester decoding and timing recovery when in 10 Mbps mode. The Manchester-encoded data stream is decoded from the RD pair to separate Receive Clock and Receive Data from the differential signal. This data is transferred to the CSMA unit at 2.5 MHz/ nibble. In 10 Mbps mode, data is expected to be received on the receive differential pair after passing through isolation transformers. The input differential voltage range capability for the Twisted Pair Ethernet (TPE) receiver is greater than 585 mV and less than 3.1 V . The TPE receive buffer distinguishes valid receive data, link test pulses, and idles, according to the requirements of the 10BASE-T standard. In 10 Mbps mode, the PHY unit can detect errors in the receive data, including voltage drops prior to the end-of-frame bit. Collision detection in 10 Mbps mode is initiated by simultaneous transmission and reception. If the PHY unit detects this condition, it asserts a collision indication to the CSMA/CD unit.

Networking Silicon — 82551IT Datasheet 37 6.2.4 10BASE-T Link Integrity and Full Duplex The link integrity in 10 Mbps works with link pulses. The PHY unit senses and differentiates those link pulses from fast link pulses and from 100BASE-TX idles. The link beat pulse is also used to determine if the receive pair polarity is reversed. If it is, the polarity is corrected internally. The PHY unit supports 10 Mbps full duplex by disabling the collision function, the squelch test, and the carrier sense transmit function. This allows the PHY unit to transmit and receive simultaneously, achieving up to 20 Mbps network bandwidth using Auto-Negotiation. Full duplex can only be used in point-to-point connections (no shared media).

6.3 Auto-Negotiation

The PHY unit supports Auto-Negotiation, which is an automatic configuration scheme designed to manage interoperability in multifunctional LAN environments. An Auto-Negotiation capable device can detect and automatically configure its port to take maximum advantage of common modes of operation without user intervention or prior knowledge by either station. Auto- Negotiation is described in IEEE Standard 802.3u, clause 28.

6.3.1 Description

A PHY’s capability is encoded by bursts of link pulses called Fast Link Pulses (FLPs). Connection is established by FLP exchange and handshake during link initialization time. After the link is established by this handshake, the native link pulse scheme resumes. A reset or management re- negotiate command (through the MDI interface) will restart the process. If the PHY unit cannot perform Auto-Negotiation, it will set this bit to 0 and determine the speed using Parallel Detection. The PHY unit supports four technologies: 100BASE-Tx Full and Half Duplex and 10BASE-T Full and Half Duplex. Since only one technology can be used at a time (after every re-negotiate command), a prioritization scheme is used to ensure that the ability of the highest common denominator is chosen.

6.3.2 Parallel Detect and Auto-Negotiation

The PHY unit can automatically determine the speed of the link by using Parallel Detect as an alternative to Auto-Negotiation. Upon a reset, a link status fail, or a negotiate/re-negotiate command, the PHY unit inserts a long delay during which no link pulses are transmitted. This period insures that the PHY unit‘s link partner has gone into a Link Fail state before Auto- Negotiation or Parallel Detection begins. The PHY unit will look for both FLPs and link integrity pulses. The following diagram illustrates this process.

38 Datasheet

6.4 LED Description

The PHY unit supports three LED pins to indicate link status, network activity and network speed.

• Link: This LED is off until a valid link has been detected. After a valid link has been detected, the LED will remain on (active-low).
• Activity: This LED blinks on and off when activity is detected on the wire.
• Speed: This LED will be on if a 100BASE-TX link is detected and off if a 10BASE-T link is detected. If the link fails while in Auto-Negotiation, this LED will keep the last valid link state. If 100BASE-TX link is forced this LED will be on, regardless of the link status. This LED will be off if the 10BASE-T link is forced, regardless of the link status. MDI register 27 in Section 9.3.12, “Register 27: PHY Unit Special Control Register” details the information for LED function mapping and support enhancements. Figure 12 provides possible schematic diagrams for configurations using two and three LEDs.

Figure 11. Auto-Negotiation and Parallel Detect

Figure 12. Two and Three LED Schematic Diagram

82551IT — Networking Silicon

40 Datasheet

Note: This page is intentionally left blank.

7.0 Configuration Registers

that allow it to process receive and transmit data.

7.1 Function 0: LAN (Ethern et) PCI Configuration Space

7.1.1 PCI Vendor ID and Device ID Registers

Figure 13. PCI Configuration Registers

42 Datasheet

7.1.2 PCI Command Register

. The format of this register is shown in the figure below. Figure 14. PCI Command Register Table 13. PCI Command Register Bits 15:10 Reserved These bits are reserved and should be set to 0b.

8 SERR# Enable

configurable and has a default value of 0b.

6 Parity Error Control

the 82551IT, this bit is configurable and has a default value of 0b.

4 Memory Write and

configurable and has a default value of 0b. configurable and has a default value of 0b.

1 Memory Space

configurable and its default value of 0b.

0 I/O Space

7.1.3 PCI Status Register

format of this register is shown in the figure below. Figure 15. PCI Status Register Table 14. PCI Status Register Bits

31 Detected Parity Error

Parity Error bit is 0b. This bit is set until cleared by writing a 1b.

30 Signaled System Error

29 Received Master

bit is 0b. This bit is set until cleared by writing a 1b.

28 Received Target Abort

bit is 0b. This bit is set until cleared by writing a 1b.

27 Signaled Target Abort

This bit indicates whether a transaction was terminated by a target abort. with target abort. In the 82551IT, this bit is always set to 0b. In the 82551IT, these bits are always set to 1b, medium.

44 Datasheet

24 Parity Error Detected

1. The bus agent asserted PERR# itself or observed PERR# asserted.
2. The agent setting the bit acted as t he bus master for the operation in
3. The Parity Error Response bit in th e command register (bit 6) is set.

bit is set until cleared by writing a 1b.

23 Fast Back-to-Back

the 82551IT, this bit is read only and is set to 1b.

20 Capabilities List

only if the power management bit in the EEPROM is set. 19:16 Reserved These bits are reserved and should be set to 0b.

7.1.4 PCI Revision ID Register

7.1.5 PCI Class Code Register

7.1.6 PCI Cache Line Size Register

is read. The figure below shows the format of this register. return a value of 0b on read. The BIOS is expected to write to this register. Therefore, the 82551IT driver should not write to it.

7.1.7 PCI Latency Timer

register defines the amount of time, in PCI clock cycles, that it may own the bus.

7.1.8 PCI Header Type

Figure 16. Cache Line Size Register

000 R W R W 000

46 Datasheet

7.1.9 PCI Base Address Registers

determine the mapping of a particular device. map to I/O space must return 1b in bit 0. reserved and must return 0b on reads, and the other bits are used to map the device into I/O space. The 82551IT contains BARs for the Control/Status Register (CSR), Flash, and Expansion ROM. Figure 17. Base Address Register for Memory Mapping Figure 18. Base Address Register for I/O Mapping

7.1.9.1 CSR Memory Mapped Base Address Register

or I/O, is used to access the 82551IT CSR registers. not prefetchable and is mapped anywhere in the 32-bit memory address space.

7.1.9.2 CSR I/O Mapped Base Address Register

7.1.9.3 Flash Memory Mapped Base Address Register

7.1.9.4 Expansion ROM Base Address Register

7.1.10 Base Address Registry Summary

The preceding description of the Base Address Registers’ functions are listed in Table 15.

7.1.11 PCI Subsystem Vendor ID and Subsystem ID Registers

indicated in the Subsystem Vendor ID field. Table 15. Base Address Register Functions

48 Datasheet

The 82551IT provides support for configurable Subsystem Vendor ID and Subsystem ID fields. the EEPROM. The first of these 16-bit values is used for controlling various 82551IT functions. default values for the Subsystem ID and Subsystem Vendor ID are 0h and 0h, respectively. of the Revision ID field are programmed by bits 10:8 of the first EEPROM word, Ah.

7.1.12 Capability Pointer

within the Configuration Space for the location of the Power Management registers.

7.1.13 Interrupt Line Register

the device’s PCI interrupt request pin (as defined in the Interrupt Pin register) is routed to.

7.1.14 Interrupt Pin Register

INTA# through INTD#, a PCI device is connected to. The 82551IT is connected the INTA# pin. Table 16. ID Fields Programming a. The Revision ID is subject to ch ange according to the silicon stepping. b. If bit 15 equals 1b, the EEPROM is invalid and the default values are used.

7.1.15 Minimum Grant Register

7.1.16 Maximum Latency Register

PCI bus. The default value of this register for the 82551IT is 18h.

7.1.17 Capability ID Register

7.1.18 Next Item Pointer

capability list. Since power management is the last item in the list, this register is set to 0b.

7.1.19 Power Management Capabilities Register

Table 17. Power Management Capability Register D1, D2, and D3hot if it is fed by PCI power. able to use it. DSI is required for the 82551IT after D3-to-D0 reset.

50 Datasheet

7.1.20 Power Management Control/Status Register (PMCSR)

20 0b (PCI) Read Only Reserved PCI. the PCI Power Management Specification, Revision 2.2. Table 18. Power Management Control and Status Register the Data register and Data Scale field. 8 0b Read Clear PME Enable. This bit enables the 82551IT to assert PME#. 7:5 0b Read Only Reserved. These bits are reserved and should be set to 0b. the power consumption dynamically. 3:2 0b Read Only Reserved. These bits are reserved and should be set to 0b. state of the 82551IT and to set the 82551IT into a new power state. The definition of the field values is as follows.

7.1.21 Data Register

the data register is presented below. Table 19. Ethernet Data Register

82551IT — Networking Silicon

52 Datasheet

Note: This page is intentionally left blank.

8.0 Control/Status Registers

8.1 LAN (Ethernet) Control/Status Registers

The 82551IT’s Control/Status Register (CSR) is shown in the figure Figure 19. as the Power Management Driver Register. indications in this register for the CPU to read. register. Interrupts are also acknowledged in this register. memory depending on the current SCB Command word. dump information to main memory, or perform an internal self test. Figure 19. Control/Status Register

54 Datasheet

from the PHY unit (or an external PHY component) through the Management Data Interface. bytes of receive data have been passed into host memory via DMA. control commands to the 82551IT. that a wake-up interrupt has occurred. state and provides the ability to disable the Clockrun functionality. condition that may cause a status change or interrupt.

8.1.1 System Control Block Status Word

82551IT’s Command and Receive units. Table 20. System Control Block Status Word completed executing a command with its interrupt bit set. either an idle or suspended state.

12 RNR

situation, or set suspend bit due to a filled Receive Frame Descriptor.

11 MDI

Interface Control register in the CSR).

10 SWI

9 Reserved This bit is reserved and should be set to 0b. Flow Control Pause. The FCP bit is used as the flow control pause bit.

8.1.2 System Control Block Command Word

Commands for the 82551IT’s Command and Receive units are placed in this register by the CPU.

8.1.3 System Control Block General Pointer

structures depending on the command in the CU Command or RU Command field.

8.1.4 PORT

• Address and Data (bits 32:4)
• PORT Function Selection (bits 3:0) The 82551IT supports four PORT commands: Software Reset, Self-test, Selective Reset, and Dump.

8.1.5 Flash Control Register

The Flash Control Register is a 32-bit field that allows access to an external Flash device. 5:2 RUS Receive Unit Status. The RUS field contains the status of the Receive Unit. 1:0 Reserved These bits are reserved and should be set to 0b. Table 21. System Control Block Command Word generate an interrupt. Writing a 0b to this bit has no effect. Interrupt Mask bits and the SI bit. 23:20 CUC Command Unit Command. This field contains the CU command. 19:16 RUC Receive Unit Command. This field contains the RU command.

56 Datasheet

8.1.6 EEPROM Control Register

8.1.7 Management Data In terface Control Register

8.1.8 Receive Direct Memo ry Access Byte Count

passed into host memory via DMA.

8.1.9 Flow Control Register

• Flow Control Command The Flow Control Command field describes the action of the flow control process (for example, pause, on, or off).
• Flow Control Threshold The Flow Control Threshold field contains the threshold value (in other words, the number of free bytes in the Receive FIFO).

Table 22. MDI Control Register 31:30 These bits are reserved and should be set to 0b. indicate the end of an MDI cycle. set this bit to 0 at the same time the command is written. 25:21 PHY Address. This field of bits contains the PHY address. 20:16 PHY Register Address. This field of bits contains the PHY Register Address. the PHY unit, and software reads the data from this location.

8.2 Statistical Counters

Table 23. Statistical Counters

0 Transmit Good Frames

4 Transmit Maximum Collisions

maximum number of collisions.

8 Transmit Late Collisions

12 Transmit Underrun Errors

updated multiple times for a single frame.

16 Transmit Lost Carrier Sense (CRS)

de-assertion of CRS during the transmission.

20 Transmit Deferred This counter contains the number of frames that were

deferred before transmission due to activity on the link.

24 Transmit Single Collisions This counter contains the number of transmitted frames that

28 Transmit Multiple Collisions This counter contains the number of transmitted frames that

encountered more than one collision.

32 Transmit Total Collisions

late collisions and frames that encountered MAXCOL.

36 Receive Good Frames

40 Receive CRC Errors

and Receive Short Frame Errors counters.

58 Datasheet

44 Receive Alignment Errors

CRC Errors and Receive Short Frame Errors counters.

48 Receive Resource Errors

frame, the Receive Resource Errors counter is not updated.

52 Receive Overrun Errors

frame indicator, they are not counted.

56 Receive Collision Detect (CDT) This counter contains the number of frames that encountered

collisions during frame reception.

60 Receive Short Frame Errors

64 Flow Control Transmit Pause

frames transmitted and Xon (PAUSE(0)) frames transmitted.

68 Flow Control Receive Pause

frames received and Xon (PAUSE(0)) frames received.

72 Flow Control Receive Unsupported

but has an unsupported opcode.

Networking Silicon — 82551IT Datasheet 59 The Statistical Counters are initially set to zero by the 82551IT after reset. They cannot be preset to anything other than zero. The 82551IT increments the counters by internally reading them, incrementing them and writing them back. This process is invisible to the CPU and PCI bus. In addition, the counters adhere to the following rules:

• The counters are wrap-around counters. After reaching FFFFFFFFh the counters wrap around to 0.
• The 82551IT updates the required counters for each frame. It is possible for more than one counter to be updated as multiple errors can occur in a single frame.
• The counters are 32 bits wide and their behavior is fully compatible with the IEEE 802.1 standard. The 82551IT supports all mandatory and recommend statistics functions through the status of the receive header and directly through these Statistical Counters. The CPU can access the counters by issuing a Dump Statistical Counters SCB command. This provides a “snapshot”, in main memory, of the internal 82551IT statistical counters. The 82551IT supports 19 counters. The dump could consist of either 16 or 19 counters, depending on the status of the Extended Statistics Counters configuration bits in the Configuration command.

82551IT — Networking Silicon

60 Datasheet

Note: This page is intentionally left blank.

9.0 PHY Unit Registers

Interface (MDI) within the CSR space.

9.1 MDI Registers 0 - 7

9.1.1 Register 0: Control Register

Table 24. Register 0: Control

15 Reset This bit sets the status and control register of the PHY to

accepts a read or write transaction.

14 Loopback This bit enables loopback of transmit data nibbles from

unit’s receive circuitry is isolated from the network.

13 Speed Selection This bit controls s peed when Auto-Negotiation is disabled

and is valid on read when Auto-Negotiation is disabled.

12 Auto-Negotiation

when Auto-Negotiation is enabled.

62 Datasheet

9.1.2 Register 1: Status Register

9 Restart Auto-

8 Duplex Mode This bit controls the duplex mode when Auto-Negotiation

correspond to the mode which the PHY can operate.

7 Collision Test This bit will force a co llision in response to the assertion

of the transmit enable signal. Table 25. Register 1: Status

6 Management

5 Auto-Negotiation

4 Remote Fault 0 = No remote fault condition detected 0 RO

9.1.3 Register 2: PHY Identifier Register

9.1.4 Register 3: PHY Identifier Register

9.1.5 Register 4: Auto-Negotia tion Advertisement Register

3 Auto-Negotiation

2 Link Status 1 = Valid link has been established

1 Jabber Detect 1 = Jabber condition detected

0 Extended

Table 26. Register 2: PHY Identifier Table 27. Register 3 PHY Identifier Table 28. Register 4: Auto-Negotiation Advertisement

15 Next Page Constant 0 = Transmitting primary capability data

13 Remote Fault 1 = Indicate link partner’s remote fault

to the selector field value. 00001b, IEEE Standard 802.3.

64 Datasheet

9.1.6 Register 5: Auto-Negotiation Link Partner Ability Register

9.1.7 Register 6: Auto-Negot iation Expansion Register

9.2 MDI Registers 8:15

Registers 8 through 15 are reserved for IEEE. Table 29. Auto-Negotiati on Link Partner Ability

15 Next Page This bit reflects the PHY’s link partner’s Auto-

14 Acknowledge This bit is used to indicate that the 82551IT’s PHY unit

Negotiation advertising ability.

13 Remote Fault This bit reflects the PHY’s link partner’s Auto-

4 Parallel Detection

3 Link Partner Next

2 Next Page Able 1 = Local drive is Next Page able

1 Page Received 1 = New Page received

This bit will self-clear on read.

0 Link Partner Auto-

9.3 MDI Register 16:31

9.3.1 Register 16: PHY Unit St atus and Control Register

9.3.2 Register 17: PHY Unit Special Control Register

Table 31. PHY Unit Status and Control

13 Carrier Sense

This bit enables the disconnect function.

12 Transmit Flow

11 Receive De-

receive de-serializer in-sync. 8 Polarity This bit indicates 10BASE-T polarity. 1 Speed This bit indicates the Auto-Negotiation result. 0 Duplex Mode This bit indicates the Auto-Negotiation result. Table 32. Register 17: PHY Unit Special Control

15 Scrambler By-

14 By-pass 4B/5B 1 = 4 bit to 5 bit by-pass

13 Force Transmit H-

66 Datasheet

9.3.3 Register 18: PHY Address Register

9.3.4 Register 19: 100BASE-TX Receive False Carrier Counter

12 Force 34

11 Good Link 1 = 100BASE-TX link good

9 Transmit Carrier

8 Disable Dynamic

7 Auto-Negotiation

6 MDI Tri-State 1 = MDI Tri-state (transmit driver tri-states)

5 Filter By-pass 1 = By-pass filter

4 Auto Polarity

3 Squelch Disable 1 = 10BASE-T squelch test disable

2 Extended

1 Link Integrity

0 Jabber Function

Table 33. Register 18: PHY Address Table 34. Register 19: 100BASE-TX Receive False Carrier Counter

9.3.5 Register 20: 100BASE-TX Receive Disconnect Counter

9.3.6 Register 21: 10 0BASE-TX Receive Error Frame Counter

9.3.7 Register 22: Receive Symbol Error Counter

9.3.8 Register 23: 100 BASE-TX Receive Premature End of Frame Error

9.3.9 Register 24: 10 BASE-T Receive End of Frame Error Counter

Table 35. Register 20: 100BASE-TX Receive Disconnect Counter Table 37. Register 22: Receive Symbol Error Counter Table 38. Register 23: 100BASE-TX Receive Premature End of Frame Error Counter freezes when full and self-clears on read.

68 Datasheet

9.3.10 Register 25: 10BASE-T Tr ansmit Jabber Detect Counter

9.3.11 Register 26: Equalizer Control and Status Register

9.3.12 Register 27: PHY Unit Special Control Register

Table 40. Register 25: 10BASE-T Transmit Jabber Detect Counter Table 42. Register 27: PHY Unit Special Control

9.3.13 Register 28: MDI/ MDI-X Control Register

9.3.14 Register 29: Hardware Integrity Control Register

Table 43. Register 28: MDI/MDI-X Control

7 Auto Switch

overwrites the default value). Manual switch (valid only if bit 7 is set to 0). 1 = Forces the port to be MDI-X (cross-over). Indicates the state of the MDI pair.

4 Auto Switch

Indicates when the correct configuration is achieved. 1 = Resolution algorithm has completed. 0 = Resolution algorithm has not completed. order to switch between one configuration or another.

0000 R/W

Table 44. Register 29: Hardware Integrity Control

15 HWI Enable This bit enables the HW I feature causing the PHY unit

14 Ability Check This bit reports t he results of the HWI ability check

13 Test Execute When this bit is se t, the PHY unit launches test pulses

high or low impedance point.

70 Datasheet

Test Execute bit (bit 13 of this register) is set. defined in granularities of 80 cm (35 inches).

Networking Silicon — 82551IT Datasheet 71 10.0 82551IT Test Port Functionality

10.1 Introduction

The 82551IT’s XOR Tree Test Access Port (TAP) is the access point for test data to and from the device. The port provides the ability to perform basic production level testing.

10.2 Test Function Description

The 82551IT TAP mode supports two tests that can be used in board level design. These tests help verify basic functionality as well as test the integrity of solder connection on the board. The tests are described in the following subsections.

10.2.1 Tristate

The tristate command sets all 82551IT input and output pins into a tristate (high-Z) mode (all internal pull-ups and pull-downs are disabled). This mode is entered by setting the following test pin combination and resetting the device: TEST = 1 TEXEC = 0 TCK = 0 TI = 1

72 Datasheet

10.2.2 XOR Tree

Table 45. XOR Tree Chains

2 IDSEL ACTLED#

3 REQ# SPDLED#

4 AD[23]

5 SERR#

6 AD[22]

7 AD[21]

8 AD[20] ALTRST#

9 AD[19] CLK_RUN#

10 AD[18] AD[31]

11 AD[17] AD[30]

12 C/BE#[2] AD[29]

13 FRAME# AD[28]

14 IRDY# AD[27]

15 TRDY# PME#

16 CLK

17 DEVSEL# AD[26]

18 INTA# AD[25]

19 STOP# C/BE#[3]

20 GNT# AD[24]

21 PERR# FLD0

22 PAR FLD1

23 AD[16] FLD2

24 C/BE#[1] FLD3

25 AD[15] FLD4

26 AD[14] FLD5

27 AD[13] FLD6

28 AD[12] FLD7

29 AD[11] FLA0

30 AD[10] FLA1

31 AD[9] FLA2

32 AD[8] FLA3

33 C/BE#[0] FLA4

34 AD[7] FLA5

35 AD[6] FLA6

36 AD[5] FLA7

37 AD[4] FLA8

37 AD[3] FLA9

39 AD[2] FLA10

40 AD[1] FLA11

41 AD[0] FLA12

42 EECS FLA13/EEDI

43 FLA14/EEDO

44 FLA15/EESK

45 FLA16

46 FLCS#

82551IT — Networking Silicon

74 Datasheet

Note: This page is intentionally left blank.

Networking Silicon — 82551IT Datasheet 75

11.0 Electrical and Timing Specifications

Note: This section contains information on products in sampling and early production phase of development. Do not finalize a design with this information. Revised information will be published when the product becomes available.

11.1 Absolute Maximum Ratings

Maximum ratings are listed below: Stresses above the listed absolute maximum ratings may cause permanent damage to the 82551IT device. Note: The 82551QM/82551ER maximum rating for the Ambient Temperature is 0° C to 85° C.

76 Datasheet

11.2 DC Specifications

1. Preferably, VIO should be 5 V ± 5% in any PCI environment (either 5 V or 3.3 V signaling). If 5 V is not

available in a 3.3 V signaling environment, 3.3 V ± 5% may be used instead.

1. Typical current consumption is in nominal operating conditions (VCC = 3.3 V) and average link activity.

Maximum current consumption is in maximum VCC and maximum link activity. Table 46. General DC Specifications

supports both 5 V and 3.3 V signaling environments.

1. These values are only applicable in 3.3 V signaling environments. Outside of this limit the input buffer must

consume its minimum current.

1. Input leakage currents include high-Z output leakage for all bidirectional buffers with tristate outputs.
2. Signals without pull-up resistors have 3 mA low output current; and signals requiring pull-up resistors, 6 mA.
3. This value is characterized but not tested.
4. This input leakage current is the maximum allowable leakage into the PME# open drain driver when power is
5. This value is characterized but not tested.

Table 47. PCI Interface DC Specifications Table 48. Flash/EEPROM In terface DC Specifications

78 Datasheet

1. Current is measured on all VCC pins (VCC = 3.3 V).
2. Transmitter peak current is attained by dividing the measured maximum differential output peak voltage by
3. Recommended starting value for RBIAS100.

Table 49. LED Voltage/Current Characteristics Table 50. 100BASE-TX Voltage/Current Characteristics

1. Current is measured on all VCC pins (VCC = 3.3 V).
2. Transmitter peak current is attained by dividing the measured maximum differential output peak voltage by
3. Recommended starting value for RBIAS10.

Table 51. 10BASE-T Voltage/Current Characteristics Table 52. Digital I/O Characteristics Table 53. Crystal Input One (X1) Characteristics

80 Datasheet

11.3 AC Specifications

1. Switching Current High specifications are not relevant to PME#, SERR#, or INTA#, which are open drain
2. Maximum current requirements will be met as drivers pull beyond the first step voltage (AC drive point).

current test point is defined for each side of the output driver.

1. Do not test. Guaranteed by design.

Table 54. AC Specifications for PCI Signaling

11.4 Timing Specifications

11.4.1 Clocks Specifications

11.4.1.1 PCI Clock Specifications

measurement points for the PCI Clock signal. Table 55 summarizes the PCI Clock specifications.

1. The 82551IT will work with any PCI clock frequency up to 33 MHz.
2. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate is met across the

minimum peak-to-peak portion of the clock waveform as shown in Figure 20.

11.4.1.2 X1 Specifications

requirements from this signal. Figure 20. PCI Clock Waveform Table 55. PCI Clock Specifications Table 56. X1 Clock Specifications

82 Datasheet

11.4.2 Timing Parameters

11.4.2.1 Measurement and Test Conditions

Figure 21. Output Timing Measurement Conditions Figure 22. Input Timing Measurement Conditions Table 57. Measure and Test Condition Parameters

11.4.2.2 PCI Timings

1. Timing measurement conditions are illustrated in Figure 21.
2. PCI minimum times are specified with loads as detailed in the PCI Bus Specification, Revision 2.1, Section
3. n a PCI environment, REQ# and GNT# are point-to-point signals and have different output valid delay times

and input setup times than bussed signals. All other signals are bussed.

1. Timing measurement conditions are illustrated in Figure 22.
2. RST# is asserted and de-asserted asynchronously with respect to the CLK signal.
3. All PCI interface output drivers are floated when RST# is active.

11.4.2.3 Flash Interface Timings

illustrated in Figure 23 and Figure 24. Table 58. PCI Timing Parameters

84 Datasheet

1. These timing specifications apply to Flash read cycles. The Flash timings referenced are 28F020-150
2. These timing specifications apply to Flash write cycles. The Flash timings referenced are 28F020-150

Table 59. Flash Timing Parameters

86 Datasheet

11.4.2.4 EEPROM Interface Timings

Table 60. EEPROM Timing Parameters Figure 25. EEPROM Timings

11.4.2.5 PHY Timings

Table 61. 10BASE-T Normal Link Pulse (NLP) Timing Parameters Figure 26. 10BASE-T Normal Link Pulse (NLP) Timings Table 62. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters Figure 27. Auto-Negotiation Fast Link Pulse (FLP) Timings

88 Datasheet

Table 63. 100Base-TX Transmitter AC Specification

12.0 Package and Pinout Information

12.1 Package Information

Figure 28. More information on Intel® device packaging is available in the Intel Packaging Note: No changes to existing soldering processes are needed for the 0.32 mm substrate change. Figure 28. Dimension Diagram for the 196-pin BGA Note: All dimensions are in millimeters.

90 Datasheet

Figure 29. 196 PBGA Package Pad Detail

12.2 Pinout Information

12.2.1 Pin Assignments

Table 62. Pin Assignments

92 Datasheet

12.2.2 Ball Grid Array Diagram

Figure 30. Ball Grid Array Diagram

100 TDP TEXEC RDP FLD1 VCC FLD5 FLA0 FLA9FLA10FLA7FLA4VCCTEST

10 TDN TCK RDN FLD0 VSSPL FLD4 FLD7 NCFLA8FLA6FLA3FLA2NC

82551IT — Networking Silicon

94 Datasheet

13.0 Reference Schematics

This section shows a 10/100 Mbps design using the 82551IT Fast Ethernet PCI Controller.

Figure 31. Reference Schematic Layout (Sheet 1 of 2) each time activity is detected. are used on the bottom side of the board, then place decoupling under the 82551IT. should not have any direct connection. Keep trace length from magnetics to RJ-45 connector under one inch. close to the 82551 as possible. This capacitor is normally not installed; however a placement can be provided. must be taken in selecting the values used.

10 TX+

75 Ohms

11 TX- TD-

96 Datasheet

Figure 32. Reference Schematic Layout (Sheet 2 of 2) other than hard strapping the pins. following the PCI bus re-activation. acheived if this signal is connected to +5V in PCI bus systems regardless of bus voltage.