82541ER INTEL | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1.0 Introduction
- 1.1 Document Scope
- 1.2 Reference Documents
- 1.3 Product Codes
- 1.4 Block Diagram
- 2.0 Product Code
- 3.0 Signal Descriptions
- 3.1 Signal Type Definitions
- 3.2 PCI Bus Interface Signals (56)
- 3.2.1 PCI Address, Data and Control Signals (44)
- 3.2.2 Arbitration Signals (2)
- 3.2.3 Interrupt Signal (1)
- 3.2.4 System Signals (3)
- 3.2.5 Error Reporting Signals (2)
- 3.2.6 Power Management Signals (2)
- 3.3 EEPROM and Serial FLASH Interface Signals (9)
- 3.4 Miscellaneous Signals
- 3.4.1 LED Signals (4)
- 3.4.2 Other Signals (4)
- 3.5 PHY Signals
- 3.5.1 Crystal Signals (2)
- 3.5.2 Analog Signals (10)
- 3.6 Test Interface Signals (6)
- 3.7 Power Supply Connections
- 3.7.1 Digital and Analog Supplies
- 3.7.2 Grounds, Reserved Pins and No Connects
- 3.7.3 Voltage Regulation Control Signals (2)
- 4.0 Voltage, Temperature, and Timing Specifications
- 4.1 Absolute Maximum Ratings
- 4.2 Targeted Recommended Operating Conditions
- 4.2.1 General Operating Conditions
- 4.2.2 Voltage Ramp and Sequencing Recommendations
- 4.3 DC Specifications
- 4.4 AC Characteristics
- 4.5 Timing Specifications
- 4.5.1 PCI Bus Interface
- 4.5.1.1 PCI Bus Interface Clock
- 4.5.1.2 PCI/PCI-X Bus Interface Timing
- 4.5.2 Link Interface Timing
- 4.5.3 EEPROM Interface
- 5.0 Package and Pinout Informatio n
- 5.1 Package Information
- 5.2 Thermal Specifications
82541ER Gigabit Ethernet Controller Networking Silicon Datasheet Product Features ■ PCI Bus — PCI revision 2.3, 32-bit, 33/66 MHz — Algorithms that optimally use advanced PCI, MWI, MRM, and MRL commands — 3.3 V (5 V tolerant PCI signaling) ■ MAC Specific — Low-latency transmit and receive queues — IEEE 802.3x-compliant flow-control support with software-controllable thresholds — Caches up to 64 packet descriptors in a single burst — Programmable host memory receive buffers (256 B to 16 KB) and cache line size (16 B to 256 B) — Wide, optimized internal data path architecture — 64 KB configurable Transmit and Receive FIFO buffers ■ PHY Specific — Integrated for 10/100/1000 Mb/s operation — IEEE 802.3ab Auto-Negotiation support — IEEE 802.3ab PHY compliance and compatibility — State-of-the-art DSP architecture implements digital adaptive equalization, echo cancellation, and cross-talk cancellation — Automatic polarity detection — Automatic detection of cable lengths and MDI vs. MDI-X cable at all speeds ■ Host Off-Loading — Transmit and receive IP, TCP, and UDP checksum off-loading capabilities — Transmit TCP segmentation — Advanced packed filtering — Jumbo frame support up to 16 KB — Intelligent Interrupt generation (multiple packets per interrupt) ■ Manageabiltiy — Network Device Class Power Management Specification 1.1 — Compliance with PCI Power Management 1.1 and ACPI 2.0 — SNMP and RMON statistic counters — D0 and D3 power states ■ Additional Device — Four programmable LED outputs — On-chip power control circuitry — BIOS LAN Disable pin — JTAG (IEEE 1149.1) Test Access Port built in silicon ■ Lead-freea 196-pin Ball Grid Array (BGA). Devices that are lead-free are marked with a circled “e1” and have the product code: LUxxxxxx. a. This device is lead-free. That is, lead has not been intentionally added, but lead may still exist as an impurity at <1000 ppm. The Material Declaration Data Sheet, which includes lead impurity levels and the concentration of other Restriction on Hazardous Substances (RoHS)-banned materials, is available at: ftp://download.intel.com/design/packtech/material_content_IC_Package.pdf#pagemode=bookmarks In addition, this device has been tested and conforms to th e same parametric specifications as previous versions of the device. For more information regarding lead-free products from Intel Corporation, contact your Intel Field Sales represen- tative Revision 4.1 September 2006
Revision History
Aug 2003 2.0 Non-classified release. Mar 2004 3.0 Updated Section 4, “Voltage, Temperature, and Timing Specifications,” for the C-0 stepping. Oct 2004 3.1 Corrected EEMODE signal description. Updated signal names to match design guide and reference schematics. Nov 2004 3.2 Added lead free information. Added information about migrating from a 2-layer 0.36 mm wide-trace substrate to a 2-layer 0.32 mm wide-trace substrate. Refer to the section on Package and Pinout Information. Added statement that no changes to existing soldering processes are needed for the 2-layer 0.32 mm wide-trace substrate change in the section describing “Package Information”. Corrected pinout discrepancies between sections “Signal Descriptions” and “Package and Pinout Information”. Jan 2005 3.3 Added new maximum values for DC supply voltages on 1.2 V and 1.8 V pins. See Table 2, Recommended Operating Conditions and Table 6, DC Characteristics. Feb 2005 3.4 Updated Visual Pin Assignment diagram for pinouts F9, F10, E14, F14, and H14. Apr 2005 3.5 Removed all references to CLK_RUN# signal. Corrected the FLSH_SO/LAN_DISABLE signal definition. If Flash functionality is not used then an exter nal pull-down resistor is required. July 2005 3.6 Added pin C8 description to Table 29 and Table 31. Aug 2005 3.7 Corrected 25 MHz Clock Input Requirements in Table 13. June 2006 3.8 Corrected the FLSH_SO/LAN_DISABLE signal definition. If Flash functionality is not used then an exte rnal pull-up resistor is required. June 2006 3.9 Updated Table 13 “25 MHz Clock Input Requirements”. Aug 2006 4.0 Updated Table 40 descriptions for pins A10, B10, and C9. Updated pinout descriptions from Tables 25 - 42 to match Figure 13. Sept 2006 4.1 Removed note “b” from Table 2 and note “a” from Tables 3 and 4. Moved the note following Table 5 before Table 3 “3.3V Supply Voltage Ramp”. Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 82541ER Gigabit Ethernet Controller may contain design defects or errors known as errata which may cause the product to dev iate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtaine d by calling 1-800- 548-4725 or by visiting Intel's website at http://www.intel.com. Intel® is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries . Copyright © Intel Corporation, 2006 *Third-party brands and names are the property of their respective owners.
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82541ER Gigabit Ethernet Controller Datasheet 1
1.0 Introduction
The Intel® 82541ER Gigabit Ethernet is a single, compact component with an integrated Gigabit Ethernet Media Access Control (MAC) and physical layer (PHY) functions. For embedded communication and network devices such as web kiosks, and Point-of-Sale terminal designs with critical space constraints, the Intel 82541ER allows for a Gigabit Ethernet implementation in a very small area that is footprint compatible with current generation 10/100 Mbps Fast Ethernet designs. The Intel® 82541ER integrates fourth generation gigabit MAC design with fully integrated, physical layer circuitry to provide a standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE_TX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab). The controller is capable of transmitting and receiving data at rates of 1000 Mbps, 100 Mbps, or 10 Mbps. In addition to managing MAC and PHY layer functions, the controller provides a 32-bit wide direct Peripheral Component Interconnect (PCI) 2.3 compliant interface capable of operating at 33 or 66 MHz. The 82541ER Architecture is designed for high performance and low memory latency. Wide internal data paths eliminate performance bottlenecks by efficiently handling large address and data words. The 82541ER controller includes advanced interrupt handling features to limit PCI bus traffic and a PCI interface that maximizes efficient bus usage. The 82541ER uses efficient ring buffer descriptor data structures, with up to 64 packet descriptors cached on chip. A large 64 KByte on-chip packet buffer maintains superior performance as available PCI bandwidth changes. In addition, using hardware acceleration, the controller offloads tasks from the host controller, such as TCP/UDP/IP checksum calculations and TCP segmentation. The 82541ER is packaged in a 15 mm X 15 mm 196-ball grid array and is pin compatible with the 82559ER/82551ER 10/100 Mbps Fast Ethernet Multifunction PCI/CardBus Controller, 82562EZ/ 82562EX Platform LAN Connect devices, the 82540EM Gigabit Ethernet Controller and the 82540EP Gigabit Ethernet Controller.
1.1 Document Scope
This document contains datasheet specifications for the 82541ER Gigabit Ethernet Controller, including signal descriptions, DC and AC parameters, packaging data, and pinout information.
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1.2 Reference Documents
This document assumes that the designer is acquainted with high-speed design and board layout techniques. The following documents provide additional information: 825462EZ(EX)/82551ER(IT) & 82541ER Combined Footprint LOM Design Guide. Intel Corporation. 82547GI(EI)/82541(PI/GIEI) & 82541ER EEPROM Map and Programming Information Guide. Intel Corporation. PCI Local Bus Specification, Revision 2.3. PCI Special Interest Group. PCI Bus Power Management Interface Specification, Revision 1.1. PCI Special Interest Group. IEEE Standard 802.3, 2003 Edition. Incorporates various IEEE standards previously published separately. Institute of Electrical and Electronics Engineers (IEEE). Intel Ethernet Controllers Timing Device Selection Guide. Intel Corporation. PCI Mobile Design Guide, Revision 1.1. PCI Special Interest Group. Software driver developers should contact their local Intel representatives for programming information.
1.3 Product Codes
The product ordering codes are: GD82541ER LU82541ER
1.4 Block Diagram
Figure 1. 82541ER Block Diagram
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2.0 Product Code
The product code for the 82541ER Gigabit Ethernet Controller is: GD82541ER.
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3.0 Signal Descriptions
3.1 Signal Type Definitions
The signals of the 82541ER controller are electrically defined as follows:
3.2 PCI Bus Interface Signals (56)
When the Reset signal (RST#) is asserted, the 82541ER will not drive any PCI output or bi- directional pins. Name Definition I Input. Standard input only digital signal. O Output. Standard output only digital signal. TS Tri-state. Bi-directional tri-state digital input/output signal. STS Sustained Tri-state. An active low tri-state signal owned and driven by only one agent at a time. The agent that drives an STS pin low must drive it high for at least one clock before letting it float. A new agent cannot start driving an STS signal any sooner than one clock after the previous owner tri-states it. A pullup is required to sustain the inactive state until another agent drives it, and must be provided by the central resource. OD Open Drain. Wired-OR with other agents. The signaling agent asserts the OD signal, but the signal is returned to the inactive state by a weak pull-up resistor. The pull-up resistor may require two or three clock periods to fully restore the signal to the de-asserted state. A Analog. PHY analog data signal. P Power. Power connection, voltage reference, or other reference connection.
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3.2.1 PCI Address, Data and Control Signals (44)
Symbol Type Name and Function AD[31:0] TS Address and Data. Address and data signals are multiplexed on the same PCI pins. A bus transaction includes an address phase followed by one or more data phases. The address phase is the clock cycle when the Frame signal (FRAME#) is asserted low. During the address phase AD[31:0] contain a physical address (32 bits). For I/O, this is a byte address, and for configuration and memory, a DWORD address. The 82541ER device uses little endian byte ordering. During data phases, AD[7:0] contain the least significant byte (LSB) and AD[31:24] contain the most significant byte (MSB). C/BE#[3:0] TS Bus Command and Byte Enables. Bus command and byte enable signals are multiplexed on the same PCI pins. During the address phase of a transaction, C/ BE#[3:0] define the bus command. In the data phase, C/BE#[3:0] are used as byte enables. The byte enables are valid for the entire data phase and determine which byte lanes contain meaningful data. C/BE#[0] applies to byte 0 (LSB) and C/BE#[3] applies to byte 3 (MSB). PAR TS Parity. The Parity signal is issued to implement even parity across AD[31:0] and C/ BE#[3:0]. PAR is stable and valid one clock after the address phase. During data phases, PAR is stable and valid one clock after either IRDY# is asserted on a write transaction or TRDY# is asserted after a read transaction. Once PAR is valid, it remains valid until one clock after the completion of the current data phase. When the 82541ER controller is a bus mast er, it drives PAR for address and write data phases, and as a slave device, drives PAR for read data phases. FRAME# STS Cycle Frame. The Frame signal is driven by the 82541ER device to indicate the beginning and length of a bus transaction. While FRAME# is asserted, data transfers continue. FRAME# is de-asserted when the transaction is in the final data phas IRDY# STS Initiator Ready. Initiator Ready indicates the ability of the 82541ER controller (as a bus master device) to complete the current data phase of the transaction. IRDY# is used in conjunction with the Target Ready signal (TRDY#). The data phase is completed on any clock when both IRDY# and TRDY# are asserted. During the write cycle, IRDY# indicates that valid data is present on AD[31:0]. For a read cycle, it indicates the master is ready to accept data. Wait cycles are inserted until both IRDY# and TRDY# are asserted toget her. The 82541ER controller drives IRDY# when acting as a master and samples it when acting as a slave. TRDY# STS Target Ready. The Target Ready signal indicates the ability of the 82541ER controller (as a selected device) to complete the curr ent data phase of the transaction. TRDY# is used in conjunction with the Initiator Ready signal (IRDY#). A data phase is completed on any clock when both TRDY# and IRDY# are sampled asserted. During a read cycle, TRDY# indicates that valid data is present on AD[31:0]. For a write cycle, it indicates the target is ready to accept data. Wait cycles are inserted until both IRDY# and TRDY# are asserted together. The 82541ER device drives TRDY# when acting as a slave and samples it when acting as a master. STOP# STS Stop. The Stop signal indicates the current target is requesting the master to stop the current transaction. As a slave, the 82541E R controller drives STOP# to request the bus master to stop the transaction. As a master, the 82541ER controller receives STOP# from the slave to stop the current transaction.
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3.2.2 Arbitration Signals (2)
3.2.3 Interrupt Signal (1)
3.2.4 System Signals (3)
IDSEL# I Initialization Device Select. The Initialization Device Select signal is used by the 82541ER as a chip select signal during configuration read and write transactions. DEVSEL# STS Device Select. When the Device Select signal is actively driven by the 82541ER, it signals notifies the bus master that it has decoded its address as the target of the current access. As an input, DEVSEL# indicates whether any device on the bus has been selected. VIO P VIO. The VIO signal is a voltage reference for the PCI interface (3.3 V or 5 V PCI signaling environment). It is used as the clamping voltage. Note: VIO should be connected to 3.3V Aux or 5V Aux in order to be compatible with the pull-up clamps specification. Symbol Type Name and Function REQ# TS Request Bus. The Request Bus signal is used to r equest control of the bus from the arbiter. This signal is point-to-point. GNT# I Grant Bus. The Grant Bus signal notifies the 82541ER that bus access has been granted. This is a point-to-point signal. Symbol Type Name and Function INTA# TS Interrupt A. Interrupt A is used to request an inte rrupt of the 82541ER. It is an active low, level-triggered interrupt signal. Symbol Type Name and Function CLK I PCI Clock. The PCI Clock signal provides timing for all transactions on the PCI bus and is an input to the 82541ER device. All other PCI signals, except the Interrupt A (INTA#) and PCI Reset signal (RST#), are sampled on the rising edge of CLK. All other timing parameters are defined with respect to this edge. M66EN I 66 MHz Enable. M66EN indicates whether the system bus is enabled for 66MHz RST# I PCI Reset. When the PCI Reset signal is asserted, all PCI output signals are floated and all input signals are ignored. Most of the internal state of the 82541ER is reset on the de-assertion (rising edge) of RST#. Symbol Type Name and Function
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3.2.5 Error Reporting Signals (2)
3.2.6 Power Management Signals (2)
3.3 EEPROM and Serial FLASH Interface Signals (9)
Symbol Type Name and Function SERR# OD System Error. The System Error signal is used by the 82541ER controller to report address parity errors. SERR# is open drain and is actively driven for a single PCI clock when reporting the error. PERR# STS Parity Error. The Parity Error signal is used by the 82541ER controller to report data parity errors during all PCI transactions except by a Special Cycle. PERR# is sustained tri-state and must be driven active by the 82541ER controller two data clocks after a data parity error is detected. The minimum duration of PERR# is one clock for each data phase a data parity error is present.Symbol Type Name and Function LAN_PWR GOOD I Power Good (Power-on Reset). The Power Good signal is used to indicate that stable power is available for the 82541ER. When the signal is low, the 82541ER holds itself in reset state and floats all PCI signals. AUX_PWR I Auxiliary Power. If the Auxiliary Power signal is high, then auxiliary power is available and the 82541ER device should s upport the D3cold power state. Symbol Type Name and Function EEMODE I EEPROM Mode. The EEPROM Mode pin is used to select the interface and source of the EEPROM used to initialize the device. For a MIcrowire* EEPROM on the standard EEPROM pins, tie this pin to ground with a 100 Ω pull-down resistor. For a Serial Peripheral Interface (SPI*) EEPROM, leave this pin disconnected. EEDI O EEPROM Data Input. The EEPROM Data Input pin is used for output to the memory device. EEDO I EEPROM Data Output. The EEPROM Data Output pin is used for input from the memory device. The EEDO includes an internal pull-up resistor. Note: Voltage for EEDO must be less than 0.7 V. EECS O EEPROM Chip Select. The EEPROM Chip Select signal is used to enable the device. EESK O EEPROM Serial Clock. The EEPROM Shift Clock provides the clock rate for the EEPROM interface, which is approximately 1 MHz for Microwire* and 2 MHZ for SPI. FLSH_CE# O Flash Chip Enable Output. Used to enable FLASH device. FLSH_SCK O Flash Serial Clock Output. The clock rate of the serial FLASH interface is approximately 1 MHz. FLSH_SI O Flash Serial Data Input. This pin is an output to the memory device. FLSH_SO/ LAN_DISABLE# I Flash Serial Data Output / LAN Disable. This pin is an input from the Flash memory. Alternatively, the pin can be used to disable the LAN port from a system General Purpose Input Output (GPIO) port. It has an internal pullup device. If the 82541ER is not using Flash functionality, the pin should be connected to an external pull-up resistor. If this pin is used as LAN_DISABLE#, the device goes to low power state and the LAN port is disabled when this pin is sampled low on rising edge of PCI reset.
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3.4 Miscellaneous Signals
3.4.1 LED Signals (4)
3.4.2 Other Signals (4)
3.5 PHY Signals
3.5.1 Crystal Signals (2)
Symbol Type Name and Function LINK_LED# O LED0 / LINK Up. Programmable LED indication. Defaults to indicate link connectivity. ACTIVITY# O LED1 / Activity. Programmable LED indication. Defaults to flash to indicate transmit or receive activity. LINK100# O LED2 / LINK 100. Programmable LED indication. Defaults to indicate link at 100 Mbps. LINK1000# O LED3 / LINK 1000. Programmable LED indication. Defaults to indicate link at 1000 Mbps. Symbol Type Name and Function SDP[3:0] TS Software Defined Pin. The Software Defined Pins are reserved and programmable with respect to input and output capability. These default to input signals upon power-up but may be configured differently by the EEPROM. The upper four bits may be mapped to the General Purpose Interrupt bits if they are configured as input signals. Symbol Type Name and Function XTAL1 I Crystal One. The Crystal One pin is a 25 MHz +/- 50 ppm input signal. It should be connected to a crystal, and the other end of the crystal should connect to XTAL2. XTAL2 O Crystal Two. Crystal Two is the output of an internal oscillator circuit used to drive a crystal into oscillation.
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3.5.2 Analog Signals (10)
3.6 Test Interface Signals (6)
Symbol Type Name and Function MDI[0]+/- A Media Dependent Interface [0]. 1000BASE-T: In MDI configuration, MDI[0]+/- corresponds to BI_DA+/-, and in MDI-X configuration, MDI[0]+/- corresponds to BI_DB+/-. 100BASE_TX: In MDI configuration, MDI[0]+/- is used for the transmit pair, and in MDI-X configuration, MDI[0]+/- is used for the receive pair. 10BASE-T: In MDI configuration, MDI[0]+/- is used for the transmit pair, and in MDI-X configuration, MDI[0]+/- is used for the receive pair. MDI[1]+/- A Media Dependent Interface [1]. 1000BASE-T : In MDI configuration, MDI[1]+/- corresponds to BI_DB+/-, and in MDI-X configuration, MDI[1]+/- corresponds to BI_DA+/-. 100BASE_TX: In MDI configuration, MDI[1]+/- is used for the receive pair, and in MDI-X configuration, MDI[1]+/- is used for the transit pair. 10BASE-T: In MDI configuration, MDI[1]+/- is used for the receive pair, and in MDI-X configuration, MDI[1]+/- is used for the transit pair. MDI[2]+/- A Media Dependent Interface [2]. 1000BASE-T : In MDI configuration, MDI[2]+/- corresponds to BI_DC+/-, and in MDI- X configuration, MDI[2]+/- corresponds to BI_DD+/-. 100BASE_TX: Unused. 10BASE-T: Unused. MDI[3]+/- A Media Dependent Interface [3]. 1000BASE-T : In MDI configuration, MDI[3]+/- corresponds to BI_DC+/-, and in MDI- X configuration, MDI[3]+/- corresponds to BI_DD+/-. 100BASE_TX: Unused. 10BASE-T: Unused. IEEE_TEST- A IEEE test pin output minus. Used to gain access to the internal PHY clock for 1000BASE-T IEEE physical layer conformance testing. IEEE_TEST+ A Analog test pin output plus. Used to gain access to the internal PHY clock for 1000BASE-T IEEE physical layer conformance testing. Symbol Type Name and Function TEST I Test Enable. Enables test mode. Normal mode: connect to VSS. JTAG_TCK I JTAG Test Access Port Clock. JTAG_TDI I JTAG Test Access Port Data In. JTAG_TDO O JTAG Test Access Port Data Out. JTAG_TMS I JTAG Test Access Port Mode Select. JTAG_TRST# I JTAG Test Access Port Reset. This is an active low reset signal for JTAG. To disable the JTAG interface, this signal should be terminated using a 100 Ω pull-down resistor to ground. It must not be left unconnected.
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3.7 Power Supply Connections
3.7.1 Digital and Analog Supplies
3.7.2 Grounds, Reserved Pins and No Connects
3.7.3 Voltage Regulation Control Signals (2)
Symbol Type Name and Function 3.3V P 3.3 V I/O Power Supply. Analog_1.8V P 1.8V Analog Power Supply. CLKR_1.8V P 1.8V analog power supply for the clock recovery. XTAL_1.8V P Input power for the XTAL regulator. 1.2V P 1.2V Power supply. This is for analog and digital circuits. Analog_1.2V P 1.2V Analog Power Supply. PLL_1.2V P Input power for the ICS regulator. Symbol Type Name and Function VSS P Ground. AVSS P Shared analog Ground. RSVD_VSS P Reserved Ground. This pin is reserved by Intel and may have factory test functions. For normal operation, connect to ground. RSVD_NC P Reserved No connect. This pin is reserved by Intel and may have factory test functions. For normal operation, do not connect any circuit to these pins. Do not connect pull-up or pull-down resistors. NC P No Connect. This pin is not connected internally. RSVD_VCC P Reserved VCC. This pin is reserved by Intel and may have factory test functions. For normal operation, connect to VCC through a 1K pull-up resistor Symbol Type Name and Function CTRL12 A 1.2V Control. LDO voltage regulator output to drive external PNP pass transistor. If 1.2V is already present in the system, leave output unconnected. To achieve optimal D3 power consumption, leave the output unc onnected and use a high-efficiency external switching regulator. CTRL18 A 1.8V Control. LDO voltage regulator output to drive external PNP pass transistor. If 1.8V is already present in the system, leave output unconnected. To achieve optimal D3 power consumption, leave the output unc onnected and use a high-efficiency external switching regulator.
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4.0 Voltage, Temperature, and Timing Specifications
4.1 Absolute Maximum Ratings
4.2 Targeted Recommended Operating Conditions
4.2.1 General Operating Conditions
Table 1. Absolute Maximum Ratings a exceeded. These values should not be used as the limits for normal device operations. state for an indefinite duration. d. The maximum value must also be less than VIO. Table 2. Recommended Operating Conditions (Sheet 1 of 2) a
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4.2.2 Voltage Ramp and Sequencing Recommendations
its final value, all voltage rails (1.8V and 1.2V) have 150 ms to reach their final operating values. limits, might result in permanent damage. Table 3. 3.3V Supply Voltage Ramp Table 4. 1.8V Supply Voltage Ramp Table 2. Recommended Operating Conditions (Sheet 2 of 2) a
a. Operating with an internal regulator (PNP) supports a wider tolerance output voltage due to process tracking. b. Tantalum capacitors must not be used. Table 5. 1.2V Supply Voltage Ramp a. Operating with an internal regulator (PNP) supports a wider tolerance output voltage due to process tracking. b. Tantalum capacitors must not be used.
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4.3 DC Specifications
Table 6. DC Characteristics Table 7. Power Specifications - D0a and PCI 33 MHz system interface. traffic at full duplex, and PCI 33 MHz system interface. Table 8. Power Specifications - D3cold
going into the D3 state to conserve power. and PCI 33 MHz system interface. traffic at full duplex, and PCI 33 MHz system interface. Table 9. Power Specifications D(r) Uninitialized) Table 10. Power Specifications - Complete Subsystem
10 Mbps
1000 Mbps
3.3 V 4 5 7 1 0 1 21 53 34 5
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1.8 V 1 7 2 30 35 135 140 410
1.2 V 7 1 03 0 3 58 08 5 3 8 0
plex, and PCI 33 MHz system interface. Table 11. I/O Characteristics (Sheet 1 of 2)
4.4 AC Characteristics
Table 12. AC Characteristics: 3.3 V Interfacing Table 13. 25 MHz Clock Input Requirements 105 clock edges, filtered by HPF with cut off frequency 5000 Hz). Table 11. I/O Characteristics (Sheet 2 of 2) (Continued)
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Table 14. Reference Crystal Specification Requirements Table 15. Link Interface Clock Requirements a. GTX_CLK is used externally for test purposes only. Table 16. EEPROM Interface Clock Requirements Table 17. AC Test Loads for General Output Pins
Figure 2. AC Test Loads for General Output Pins
4.5 Timing Specifications
4.5.1 PCI Bus Interface
4.5.1.1 PCI Bus Interface Clock
Figure 3. PCI Clock Timing Table 18. PCI Bus Interface Clock Parameters minimum peak-to-peak portion of the clock waveform as shown. noise cannot render a monotonic signal to appear bouncing in the switching range.
0.6 Vcc
0.2 Vcc
0.5 Vcc
0.4 Vcc
0.3 Vcc
0.4 Vcc p-to-p
3.3 V Clock
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4.5.1.2 PCI/PCI-X Bus Interface Timing
- Output timing measurements are as shown.
- REQ# and GNT# signals are point-to-point and have different output valid delay and input setup times than
bussed signals. GNT# has a setup of 10 ns; REQ# has a setup of 12 ns. All other signals are bussed.
- Input timing measurements are as shown.
Figure 4. PCI Bus Interface Output Timing Measurement Table 19. PCI Bus Interface Timing Parameters
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Figure 7. TVAL (max) Falling Edge Test Load Figure 8. TVAL (min) Test Load Figure 9. TVAL Test Load (PCI 5 V Signaling Environment) NOTE: Note: 50 pF load used for maximum times. Minimum times are specified with 0 pF load.
4.5.2 Link Interface Timing
Figure 10. Link Interface Rise/Fall Timing
4.5.3 EEPROM Interface
Table 21. Rise and Fall Times Table 22. Link Interface Clock Requirements a. The EEPROM clock is derived from a 125 MHz internal clock. Table 23. Link Interface Clock Requirements a. The EE_DO setup and hold time is a function of the PCI bus clock cycle time but is referenced to O_EE_SK.
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5.0 Package and Pinout Information
indicated beginning with Table 25.
5.1 Package Information
package dimensions are detailed below. The nominal ball pitch is 1 mm. Figure 11. 82541ER Mechanical Specifications Note: No changes to existing soldering processes are needed for the 0.32 mm substrate change.
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Figure 12. 196 PBGA Package Pad Detail
5.2 Thermal Specifications
thermal resistances are shown in Table 24. be used to assure that the 82541ER device is operating under recommended conditions. Table 24. Thermal Characteristics
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5.3 Pinout Information
Table 25. PCI Address, Data and Control Signals Table 26. PCI Arbitration Signals Table 27. Interrupt Signals Table 28. System Signals
Table 29. Error Reporting Signals Table 30. Power Management Signals Table 31. Serial EEPROM Interface Signals Table 32. Serial FLASH Interface Signals Table 33. LED Signals Table 34. Other Signals
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Table 35. IEEE Test Signals Table 36. PHY Signals Table 37. Test Interface Signals Table 38. Digital Power Signals
Table 39. Analog Power Signals Table 40. Grounds and No Connect Signals Table 41. Voltage Regulation Control Signals
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Table 42. Signal Names in Pin Order (Sheet 1 of 6)
Table 42. Signal Names in Pin Order (Sheet 2 of 6) (Continued)
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Table 42. Signal Names in Pin Order (Sheet 3 of 6) (Continued)
Table 42. Signal Names in Pin Order (Sheet 4 of 6) (Continued)
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Table 42. Signal Names in Pin Order (Sheet 5 of 6) (Continued)
Table 42. Signal Names in Pin Order (Sheet 6 of 6) (Continued)
42 Datasheet
5.4 Visual Pin Assignments
Figure 13. Visual Pin Assignments Pins A10, B-10, and C9 - Use 1K ohm resistors.