82540EM INTEL | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1.0 Introduction
- 1.1 Document Scope
- 1.2 Reference Documents
- 1.3 Block Diagram
- 2.0 Product Code
- 3.0 Signal Descriptions
- 3.1 Signal Type Definitions
- 3.2 PCI Bus Interface
- 3.2.1 PCI Address, Data and Control Signals
- 3.2.2 Arbitration Signals
- 3.2.3 Interrupt Signal
- 3.2.4 System Signals
- 3.2.5 Error Reporting Signals
- 3.2.6 Power Management Signals
- 3.2.7 Impedance Compensation Signals
- 3.2.8 SMB Signals
- 3.3 EEPROM and Flash Interface Signals
- 3.4 Miscellaneous Signals
- 3.4.1 LED Signals
- 3.4.2 Other Signals
- 3.5 PHY Signals
- 3.5.1 Crystal Signals
- 3.5.2 Analog Signals
- 3.6 Test Interface Signals
- 3.7 Power Supply Connections
- 3.7.1 Digital Supplies
- 3.7.2 Analog Supplies
- 3.7.3 Ground and No Connects
- 3.7.4 Control Signals
- 4.0 Voltage, Temperature, and Timing Specifications
- 4.1 Absolute Maximum Ratings
- 4.2 Recommended Operating Conditions
- 4.3 DC Specifications
- 4.4 AC Characteristics
- 4.5 Timing Specifications
- 4.5.1 PCI Bus Interface
- 4.5.2 Link Interface Timing
- 4.5.3 EEPROM Interface
82540EM Gigabit Ethernet Controller Networking Silicon Datasheet Product Features ■ PCI Bus — PCI Revision 2.3 support for 32-bit wide interface at 33 MHz and 66 MHz — Algorithms that optimally use advanced PCI, MWI, MRM, and MRL commands ■ MAC Specific — Low-latency transmit and receive queues — IEEE 802.3x-compliant flow-control support with software-controllable thresholds — Caches up to 64 packet descriptors in a single burst — Programmable host memory receive buffers (256 B to 16 KB) and cache line size (16 B to 256 B) — Wide, optimized internal data path architecture — 64 KB configurable Transmit and Receive FIFO buffers ■ PHY Specific — Integrated for 10/100/1000 Mb/s operation full and half duplex operation — IEEE 802.3ab Auto-Negotiation support — IEEE 802.3ab PHY compliance and compatibility. — State-of-the-art DSP architecture implements digital adaptive equalization, echo cancellation, and cross-talk cancellation — Automatic detection of cable lengths and MDI vs. MDI-X cable at all speeds ■ Host Off-Loading — Transmit and receive IP, TCP, and UDP checksum off-loading capabilities — Transmit TCP segmentation — Advanced packed filtering — Jumbo frame support up to 16 KB — IEEE 802.1q VLAN support with VLAN tag insertion, stripping and packet filtering for up to 4096 VLAN tags — Descriptor ring management hardware for transmit and receive — Interrupt coalescing (multiple packets per interrupt) — Jumbo frame support ■ Manageability — Manageability features: SMB port, ASF 1.0, ACPI, Wake on LAN, and PXE — On-board SMB port — Compliance with PCI Power Management 1.1 and ACPI 2.0 register set compliant — SNMP and RMON statistic counters — SDG 3.0, WfM 2.0, and PC2001 compliance ■ Additional Device — Four activity and link indication outputs that directly drive LEDs — JTAG (IEEE 1149.1) Test Access Port built in silicon — Internal PLL for clock generation can use a 25 MHz crystal — Programmable LED functionality Revision 1.7 September 2006
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY , RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY , OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel products referenced in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548- 4725 or by visiting Intel's website at http://www.intel.com. Intel® is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries . * Other names and brands may be claimed as the property of others. Copyright © Intel Corporation, 2002-2006
Networking Silicon — 82540EM
Revision History
May 2002 0.25 Initial Release Nov 2002 1.0 Section 3.6.Test Signal from O to I. Figures 7-8 added Section 5.2. changed 194 balls to 196 Jan 2003 1.1 Section 1.0. Replaced Block Diagram Section 2.6. Added Table footnote Section 4.1, 4.2, 4.3. Replaced tables Section 5.1. Added Visual Pin Reference Section 4.3 Deleted empty row; added footnote to I/O Characteristics table Section 4.4 Removed Power Supply Characteristics table Apr 2003 1.2 Removed confidential status. Section 1.0. Added product ordering code information. Sep 2004 1.3 Removed references to REQ64#. Th is was a typing error and references to REQ64# should be “REQ#” since the 82540EM is a 32-bit part. Nov 2004 1.4 Added product features to cover. Updated signal names to match design guide and reference schematics. Nov 2004 1.5 Added information about migrating from a 2-layer 0.36 mm wide-trace sub- strate to a 2-layer 0.32 mm wide-trace substrate. Refer to the section on Pack- age and Pinout Information. Added statement that no changes to ex isting soldering processes are needed for the 2-layer 0.32 mm wide-trace substrate change in the section describing “Package Information”. Corrected pinout discrepancies between Table 36 and the section “Visual Pin Reference”. July 2006 1.6 Added LAN Disable solution information to section 3.2.6. Sept 2006 1.7 Added a note to Figure 12 clarifying the device pin 1 location.
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Networking Silicon — 82540EM Datasheet 1
1.0 Introduction
The Intel® 82540EM Gigabit Ethernet Controller is a single, compact component with an integrated Gigabit Ethernet Media Access Control (MAC) and physical layer (PHY) functions. For desktop, workstation and mobile PC Network designs with critical space constraints, the Intel® 82540EM allows for a Gigabit Ethernet implementation in a very small area that is footprint compatible with current generation 10/100 Mbps Fast Ethernet designs The Intel ® 82540EM integrates Intel’s fourth generation gigabit MAC design with fully integrated, physical layer circuitry to provide a standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE-TX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab). The controller is capable of transmitting and receiving data at rates of 1000 Mbps, 100 Mbps, or 10 Mbps. In addition to managing MAC and PHY layer functions, the controller provides a 32-bit wide direct Peripheral Component Interconnect (PCI) 2.2 compliant interface capable of operating at 33 or 66 MHz. The Intel ® 82540EM’s on-board System Management Bus (SMB) port enables network manageability implementations required by information technology personnel for remote control and alerting via the LAN. With SMB, management packets can be routed to or from a management processor. The SMB port enables industry standards, such as Intelligent Platform Management Interface (IPMI) and Alert Standard Forum (ASF), to be implemented using the 82540EM. In addition, on chip ASF 1.0 circuitry provides alerting and remote control capabilities with standardized interfaces. The 82540EM Gigabit Ethernet Controller architecture is designed to deliver high performance and PCI bus efficiency. Wide internal data paths eliminate performance bottlenecks by efficiently handling large address and data words. The 82540EM controller includes advanced interrupt handling features to limit PCI bus traffic and a PCI interface that maximizes the use of bursts for efficient bus usage. The 82540EM caches up to 64 packet descriptors in a single burst for efficient PCI bandwidth use. A large 64 KByte on-chip packet buffer maintains superior performance as available PCI bandwidth changes. In addition, using hardware acceleration, the controller offloads tasks from the host controller, such as TCP/UDP/IP checksum calculations and TCP segmentation. The 82540EM is packaged in a 15 mm 2 196-ball grid array and is pin compatible with the Intel® 82551QM 10/100 Mbps Fast Ethernet Multifunction PCI/CardBus Controller.
1.1 Document Scope
This document contains datasheet specifications for the 82540EM Gigabit Ethernet Controller, including signal descriptions, DC and AC parameters, packaging data, and pinout information.
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1.2 Reference Documents
This application assumes that the designer is acquainted with high-speed design and board layout techniques. The following documents provide additional information: 82544EI/82544GC Gigabit Ethernet Controller Software Developer's Manual, Revision 0.25, Intel Corporation. PCI Local Bus Specification, Revision 2.3, PCI Special Interest Group. PCI Bus Power Management Interface Specification, Rev. 1.1, PCI Special Interest Group. IEEE Standard 802.3, 1996 Edition, Institute of Electrical and Electronics Engineers (IEEE). IEEE Standard 802.3u, 1995 Edition, Institute of Electrical and Electronics Engineers (IEEE). IEEE Standard 802.3x, 1997 Edition, Institute of Electrical and Electronics Engineers (IEEE). IEEE Standard 802.3z, 1998 Edition, Institute of Electrical and Electronics Engineers (IEEE). IEEE Standard 802.3ab, 1999 Edition, Institute of Electrical and Electronics Engineers (IEEE). Intel Ethernet Controllers Timing Device Selection Guide, AP-419, Intel Corporation. PCI Mobile Design Guide, Rev. 1.1, PCI Special Interest Group 82562EZ(EX)/82551QM & 82540EM Combined Footprint LOM Design Guide, AP-434, Intel Corporation.
1.3 Block Diagram
Figure 1. 82540EM Block Diagram
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2.0 Product Code
The product ordering code for the 82540EM is: RC82540EM.
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3.0 Signal Descriptions
3.1 Signal Type Definitions
The signals of the 82540EM controller are electrically defined as follows:
3.2 PCI Bus Interface
When the Reset signal (RST#) is asserted, the 82540EM will not drive any PCI output or bi- directional pins except the Power Management Event signal (PME#).
3.2.1 PCI Address, Da ta and Control Signals
I Input. Standard input only digital signal. O Output. Standard output only digital signal. TS Tri-state. Bi-directional three-state digital input/output signal. STS Sustained Tri-state. Sustained digital three-state signal driven by one agent at a time. An agent driving the STS pin low must actively drive it high for at least one clock before letting it float. The next agent of the signal cannot drive the pin earlier than one clock after it has been released by the previous agent. OD Open Drain. Wired-OR with other agents. The signaling agent asserts the OD signal, but the signal is returned to the inactive state by a weak pull-up resistor. The pull-up resistor may require two or three clock periods to fully restore the signal to the de-asserted state. A Analog. PHY analog data signal. P Power. Power connection, voltage reference, or other reference connection. Symbol Type Name and Function AD[31:0] TS Address and Data. Address and data signals are multiplexed on the same PCI pins. A bus transaction includes an address phase followed by one or more data phases. The address phase is the clock cycle when the Frame signal (FRAME#) is asserted low. During the address phase AD[31:0] contain a physical address (32 bits). For I/O, this is a byte address, and for confi guration and memory, a DWORD address. The 82540EM device uses little endian byte ordering. During data phases, AD[7:0] contain the least significant byte (LSB) and AD[31:24] contain the most significant byte (MSB). C/BE#[3:0] TS Bus Command and Byte Enables. Bus command and byte enable signals are multiplexed on the same PCI pins. Duri ng the address phase of a transaction, C/ BE#[3:0] define the bus command. In the data phase, C/BE#[3:0] are used as byte enables. The byte enables are valid for the entire data phase and determine which byte lanes contain meaningful data. C/BE#[0] applies to byte 0 (LSB) and C/BE#[3] applies to byte 3 (MSB).
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3.2.2 Arbitration Signals
Parity. The Parity signal is issued to implement even parity across AD[31:0] and C/ BE[#3:0]. PAR is stable and valid one clock after the address phase. During data phases, PAR is stable and valid one clock after either IRDY# is asserted on a write transaction or TRDY# is asserted after a read transaction. Once PAR is valid, it remains valid until one clock after the completion of the current data phase. When the 82540EM controller is a bus master, it drives PAR for address and write data phases, and as a slave device, drives PAR for read data phases. FRAME# STS Cycle Frame. The Frame signal is driven by the 82540EM device to indicate the beginning and length of an access and indicate the beginning of a bus transaction. While FRAME# is asserted, data transfers continue. FRAME# is de-asserted when the transaction is in the final data phase. IRDY# STS Initiator Ready. Initiator Ready indicates the abilit y of the 82540EM controller (as bus master device) to complete the current data phase of the transaction. IRDY# is used in conjunction with the Target Ready signal (TRDY#). The data phase is completed on any clock when both IRDY# and TRDY# are asserted. During the write cycle, IRDY# indicates that valid data is present on AD[31:0]. For a read cycle, it indicates the master is ready to accept data. Wait cycles are inserted until both IRDY# and TRDY# are asserted together. The 82540EM controller drives IRDY# when acting as a master and samples it when acting as a slave. TRDY# STS Target Ready. The Target Ready signal indicates the ability of the 82540EM controller (as a selected device) to complete the curr ent data phase of the transaction. TRDY# is used in conjunction with the Initiator Ready signal (IRDY#). A data phase is completed on any clock when both TRDY# and IRDY# are sampled asserted. During a read cycle, TRDY# indicates that valid data is present on AD[31:0]. For a write cycle, it indicates the target is ready to accept data. Wait cycles are inserted until both IRDY# and TRDY# are asserted together. The 82540EM device drives TRDY# when acting as a slave and samples it when acting as a master. STOP# STS Stop. The Stop signal indicates the current target is requesting the master to stop the current transaction. As a slave, the 82540EM controller drives STOP# to request the bus master to stop the transaction. As a master, the 82540EM controller receives STOP# from the slave to stop the current transaction. IDSEL# I Initialization Device Select. The Initialization Device Select signal is used by the 82540EM as a chip select signal during c onfiguration read and write transactions. DEVSEL# STS Device Select. When the Device Select signal is actively driven by the 82540EM, it signals notifies the bus master that it has decoded its address as the target of the current access. As an input, DEVSEL# indicates whether any device on the bus has been selected. VIO P VIO. The VIO signal is a voltage reference for the PCI interface (3.3 V or 5 V PCI signaling environment). It is used as the clamping voltage. Note: An external resistor is required between the voltage reference and the VIO pin. The target resistor value is 100 K Ω Symbol Type Name and Function REQ# TS Request Bus. The Request Bus signal is used to request control of the bus from the arbiter. This signal is point-to-point. GNT# I Grant Bus. The Grant Bus signal notifies the 82540EM that bus access has been granted. This is a point-to-point signal. LOCK# I Lock Bus. The Lock Bus signal is asserted by an initiator to require sole access to a target memory device during two or mo re separate transfers. The 82540EM device does not implement bus locking. Symbol Type Name and Function
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3.2.3 Interrupt Signal
3.2.4 System Signals
3.2.5 Error Reporting Signals
Symbol Type Name and Function INTA# TS Interrupt A. Interrupt A is used to request an interr upt by port 1 of the 82540EM. It is an active low, level-triggered interrupt signal. Symbol Type Name and Function CLK I PCI Clock. The PCI Clock signal provides timing for all transactions on the PCI bus and is an input to the 82540EM device. All other PCI signals, except the Interrupt A (INTA#) and PCI Reset signal (RST#), are sampled on the rising edge of CLK. All other timing parameters are defined with respect to this edge. M66EN I 66 MHz Enable. M66EN indicates whether the system bus is enabled for 66MHz. RST# I PCI Reset. When the PCI Reset signal is asserted, all PCI output signals, except the Power Management Event signal (PME#), are floated and all input signals are ignored. The PME# context is preserved, depending on power management settings. Most of the internal state of the 82540EM is reset on the de-assertion (rising edge) of RST#. Symbol Type Name and Function SERR# OD System Error. The System Error signal is used by the 82540EM controller to report address parity errors. SERR# is open drain and is actively driven for a single PCI clock when reporting the error. PERR# STS Parity Error. The Parity Error signal is used by the 82540EM controller to report data parity errors during all PCI transactions except by a Special Cycle. PERR# is sustained tri-state and must be driven active by the 82540EM controller two data clocks after a data parity error is detected. The minimum duration of PERR# is one clock for each data phase a data parity error is present.
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3.2.6 Power Management Signals
3.2.7 Impedance Compensation Signals
3.2.8 SMB Signals
Symbol Type Name and Function LAN_ PWR_ GOOD I Power Good (Power-on Reset). The Power Good signal is used to indicate that stable power is available for the 82540EM. When the signal is low, the 82540EM holds itself in reset state and floats all PCI signals. Note: The 82540EM does not support LAN Disable; however, A LAN Disable solution can be implemented by holding LAN_PWR_GOOD to 0b. PME# OD Power Management Event. The 82540EM device drives this signal low when it receives a wake-up event and either the PME Enable bit in the Power Management Control/Status Register or the Advanced Power Management Enable (APME) bit of the Wake-up Control Register (WUC) is 1b. APM_WAKEUP O Advance Power Management Wakeup. When APM Wakeup is enabled in the 82540EM controller and the 82540EM controller receives a Magic Packet* it will set this signal to a logic 1 for 50 ms. AUX_PWR I Auxiliary Power. If the Auxiliary Power signal is high, then auxiliary power is available and the 82540EM device should support the D3cold power state. Symbol Type Name and Function ZN_COMP I/O N Device Impedance Compensation. This signal should be connected to an external precision resistor (to VDD) that is indicative of the PCI trace load. This cell is used to dynamically determine the drive strength requi red on the N-channel transistors in the PCI I/O cells. ZP_COMP I/O P Device Impedance Compensation. This signal should be connected to an external precision resistor (to VSS) that is indicative of the PCI trace load. This cell is used to dynamically determine the drive strength r equired on the P-channel transistors in the PCI I/O cells. Symbol Type Name and Function SMBCLK I/O SMB Clock. The SMB Clock signal is an open drain signal for serial SMB interface. SMBDATA I/O SMB Data. The SMB Data signal is an open drain signal for serial SMB interface. SMB_ ALERT# O SMB Alert. The SMB Alert signal is open drain for serial SMB interface.
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3.3 EEPROM and Flash Interface Signals
Symbol Type Name and Function EEDI O EEPROM Data Input. The EEPROM Data Input pin is used for output to the memory device. EEDO I EEPROM Data Output. The EEPROM Data Output pin is used for input from the memory device. The EE_DO includes an internal pull-up resistor. EECS O EEPROM Chip Select. The EEPROM Chip Select signal is used to enable the device. EESK O EEPROM Serial Clock. The EEPROM Shift Clock provides the clock rate for the EEPROM interface, which is approximately 1 MHz. FL_CE# O FLASH Chip Enable Output. Used to enable FLASH device. FL_SCK O FLASH Serial Clock Output. The clock rate of the serial FLASH interface is approximately 1 MHz. FL_SI O FLASH Serial Data Input. This pin is an output to the memory device. FLSH_SO I FLASH Serial Data Output. This pin is an input from the FLASH memory. It has an internal pullup device.
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3.4 Miscellaneous Signals
3.4.1 LED Signals
3.4.2 Other Signals
3.5 PHY Signals
3.5.1 Crystal Signals
Symbol Type Name and Function LED0 / LINK_UP# O LED0 / LINK Up. Programmable LED indication. Defaults to indicate link connectivity. LED1 / ACTIVITY# O LED1 / Activity. Programmable LED indication. Defaults to flash to indicate transmit or receive activity. LED2 / LINK100# O LED2 / LINK 100. Programmable LED indication. Defaults to indicate link at 100 Mbps. LED3 / LINK1000# O LED3 / LINK 1000. Programmable LED indication. Defaults to indicate link at 1000 Mbps. Symbol Type Name and Function SDP[7:6] SDP[1:0] TS Software Defined Pin. The Software Defined Pins are reserved and programmable with respect to input and output capability. These default to input signals upon power-up but may be configured differently by the EEPROM. The upper four bits may be mapped to the General Purpose Interrupt bits if they are configured as input signals. Note: SDP5 is not included in the group of Software Defined Pins. Symbol Type Name and Function XTAL1 I Crystal One. The Crystal One pin is a 25 MHz +/- 30 ppm input signal. It can be connected to either an oscillator or crystal. If a crystal is used, Crystal Two (XTAL2) must also be connected. XTAL2 O Crystal Two. Crystal Two is the output of an internal oscillator circuit used to drive a crystal into oscillation. If an external oscillator is used in the design, XTAL2 must be disconnected.
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3.5.2 Analog Signals
3.6 Test Interface Signals
Symbol Type Name and Function REF P Reference. This Reference signal should be connec ted to VSS through an external 2.49 K Ω resistor. MDI[0]+/- A Media Dependent Interface [0]. 1000BASE-T: In MDI configuration, MDI[0]+/- corresponds to BI_DA+/-, and in MDI-X configuration, MDI[0]+/- corresponds to BI_DB+/-. 100BASE-TX: In MDI configuration, MDI[0]+/- is used for the transmit pair, and in MDI-X configuration, MDI[0]+/- is used for the receive pair. 10BASE-T: In MDI configuration, MDI[0]+/- is used for the transmit pair, and in MDI-X configuration, MDI[0]+/- is used for the receive pair. MDI[1]+/- A Media Dependent Interface [1]. 1000BASE-T: In MDI configuration, MDI[1]+/- corresponds to BI_DB+/-, and in MDI-X configuration, MDI[1]+/- corresponds to BI_DA+/-. 100BASE-TX: In MDI configuration, MDI[1]+/- is used for the receive pair, and in MDI-X configuration, MDI[1]+/- is used for the transit pair. 10BASE-T: In MDI configuration, MDI[1]+/- is used for the receive pair, and in MDI-X configuration, MDI[1]+/- is used for the transit pair. MDI[2]+/- A Media Dependent Interface [2]. 1000BASE-T: In MDI configuration, MDI[2]+/- corresponds to BI_DC+/-, and in MDI-X configuration, MDI[2]+/- corresponds to BI_DD+/-. 100BASE-TX: Unused. 10BASE-T: Unused. MDI[3]+/- A Media Dependent Interface [3]. 1000BASE-T: In MDI configuration, MDI[3]+/- corresponds to BI_DD+/-, and in MDI-X configuration, MDI[3]+/- corresponds to BI_DC+/-. 100BASE-TX: Unused. 10BASE-T: Unused. Symbol Type Name and Function JTAG_TCK I JTAG Clock. JTAG_TDI I JTAG TDI. JTAG_TDO O JTAG TDO. JTAG_TMS I JTAG TMS. JTAG_ TRST# I JTAG Reset. This is an active low reset signal for JTAG. This signal should be terminated using a pull-down resistor to ground. It must not be left unconnected. TEST I Factory Test Pin. CLK_VIEW O Clock View. Output for GTX_CLK and RX_CLK during IEEE PHY conformance testing. The clock is selected by register programming.
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3.7 Power Supply Connections
3.7.1 Digital Supplies
3.7.2 Analog Supplies
3.7.3 Ground and No Connects
3.7.4 Control Signals
Symbol Type Name and Function VDDO P 3.3 V I/O Power Supply. DVDD P 1.5 V Digital Core Power Supply. Symbol Type Name and Function AVDDH P 3.3 V Analog Power Supply. AVDDL P 2.5 V Analog Power Supply. Symbol Type Name and Function GND P Ground. NC P No Connect. Do not connect any circuitry to these pins. Pull-up or pull-down resistors should not be connected to these pins. Symbol Type Name and Function CTRL15 A 1.5V Control. LDO voltage regulator output to drive exte rnal pass transistor. If 1.5 V is already present in the system, leave output unconnected. CTRL25 A 2.5V Control. LDO voltage regulator output to drive exte rnal pass transistor. If 2.5 V is already present in the system, leave output unconnected.
4.0 Voltage, Temperature, and Timing Specifications
local Intel sales office that you have the latest information before finalizing a design.
4.1 Absolute Maximum Ratings
4.2 Recommended Operating Conditions
4.3 DC Specifications
Table 1. Absolute Maximum Ratings a Table 2. Recommended Operating Conditions a limits, might result in permanent damage. Table 3. DC Characteristics
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Table 4. Power Specifications - D0a
3.3 V 40 40 55 65 65 80 125 125
2.5 V 20 20 30 35 55 60 145 150
1.5 V 100 120 95 100 115 125 400 425
Table 5. Power Specifications - D3cold
3.3 V 40 40 55 55 50 50 40 40
2.5 V 20 20 30 30 55 55 20 20
1.5 V 40 40 30 35 55 60 10 10
Table 6. Power Specifications - D(r)
3.3 V 40 45
2.5 V 40 45
1.5 V 190 200
Table 7. Power Specifications - Complete Subsystem
3.3 V 40 40 60 60 60 60 130 130
2.5 V 20 20 40 40 80 80 240 245
1.5 V 10 10 30 35 55 60 400 425
3.3 V current 70 mA 135 mA 200 mA 800 mA
Table 8. I/O Characteristics (Sheet 1 of 2)
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4.4 AC Characteristics
a. TTL3 signals include: EEDI, EESK, EECS, and JTAG_TDO. TTL6 signals include: APM_WAKEUP, FL_CE#, FL_SCK, FL_SI, and CLK_VIEW. Table 9. AC Characteristics: 3.3 V Interfacing Table 8. I/O Characteristics (Sheet 2 of 2) Table 10. 25 MHz Clock Input Requirements to XTAL1 and XTAL2 as the frequency source for the internal oscillator. Table 11. Link Interface Clock Requirements a. GTX_CLK is used externally for test purposes only.
4.5 Timing Specifications
the latest information before finalizing a design.
4.5.1 PCI Bus Interface
4.5.1.1 PCI Bus Interface Clock
Table 12. EEPROM Interface Clock Requirements Table 13. AC Test Loads for General Output Pins Figure 1. AC Test Loads for General Output Pins Table 14. PCI Bus Interface Clock Parameters
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minimum peak-to-peak portion of the clock waveform as shown. noise cannot render a monotonic signal to appear bouncing in the switching range. Figure 2. PCI Clock Timing
0.6 Vcc
0.2 Vcc
0.5 Vcc
0.4 Vcc
0.3 Vcc
0.4 Vcc p-to-p
3.3 V Clock
4.5.1.2 PCI Bus Interface Timing
- Output timing measurements are as shown.
- REQ# and GNT# signals are point-to-point and have different output valid delay and input setup times than
bussed signals. GNT# has a setup of 10 ns; REQ# has a setup of 12 ns. All other signals are bussed.
- Input timing measurements are as shown.
Table 15. PCI Bus Interface Timing Parameters Figure 3. PCI Bus Interface Output Timing Measurement
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Figure 4. PCI Bus Interface Input Timing Measurement Conditions Table 16. PCI Bus Interface Timing Measurement Conditions Figure 5. TVAL (max) Rising Edge Test Load
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4.5.2 Link Interface Timing
4.5.3 EEPROM Interface
Table 17. Rise and Fall Times Figure 9. Link Interface Rise/Fall Timing Table 18. Link Interface Clock Requirements Table 19. Link Interface Clock Requirements a. The EEDO setup and hold time is a function of the CLK cycle time but is referenced to EESK.
5.0 Package and Pinout Information
1mm. The pin number-to-signal mapping is indicated beginning with Table 36.
5.1 Device Identification
Figure 10. 82540EM Device Identification Markings
5.2 Package Information
dimensions are detailed in Figure 11. The nominal ball pitch is 1 mm. Figure 11. Mechanical Specifications Note: No changes to existing soldering processes are needed for the 0.32 mm substrate change. Note: All dimensions are in millimeters.
5.3 Thermal Specifications
VCC. The thermal resistances are shown in Table 18. be used to assure that the 82540EM device is operating under recommended conditions. Table 18. Thermal Characteristics
5.4 Pinout Information
Table 19. PCI Address, Data, and Control Signals Table 20. PCI Arbitration Signals Table 21. Interrupt Signals Table 22. System Signals Table 23. Error Reporting Signals
Table 24. Power Management Signals Table 25. Impedance Compensation Signals Table 26. SMB Signals Table 27. EEPROM and Serial FLASH Interface Signals Table 28. LED Signals Table 29. Other Signals Table 30. IEEE Test Signals
Table 31. PHY Signals Table 32. Test Interface Signals Table 33. Digital Power Signals Table 34. Analog Power Signals
Table 35. Grounds and No Connect Signals Table 36. Signal Names in Pin Order (Sheet 1 of 6)
Table 36. Signal Names in Pin Order (Sheet 2 of 6) (Continued)
Table 36. Signal Names in Pin Order (Sheet 3 of 6) (Continued)
Table 36. Signal Names in Pin Order (Sheet 4 of 6) (Continued)
Table 36. Signal Names in Pin Order (Sheet 5 of 6) (Continued)
Table 36. Signal Names in Pin Order (Sheet 6 of 6) (Continued)
5.5 Visual Pin Reference
Figure 12. Ball Grid Array / Pin Reference for 196-TFBGA (Bottom/Pin View) Note: Figure 12 is rotated 90 degrees counter-clockwise from the pin 1 position (corner) in Figure 11.
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