8254

8254 INTEL | Alldatasheet

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Table 1. Pin Description ciuko | 9 | 1 | CLOCKO: Clock input of Counter 0. | ouro | 10 | © | OUTPUT o: Output of Counter 0. GaTeo | 11 | |__| GATE: Gate input of Counter 0. | GND | 12 | __|_ GROUND: Power supply connection. | Voc | 24 | _|_ POWER: +5V power supply connection. | wR | 23 | 4 | WRITE CONTROL: This inputs low during CPU write operations. | AO | 22 | | | READ CONTROL: This inputis low during CPU read operations. RD and WR signals. RD and WR are ignored otherwise. cuke | 18 | 1 | CLOCK 2:Clock input of Counter 2. out2. | 17 | © | OUT2:Outputof Counter2. GaTe2 | 16 | 1 | GATE 2:Gate input of Counter 2. cuK1 | 15 | 1 | CLOCK 4: Clock input of Counter 1. GATE 1 {| 4 | 4 | GATE 1: Gate input of Counter 1. ouTt | 13 | © | OUT 14:Outputof Counter 1. length delays can easily be accommodated. terface the 8254 to the system bus (see Figure 3). www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Figure 3. Block Diagram Showing Data Bus Buffer and Read/Write Logic Functions of the three counters or the Control Word Register in Figure 5. counters. A “low” on the WR input tells the 8254 may operate in a different Mode. selected by holding CS low. termine how the Counter operates. data is stored in the Control Word Register and is i” . The Control Word Register can only be written to; . www.chipdocs.com Be sure to visit ChipDocs web site for more information.

mand is sent to the 8254, the latches “latch” the register for MODE programming. the OL that is being read. tems. Control Logic allows one register at a time to be . . loaded from the internal bus. Both bytes are trans- After power-up, the state of the 8254 is undefined. cleared when the Counter is programmed. In this are undefined. The Control Logic is also shown in the diagram. outside world through the Contro! Logic.

8254 SYSTEM INTERFACE The Control Words are written into the Control Word

Figure 6. 8254 System Interface www.chipdocs.com Be sure to visit ChipDocs web site for more information.

1 Read/Write least significant byte first,

Don't care bits (X) should be 0 to insure compatibility with future Intel products. Figure 7. Control Word Format 1) For each Counter, the Control Word must be writ- must follow the programmed count format. be loaded with an incorrect count. www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Figure 8. A Few Possible Programming Sequences Latch Command, and the Read-Back Command. when it is read, giving an undefined result. . to the Control Word Register, which is selected with future Intel products. www.chipdocs.com Be sure to visit ChipDocs web site for more information.

intel. 8254 The selected Counter’s output latch (OL) latches the AO,A1=11 CS=0 RD=1 WR=0 count at the time the Counter Latch Command is received. This count is held in the Jatch until it is read D7 Dg Os Ds O3 Dz Dy Do by the CPU (or until the Counter is reprogrammed). [status The count is then unlatched automatically and the [+ [+ [eoorr| US| CNT2 Lo] OL returns to “following” the counting element (CE). Ds: 0 = Latch count of selected - This allows reading the contents of the Counters Ds: O= Latch Status of sheeted counters) “on the fly” without affecting counting in progress. Dg: 1 = Select Counter 2 Multiple Counter Latch Commands may be used to Dz: 1 = Select Counter 1 latch more than one Counter. Each latched Coun- Dy: 1 = Select Counter 0 ; ter’s OL holds its count until it is read. Counter Latch Do: Reserved for future expansion; Must be 0 Commands do not affect the programmed Mode of 7 the Counter in any way. Figure 10. Read-Back Command Format A ‘ The read-back command may be used to latch multi- lf a Counter is latched and then, some time later, latched again before the count is read, the second ie cou Te oO ana colacting the deuired dome Counter Lath Command 's ignored. The count read ter(s). This single command is functionally equiva- will be the count at the time the first Counter Latch lent to several counter latch commands. one for Command was issued. each counter latched. Each counter’s latched count thy ei 7 is held until it is read (or the counter is repro- with either method, the count must be read accord grammed). The counter is automatically unlatched cg to the programmed format; specifically, if the when read, but other counters remain latched until bytes must programmed moons me rns ee they are read. {f multiple count read-back commands 3 read one right after the other: read or write or pro- are issued to the same counter without reading the " i , " 1, all but the fi i ; Le., the t Serted between them. read-back command was issued. Another feature of the 8254 is that reads and writes of the same Counter may be interleaved; for exam- Ue reac back cor mmmmand may aso OO to tatch ple, if the Counter is programmed for two byte STATUS bit D4 = 0. Status must be latched to be counts, the following sequence is valid. read; status of a counter is accessed by a read from 1) Read least significant byte. that counter. 2) Write new least significant byte. Fi B . ag The counter status format is shown in Figure 11. Bits 3) Read most significant byte. D5 through DO contain the counter’s programmed 4) Write new most significant byte. Mode exactly as written in the last Mode Control . | Word. OUTPUT bit D7 contains the current state of 'f a Counter is programmed to read/write two-byte the OUT pin. This allows the user to monitor the counts, the following precaution applies: A program counter's output via software, possibly eliminating must not transfer control between reading the first some hardware from a system. and second byte to another routine which also reads from that same Counter. Otherwise, an incorrect count will be read. D7 Ds Ds Ds D3 Dg Dy Do Null | aw1 | RWo BCD READ-BACK COMMAND Count The third method uses the Read-Back Command. D7 1 = OUT Pinis 1 This command allows the user to check the count 0 = OUT Pin isO value, programmed Mode, and current states of the 1 = Null t OUT pin and Null Count flag of the selected coun- | 75 4 ANCONA ine ter(s). ) Ds—Dp Counter programmed mode (see Figure ig The command is written into the Control Word Reg- 7) ister and has the format shown in Figure 10. The command applies to the counters selected by set- Figure 11. Status Byte ting their corresponding bits D3, D2, D1 = 1. 3-69 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

intel. 8254 Mode Definitions OUT will then go high and remain high until the CLK pulse after the next trigger. The following are defined for use in describing the operation of the 8254. After writing the Contro} Word and initial count, the . cei " A Counter is armed. A trigger results in loading the K Pulse: s 5 a CLK Pulse a.eing edge, then a tain ocee in Counter and setting OUT low on the next CLK pulse, put , thus starting the one-shot pulse. An initial count of N . , will result in a one-shot pulse N CLK cycles in dura- Trigger: a rising edge of a Counter's GATE —_ tion. The one-shot is retriggerable, hence OUT will input. remain low for N CLK pulses after any trigger. The Counter loading: the transfer of a count from the CR one-shot pulse can be repeated without rewriting the to the CE (refer to the “Functional same count into the counter. GATE has no effect on Description”) OUT. If a new count is written to the Counter during a one- MODE 0: INTERRUPT ON TERMINAL COUNT shot pulse, the current one-shot is not affected un- Control Word is written, OUT is initially low, and will shot pulse continues until the new count expires. remain low until the Counter reaches zero. OUT then pul pres. goes high and remains high until a new count or a new Mode 0 Control Word is written into the Coun- MODE 2: RATE GENERATOR ter. This Mode functions like a divide-by-N counter. It is GATE = 1 enables counting; GATE = 0 disables _typically used to generate a Real Time Clock inter- counting. GATE has no effect on OUT. rupt. OUT will initially be high. When the initial count has decremented to 1, OUT goes low for one CLK After the Control Word and initial count are written to pulse. OUT then goes high again, the Counter re- a Counter, the initial count will be loaded on the next loads the initial count and the process is repeated. CLK pulse. This CLK pulse does not decrement the Mode 2 is periodic; the same sequence is repeated count, so for an initial count of N, OUT does not go indefinitely. For an initial count of N, the sequence high until N + 1 CLK pulses after the initial count is repeats every N CLK cycles. written, GATE = 1 enables counting; GATE = 0 disables If a new count is written to the Counter, it will be counting. If GATE goes low during an output pulse, loaded on the next CLK pulse and counting will con- OUT is set high immediately. A trigger reloads the tinue from the new count. If a two-byte count is writ- Counter with the initial count on the next CLK pulse; ten, the following happens: OUT goes low N CLK pulses after the trigger. Thus 1) Writing the first byte disables counting. OUT is set a GATE input can be used to synchronize the low immediately (no clock pulse required) ‘ounter. 2) Writing the second byte allows the new count to — after writing a Control Word and initial count, the be loaded on the next CLK pulse. Counter will be loaded on the next CLK pulse. OUT . . . goes low N CLK Pulses after the initial count is writ- This allows the counting sequence to be synchroniz- _ten. This allows the Counter to be synchronized by ed by software. Again, OUT does not go high until software also. * N+ 1 CLK pulses after the new count of N is written. ae . . oo, Writing a new count while counting does not affect If an initial count is written while GATE = 0, it will the current counting sequence. If a trigger is re- still be loaded on the next CLK pulse. When GATE —_ ceived after writing a new count but before the end goes high, OUT will go high N CLK pulses later;no —_of the current period, the Counter will be loaded with CLK pulse is needed to load the Counter as this has the new count on the next CLK pulse and counting already been done. will continue from the new count. Otherwise, the new count will be loaded at the end of the current MODE 1: HARDWARE RETRIGGERABLE counting cycle. In mode 2, a COUNT of 1 is illegal. ONE-SHOT OUT will be initially high. OUT will go low onthe CLK MODE 3: SQUARE WAVE MODE Pulse following a trigger to begin the one-shot pulse, — Mode 3 is typically used for Baud rate generation. and will remain low until the Counter reaches zero. Mode 3 is similar to Mode 2 except for the duty cycle of OUT. OUT will initially be high. When half the 3-71 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

1. Counters are programmed for prey {not BCD) counting and for reading/writing least significant byte (LSB) only.
2. The counter is always selected (CS always low).

‘3. CW stands for “Control Word"; CW = 10 means a control word of 10 HEX is written to the counter.

1. LSB stands for “Least Significant Byte” of count.
2. Numbers below diagrams are count values. The lower number is the least significant byte. The upper number is the

most significant byte. Since the counter is programmed to read/write LSB only, the most significant byte cannot be read. 'N stands for an undefined count. Vertical lines show transitions between count values. Figure 15. Mode 0 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Figure 16. Mode 1 count of N results in a square wave with a period of also. used to synchronize the Counter. www.chipdocs.com Be sure to visit ChipDocs web site for more information.

intel. 8254 CW=14 LsB=3 sate .v_OODCVCV TT Ietweim tm fodetsdsbeleis| CWelt4 LSB} GATE \\ | o}ofo Ieletudmisteleisieleds| Cwat4 (S824 UsB=5 RT a o}osolo Ielmlwtwielstsdeisiets| 231164-9 NOTE: AGATE transition should not occur one clock prior to terminal count. Figure 17, Mode 2 new count. Otherwise, the new count will be loaded Odd counts: OUT is initially high. The initial count at the end of the current half-cycle. minus one (an even number) is loaded on one CLK pulse and then is decremented by two on succeed- Mode 3 is implemented as follows: ing CLK pulses. One CLK pulse after the count ex- pires, OUT goes low and the Counter is reloaded Even counts; OUT is initially high. The initial count is with the initial count minus one. Succeeding CLK loaded on one CLK pulse and then is decremented pulses decrement the count by two. When the count by two on succeeding CLK pulses. When the count expires, OUT goes high again and the Counter is expires OUT changes value and the Counter is re- reloaded with the initial count minus one. The above loaded with the initial count. The above process is process is repeated indefinitely. So for odd counts, repeated indefinitely. OUT will be high for (N + 1)/2 counts and low for (N ~ 1)/2 counts. 3-74 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

A GATE transition should not occur one clock prior to terminal count. Figure 18. Mode 3 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

1 CLK pulses after the initial count is written. 7 ig the first byte has no effect on counting. counting. GATE has no effect on OUT. After writing a Control Word and initial count, the be loaded on the next CLK pulse. the new count of N is written. Figure 19. Mode 4 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

rising edge of GATE. When the initial count has ex- no effect on OUT. count, so for an initial count of N, OUT does not counting will continue from there. strobe low until N + 1 CLK pulses after a trigger. Figure 20. Mode 5 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Figure 21. Gate Pin Operations Summary immediately following WR of a new count value. 0 mented on the falling edge of CLK.

0 The largest possible initial count is 0; this is equiva-

Figure 22. Minimum and Maximum Initial Counts sel wa the initial count and continues counting www.chipdocs.com Be sure to visit ChipDocs web site for more information.

intel. 8254 ABSOLUTE MAXIMUM RATINGS* NOTICE: This is a production data sheet. The specifi- . - cations are subject to change without notice. Voltage on Any Pin with These are stress ratings only. Operation beyond the tn ge tended exposure beyond the “Operating Conditions” D.C. CHARACTERISTICS Tx, = 0°C to 70°C, Veg = 5V + 10% [ symbot | Parameter | Min | Max | Units | Test Gondiions InputHigh Voltage [20 | Voc+osv | vo [| OuiputLowVvottage [| | 04s |v tp = 20m Cio 1/O Capacitance Unmeasured pins returned to Vsg(4) A.C. CHARACTERISTICS T, = 0°C to 70°C, Voc = 5V + 10%, GND = OV Bus Parameters(1) READ CYCLE | min | Max | win | max | min | max | RD 1 to Data Floating | s | «| s {| o | 5 | 6 | ns | NOTE: 1. AC timings measured at Voy = 2.0V, VoL = 0.8V. 3-79 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

intel. 8254 A.C. CHARACTERISTICS Ty, = 0°C to 70°C, Voc = 5V + 10%, GND = OV (Continued) WRITE CYCLE | min | max | min | Mex | in | Max | Ti | AdtessStbiosaiooWRT | 0 | |e] [oe] | w | [tsw | Ssubioseiromms | 0 | [| 0 | | 0 | | ww Tx | Adeess old Time aterWRt | o | [0 | [0 | | me | Two | WReuse wan tvs | | vo | os | ne | Cow | DataSets Tine Seiro A T | 120 | [120] [os || ve | [wo | Batarold Tine ater T | 0 | | o | [0 | | ms | Ltav | Command Recovery time | 200 | | 200 | [tes [| CLOCK AND GATE | Min [ max | win | Max | min | Max | cx | GoaxPeroa =i aoa 0c | vas | oc | 00 | oc | ne | [in | Gockriserine | if as | [=| | =| | fe | oboekrantime | | as || as] | 5 | ms | ton | Gate Setup Tine ater cc? | so@ | | o@ | | aoe | | re | Hop | Outrutdelayromcuks || wo | | aso | | 100 | oe | Fons | OutrutDetay tomate | | | rao | [va | | 100 | ow | two | CLK DelaytorLoading | | 0 | ss | o | s5 | o | 65 | ns | [we | Gate stay frsarsing | -s | so | -s | so | -s | | me | [wo | OUT Belay fom Mode wite |_| aso |_| a0] | 0 | mw | Ite, | uk SetUptorcountuatcn | —a0 | as | | as | ao] «0 | re | ain Medes 1 and 5 triggers are sampled on each rising clock edge. A second trigger within 120 ns (70 ns for the 6254-2) of the rising clock edge may not be detected. 3. Low-going glitches that violate tpwy, tpwL May Cause errors requiring counter reprogramming. 4. Sampled, not 100% tested. Ta = 25°C. 5, If CLK present at TWC min then Count equals N+ 2 CLK pulses, TWC max equals Count N+ 1 CLK pulse. TWC min to TWC max, count will be either N+ 1 or N+2 CLK pulses. 6. In Modes 1 and 5, if GATE is present when writing a new Count value, at TWG min Counter will not be triggered, at TWG max Counter will be triggered. 7. If CLK present when writing a Counter Latch or ReadBack Command, at TCL min CLK will be reflected in count value latched, at TCL max CLK will not be reflected in the count value latched. 3-80 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

intel. 8254 . ae WAVEFORMS WRITE cs =F | paTa Bus {| vai | . 3 | ——] we | 231164-13 READ > es tna : Ee: Lied | tap > tor to ae as es a 231164-14 381 ‘www.chipdocs.com Be sure to visit ChipDocs web site for more information.

intel. 8254 WAVEFORMS (Continued) RECOVERY tay RD. WR 231164-15 CLOCK AND GATE “ MODE COUNT* wR we cLK | | te tos >| toH ] ‘we GATE AQw: tow to too OUTPUT O | | to0a |___ two. 231164-16 “Last byte of count being written. A.C. TESTING INPUT, OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT 20 20. 04s. of o* © = 150 pF 231164~17 T AG. Testing: Inputs are drivan at 2.4V for a Logic “1” and 0.45V = for @ Logic “0.” Timing measurements are made at 2.0V for a = Logic "1" and 0.8V for a Logic 0”, 231164-18 Cy = 150 pF Cy Includes Jig Capacitance 3-82 www.chipdocs.com Be sure to visit ChipDocs web site for more information.