8253

8253 INTEL | Alldatasheet

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intel. 8253/8253-5 FUNCTIONAL DESCRIPTION RD (Read) A “low” on this input informs the 8253 that the CPU General is inputting data in the form of a counters value. The 8253 is programmable interval timer/counter specifically designed for use with the intel™ Micro- WR (Write) computer systems. Its function is that of a general purpose, multi-timing element that can be treated as. A “low” on this input informs the 8253 that the CPU an array of 1/O ports in the system software. is outputting data in the form of mode information or loading counters. The 8253 solves one of the most common problems in any microcomputer system, the generation of ac- curate time delays under software control. Instead of AQ, A1 setting up timing loops in systems software, the pro- grammer configures the 8253 to match his require- These inputs are normally connected to the address ments, initializes one of the counters of the 8253 bus. Their function is to select one of the three coun- with the desired quantity, then upon command the ters to be operated on and to address the contro! 8253 will count out the delay and interrupt the CPU word register for mode selection. when it has completed its tasks. itis easy to see that the software overhead is minimal and that multiple = __ delays can easily be maintained by assignment of | CS (Chip Select) priority levels. A “low” on this input enables the 8253. No reading Other counter/timer functions that are non-delay in OF writing will occur unless the device is selected. nature but also common to most microcomputers The CS input has no effect upon the actual opera- can be implemented with the 6253. tion of the counters. ‘* Programmable Rate Generator * Event Counter * Binary Rate Multiplier . exe * Real Time Clock 6 SS Ko onteo © Digital One-Shot oure * Complex Motor Controller | wo 4 | CuK) Data Bus Buffer ———-d aby caves The 3-state, bi-directional, 8-bit buffer is used to in. | | ours terface the 8253 to the system data bus. Data is . i | | transmitted or received by the buffer upon execution of INput or OUTput CPU instructions. The Data Bus | Buffer has three basic functions. 1. Programming the MODES of the 8253. or atk 2. Loading the count registers. NT our 3, Reading the count values. Read/Write Logic { The Read/Write Logic accepts inputs from the sys- meanaceus tem bus and in turn generates control signals for 291906-3 "so that no dperation ean occur fo change the Figure3 Block Diagram Showing Data Bus function unless the device has been selected by the Buffer and Read/Write Logic Functions system logic. 3-52

intel. 8253/8253-5 eee [ES] RO[WATA, [Ao] ]_spstems software as an aray of perpheral 1/0 Ports; three are counters and the fourth is a contro! [0 [4 [0 [0 | 0 | toad Counter No.0 register for MODE programming. [o [4 | | 0 [4 [toad Counter No. 1 Load Counter No. 2 Basically, the select inputs AO, A1 connect to the BR = AO, A1 address bus signals of the CPU. The C5 can 1_| 1 | Write Mode Word be derived directly from the address bus using a lin- [o | o | 1 | 0 | 0 | Read Counter No.0 ear select method. Or it can be connected to the [o | 0 | 1 | 0 | 1 | Read Counter No.1 output of a decoder, such as an Intel 8205 for larger systems. [o | o {4 [4 | 0 | Read Counter No.2 [0 | 0 | 1 | 4 | 4 | No-Operation 3-State 11 |x] x [x] x | Disable 3-state Lo | + | 1 [x [x | No-Operation 3-State op para ane ‘oure Control Word Register The Control Word Register is selected when AO, A1 20 d are 11. It then accepts information from the data bus | aa d scans | on buffer and stores it in a register. The information sate KC ates stored in this register controls the operation MODE “7 our of each counter, selection of binary or BCD counting — . and the loading of each count register. The Control Word Register can only be written into; | no read operation of its contents is available. a cue Counter #0, Counter #1, Counter #2 2 Te on These three functional blocks are identical in opera- tion so only a single counter will be described. Each Counter consists of a single, 16-bit, pre-settable, INTERNAL 8US /| DOWN counter. The counter can operate in either binary or BCD and its input, gate and output are con- 291906-4 figured by the selection of MODES stored in the “Figure 4. Block Diagram Showing Control Word intro! Word Register. Register and Counter Functions The counters are fully independent and each can have separate MODE configuration and counting op- _ eration, binary or BCD. Also, there are special fea- ADDRESS OS tures in the control word that handle the loading of bl | the count value so that software overhead can be 1 minimized for these functions. LT [fr fw The reading of the contents of each counter is avail- - oan able to the programmer with simple READ opera- . tions for event counting applications and special commands and logic are included in the 8253 so rrr Deo no that the contents of each counter can be read “on ess the fly” without having to inhibit the clock input. couse COUNTER counren

8253 SYSTEM INTERFACE | | t

' H The 8253 is a component of the Intel™ Microcom- 291906-5 puter systems and interfaces in the same manner as all other peripherals of the family. It is treated by the Figure 5. 8253 System Interface 3-53

intel. 8253/8253-5 Se OPERATIONAL DESCRIPTION RL—READ/LOAD: RL1_ ALO General f°]? Counter Latching operation (see The complete functional definition of the 8253 is READ/WRITE Procedure Section). programmed by the systems software, A set of cone [1 | 0 | Read/Load most significant byte only. +erae tor ot ine 0289 win the. desvod MODE coun countor of the 8259 with the desited MODE |__| _1_| Read/Load least significant byte only. and quantity information. Prior to initialization, the Read/Load least significant byte first, MODE, count, and output of all counters is unde- then most significant byte. fined. These control words program the MODE, Loading sequence and selection of binary or BCD counting. M—MODE: Once programmed, the 8253 is ready to perform m2 M1 MoO whatover iming tasks tis assignod.o accomplsh. ""g To To | wodeo | Mode 0 The aca couing operation ofeach coutr« [0 | 0 | 1 | Modet | completely independent and additional logic is pro- Aided oncchip so thatthe usual problems assocated |__| 1 | 0 | Mode2 | with efficient monitoring and management of eter. [x [1 |v [Modes | nal, asynchronous events or rates to the microcom- puter system have been eliminated. re Pe ee Programming the 8253 All of the MODES for each counter are programmed BCD: Each counter of the 8253 is individually programmed Lt | Binary Coded Decimal (BCD) Counter by writing a control word into the Control Word Reg- (4 Decades) ister. (AO, A1 = 11) Counter Loading Control Word Format The count register is not loaded until the count value Dy Ds Ds Da Dz Dp Di Do is written (one or two bytes, depending on the mode selected by the RL bits), followed by a rising edge [sot [soo [us| ruo[ M2] mi [Mo[ BC] anda falling edge of the clock. Any read of the coun- ter prior to that falling clock edge may yield invalid data. Definition Of Control MODE DEFINITION LECT COUNTER: Sc—SEl MODE 0: Interrupt on Terminal Count. The output sc1 sco will be initially low after the mode set operation. After [0 | 0 | SelectCountero | ‘the count is loaded into the selected count register, Select Counter 0 the output will remain low and the counter will count. fo | 1 | ‘Select Counter 1 When termina! count is reached, the output will go high and remain high until the selected count regis- [1 | 0 | _SelectCounter2 | ter is reloaded with the mode or a new count is load- [a | 1 | we ed. The counter continues to decrement after termi- nal count has been reached. Rewriting a counter register during counting results in the following: (1) Write 1st byte stops the current counting. (2) Write 2nd byte starts the new count. 3-54

intel. 8253/8253-5 SSeS MODE 1: Programmable One-Shot. The output will In Modes 2 and 3, if a CLK source other than the go low on the count following the rising edge of the system clock is used, GATE should be pulsed imme- gate input. diately following WR of a new count value: The output will go high on the terminal count. Ifa MODE 4: Software Triggered Strobe. After the New count value is loaded while the output is low it mode is set, the output will be high. When the count will not affect the duration of the one-shot pulse until _is loaded, the counter will begin counting. On termi- the succeeding trigger. The current count can be _nal count, the output will go low for one input clock fead at any time without affecting the one-shot _ period, then will go high again. pulse. If the count register is reloaded during counting, the The one-shot is retriggerable, hence the output will new count will be loaded on the next CLK pulse. The remain low for the full count after any rising edge of count will be inhibited while the GATE input is low. the gate input. MODE 5: Hardware Triggered Strobe. The counter MODE 2: Rate Generator. Divide by N counter. The —_will start counting after the rising edge of the trigger output will be low for one period of the input clock. _input and will go low for one clock period when the The period from one output pulse to the next equals _ terminal count is reached. The counter is retriggera- the number of input counts in the count register. If ble. The output will not go low until the full count the count register is reloaded between output pulses _aftar the rising edge of any trigger. the present period will not be affected, but the sub- sequent period will reflect the new value. Signal] Low The gate input, when low, will force the output high. _| Status] Or Going 3 When the gate input goes high, the counter will start |Modes. Low from the initial count. Thus, the gate input can be Disables Enables used to synchronize the counter. counting counting When this mode is set, the output will remain high 1 1) Initiates until after the count register is loaded. The output counting then can also be synchronized by software. 2) Resets output after next MODE 3: Square Wave Rate Generator. Similar to clock MODE 2 except that the output will remain high until ‘one half the count has been completed (or even 1) Disables | 1) Reloads Enables numbers) and go low for the other half of the count. counting counter counting This is accomplished by decrementing the counter 2) Sets output | 2) Initiates by two on the falling edge of each clock pulse. When immediately! counting the counter reaches terminal count, the state of the high output is changed and the counter is reloaded with the full count and the whole process is repeated. 1) Disables _| 1) Reloads Enables counting counter counting If the count is odd and the output is high, the first 2) Sets output | 2) Initiates clock pulse (after the count is loaded) decrements immediately] counting the count by 1. Subsequent clock pulses decrement high the clock by 2. After timeout, the output goes low and the full count is reloaded. The first clock pulse Disables Enables (following the reload) decrements the counter by 3. counting counting Subsequent clock pulses decrement the count by 2 [=] fete | | until timeout. Then the whole process is repeated. In ¢ this way, if the count is odd, the output will be high counting for (N + 1)/2 counts and low for (N — 1)/2 counts. Figure 6. Gate Pin Operations Summary 3-55

Figure 7. 8253 Timing Diagrams.

8253 READ/WRITE PROCEDURE

Writing out of the MODE control word can be in any used. quence independent. (SCO, SC1). will result if this feature is fully initilized. Figure 9. Alternate Programming Formats

Event counters are probably the most common ap- . disturbing the actual count in progress. inhibits the clock input. The contents of the counter Stce'a normal resd command to tne selected coun. First 1/O Read contains the least significant byte *Vallable. bytes must be read before any loading WR com- C1, SCO— specify counter to be latched. Figure 10. MCS-85™ Clock interface*

intel. 8253/8253-5 ABSOLUTE MAXIMUM RATINGS* NOTICE: This is a production data sheet. The specifi- vont T - cto 70° [cations are subject to change without notice. Voltage On Any Pin. These Soy contin’ ts only Operation beyond the with Respect to Ground 0.5V to 7 the “Cperating Conditions” D.C. CHARACTERISTICS T, = 0°C to 70°C, Voc = 5V 10%" [_Symbor | Parameter [| min | Max | unit_[ Test Conditions Ouputtow votage |_| 04s |v | Ween | Output High Votage | 24 | |v | ote Inputtoadcurent [| | eto | nA _| Vi=Voctoov Output Fioat Leakage | | #10 [nA | Vour = Voo 0 0.45V 3 [tcc | VocSuppiycurent | [tao [ma CAPACITANCE Ty = 25°C, Vcc = GND = 0V [ symbot | Parameter | win | typ | Max | unt | TestConaitions | impuCopectance | || 10 | oF | eaiMe L_cvo | vocepactance [| | 20 | pF | Unmeasured pins returned to Ves A.C. CHARACTERISTICS Ta = 0°C to 70°C, Voc = 5.0V +10%, GND = OV* Bus Parameters(3) READ CYCLE [min [Max | min [max | | tra | AddressHoldTimeforREAD | 5 | | 5 | | ns | | tan | READ Pulse width | 40 | | soo | | ns | DataDelaytromREAD®) || s00 | | 200 | ns | tor | FEADtoDataFioating | as [tas | as | 100 | ns | tav Recovery Time between READ 1 Bs and Any Other Control Signal 3-59

intel. 8253/8253-5 A.C. CHARACTERISTICS (Continued) WRITE CYCLE Sa ee a | tw | Address StablobeforewniTe | so | | a0 [| ns | [twa | AddressHoldTimetorwarme | 30 [| a0 | ns [ww | WAITEPusewiam | 400 || a0 | ns [tow | DataSetUptimetorwrire | 300 | | aso | | ns | | two | DataHoldTimetorwrrre | ao | | go | ns Co em OT and Any Other Control Signal CLOCK AND GATE TIMING ae ee om | ee [tax | CockPeiog | aso de | aso | dens | [town | HighPusewietn | aa0 [a0 Ts [tem | towPusewietn | ts0 | | ts0 | ns | [tew | GatewiatnHign | itso | ts0 Ts | [ta | Gatewiathtow | too | | too | Ts | [tas | Gatesetuptimetoctxt | too | | 100 | | ns | [ton | Gate HosTine anorcixt [so | |_s0 | |__| [00 | owpdemyromoct || ao || ao | ns | toos | OuputDetayromGaes® [| so | | 30 | os _| NOTES: 1. lo, = 22 mA. 2.loH = —400 pA. 3. AC timings measured at Vox 2.2, VoL = 0.8. 4.C, = 150 pF. “ortiaendod Femperaixe EXPRESS, use M8253 eloccal parameters A.C. TESTING INPUT, OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT 24 22v 2av- eas oe o* ©, = 180 pF 231306-13 T {AG. Testing Inputs are devon at 2.4V fra Logie “t" and 0 5V 4 tora Loge*0" Timing mossuremonts ee tnade at 22V for & = (gee and 0.8V tora Lope “0” 2a1906-14 ©; Includes Jig Capacitance 3-60

intel. 8253/8253-5 WAVEFORMS WRITE TIMING READ TIMING sone <>? Data sus * " l- tow two trol toe w -, oara sus YN IIE rani 231906-16 231906-15 CLOCK AND GATE TIMING “ = t tes} ton cares | ‘on tow ta e} ‘00 ourrure 231306-17 3-61