8251A INTEL | Alldatasheet
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fabricated using Intel’s high performance HMOS technology. Figure 1. Block Diagram
intel. 8251A FEATURES AND ENHANCEMENTS FUNCTIONAL DESCRIPTION The 8251A is an advanced design of the industry standard USART, the Intel® 6251. The 8251A oper- General ates with an extended range of Intel microproces- 80rs and maintains compatibility with the 6251. Fa- The 8251A is a Universal Synchronous/Asynchro- miliarization time is minimal because of compatibility ous Recelver/Transmitter designed for a wide and involves only knowing the additional teatures range of Intel microcomputers such as 8048, 8080, and enhancements, and reviewing the AC and DC 68085, 6086 and 6088. Like other I/O devices in a specifications of the 6251A. microcomputer system, its functional configuration is programmed by the system's software for maximum The 6251A incorporates all the key features of the _flexibility. The 8251A can support most serial data 8251 and has the following additional features and —techniques in use, including IBM “bi-sync”. In a communication environment an interface device * 8251A has double-buttered data paths with sopa- 2 an rate 1/0 rogisters for control, status, Data In, and ust convert parallel format system data into serial Data Out, which considerably simplifies contro! f0Fmat for transmission and convert incoming serial programming and minimizes CPU overhead format data into paraliel system data for reception. a The interface device must also delete or insert bits * In asynchronous operations, the Receiver de- or characters that are functionally unique to the ing the CPU of this task. should appear “transparent” to the CPU, a simple * A refined Rx initialization prevents the Receiver: _input or output of byte-oriented system data. from starting when in “break” state, preventing unwanted interrupts from a_ disconnected USART. Data Bus Buffer * At the conclusion of a transmission, TxD line will ‘ i . This 3-state bidirectional, 8-bit is inter- aiways coturn to the marking state unless SBRK face the 82514 to the eysiem Dats Bus. Data i Is programmed. 7 transmitted or received by the butfer upon execution * Tx Enable logic enhancement prevents a Tx Dis- of INput or OUTput instructions of the CPU. Control able command from halting transmission until alt —_ words, Command words and Status information are data previously written has been transmitted. The aiso transferred through the Data Bus Buffer. The logic also prevents the transmitter from turning Command Status, Data-in and Data-Out registers oft in the middle of a word. are separate, 6-bit registers communicating with the * When External Syne Detect is programmed, In. System bus through the Data Bus Buffer. ternal Sync Detect is disabled, and an External Sync Detect status is provided via a flip-flop This functional block accepts inputs from the system * Posebblity of false sync detect is minimized by iter and Command Word Register that etre, the ensuring that if double character sync is PFO- various control formats for the davice functional defi grammed, the characters be contiguously detect- nition. ed and also by clearing the Rx register to all ones . whenever Enter Hunt command is issued in Sync mode. RESET (Reset, * As long as the 6251A is not selected, the RD and ) WR do not affect the internal operation of the A “high" on this input forces the 8251A into an device. “Idle” mode. The device will remain at “Idle” until a © The 8251A Status can be read at any time but the new set of control words is written into the 8251A to satus update wil be inbted ving stats read. Program ie functional deiton. Minimum RESET © The 82514 is free from extraneous glitches and ‘ey oe. ing higher speed and better operating margins. Ital "Mie" een pus * Synchronous Baud rate from DC to 64K.
Figure 3. 8251A Block Diagram Showing Data Bus Suffer and Read/Write Logic Functions A “low” on this input informs the 6251A that the 1 = CONTROL/STATUS; 0 = DATA.
intel. 82518 CS (Chip Select) Transmitter Buffer A“low’ on this input selects the 8251A. No reading The Transmitter Buffer accepts parallel data from or writing wil occur urvess me device ie eon the Data Bus Buffer, converts it to a serial bit stream, When is high, the Data Bus is in the float state inserts the appropriate characters or bits (based on and RD and have no effect on the chip. the communication technique) and outputs a com- posite serial stream of data on the TxD output pin on . the falling edge of TxC. The transmitter will begin Modem Control transmission upon being enabled it CTS = 0. The TxD fine will be held in the marking state immediate- The 8251A has a set of control inputs and outputs —_—ly upon a master Reset or when Tx Enable or CTS is that can be used to simplity the interface to almost off or the transmitter is empty. any modem. The modem control signals are general purpose in nature and can be used for functions oth- er than modem control, if necessary. Transmitter Control The Transmitter Control manages all activities asso- DSR (Data Set Ready) ciated with the transmission of serial data. It accepts and issues signals both externally and internally to The DSR input signal is @ general-purpose, 1-bit in- accomplish this function. verting input port. Its condition can be tested by the CPU using a Status Read operation. The DSR input Beet ama Om monn commons oath a0 TxRDY (Transmitter Ready) This output signals the CPU that the transmitter is ready to accept a data character. The TxADY output DTR (Data Terminal Ready) pin can be used as an interrupt to the system, since it is masked by TxEnable; or, for Polled operation, The BTA output signa! is a general-purpose, 1-bit the CPU can check TxADY using a Status Read op- inverting output port. It can be set “low” by program- eration. TxADY is automatically reset by the leading ming the appropriate bitin the Command instruction edge of WR when a data character is loaded from word, The output signal is normally used for the CPU, modem contro! such as Data Terminal Ready. Note that when using the Polled operation, the TxADY status bit is not masked by TxEnable, but will RTS (Request to Send) only indicate the Empty/Full Status of the Tx Data i Register. The ATS output signal is a general-purpose, 1-bit “om inverting output port. It can be set “low” by program- ming the appropri bit in the Command Instruction ransmitter Empty word. The output signal is normally used for THE (9 E ) modem control such as Request to Send. When the 6251A has no characters to send, the TxEMPTY output will go “high”. it resets upon re- ceiving a character from CPU if the transmitter is CTS (Clear to Send) enabled. TxEMPTY remains high when the transmit- tor is disabled. TxEMPTY can be used to indicate A “low” on this input enables the 8251A to transmit the end of a transmission mode, so that the CPU serial data if the Tx Enable bit in the Command byte “knows” when to “turn the line around” in the half- is set to a “one”. Hf either a Tx Enable off or CTS off duplex operational mode. condition occurs while the Tx is in operation, the Tx will transmit all the data in the USART, written prior —_ in the Synchronous mode, a “high” on this output to Tx Disable command before shutting down. indicates that a character has not been loaded and the SYNC character or characters are about to be or EMPTY does not go low when the SYNC characters are being shifted out.
Figure 4. 8251A Block Diagram Showing Modem and Transmitter Buffer and Control Functions character is to be transmitted. In the Synchronous activities which consists of the following features. must first be detected after a chip master Reset. TxC equals 110 Hz in the 1x mode. for each master Reset. TxC equals 1.72 kHz in the 16x mode. the 8251A. of the Start bit (RxD = low). ters that are unique to the communication technique mode). and sends an “assembled” character to the CPU.
RxRDY (Fi Ready) will be set and the old character will be lost. character that is ready to be input to the CPU. of the CPU or, for polled operation, the CPU can . . complete character must be assembied and trans- Px. Failure to read the received character from the Rx Fx equals 19.2 kHz in the 64x mode. Data Output Register prior to the assembly of the Baud als Baud. and lost. It the Rx Data is being reed by the CPU == Fx equals 153.6 kHz in the 64 mode. Figure 5. 8251A Block Diagram Showing Receiver Buffer and Control Functions
In most communication systems, the 8251A will be matically reset upon a Status Read operation. mode low upon RESET. When used as an output bits). Break Detect may also be read as a Status bit. to indicate that the 6251A has located the SYNC returning to a “one” state. Figure 6. 8251A Interface to 8080 Standard System Bus
trol words must be sent out by the CPU to initialize of external). upon the CPU data read operation. the actual operation of the 8251A. marking state upon Reset. prior to using the 6251A for data communication. ci. 1 [moor mstaucnow Mode Instruction will load the Command Instruction. must follow the Mode Instruction or Sync characters. Figure 7. Typical Data Block the two formats will be isolated.
word length. The actual parity bit received on the grammed. the programmed number of Stop bits to each char- _— pled on the RxD pin with the rising edge of the Aixc.
1 ENABLE 0- DISABLE
Figure 8. Mode instruction Format, Asynchronous Mode
acters are shifted out on the falling edge of TxC, B251A. Data is shifted out at the same rate as the TxC. it character length is defined as 5, 6, or 7 bits the unused bits are set to “zero”. Figure 9. Asynchronous Mode
In this mode, character synchronization canbe inter- _high, and is reset automatically by a STATUS READ. be included in the first command instruction word _the last data bit. character until a match occurs. if the 8251A has _ pin, thus forcing the 8251A out of the HUNT mode. been programmed for two SYNC characters, the ‘The high level can be removed after one Rx cycle. when both SYNC characters have been detected, asynchronous mode of operation. In external sync mode, programming double character sync will affect only the Tx. Figure 10. Mode Instruction Format, Synchronous Mode
The CPU can command the receiver to enter the Controls are provided by the Command instruction. internal or external SYNC has been programmed. tion format. DET indication). When external SYNDET mode is ae a ree Cokie consecutively into ine de. the device to the “idle” state. Figure 11. Data Format, Synchronous Mode
Error Reset must be performed whenever AxEnable and Enter Hunt are programmed. Figure 12. Command Instruction Format the status of the device at any time during the func- _ tion.
SAME DEFINITIONS AS 1/0 PINS .
- TXRDY status bit has differant meanings from the TxADY output pin. The former is not conditioned by CTS and TxEN;
‘he latter is conditioned by both TTS and TxEN. Figure 13. Status Read Format
intel. B251A moureunoauenes, (See Voltage on Pin These are stress ratings only. Operation beyond the Power DiBSipation «os sceeeecsseseseees TW puma eipesune bewooe tne “Operating Condivons D.C. CHARACTERISTICS T, = 0°C to 70°C, Voc = 5.0V 4.10%, GND = OV" | Yu | inputHigh Voltage | 20 | vc | OV [CS | Vo. | OutputLowvotage | | 04s [VT t= 22ma [Vou | Owputtign votage | 2a |__| _v_| tow = - 400A | lor. __| Output Float Leakage [| +10 | HA | Vour=Voctoo4sv | | in| inputLeakage | | 10 | HA | Vin =Vootooasv | | tcc | Power SuppiyCurent | [100 [ma AllOutputs = High | CAPACITANCE T, = 25°C, Voc = GND = OV | Symbol | Parameter | Min | Max | Unit | TestConditions —i | Cw | tnputCapacitance [| 10 | pF | tc=1MHz pe pee to GND A.C, CHARACTERISTICS T, = 0°C to 70°C, Voc = 5.0V + 10%, GND = OV" Bus Parameters (Note 1) READ CYCLE [ Symbol [Parameter =| Min’ | Max | Unit | TestConditions | | tan _|_ Address Stable BetoreREAD(CS,C/D) [0 | | ns | (Note2) | | tra | AddressHold TimeforREAD(CS.c/D) | o | [ns | (Note) | [tan __| FEADPulsewidtn | 280 || os | tao | DataDelaytromREAD || 200 [ons | 3 = 150pF | | tor | READtoDataFioating =| st «| «100: | ns | (Notet.o) | WRITE CYCLE | Symbol | __—Parameter =| Min’ | Max | Unit | TestConditions | | tw | Address StabloBotoreWHITE [| o | | on | | twa | AddressHoldTimeforWRITE [ o | | ns | | tww | WAITEPusewiatn = | oso | Ts | | tow _| DataSetUpTimotor WRITE | 150 | =| ne | ee eee tay |_ Recovery TimeBetweenwaites | 6 | | ty | (Note 4) } 247
intel. 8251A A.C. CHARACTERISTICS (Continued) OTHER TIMINGS __Symbot [Parameter | tin | ax | Unit | Test Conditions | fey | CockPeod | 820 | 1950 | ns | (Noto5.6) a [& | CrocktowPusewiatn | oo | ns | [tate | GlockRiseandFailTime | S| S| ws | tore | TxD DelaytromFalingEdgeotTS | | St | ws | 1x Baud Rate 64 kHz 16x Baud Rate 310 | kHz 64x Baud Rate 615 | kHz trew Transmitter Input Clock Pulse Width 1x Baud Rate tev 16x and 64x Baud Rate toy Transmitter Input Clock Pulse Delay | 1x Baud Rate tey 16x and 64x Baud Rate icy Receiver Input Clock Frequency 1x Baud Rate 64 16x Baud Rate 310 64x Baud Rate 615 Receiver input Clock Pulse Width 1x Baud Rate ley 16x and 64x Baud Rate toy Receiver Input Clock Pulse Delay 1x Baud Rate tcy 18x and 64x Baud Rate toy [fanor | TeAOYPin Delay rom Ceniorattastoe |__| 4 | ty |moen | [ tenovcLEAR | TXADY | tromLeading EdgeotWA | | 400_| ns | (Noto7) | metoy | PXADY Pin Deay tom Cortorof ast | | 28 | wor [Noten _| | txov CLEAR | RXRDY | tromLeadingEdgeotRD || 400 | ne | (Note7) Internal SYNDET Delay from Rising [s [eeamerrrns || le fom | Extemal SYNDET Set-Up Time Aftor fs [Rageseume 7" | eer] wo-er| me [owen | Ltreewery | THEMPTY Delay trom Center ottast et | | 20 | toy | (Not7) aE a WRITE (TxEn, DTA, ATS) [tcn____| Controlto READ Set-Up Time (OSA.CTS) | 20 | | toy | (Note7) Fer Extended Tempersture EXPRESS, use MIL 8251A electrical parameters 2-48
intel. 8251A A.C, CHARACTERISTICS (Continued) TYPICAL 4 OUTPUT DELAY VS. 4 CAPACITANCE (pF) +20 é g yi Soo 0 ° 7 +100 a CAPACITANCE pF) ‘e A.C, TESTING INPUT, OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT - : aa 2 ous ha O ouT 205222-20 { o | AC Testing: Inputs are driven at 2.44 for a Logic “1” and OAV T for @ Logic 0". Timing measurements are made at 2.0V tor a = Logic "?" and 0.8 for @ Logic "0" €, - 0 pe 205222-21 Figure 18 WAVEFORMS SYSTEM CLOCK INPUT fey - ; ‘se S a CLOCK ¢ y 4 205222-22 2-19
intel. 6251A WAVEFORMS (Continued) ; Fi j + Z 5 3 Ae = LEIS, an | § 3 go ee ee pe iii PPP ep jas fe
intel. 8251A WAVEFORMS (Continued) WRITE DATA CYCLE (CPU — USART) TaRDY / ; tTARDY CLEAR — ww ww -— tow 4 two DATAmIDS) CONT CARE OON'T CARE co i 205222-25 READ DATA CYCLE (CPU «— USART) manov ‘WuADY CLEAR a ‘ie fro ‘wor naTaouTio) omansent {bara cur active} Sava roost “ CMs a wr TRA 205222-26 2-21
intel. 8251A WAVEFORMS (Continued) oe ee ‘ow +|+-+{ wo DATA IN (0.8) WA 6 ; a 7" j twa. 208222-27 OSA, CTs (wore #2) a tcr — tar cry |r tno ‘DF DATA OUT (0.8) a i tar ma x | oT" _-— — 208222-28 NOTES: 1. Two includes the response timing of a control byte. 2. Tea includes the effect of CTS on the TxENBL circuity. 2-22
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WAVEFORMS (Continued) — es if eS Se eee ae ee ‘es | eeiae: | To ete g Cael rr gt HE: Pi @ . 53 ; a i g | iS i |