82503 INTEL | Alldatasheet
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*Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. October 1995COPYRIGHT © INTEL CORPORATION, 1996 Order Number: 290421-004 82503 DUAL SERIAL TRANSCEIVER (DST)
82503 PRODUCT FEATURE SET OVERVIEW
Y Single Component Ethernet * Interface to Both 802.3 10BASE-T and AUI Y Automatic or Manual Port Selection Y Manchester Encoder/Decoder and Clock Recovery Y No Glue Interface to Industry-Standard LAN Controllers Ð Intel 82586, 82590, 82593 and 82596 Ð AMD 7990 (LANCE *) Ð National Semiconductor 8390 and 83932 (SONIC *) Ð Western Digital 83C690 Ð Fujitsu 86950 (Etherstar *) Y Diagnostic Loopback Y Reset, Low Power Modes Y Network Status Indicators Y Defeatable Jabber Timer Y User Test Modes Y 10 MHz Transmit Clock Generator Y One Micron CHMOS IV (Px48) Technology Y Single 5-V Supply INTERFACE FEATURES TPE Y Complies with 10BASE-T, IEEE Std. 802.3i-1990 for Twisted Pair Ethernet Y Selectable Polarity Switching Y Direct Interface to TPE Analog Filters Y On-Chip TPE Squelch Y Defeatable Link Integrity (LI) Y Support of Cable Lengths l100m AUI Y Complies with IEEE 802.3 AUI Standard Y Direct Interface to AUI Transformers Y On-Chip AUI Squelch A block diagram of a typical application is shown in Figure 1. The 82503 Dual Serial Transceiver is a high-inte- gration CMOS device designed to simplify interfacing industry standard Ethernet LAN Controllers to IEEE 802.3 local area network applications (10BASE5, 10BASE2, and 10BASE-T). The component supports both an attachment unit interface (AUI) and a Twisted Pair Ethernet interface (TPE). It allows OEMs to design a state-of-the-art media interface that is jumperless and fully automatic. The 82503 includes on-chip AUI and TPE drivers and receivers; it offers designers a cost-effective, integrated solution for interfacing LAN control- lers to the wire medium. CHMOS is a patented process of Intel Corporation. *Ethernet is a registered trademark of Xerox Corporation. LANCE is a registered trademark of Advanced Micro Devices. Etherstar is a registered trademark of Fujitsu Electronics. Sonic is a registered trademark of National Semiconductor Corporation.
82503 Dual Serial Transceiver (DST)
1.0 82503 PRODUCT FEATURES ÀÀÀÀÀÀÀÀÀ 3
2.0 PIN DEFINITION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5
2.1 Power Pins ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6
2.2 Clock Pins ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6
2.3 AUI Pins ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6
2.4 TPE Pins ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7
2.5 Controller Interface Pins ÀÀÀÀÀÀÀÀÀÀÀÀÀ 7
2.6 Mode Pins ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8
2.7 LED Pins ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 9
3.0 82503 ARCHITECTURE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 10
3.1 Clock Generation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 10
3.2 Transmit Blocks ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 10
3.3 Receive Blocks ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 11
3.4 Collision Detection ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 13
3.5 Link Integrity ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 13
3.6 Jabber Function ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 13
3.7 TPE Loopback ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 13
3.8 SQE Test Function ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 14
3.9 Port Selection ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 14
3.10 LED Description ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 14
3.11 Polarity Switching ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 14
3.12 Controller Interface ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 15
4.0 RESET, LOW POWER AND TEST
MODES ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 16
4.1 Reset ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 16
4.2 Low Power and High Impedance
Modes ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 16
4.3 Diagnostic Loopback ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 16
4.4 Customer Test Modes (Continuous
AUI/TPE Transmit) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 16
5.0 APPLICATION EXAMPLE ÀÀÀÀÀÀÀÀÀÀÀÀ 17
5.1 Introduction ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 17
5.2 Design Guidelines ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 17
5.3 Layout Guidelines ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 17
6.0 PACKAGE THERMAL
SPECIFICATIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 19
7.0 ELECTRICAL SPECIFICATIONS
AND TIMINGS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 20
Figure 1. Application Block Diagram 86950 (Etherstar) controllers. overcharge and reduces jitter on 10BASE-T links. facilitate board-level testing.
Figure 2. 82503 Functional Block Diagram
2.0 PIN DEFINITION
Figure 3. 44-Lead PLCC Pin Configuration Figure 4. 44-Lead QFP Pin Configuration
2.1 Power Pins
Symbol PLCC QFP Type Name and FunctionPin Pin VSS(1) 7, 17, 39 1, 11, 33 Supply Digital Ground. VCC(1) 6, 18, 40 44, 12, 34 Supply Digital V CC. A 5-V g 5% Power Supply. VCCA(1) 28 22 Supply Analog V CC. A 5-V g 5% Power Supply. VSSA(1) 29 23 Supply Analog Ground. NOTE: 1. V CC and V CCA must be connected to the same power supply. V SS and V SSA must be connected to the same ground. Separate decoupling and noise conditioning (e.g., ferrite beads) should be used.
2.2 Clock Pins
Symbol PLCC QFP Type Name and FunctionPin Pin X1 21 15 I CLOCK CRYSTAL. A 20 MHz crystal input. This pin can be driven with an external MOS level clock when X2 is left floating. X2 20 14 O CLOCK CRYSTAL. A 20 MHz crystal output. X1 can be driven with an external MOS level clock when this pin is left floating.
2.3 AUI Pins
Symbol PLCC QFP Type Name and FunctionPin Pin TRMT 27 21 O TRANSMIT PAIR. A differential output driver pair that drives the transmit pair of the transceiver cable. The output bit stream isTRMT 26 20 O Manchester encoded. Following the last transition, which is positive at TRMT, the differential voltage is reduced to zero volts. RCV 31 25 I RECEIVE PAIR. A differentially driven input pair which is tied to the receive pair of the Ethernet transceiver cable. The first transition onRCV 30 24 I RCV is negative-going to indicate the beginning of the frame. The last transition is positive-going to indicate the end of the frame. The received bit stream is assumed to be Manchester encoded. CLSN 25 19 I COLLISION PAIR. A differentially driven input pair tied to the collision presence pair of the Ethernet transceiver cable. TheCLSN 24 18 I collision presence signal is a 10 MHz square wave. The first transition at CLSN is negative-going to indicate the beginning of the signal; the last transition is positive-going to indicate the end of the signal.
2.4 TPE Pins
Symbol PLCC QFP Type Name and FunctionPin Pin TDH 35 29 O TP TRANSMIT PAIR DRIVERS. These four outputs constitute the twisted-pair drivers, which have predistortion capabilities. The TDH/TDH 37 31 O TDH outputs generate the 10 Mb/s Manchester Encoded data. TheTDL 34 28 O TDL/TDL outputs mirror the TDH/TDH outputs except for fat bitTDL 36 30 O occurrences (100 ns pulses). During the second half of a fat bit (either high or low), the TDL/TDL outputs are inverted with respect to TDH/TDH outputs. This signal behavior reduces the amount of jitter by preventing overcharge on the twisted pair medium. RD 32 26 I TP RECEIVE PAIR. The differential twisted pair receiver. The receiver pair is connected to the twisted pair medium and is drivenRD 33 27 I with 10 Mb/s Manchester encoded data.
2.5 Controller Interface Pins
Symbol PLCC QFP Type Name and FunctionPin Pin TxC 93 O TRANSMIT CLOCK. A 10 MHz clock output tied directly to the transmit clock pin of the Ethernet controller. Changes sense depending on controller selected. Active low for Intel and Fujitsu controller interfaces, active high for National and AMD interfaces. Can drive one TTL load. TxD 16 10 I TRANSMIT DATA. TTL input. NRZ serial data is clocked in on TxD from the Ethernet controller. Connects directly to the transmit data pin of the Ethernet controller. RTS 15 9 I REQUEST TO SEND. TTL input. An active low input signal synchronous to TxC which enables data transmission on the active port. Changes sense depending on controller selected. Active low for the Intel controller interface, active high for National, AMD, and Fujitsu interfaces. RxC 14 8 O RECEIVE CLOCK. A 10 MHz clock output tied directly to the receive clock pin of the Ethernet controller. This clock is the recovered clock from incoming data on the active port. Changes sense depending on controller selected. Active low for Intel and Fujitsu controller interfaces, active high for National and AMD interfaces. Can drive one TTL load. RxD 13 7 O RECEIVE DATA. Received NRZ data (synchronous to RxC ) passed to the Ethernet controller. Connect directly to the receive data pin of the controller. Can drive one TTL load. CRS 10 4 O CARRIER SENSE. Output that alerts the Ethernet controller that data is present on the active port. Connects directly to the carrier sense pin of the Ethernet controller. Changes sense depending on controller mode selected. Active low for Intel controller interface, active high for National, AMD, and Fujitsu interfaces. Can drive one TTL load. CDT 12 6 O COLLISION DETECT. Output that indicates presence of a collision. Connects directly to the collision detect pin of the Ethernet controller. Changes sense depending on controller selected. Active low for Intel and Fujitsu controller interfaces, active high for National and AMD interfaces. Can drive one TTL load.
2.6 Mode Pins
Symbol PLCC QFP Type Name and FunctionPin Pin TPE/AUI 2 40 I/O PORT SELECT. TTL input/LED output. If APORT is low, TPE/AUI is an input and selects either the TPE port (TPE/AUI high) or AUI port (TPE/AUI low). If APORT is high, the 82503 will indicate the port selected by driving TPE/AUI high (TPE) or low (AUI). TPE/AUI can drive an LED pull-up. APORT 3 41 I AUTOMATIC PORT SELECTION. TTL input. When high, 82503 will automatically select TPE or AUI port based on presence of valid link beats or frames on the TPE receive input. Mode selected will be indicated on TPE/AUI APOL/XSQ 4 42 I AUTOMATIC POLARITY CORRECTION/EXTENDED SQUELCH ENABLE. TTL input. When high, the extended squelch mode is disabled and automatic polarity correction is enabled. Both junctions (APOL and XSQ) are enabled when this pin is at a high impedance state. When low, both functions become disabled. The presence of a polarity fault on the TPE receive pair is indicated on POLED regardless of the state of APOL. LID 38 32 I LINK INTEGRITY DISABLE. TTL input. If high, link integrity function is disabled. If low, link integrity function is enabled. CS0 5 43 I CONTROLLER SELECT. Selects the appropriate interface for the desired Ethernet controller. When CS0/1 e 0/0, supportsCS1 8 2 I Intel controllers. When CS0/1 e 0/1, supports Fujitsu controllers. When CS0/1 e 1/0, supports Western Digital and National controllers. When CS0/1 e 1/1, supports AMD controllers. (See Table 2.) LPBK 11 5 I LOOPBACK. TTL input. An active low input signal that causes the 82503 to enter diagnostic loopback mode. The twisted pair or AUI medium will be removed from the circuit, thus isolating the node from the network. When not connected, this pin assumes the inactive (high) state. Diagnostic loopback does not disable the operation of the link integrity processor, link beat generator, or automatic port selection. JABD 23 17 I JABBER DISABLE. TTL input. When high, this pin disables the jabber function. When low, the jabber function is enabled and the device performs AUI or TP jabber protection for the active port. If this pin and TEST are asserted during a falling edge of RESET, the 82503 enters its low power mode; when either this pin or TEST deasserts, then the 82503 transitions to its normal operating mode. TEST 19 13 I TEST MODE ENABLE. TTL input. When TEST is high and RESET is deasserted, a customer test mode is directly accessed. When driven low, test mode is disabled. If this pin and JABD are asserted during a falling edge of RESET, the 82503 enters its low power mode; when either this pin or JABD deasserts, then the 82503 transitions to its normal operating mode. RESET 22 16 I RESET. TTL input. When high, resets internal circuitry. On the falling edge of RESET, either test mode or low power mode can be entered depending on the state of JABD and TEST.
2.7 LED Pins
Symbol PLCC QFP Type Name and FunctionPin Pin TxLED 42 36 I/O TRANSMIT LED. LED output. Indicates transmit status of the AUI or TPE port. Normally off (high) output. Turns on to indicate transmission. Flashes at a rate dependent on the level of transmit activity. Upon entering a customer test mode, this pin must be driven high either through an LED, or a resistor. RxLED 43 37 I/O RECEIVE LED. LED output. Indicates receive status of the AUI or TPE port. Normally off (high) output. Turns on to indicate reception. Flashes at a rate dependent on the level of receive activity. Upon entering a customer test mode, this pin must be driven high either through an LED, or a resistor. COLED 44 38 I/O COLLISION LED. LED output. Indicates collision status of the AUI or TPE port. Normally off (high) output. Turns on to indicate collision. Flashes at a rate dependent on the level of collision activity. This pin is also used to determine which customer test modes are entered. LILED 41 35 O LINK INTEGRITY LED. LED output. Normally on (low) output which indicates good link integrity on the TPE port during TPE mode. Remains on when link integrity function has been disabled. Turns off during AUI mode or when link integrity fails in TPE mode. Minimum off time is 100 ms, minimum on time is set by the link integrity function. POLED 1 39 O POLARITY INDICATION. LED output. If the 82503 detects that the receive TPE wires are reversed, POLED will turn on (low) to indicate the fault. POLED remains on even if APOL/XSQ is high and the 82503 has automatically corrected for the reversed wires. NOTE: 1. The LED outputs have a weak pull-up capable of sourcing 500 mA. They can sink 10 mA while still meeting TTL levels. All LEDs can be used as indication pins if no LED is needed. Some of these outputs include pulse width conditioning, which should be accounted for in software.
3.0 82503 ARCHITECTURE
3.1 Clock Generation
A 20 MHz parallel resonant crystal is used to control the clock generation oscillator, which provides the basic 20 MHz clock source. An internal divide-by- two counter generates the 10 MHz g0.01% clock required by the IEEE 802.3 specification. We recommend a crystal that meets the following specifications be used. # Quartz Crystal # 20 MHz g 0.002% at 25 §C # Accuracy g 0.005% over full operating tempera- ture, 0 §Ct o a70§C # Parallel resonant with 20 pF Load Fundamental Mode # Maximum Series Resistance: R SERIES e 30X Several vendors have such crystals; either-off-the shelf or custom made. Two possible vendors are: 1. M-Tron Industries, Inc. Yankton, SD 57078 Specifications; Part No. HC49 with 20 MHz, 50 PPM over 0 §Ct o a70§C, and 20 pF fundamental load. 2. Crystek Corporation
100 Crystal Drive
Ft. Myers, FL 33907 Part No. 013212 The accuracy of the Crystal Oscillator frequency de- pends on the PC board characteristics, therefore it is advisable to keep the X1 and X2 traces as short as possible. The optimum value of C1 and C2 should be determined experimentally under nominal operat- ing conditions. The typical value of C1 and C2 is between 22 pF and 35 pF. An external 20 MHz MOS-level clock may be applied to pin X1, if pin X2 is left floating.
3.2 Transmit Blocks
3.2.1 MANCHESTER ENCODER
The 20 MHz clock is used to Manchester-encode data on the TxD input. This clock is also divided by two to produce the 10 MHz clock the LAN controller needs for synchronizing its RTS and TxD signals. Data encoding and transmission begins with RTS asserting. Since the first bit of a transmission is a 1, the first transition is always negative on the transmit outputs (TRMT or TD pins). Transmission ends when RTS deasserts. The last transition is always positive at the transmit outputs (TRMT or TD pins) and may occur at the center of the bit cell if the last data bit to be transmitted is a 1, or at the boundary of the bit cell if the last data bit to be sent is a 0. Immediately after the end of a transmission, all sig- nals on the RCV pair (when AUI mode is selected) are inhibited for 4 to 5 ms. This dead time is neces- sary for proper operation of the SQE (heartbeat) test.
3.2.2 AUI CABLE DRIVER
The AUI cable driver (TRMT pair) is a differential circuit, which interfaces to the AUI cable through a pulse transformer. High voltage protection is achieved by using a trans- former to isolate the transmit pins (TRMT pair) from the transceiver cable. The total transmit circuit in- ductance, including the 802.3 transceiver transform- ers, should be a minimum of 27 mH for Ethernet ap- plications.
3.2.3 TWISTED PAIR CABLE DRIVER
The twisted pair line drivers (TD pairs) begin trans- mitting the serial Manchester bit stream 3 bit times after RTS is asserted. The line drivers use a predis- tortion algorithm to improve jitter performance for up to 100 meters of twisted pair cable. The line drivers reduce their drive level during the second half of ‘‘fat’’ (100 ns) Manchester pulses and maintain a full drive level during all ‘‘thin’’ (50 ns) pulses and during the first half of the ‘‘fat’’ pulses. This reduces line overcharging during ‘‘fat’’ pulses, a major source of jitter.
Figure 5. TPE Predistortion
3.3 Receive Blocks
3.3.1 MANCHESTER DECODER AND CLOCK
the phase of the incoming data bit-center transition. the digital filter to zero at the start of a new frame.
Figure 6. Manchester Decoder and Clock Recovery
3.3.2 AUI RECEIVE AND COLLISION BUFFERS
collision detection circuitry.
3.3.3 AUI RECEIVE AND COLLISION
have the following squelch characteristics. # The squelch circuits are turned on at idle. ceive (RCV) or the AUI collision (CLSN) pair. squelch circuitry is turned on.
3.3.4 TPE RECEIVE BUFFER
3.3.5 TPE RECEIVE SQUELCH CIRCUITS
16 MHz are rejected, if the single cycle is pre-
(i.e., a signal less than 300 mV).
3.3.6 TPE Extended Squelch Mode
talk for cable lengths up to 200 meters.
TPE extended squelch mode is enabled by present- ing a high-impedance ( l100 K X) at the APOL/XSQ pin. This can be done by floating the APOL/XSQ pin, tying APOL/XSQ low through a 100 K X resistor, or driving APOL/XSQ with a three-state buffer. When driven high or low using a TTL driver or a low imped- ance pull-up or pull-down ( k2K X) extended squelch is disabled and the driven level at the APOL/XSQ pin determines the state of the polarity- correction function (APOL/XSQ e 1 enables polari- ty correction, APOL/XSQ e 0 disables polarity cor- rection). The TPE extended squelch feature is trans- parent to previous steppings of the 82503. Polarity correction is always enabled when the TPE extend- ed-squelch feature is enabled (APOL/XSQ e Z). The APOL/XSQ pin senses a high-impedance state by an active-polling circuit implemented at the pin. Two small polling devices attempt to pull the APOL/ XSQ pin up to V CC and down to V SS. If the pin is in a high-impedance state, the devices will be successful in pulling the APOL/XSQ pin high and low. If the pin is driven high or low, the polling devices will not be able to successfully pull the pin in the opposite di- rection. In this way, an internal state machine can correctly determine one of three states of the APOL/XSQ pin. The pin is polled every 25.6 ms.
3.4 Collision Detection
3.4.1 AUI COLLISION DETECTION
Collision detection in the AUI mode is performed by the attached transceiver, and signalled to the 82503 on the CLSN pair. A 10 MHz a25%, or b15%, square wave with transition times between 35 ns and 70 ns indicates the collision. The 82503 reports this to the LAN controller on the CDT pin.
3.4.2 TPE COLLISION DETECTION
Collision detection in the TPE mode is indicated by simultaneous transmission and reception on the twisted pair link segment. The CDT signal is assert- ed for the duration of both RTS and the presence of received data; CRS is asserted for the duration of either RTS or the presence of received data. During a collision, the source of RxD will be the received data. If the received data stream ends before the transmit data stream, the RxD source will be changed to transmit data stream until it ends.
3.5 Link Integrity
The 82503 supports the link integrity function as de- fined by 10BASE-T. During long periods of idle on the transmitter, link test pulses will be transmitted on to the twisted pair medium as an indication to the remote MAU that the link is good. These pulses will be transmitted 8 ms to 24 ms after the end of the last transmission or link test pulse. The link integrity function continuously monitors ac- tivity on the receive circuit. If neither valid data nor link test pulses are received, the link integrity proc- essor declares the link bad, and disables transmis- sion and reception on the media, loopback, and the SQE test function. Transmission of link test pulses and monitoring receive activity are not affected. The idle time required for the link integrity processor to determine the link is bad is 50 ms to 150 ms. Once a frame or a sequence of 2 to 10 valid consec- utive link test pulses are detected, the Link Integrity Processor declares the link is good, and reconnects the transmitter and receiver. The link integrity function can be disabled by driving the LID pin high or by disabling automatic port selec- tion (APORT e 0) and selecting the AUI port. This option is intended primarily for use with pre- 10BASE-T networks.
3.6 Jabber Function
The 82503 contains a jabber timer to implement the jabber function. If a transmission continues beyond the limits specified, the jabber function inhibits fur- ther transmission and asserts the collision indicator, CDT . The limits for jabber transmission are 20 ms to 150 ms in TPE Mode, and 8 ms to 16 ms in AUI mode. For both AUI and TPE mode, the transmis- sion inhibit period extends until the 82503 detects sufficient idle time (between 250 ms and 750 ns) on the RTS signal. The jabber function can be disabled by driving the JABD high. In TPE mode the link integrity function continues to operate even if the jabber function is inhibiting trans- mission. Link test pulses continue to be sent and the receive circuit continues to be monitored. Additional- ly, the link integrity function reconnects to a restored link without waiting for the transmit input to go idle when the jabber function is inhibiting transmission.
3.7 TPE Loopback
In TPE mode the 82503 implements the transmit to receive loopback (DO to DI) mode specified in the 10BASE-T standard. This mode loops back transmit- ted data through the receive path. This function is required to maintain full compatibility with coax MAUs where the data loopback is a natu- ral result of the architecture.
3.8 SQE Test Function
function when it detects a bad link.
3.9 Port Selection
Table 1. Port Selection
01 X * Automatic Port Selection
11 X * TPE
*TPE/AUI is an output pin when APORT e 1.
3.10 LED Description
3.10.1 TPE/AUI
3.10.2 TxLED
low, medium, and high rate of transmit activity.
3.10.3 RxLED
2.5 Hz, 5 Hz, and 10 Hz to indicate respectively a
low, medium, and high rate of receive activity.
3.10.4 COLED
low, medium, and high rate of collision activity.
3.10.5 POLED
3.10.6 LILED
3.11 Polarity Switching
Figure 7. Polarity Fault State Diagram
3.12 Controller Interface
depending on the state of and CS0 and CS1 inputs. pins according to the following table.
Table 2. Controller Interface Selection
- CS0 and CS1 are intended to be static pins only. Switching CS0 and CS1 during network reception or transmission will
produce unpredictable results.
4.0 RESET, LOW-POWER AND
4.1 Reset
4.3 Diagnostic Loopback
from the controller interface pins while in this mode. tions are not inhibited by diagnostic loopback mode. If otherwise enabled, they continue to function.
4.4 Customer Test Mode
complex software exercisers.
Table 3. Test and Low Power Mode Selection
- A standard LED connection to these pins is sufficient to pull them to a logic 1.
5.0 APPLICATION EXAMPLE
5.1 Introduction
- The serial interface signals connect directly
and the 82503 without the need for external logic.
5.2 Design Guidelines
of 75 mH minimum (100 mH recommended).
- Pulse Engineering (P/N PE-64103)
- Valor Electronics (P/N LT6003)
End through a resistor summing network (Figure 7). CCA and V CCD of the 82503 to V SSA and V SSD. tion is shown at the end of this section.
5.3 Layout Guidelines
achieve this, the following guidelines are presented.
Figure 8. Application Example Schematic
pling caused by the inductance of thin traces. Connect logic and chassis ground together. and X2 traces should be symmetrical.
82503 Analog Differential Signals
eliminate excessive trace inductance. well as on any sublayers of the PCB. separate from each other. Separate their grounds. noise from being induced into the analog front end. All trace bends should not exceed 45 degrees. of the top surface opposite the pins. Table 4. Thermal Resistance Table 5. Maximum T A at Various Airflows
Case Temperature Under Bias ÀÀÀÀÀÀÀ0 §Ct o a85§C Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b65§Ct o a140§C All Output and Supply Voltages ÀÀÀÀÀ b0.5V to a7V All Input Voltages ÀÀÀÀÀÀÀÀÀÀÀÀÀ b1.0V to a6.0V(1) NOTICE: This is a production data sheet. The specifi- cations are subject to change without notice. *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability. DC CHARACTERISTICS (TC e 0§Ct o a85§C, V CC e 5V g5%, V CCA e 5V g5%) Symbol Parameter Min Max Units Test Conditions VIL(TTL)(2) Input Low Voltage b0.3 0.8 V VIH(TTL)(2) Input High Voltage 2.0 V CC V ILI(2) Input Leakage Current g10 mA 0.0V s VI s VCC, RESET e 1 VOL(MOS)(3) Output Low Voltage 0.45 V I OL e 4m A VOH(MOS) Output High Voltage 3.9 V I OH eb 500 mA VOL(LED)(4) Output Low Voltage 0.45 V I OL e 10 mA VOH(LED) Output High Voltage 3.9 V I OH eb 500 mA ILP Leakage Current, Low g10 mA 0.0V s VI s VCC Power Mode (5) RDIFF Input Differential Resistance (6) 10 k X dc VIDF(TPE)(7) Input Differential Accept g0.500 g3.1 V P 5 MHz s f s 10 MHz Input Differential Reject g0.300 V P Input Differential Accept (XSQ) (Note 8) g3.1 V P Input Differential Reject (XSQ) g0.180 V P RS(TPE)(8) Output Source Resistance 6 13 X lILOADl e 25 mA VIDF(AUI)(9) Input Differential Accept g0.300 g1.5 V P Input Differential Reject g0.160 V P VODF(AUI)(10) Output Differential Voltage g0.450 g1.20 V NOTES: 1. The voltage levels for RCV, CLSN, and RD pairs are b0.75V to a8.5V. 2. TTL Input Pins: TxD, RTS , TPE/AUI , APORT, APOL/XSQ, LID, CS0, CS1, LPBK , JABD, TEST, RESET. 3. MOS Output Pins: TxC , RxD, RxC , CRS , CDT . 4. LED Pins: TPE/AUI , TxLED, RxLED, COLED, POLED, LILED. V OL measured 10 ns after falling edge of TxC . 5. Pins: APORT, APOL/XSQ, LID, TPE/AUI , POLED, LILED, RTS , LPBK , RxD, TxD, CRS , CDT, CS0, CS1, JABD, TEST, and RESET. 6. Pins: RD to RD , RCV to RCV , and CLSN to CLSN . 8. Typically it is b4.5 dB below normal squelch level. 9. TPE Output Pins: TDH, TDH , TDL, and TDL .R S measures V CC or V SS to Pin. 10. AUI Input Pins: RCV, and CLSN pairs. 11. AUI Output Pins: TRMT pair.
Figure 16. Transmit Timing (Intel)
Figure 17. Receive Timing (Intel)
- All delay and width measurements on TxC are made at 1.5V.
Figure 18. Transmit Timing (National)
- All delay and width measurements on RXC are made at 1.5V.
Figure 19. Receiving Timings (National)
- Delay times for TX, TENA, and TCLK are measured from 0.8V for falling edges, and 2.0V for rising edges.
Figure 20. Transmit Timings (AMD)
- Timing measurements are referenced at 1.5V level.
Figure 23. Transmit Timings (Fujitsu)
- Guarantees proper processing of transmitted packets. Violation of this specification will not result in spurious data trans-
Figure 38. Loopback Timings
- Guarantees Proper processing of data packets. Violation of these specifications will not affect the integrity of the network.
- Mode pins are: APORT, APOL/XSQ, LID, JABD, and TPE/AUI
- Any data received within 100 ms of a mode transmission will be considered invalid.
Figure 41. Mode Timings
Figure 51. Detail L. Terminal Details dimensions in mm that are specific to the 44-lead PLCC package.
- All dimensions and tolerances conform to ANSI Y14.5M-1982.
- Datum plane ÐHÐ located at top of mold parting line and coincident with top of lead, where lead exits plastic body.
- Datums D–E and F–G to be determined where center leads exit plastic body at datum plane ÐHÐ.
- To be determined at seating plane ÐCÐ.
1 and E 1 do not include mold protrusion.
- Pin 1 identifier is located within one of the two defined zones.
- Locations to datum ÐAÐ and ÐBÐ to be determined at plane ÐHÐ.
- These two dimensions determine maximum angle of the lead for certain socket applications. If unit is intended to be
socketed, it is advisable to review these dimensions with the socket supplier.
- Controlling dimension, inch.
- All dimensions and tolerances include lead trim offset and lead plating finish.
- Tweezing surface planarity is defined as the furthest any lead on a side may be from the datum. The datum is estab-
lished by touching the outermost lead on that side and parallel to D–E or F–G .
Figure 52. 44-Lead Quad Flatpack Package Unless otherwise specified, all units are in millimeters.