82433LX INTEL | Alldatasheet
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- 4.0 ELECTRICAL CHARACTERISTICS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
- 4.1 Absolute Maximum Ratings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
- 4.2 Thermal Characteristics ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
- 4.3 DC Characteristics ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
- 4.4.1 HOST AND PCI CLOCK TIMING, 66 MHz (82433LX) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
- 4.4.2 COMMAND TIMING, 66 MHz (82433LX) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
- 4.4.3 ADDRESS, DATA, TRDY Ý, EOL, TEST, TSCON AND PARITY TIMING, 66 MHz
- 4.4.4 HOST AND PCI CLOCK TIMING, 60 MHz (82433LX) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
- 4.4.5 COMMAND TIMING, 60 MHz (82433LX) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
- 4.4.6 ADDRESS, DATA, TRDY Ý, EOL, TEST, TSCON AND PARITY TIMING, 60 MHz
- 4.4.7 TEST TIMING (82433LX) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
- 4.5.1 HOST AND PCI CLOCK TIMING (82433NX) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
- 4.5.2 COMMAND TIMING (82433NX) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
- 4.5.3 ADDRESS, DATA, TRDY Ý, EOL, TEST, TSCON AND PARITY TIMING
- 4.5.4 TEST TIMING (82433NX) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
- 4.5.5 TIMING DIAGRAMS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
- 5.0 PINOUT AND PACKAGE INFORMATION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
- 5.1 Pin Assignment ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
- 5.2 Package Information ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
- 6.0 TESTABILITY ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
- 6.1 NAND Tree ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
- 6.1.1 TEST VECTOR TABLE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
- 6.1.2 NAND TREE TABLE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
- 6.2 PLL Test Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
December 1995 Order Number: 290478-004 82433LX/82433NX LOCAL BUS ACCELERATOR (LBX) Y Supports the Full 64-bit Pentium É Processor Data Bus at Frequencies up to 66 MHz (82433LX and 82433NX) Y Drives 3.3V Signal Levels on the CPU Data and Address Buses (82433NX) Y Provides a 64-Bit Interface to DRAM and a 32-Bit Interface to PCI Y Five Integrated Write Posting and Read Prefetch Buffers Increase CPU and PCI Performance Ð CPU-to-Memory Posted Write Buffer
4 Qwords Deep
Ð PCI-to-Memory Posted Write Buffer Two Buffers, 4 Dwords Each Ð PCI-to-Memory Read Prefetch Buffer Ð CPU-to-PCI Posted Write Buffer
4 Dwords Deep
Ð CPU-to-PCI Read Prefetch Buffer Y CPU-to-Memory and CPU-to-PCI Write Posting Buffers Accelerate Write Performance Y Dual-Port Architecture Allows Concurrent Operations on the Host and PCI Buses Y Operates Synchronously to the CPU and PCI Clocks Y Supports Burst Read and Writes of Memory from the Host and PCI Buses Y Sequential CPU Writes to PCI Converted to Zero Wait-State PCI Bursts with Optional TRDY Ý Connection Y Byte Parity Support for the Host and Memory Buses Ð Optional Parity Generation for Host to Memory Transfers Ð Optional Parity Checking for the Secondary Cache Ð Parity Checking for Host and PCI Memory Reads Ð Parity Generation for PCI to Memory Writes Y 160-Pin QFP Package Two 82433LX or 82433NX Local Bus Accelerator (LBX) components provide a 64-bit data path between the host CPU/Cache and main memory, a 32-bit data path between the host CPU bus and PCI Local Bus, and a 32-bit data path between the PCI Local Bus and main memory. The dual-port architecture allows concurrent operations on the host and PCI Buses. The LBXs incorporate three write posting buffers and two read prefetch buffers to increase CPU and PCI performance. The LBX supports byte parity for the host and main memory buses. The 82433NX is intended to be used with the 82434NX PCI/Cache/Memory Controller (PCMC). The 82433LX is intended to be used with the 82434LX PCMC. During bus operations between the host, main memory and PCI, the PCMC commands the LBXs to perform functions such as latching address and data, merging data, and enabling output buffers. Together, these three components form a ‘‘Host Bridge’’ that provides a full function dual-port data path interface, linking the host CPU and PCI bus to main memory. This document describes both the 82433LX and 82433NX. Shaded areas, like this one, describe the 82433NX operations that differ from the 82433LX.
290478–1 LBX Simplified Block Diagram
LOCAL BUS ACCELERATOR (LBX) CONTENTS PAGE
1.0 ARCHITECTURAL OVERVIEW ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5
1.1 Buffers in the LBX ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5
1.2 Control Interface Groups ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7
1.3 System Bus Interconnect ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7
1.4 PCI TRDY Ý Interface ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8
1.5 Parity Support ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8
2.0 SIGNAL DESCRIPTIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8
2.1 Host Interface Signals ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 9
2.2 Main Memory (DRAM) Interface Signals ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 10
2.3 PCI Interface Signals ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 10
2.4 PCMC Interface Signals ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 10
2.5 Reset and Clock Signals ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 11
3.0 FUNCTIONAL DESCRIPTION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 12
3.1 LBX Post and Prefetch Buffers ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 12
3.1.1 CPU-TO-MEMORY POSTED WRITE BUFFER ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 12
3.1.2 PCI-TO-MEMORY POSTED WRITE BUFFER ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 12
3.1.3 PCI-TO-MEMORY READ PREFETCH BUFFER ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 12
3.1.4 CPU-TO-PCI POSTED WRITE BUFFER ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 13
3.1.5 CPU-TO-PCI READ PREFETCH BUFFER ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 14
3.2 LBX Interface Command Descriptions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 14
3.2.1 HOST INTERFACE GROUP: HIG [4:0] ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 14
3.2.2 MEMORY INTERFACE GROUP: MIG [2:0] ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 18
3.2.3 PCI INTERFACE GROUP: PIG [3:0] ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 19
3.3 LBX Timing Diagrams ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 21
3.3.1 HIG [4:0] COMMAND TIMING ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 21
3.3.2 HIG [4:0] MEMORY READ TIMING ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22
3.3.3 MIG [2:0] COMMAND ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 23
3.3.4 PIG [3:0] COMMAND, DRVPCI, AND PPOUT TIMING ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 24
3.3.5 PIG [3:0]: READ PREFETCH BUFFER COMMAND TIMING ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 25
3.3.6 PIG [3:0]: END-OF-LINE WARNING SIGNAL: EOL ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 27
3.4 PLL Loop Filter Components ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 29
3.5 PCI Clock Considerations ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 30
1.0 ARCHITECTURAL OVERVIEW
The 82430 PCIset consists of the 82434LX PCMC and 82433LX LBX components plus either a PCI/ ISA bridge or a PCI/EISA bridge. The 82430NX PCI- set consists of the 82434NX PCMC and 82433NX LBX components plus either a PCI/ISA bridge or a PCI/EISA bridge. The PCMC and LBX provide the core cache and main memory architecture and serves as the Host/PCI bridge. An overview of the PCMC follows the system overview section. The Local Bus Accelerator (LBX) provides a high performance data and address path for the 82430LX/82430NX PCIset. The LBX incorporates five integrated buffers to increase the performance of the Pentium processor and PCI master devices. Two LBXs in the system support the following areas: 1. 64-bit data and 32-bit address bus of the Pentium processor. 2. 32-bit multiplexed address/data bus of PCI. 3. 64-bit data bus of the main memory. In addition, the LBXs provide parity support for the three areas noted above (discussed further in Sec- tion 1.4).
1.1 Buffers in the LBX
The LBX components have five integrated buffers designed to increase the performance of the Host and PCI Interfaces of the 82430LX/82430NX PCIset. With the exception of the PCI-to-Memory write buffer and the CPU-to-PCI write buffer, the buffers in the LBX store data only, addresses are stored in the PCMC component.
- CPU-to-Memory Posted Write Buffer: This buffer is 4 Qwords deep, enabling the Pentium processor to write back a
whole cache line in 4-1-1-1 timing, a total of 7 CPU clocks.
- PCI-to-Memory Posted Write Buffer: A PCI master can post two consecutive sets of 4 Dwords (total of one cache
line) or two single non-consecutive transactions.
- PCI-to-Memory Read Prefetch Buffer: A PCI master to memory read transaction will cause this prefetch buffer to
read up to 4 Qwords of data from memory, allowing up to 8 Dwords to be read onto PCI in a single burst transaction.
- CPU-to-PCI Posted Write Buffer: The Pentium processor can post up to 4 Dwords into this buffer. The TRDY Ý
- CPU-to-PCI Read Prefetch Buffer: This prefetch buffer is 4 Dwords deep, enabling faster sequential Pentium proc-
essor reads when targeting PCI. Figure 1. Simplified Block Diagram of the LBX Data Buffers
1.2 Control Interface Groups
- Host Interface Group: These control signals are
- Memory Interface Group: These control signals
- PCI Interface Group: These control signals are
buffering and storing PCI data and/or address.
1.3 System Bus Interconnect
to the 32-bit PCI AD [31:0] bus with 16 bits each. host address bus, A [31:16]. Figure 2. Simplified Interconnect Diagram of LBXs to System Buses
1.4 PCI TRDY Ý Interface
data when a PCI master targets main memory.
1.5 Parity Support
2.0 SIGNAL DESCRIPTIONS
tional groups according to their associated interface. when at the high voltage level. gate,o r negation indicates that a signal is inactive. in Input is a standard input-only signal. out Totem Pole output is a standard active driver. Figure 3. LBX Signals
2.1 Host Interface Signals
A[15:0] t/s ADDRESS BUS: The bi-directional A [15:0] lines are connected to the address lines of the host bus. The high order LBX (determined at reset time using the EOL signal) is connected to A [31:16], and the low order LBX is connected to A [15:0]. The host address bus is common with the Pentium processor, second level cache, PCMC and the two LBXs. During CPU cycles A [31:3] are driven by the CPU and A [2:0] are driven by the PCMC, all are inputs to the LBXs. During inquire cycles the LBX drives the PCI master address onto the host address lines A [31:0]. This snoop address is driven to the CPU and the PCMC by the LBXs to snoop L1 and the integrated second level tags, respectively. During PCI configuration cycles bound for the PCMC, the LBXs will send or receive the configuration data to/from the PCMC by copying the host data bus to/from the host address bus. The LBX drives both halves of the Qword host data bus with data from the 32-bit address during PCMC configuration read cycles. The LBX drives the 32-bit address with either the low Dword or the high Dword during PCMC configuration write cycles. In the 82433NX, these pins contain weak internal pull-down resistors. The high order 82433NX LBX samples A11 at the falling edge of reset to configure the LBX for PLL test mode. When A11 is sampled low, the LBX is in normal operating mode. When A11 is sampled high, the LBX drives the internal HCLK from the PLL on the EOL pin. Note that A11 on the high order LBX is connected to the A27 line on the CPU address bus. This same address line is used to put the PCMC into PLL test mode. D[31:0] t/s HOST DATA: The bi-directional D [31:0] lines are connected to the data lines of the host data bus. The high order LBX (determined at reset time using the EOL signal) is connected to the host data bus D [63:48] and D [31:16] lines, and the low order LBX is connected to the host data bus D [47:32] and D [15:0] lines. In the 82433LX, these pins contain weak internal pull-up resistors. In the 82433NX, these pins contain weak internal pull-down resistors. HP[3:0] t/s HOST DATA PARITY: HP[3:0] are the bi-directional byte parity signals for the host data bus. The low order parity bit HP [0] corresponds to D [7:0] while the high order parity bit HP[3] corresponds to D [31:24]. The HP [3:0] signals function as parity inputs during write cycles and as parity outputs during read cycles. Even parity is supported and the HP [3:0] signals follow the same timings as D [31:0]. In the 82433LX, these pins contain weak internal pull-up resistors. In the 82433NX, these pins contain weak internal pull-down resistors.
2.2 Main Memory (Dram) Interface Signals
MD[31:0] t/s MEMORY DATA BUS: MD[31:0] are the bi-directional data lines for the memory data bus. The high order LBX (determined at reset time using the EOL signal) is connected to the memory data bus MD [63:48] and MD [31:16] lines, and the low order LBX is connected to the memory data bus MD [47:32] and MD [15:0] lines. The MD [31:0] signals drive data destined for either the host data bus or the PCI bus. The MD [31:0] signals input data that originated from either the host data bus or the PCI bus. These pins contain weak internal pull-up resistors. MP[3:0] t/s MEMORY PARITY: MP[3:0] are the bi-directional byte enable parity signals for the memory data bus. The low order parity bit MP [0] corresponds to MD [7:0] while the high order parity bit MP [3] corresponds to MD [31:24]. The MP [3:0] signals are parity outputs during write cycles to memory and parity inputs during read cycles from memory. Even parity is supported and the MP [3:0] signals follow the same timings as MD [31:0]. These pins contain weak internal pull-up resistors.
2.3 PCI Interface Signals
AD[15:0] t/s ADDRESS AND DATA: AD[15:0] are bi-directional data lines for the PCI bus. The AD[15:0] signals sample or drive the address and data on the PCI bus. The high order LBX (determined at reset time using the EOL signal) is connected to the PCI bus AD[31:16] lines, and the low order LBX is connected to the PCI AD [15:0] lines. TRDYÝ in TARGET READY: TRDYÝ indicates the selected (targeted) device’s ability to complete the current data phase of the bus operation. For normal operation, TRDY Ý is tied asserted low. When the TRDY Ý option is enabled in the PCMC (for zero wait-state PCI burst writes), TRDY Ý should be connected to the PCI bus.
2.4 PCMC Interface Signals
HIG[4:0] in HOST INTERFACE GROUP: These signals are driven from the PCMC and control the host interface of the LBX. The 82433LX decodes the binary pattern of these lines to perform 29 unique functions (30 for the 83433NX). These signals are synchronous to the rising edge of HCLK. MIG[2:0] in MEMORY INTERFACE GROUP: These signals are driven from the PCMC and control the memory interface of the LBX. The LBX decodes the binary pattern of these lines to perform 7 unique functions. These signals are synchronous to the rising edge of HCLK. PIG[3:0] in PCI INTERFACE GROUP: These signals are driven from the PCMC and control the PCI interface of the LBX. The LBX decodes the binary pattern of these lines to perform 15 unique functions. These signals are synchronous to the rising edge of HCLK. MDLE in MEMORY DATA LATCH ENABLE: During CPU reads from DRAM, the LBX uses a clocked register to transfer data from the MD [31:0] and MP [3:0] lines to the D [31:0] and HP[3:0] lines. MDLE is the clock enable for this register. Data is clocked into this register when MDLE is asserted. The register retains its current value when MDLE is negated. During CPU reads from main memory, the LBX tri-states the D [31:0] and HP [3:0] lines on the rising edge of MDLE when HIG [4:0] eNOPC. DRVPCI in DRIVE PCI BUS: This signals enables the LBX to drive either address or data information onto the PCI AD [15:0] lines.
2.4 PCMC Interface Signals (Continued)
EOL t/s End Of Line: This signal is asserted when a PCI master read or write transaction is about to overrun a cache line boundary. The low order LBX will have this pin connected to the PCMC (internally pulled up in the PCMC). The high order LBX connects this pin to a pull- down resistor. With one LBX EOL line being pulled down and the other LBX EOL pulled up, the LBX samples the value of this pin on the negation of the RESET signal to determine if it’s the high or low order LBX. PPOUT t/s LBX PARITY: This signal reflects the parity of the 16 AD lines driven from or latched into the LBX, depending on the command driven on PIG [3:0]. The PCMC uses PPOUT from both LBXs (called PPOUT [1:0]) to calculate the PCI parity signal (PAR) for CPU to PCI transactions during the address phase of the PCI cycle. The LBX uses PPOUT to check the PAR signal for PCI master transactions to memory during the address phase of the PCI cycle. When transmitting data to PCI the PCMC uses PPOUT to calculate the proper value for PAR. When receiving data from PCI the PCMC uses PPOUT to check the value received on PAR. If the L2 cache does not implement parity, the LBX will calculate parity so the PCMC can drive the correct value on PAR during L2 reads initiated by a PCI master. The LBX samples the PPOUT signal at the negation of reset and compares that state with the state of EOL to determine whether the L2 cache implements parity. The PCMC internally pulls down PPOUT [0] and internally pulls up PPOUT [1]. The L2 supports parity if PPOUT [0] is connected to the high order LBX and PPOUT [1] is connected to the low order LBX. The L2 is defined to not support parity if these connections are reversed, and for this case, the LBX will calculate parity. For normal operations either connection allows proper parity to be driven to the PCMC.
2.5 Reset and Clock Signals
HCLK in HOST CLOCK: HCLK is input to the LBX to synchronize command and data from the host and memory interfaces. This input is derived from a buffered copy of the PCMC HCLKx output. PCLK in PCI CLOCK: All timing on the LBX PCI interface is referenced to the PCLK input. All output signals on the PCI interface are driven from PCLK rising edges and all input signals on the PCI interface are sampled on PCLK rising edges. This input is derived from a buffered copy of the PCMC PCLK output. RESET in RESET: Assertion of this signal resets the LBX. After RESET has been negated the LBX configures itself by sampling the EOL and PPOUT pins. RESET is driven by the PCMC CPURST pin. The RESET signal is synchronous to HCLK and must be driven directly by the PCMC. LP1 out LOOP 1: Phase Lock Loop Filter pin. The filter components required for the LBX are connected to these pins. LP2 in LOOP 2: Phase Lock Loop Filter pin. The filter components required for the LBX are connected to these pins. TEST in TEST: The TEST pin must be tied low for normal system operation. TSCON in TRI-STATE CONTROL: This signal enables the output buffers on the LBX. This pin must be held high for normal operation. If TSCON is negated, all LBX outputs will tri-state.
3.0 FUNCTIONAL DESCRIPTION
3.1 LBX Post and Prefetch Buffers
This section describes the five write posting and read prefetching buffers implemented in the LBX. The discussion in this section refers to the operation of both LBXs in the system.
3.1.1 CPU-TO-MEMORY POSTED WRITE
The write buffer is a queue 4 Qwords deep, it loads Qwords from the CPU and stores Qwords to memo- ry. It is 4 Qwords deep to accommodate write-backs from the first or second level cache. It is organized as a simple FIFO. Commands driven on the HIG [4:0] lines store Qwords into the buffer, while commands on the MIG [2:0] lines retire Qwords from the buffer. While retiring Qwords to memory, the DRAM control- ler unit of the PCMC will assert the appropriate MA, CAS[7:0] Ý, and WE Ý signals. The PCMC keeps track of full/empty states, status of the data and address. Byte parity for data to be written to memory is either propagated from the host bus or generated by the LBX. The LBX generates parity for data from the second level cache when the second level cache does not implement parity.
3.1.2 PCI-TO-MEMORY POSTED WRITE BUFFER
The buffer is organized as 2 buffers (4 Dwords each). There is an address storage register for each buffer. When an address is stored one of the two buffers is allocated and subsequent Dwords of data are stored beginning at the first location in that buff- er. Buffers are retired to memory strictly in order, Qword at a time. Commands driven on the PIG [3:0] lines post ad- dresses and data into the buffer. Commands driven on HIG [4:0] result in addresses being driven on the host address bus. Commands driven on MIG [2:0] result in data being retired to DRAM. For cases where the address targeted by the first Dword is odd, i.e. A [2] e1, and the data is stored in an even location in the buffer, the LBX correctly aligns the Dword when retiring the data to DRAM. In other words the buffer is capable of retiring a Qword to memory where the data in the buffer is shifted by
1 Dword (Dword is position 0 shifted to 1, 1 shifted
to 2 etc.). The DRAM controller of the PCMC asserts the correct CAS [7:0] Ý signals depending on the PCI C/BE[3:0]Ý signals stored in the PCMC for that Dword. The End Of Line (EOL) signal is used to prevent PCI master writes from bursting past the cache line boundary. The device that provides ‘‘warning’’ to the PCMC is the low order LBX. This device contains the PCI master write low order address bits necessary to determine how many Dwords are left to the end of the line. Consequently, the LBX protocol uses the EOL signal from the low order LBX to provide this ‘‘end-of-line’’ warning to the PCMC, so that it may retry a PCI master write when it bursts past the cache line boundary. This protocol is described fully in Section 3.3.6. The LBX calculates Dword parity on PCI write data, sending the proper value to the PCMC on PPOUT. The LBX generates byte parity on the MP signals for writing into DRAM.
3.1.3 PCI-TO-MEMORY READ PREFETCH
This buffer is organized as a line buffer (4 Qwords) for burst transfers to PCI. The data is transferred into the buffer a Qword at a time and read out a Dword at a time. The LBX then effectively decouples the memory read rate from the PCI rate to increase con- currence. Each new transaction begins by storing the first Dword in the first location in the buffer. The starting Dword for reading data out of the buffer onto PCI must be specified within a Qword boundary; that is the first requested Dword on PCI could be an even or odd Dword. If the snoop for a PCI master read results in a write-back from first or second level caches, this write back is sent directly to PCI and main memory. The following two paragraphs de- scribe this process for cache line write-backs. Since the write-back data from L1 is in linear order, writing into the buffer is straightforward. Only those Qwords to be transferred into PCI are latched into the PCI-to-memory read buffer. For example, if the address targeted by PCI is in the 3rd or 4th Qword in the line, the first 2 Qwords of write back data are discarded and not written into the read buffer. The primary cache write-back must always be written
completely to the CPU-to-Memory posted Write Buffer. If the PCI master read data is read from the second- ary cache, it is not written back to memory. Write- backs from the second level cache, when using burst SRAMs, are in Pentium processor burst order (the order depending on which Qword of the line is targeted by the PCI read). The buffer is directly ad- dressed when latching second level cache write- back data to accommodate this burst order. For ex- ample, if the requested Qword is Qword 1, then the burst order is 1-0-3-2. Qword 1 is latched in buffer location 0, Qword 0 is discarded, Qword 3 is latched into buffer location 2 and Qword 2 is latched into buffer location 1. Commands driven on MIG [2:0] and HIG [4:0] enter data into the buffer from the DRAM interface and the host interface (i.e. the caches), respectively. Com- mands driven on the PIG [3:0] lines drive data from the buffer onto the PCI AD [31:0] lines. Parity driven on the PPOUT signal is calculated from the byte parity received on the host bus or the mem- ory bus, whichever is the source. If the second level cache is the source of the data and does not imple- ment parity, the parity driven on PPOUT is generated by the LBX from the second level cache data. If main memory is the source of the read data, PCI parity is calculated from the DRAM byte parity. Main memory must implement byte parity to guarantee correct PCI parity generation.
3.1.4 CPU-TO-PCI POSTED WRITE BUFFER
The CPU-to-PCI Posted Write Buffer is 4 Dwords deep. The buffer is constructed as a simple FIFO, with some performance enhancements. An address is stored in the LBX with each Dword of data. The structure of the buffer accommodates the packetiza- tion of writes to be burst on PCI. This is accom- plished by effectively discarding addresses of data Dwords driven within a burst. Thus, while an address is stored for each Dword, an address is not neces- sarily driven on PCI for each Dword. The PCMC de- termines when a burst write may be performed based on consecutive addresses. The buffer also enables consecutive bytes to be merged within a single Dword, accommodating byte, word, and misa- ligned Dword string store and string move opera- tions. Qword writes on the host bus are stored within the buffer as two individual Dword writes, with sepa- rate addresses. The storing of an address with each Dword of data allows burst writes to be retried easily. In order to retry transactions, the FIFO is effectively ‘‘backed up’’ by one Dword. This is accomplished by making the FIFO physically one entry larger than it is logical- ly. Thus, the buffer is physically 5 entries deep (an entry consists of an address and a Dword of data), while logically it is considered full when 4 entries have been posted. This design allows the FIFO to be backed up one entry when it is logically full. Commands driven on HIG [4:0] post addresses and data into the buffer, and commands driven on PIG[3:0] retire addresses and data from the buffer and drive them onto the PCI AD [31:0] lines. As dis- cussed previously, when bursting, not all addresses are driven onto PCI. Data parity driven on the PPOUT signal is calculated from the byte parity received on the host bus. Ad- dress parity driven on PPOUT is calculated from the address received on the host bus.
3.1.5 CPU-TO-PCI READ PREFETCH BUFFER
This prefetch buffer is organized as a single buffer 4 Dwords deep. The buffer is organized as a simple FIFO. reads from the buffer are sequential; the buff- er does not support random access of its contents. To support reads of less than a Dword the FIFO read pointer can function with or without a pre-incre- ment. The pointer can also be reset to the first entry before a Dword is driven. When a Dword is read, it is driven onto both halves of the host data bus. Commands driven on the HIG [4:0] lines enable read addresses to be sent onto PCI, the addresses are driven using PIG [3:0] commands. Read data is latched into the LBX by commands driven on the PIG[3:0] lines and the data is driven onto the host data bus using commands driven on the HIG [4:0] lines. The LBX calculates Dword parity on PCI read data, sending the proper value to the PCMC on PPOUT. The LBX does not generate byte parity on the host data bus when the CPU reads PCI.
3.2 LBX Interface Command
This section describes the functionality of the HIG, MIG and PIG commands driven by the PCMC to the LBXs.
3.2.1 HOST INTERFACE GROUP: HIG [4:0]
The Host Interface commands are shown in Table 1. These commands are issued by the host interface of the PCMC to the LBXs in order to perform the fol- lowing functions: # Reads from CPU-to-PCI read prefetch buffer when the CPU reads from PCI. # Stores write-back data to PCI-to-memory read prefetch buffer when PCI read address results in a hit to a modified line in first or second level caches. # Posts data to CPU-to-memory write buffer in the case of a CPU to memory write. # Posts data to CPU-to-PCI write buffer in the case of a CPU to PCI write. # Drives host address to Data lines and data to ad- dress lines for programming the PCMC configura- tion registers.
Table 1. HIG Commands All other patterns are reserved.
NOPC No Operation is performed on the host bus by the LBX hence it tri-states its host bus drivers. CMR This command effectively drives DRAM data onto the host data bus. The LBX acts as a transparent latch in this mode, depending on MDLE for latch control. With the MDLE signal high the CMR command will cause the LBXs to buffer memory data onto the host bus. When MDLE is low. The LBX will drive onto the host bus whatever memory data that was latched when MDLE was negated. CPRF This command reads the first Dword of the CPU-to-PCI read prefetch buffer. The read pointer of the FIFO is set to point to the first Dword. The Dword is driven onto the high and low halves of the host data bus. CPRA This command increments the read pointer of the CPU-to-PCI read pre- fetch buffer FIFO and drives that Dword onto the host bus when it is driven after a CPRF or CPRB com- mand. If driven after another CPRA command, the LBX drives the current Dword while the read pointer of the FIFO is not incremented. The Dword is driven onto the upper and lower halves of the host data bus. CPRB This command increments the read pointer of the CPU-to-PCI read pre- fetch buffer FIFO and drives that Dword onto the host bus when it is driven after a CPRA command. If driv- en after another CPRB command, the LBX drives the current Dword while the read pointer of the FIFO is not incre- mented. The Dword is driven onto the upper and lower halves of the host data bus. CPRQ This command drives the first Dword stored in the CPU-to-PCI read prefetch buffer onto the lower half of the host data bus, and drives the second Dword onto the upper half of the host data bus, regardless of the state of the read pointer. The read pointer is not affect- ed by this command. SWB0 This command stores a Qword from the host data lines into location 0 of the PCI-to-Memory Read Buffer. Parity is either generated for the data or prop- agated from the host bus based on the state of the PPOUT signals sampled at the negation of RESET when the LBXs were initialized. SWB1 This command, (similar to SWB0), stores a Qword from the host data lines into location 1 of the PCI-to-Mem- ory Read Buffer. Parity is either gener- ated from the data or propagated from the host bus based on the state of the PPOUT signal sampled at the falling edge of RESET. SWB2 This command, (similar to SWB0), stores a Qword written back from the first or second level cache into location 2 of the PCI-to-memory read buffer. Parity is either generated from the data or propagated from the host bus based on the state of the PPOUT signal sam- pled at the falling edge of RESET. SWB3 This command stores a Qword from the host data lines into location 3 of the PCI-to-Memory Read Buffer. Parity is either generated for the data or prop- agated from the host bus based on the state of the PPOUT signal sampled at the falling edge of RESET. PCMWQ This command posts one Qword of data from the host data lines to CPU- to-Memory Write Buffer in case of a CPU memory write or a write-back from the second level cache. PCMWFQ If the PCI Memory read address leads to a hit on a modified line in the first level cache, then a write-back is scheduled and this data has to be writ- ten into the CPU-to-Memory Write Buff- er and PCI-to-Memory Read Buffer at the same time. The write-back of the first Qword is done by this command to both the buffers. PCMWNQ This command follows the previous command to store or post subsequent write-back Qwords.
PCPWL This command posts the low Dword of a CPU-to-PCI write. The CPU-to-PCI Write Buffer stores a Dword of PCI ad- dress for every Dword of data. Hence, this command also stores the address of the Low Dword in the address loca- tion for the data. Address bit 2 (A2) is not stored directly. This command as- sumes a value of 0 for A2 and this is what is stored. MCP3L This command merges the 3 most sig- nificant bytes of the low Dword of the host data bus into the last Dword post- ed to the CPU-to-PCI write buffer. The address is not modified. MCP2L This command merges the 2 most sig- nificant bytes of the low Dword of the host data bus into the last Dword post- ed to the CPU-to-PCI write buffer. The address is not modified. MCP1L This command merges the most signif- icant byte of the low Dword of the host data bus into the last Dword posted to the CPU-to-PCI write buffer. The ad- dress is not modified. PCPWH This command posts the upper Dword of a CPU-to-PCI write, with its address, into the address location. Hence, to do a Qword write PCPWL has to be fol- lowed by a PCPWH. Address bit 2 (A2) is not stored directly. This command forces a value of 1 for A2 and this is what is stored. MCP3H This command merges the 3 most sig- nificant bytes of the high Dword of the host data bus into the last Dword post- ed to the CPU-to-PCI Write Buffer. The address is not modified. MCP2H This command merges the 2 most sig- nificant bytes of the high Dword of the host data bus into the last Dword post- ed to the CPU-to-PCI Write Buffer. The address is not modified. MCP1H This command merges the most signif- icant byte of the high Dword of the host data bus into the last Dword posted to the CPU-to-PCI Write Buffer. The ad- dress is not modified. LCPRAD This command latches the host ad- dress to drive on PCI for a CPU-to-PCI read. It is necessary to latch the ad- dress in order to drive inquire address- es on the host address bus before the CPU address is driven onto PCI. DPRA The PCI memory read address is latched in the PCI A/D latch by a PIG command LCPRAD, this address is driven onto the host address bus by DPRA. Used in PCI to memory read transaction. DPWA The DPWA command drives the ad- dress of the current PCI Master Write Buffer onto the host address bus. This command is potentially driven for multi- ple cycles. When it is no longer driven, the read pointer will increment to point to the next buffer, and a subsequent DPWA command will read the address from that buffer. ADCPY This command drives the host data bus with the host address. The ad- dress is copied on the high and low halves of the Qword data bus; i.e. A[31:0] is copied onto D [31:0] and D[63:32]. This command is used when the CPU writes to the PCMC configura- tion registers. DACPYH This command drives the host address bus with the high Dword of host data. This command is used when the CPU writes to the PCMC configuration regis- ters. DACPYL This command drives the host address bus with the low Dword of host data. This command is used when the CPU writes to the PCMC configuration regis- ters. PSCD This command is used to post the val- ue of the Special Cycle code into the CPU-to-PCI Posted Write Buffer. The value is driven onto the A [31:0] lines by the PCMC, after acquiring the ad- dress bus by asserting AHOLD. The value on the A [31:0] lines is posted into the DATA location in the CPU-to- PCI Posted Write Buffer. DRVFF This command causes the LBX to drive all ‘‘1s’’ (i.e. FFFFFFFFh) onto the host data bus. It is used for CPU reads from PCI that terminate with master abort. PCPWHC This command posts the high half of the CPU data bus. The LBXs post the high half of the data bus even if A2 from the PCMC is low. This command is used during configuration writes when using PCI configuration access mechanism Ý1.
3.2.2 MEMORY INTERFACE GROUP: MIG [2:0]
# Retires data from CPU-to-Memory Write Buffer to DRAM. # Stores data into PCI-to-Memory Read Buffer when the PCI read address is targeted to DRAM. # Retires PCI-to-Memory Write Buffer to DRAM. Table 2. MIG Commands All other patterns are reserved. er is 8 Dwords or 1 cache line deep. read data from the next buffer.
3.2.3 PCI INTERFACE GROUP: PIG [3:0]
The PCI Interface commands are shown in Table 3. that it can be gated to the host address bus. # Master retires CPU-to-PCI write buffer. # Master sends CPU-to-PCI address to the AD bus. AD[31:0] lines, and the PPOUT signals. Table 3. PIG Commands All other patterns are reserved.
PPMWA This command selects a new buffer and places the PCI master address latch value into the address register for that buffer. The next PPMWD command posts write data in the first location of this newly selected buff- er. This command also causes the EOL logic to decrement the count of Dwords remaining in the line. PPMWD This command stores the value in the AD latch into the next data loca- tion in the currently selected buffer. This command also causes the EOL logic to decrement the count of Dwords remaining in the line. SPMRH This command sends the high order Dword from the first Qword of the PCI-to-Memory Read Buffer onto PCI. This command also causes the EOL logic to decrement the count of Dwords remaining in the line. SPMRL This command sends the low order Dword from the first Qword of the PCI-to-Memory Read Buffer onto PCI. This command also selects the Dword alignment for the transaction and causes the EOL logic to decre- ment the count of Dwords remaining in the line. SPMRN This command sends the next Dword from the PCI-to-Memory Read Buffer onto PCI. This com- mand also causes the EOL logic to decrement the count of Dwords re- maining in the line. This command is used for the second and all subse- quent Dwords of the current transac- tion. LCPRF This command acquires the value of the AD [31:0] lines into the first loca- tion in the CPU-to-PCI Read Pre- fetch Buffer until a different com- mand is driven. LCPRA When driven after a LCPRF or LCPRB command, this command latches the value of the AD [31:0] lines into the next location into the CPU-to-PCI Read Prefetch Buffer. When driven after another LCPRA command, this command latches the value on AD [31:0] into the same location in the CPU-to-PCI Read Prefetch Buffer, overwriting the pre- vious value. LCPRB When driven after a LCPRA com- mand, this command latches the val- ue of the AD [31:0] lines into the next location into the CPU-to-PCI Read Prefetch Buffer. When driven after another LCPRB command, this com- mand latches the value on AD [31:0] into the same location in the CPU-to- PCI Read Prefetch Buffer, overwrit- ing the previous value. DCPWA This command drives the next ad- dress in the CPU-to-PCI Write Buffer onto PCI. The read pointer of the FIFO is not incremented. DCPWD This command drives the next data Dword in the CPU-to-PCI Write Buff- er onto PCI. The read pointer of the FIFO is incremented on the next PCLK if TRDY Ý is asserted. DCPWL This command drives the previous data Dword in the CPU-to-PCI Write Buffer onto PCI. This is the data which was driven by the last DCPWD command. The read pointer of the FIFO is not incremented. DCCPD This command discards the current Dword in the CPU-to-PCI Write Buff- er. This is used to clear write data when the write transaction termi- nates with master abort, where TRDY Ý is never asserted. BCPWR For this command the CPU-to-PCI Write Buffer is ‘‘backed up’’ one en- try such that the address/data pair last driven with the DCPWA and DCPWD commands will be driven again on the AD [31:0] lines when the commands are driven again. This command is used when the tar- get has retried the write cycle. SCPA This command drives the value on the host address bus onto PCI. LPMA This command stores the previous AD[31:0] value into the PCI master address latch. If the EOL logic deter- mines that the requested Dword is the last Dword of a line, then the EOL signal will be asserted; other- wise the EOL signal will be negated.
3.3 LBX Timing Diagrams
3.3.1 HIG [4:0] COMMAND TIMING
could be address and/or data. LBX takes only one cycle to release the host bus. Figure 4. HIG [4:0] Command Timing
3.3.2 HIG [4:0] MEMORY READ TIMING
the sequencing of the signals. and HD register retains its current value. Figure 5. CPU Read from Memory
3.3.3 MIG [2:0] COMMAND
the NOPM command driven in the second clock. Figure 6. MIG [2:0] Command Timing
3.3.4 PIG [3:0] COMMAND, DRVPCI, AND PPOUT
nal relative to the PCI AD [31:0] lines. AD[31:0] lines one clock after DRVPCI is asserted. AD[31:0] lines are released in cycle N. illustrated in the sixth and seventh clock of Figure 7. Figure 7. PIG [3:0] Command Timing
3.3.5 PIG [3:0]: READ PREFETCH BUFFER
The structure of the CPU-to-PCI read prefetch buffer requires special considerations due to the partition of the PCMC and LBX. The PCMC interfaces only to the PCI control signals, while the LBXs interface only to the data. Therefore, it is not possible to latch a Dword of data into the prefetch buffer after it is quali- fied by TRDY Ý. Instead, the data is repetitively latched into the same location until TRDY Ý is sam- pled asserted. Only after TRDY Ý is sampled assert- ed is data valid in the buffer. A toggling mechanism is implemented to advance the write pointer to the next Dword after the current Dword has been quali- fied by TRDY Other considerations of the partition are taken into account on the host side as well. When reading from the buffer, the command to drive the data onto the host bus is sent before it is known that the entry is valid. This method avoids the wait-state that would be introduced by waiting for an entry’s TRDY Ý to be asserted before sending the command to drive the entry onto the host bus. The FIFO structure of the buffer also necessitates a toggling scheme to ad- vance to the next buffer entry after the current entry has been successfully driven. Also, this method gives the LBX the ability to drive the same Dword twice, enabling reads of less than a Dword to be serviced by the buffer; reads of individual bytes of a Dword would read the same Dword 4 times. The HIG [4:0] and PIG [3:0] lines are defined to en- able the features described previously. The LCPRF PIG[3:0] command latches the first PCI read Dword into the first location in the CPU-to-PCI read prefetch buffer. This command is driven until TRDY Ý is sam- pled asserted. The valid Dword would then be in the first location of the buffer. The cycle after TRDY Ý is sampled asserted, the PCMC drives the LCPRA command on the PIG [3:0] lines. This action latches the value on the PCI AD [31:0] lines into the next Dword location in the buffer. Again, the LCPRA com- mand is driven until TRDY Ý is sampled asserted. Each cycle the LCPRA command is driven, data is latched into the same location in the buffer. When TRDY Ý is sampled asserted, the PCMC drives the LCPRB command on the PIG [3:0] lines. This latches the value on the AD [31:0] lines into the next location in the buffer, the one after the location that the previ- ous LCPRA command latched data into. After TRDY Ý has been sampled asserted again, the com- mand switches back to LCPRA. In this way, the same location in the buffer can be filled repeatedly until valid, and when it is known that the location is valid, the next location can be filled. The commands for the HIG [4:0], CPRF, CPRA, and CPRB, work exactly the same way. If the same com- mand is driven, the same data is driven. Driving an appropriately different command results in the next data being driven. Figure 8 illustrates the usage of these commands.
3.3.6 PIG [3:0]: END-OF-LINE
illustrates the timing of this signal.
- The PPMWA command is driven in response to
- The EOL signal is first negated when the LPMA
until the next time the LPMA command is driven.
- If the second Dword is the last that should be
must be asserted in the fifth clock. Figure 9. EOL Signal Timing for PCI Master Writes
A similar sequence is defined for PCI master reads. commands to drive out PCI read data.
- The LPMA command sampled at the end of the
- The SPMRH command causes the count of the
STOPÝ is asserted with TRDY Ý. Figure 10. EOL Signal Timing for PCI Master Reads
3.4 PLL Loop Filter Components
CC through a 10 X 5% resistor. 0.01 mF 10% series capacitor. connected to the A27 line on the CPU address bus. Figure 11. Loop Filter Circuit
3.5 PCI Clock Considerations
Figure 12. Clock Considerations
4.0 ELECTRICAL CHARACTERISTICS
4.1 Absolute Maximum Ratings
ings may affect device reliability. total power will not exceed 1.4W. Maximum Ratings’’ may cause permanent damage. may affect device reliability.
4.2 Thermal Characteristics
the package are given in the following tables. Table 4. Thermal Resistance
4.3 DC Characteristics
A15:0, D 31:0, HIG 4:0, HP 3:0 Main Memory (DRAM) Interface Signals MD31:0, MP 3:0, MIG 2:0, MDLE(in) PCI Interface Signals AD15:0, TRDY Ý(in), PIG 3:0, DRVPCI(in), EOL(t/s), PPOUT(t/s) Reset and Clock Signals HCLK(in), PCLK(in), RESET(in), LP1(out), LP2(in), TEST(in) 4.3.1 82433LX LBX DC CHARACTERISTICS Functional Operating Range: V CC e 4.75 V to 5.25V; T CASE e 0§Ct o a85§C Symbol Parameter Min Typical Max Unit Notes VIL1 Input Low Voltage b0.3 0.8 V 1 VIH1 Input High Voltage 2.0 V CC a 0.3 V 1 VIL2 Input Low Voltage b0.3 0.3 c VCC V2 VIH2 Input High Voltage 0.7 c VCC VCC a 0.3 V 2 VOL1 Output Low Voltage 0.4 V 3 VOH1 Output High Voltage 2.4 V 3 VOL2 Output Low Voltage 0.5 V 4 VOH2 Output High Voltage V CC b 0.5 V 4 IOL1 Output Low Current 1 mA 5 IOH1 Output High Current b1m A 5 IOL2 Output Low Current 3 mA 6 IOH2 Output High Current b2m A 6
Functional Operating Range: V CC e 4.75V to 5.25V; T CASE e 0§Ct o a85§C (Continued) Symbol Parameter Min Typical Max Unit Notes IOL3 Output Low Current 3 mA 7 IOH3 Output High Current b1m A 7 IIH Input Leakage Current a10 mA IIL Input Leakage Current b10 mA CIN Input Capacitance 4.6 pF COUT Output Capacitance 4.3 pF CI/O I/O Capacitance 4.6 pF NOTES: 1. V IL1 and V IH1 apply to the following signals: AD [15:0],A [15:0],D [31:0],H P [3:0],M D [31:0],M P [3:0], TRDY Ý, RESET, HCLK, PCLK 2. V IL2 and V IH2 apply to the following signals: HIG [4:0], PIG [3:0], MIG [2:0], MDLE, DRVPCI 3. V OL1 and V OH1 apply to the following signals: AD [15:0],A [15:0],D [31:0],H P [3:0],M D [31:0],M P [3:0] 4. V OL2 and V OH2 apply to the following signals: PPOUT, EOL 5. I OL1 and I OH1 apply to the following signals: PPOUT, EOL 6. I OL2 and I OH2 apply to the following signals: AD [15:0] 7. I OL3 and I OH3 apply to the following signals: A [15:0],D [31:0],H P [3:0],M D [31:0],M P [3:0] 4.3.2 82433NX LBX DC CHARACTERISTICS Functional Operating Range: V CC e 4.75V to 5.25V; V CC3 e 3.135 to 3.465V, T CASE e 0§Ct o a85§C Symbol Parameter Min Typical Max Unit Notes VIL1 Input Low Voltage b0.3 0.8 V 1 VIH1 Input High Voltage 2.0 V CC a 0.3 V 1 VIL2 Input Low Voltage b0.3 0.3 x V CC V2 VIH2 Input High Voltage 0.7 x V CC VCC a 0.3 V 2 VIL3 Input Low Voltage b0.3 0.8 V 3 VIH3 Input High Voltage 2.0 V CC3 a 0.3 V 3 VOL1 Output Low Voltage 0.4 V 4 VOH1 Output High Voltage 2.4 V 4 VOL2 Output Low Voltage 0.5 V 5 VOH2 Output High Voltage V CC b 0.5 V 5 IOL1 Output Low Current 1 mA 6 IOH1 Output High Current b1m A 6 IOL2 Output Low Current 3 mA 7 IOH2 Output High Current b2m A 7
Functional Operating Range: V CC e 4.75V to 5.25V; V CC3 e 3.135V to 3.465V, TCASE e 0§Ct o a85§C (Continued) Symbol Parameter Min Typical Max Unit Notes IOL3 Output Low Current 3 mA 8 IOH3 Output High Current b1m A 8 IIH Input Leakage Current a10 mA IIL Input Leakage Current b10 mA CIN Input Capacitance 4.6 pF COUT Output Capacitance 4.3 pF CI/O I/O Capacitance 4.6 pF NOTES: 1. V IL1 and V IH1 apply to the following signals: AD [15:0],M D [31:0],M P [3:0], TRDY Ý, RESET, HCLK, PCLK 2. V IL2 and V IH2 apply to the following signals: HIG [4:0], PIG [3:0], MIG [2:0], MDLE, DRVPCI 3. V IL3 and V IH3 apply to the following signals: A [15:0],D [31:0],H P [3:0] 4. V OL1 and V OH1 apply to the following signals: AD [15:0],A [15:0],D [31:0],H P [3:0],M D [31:0],M P [3:0] 5. V OL2 and V OH2 apply to the following signals: PPOUT, EOL 6. I OL1 and I OH1 apply to the following signals: PPOUT, EOL 7. I OL2 and I OH2 apply to the following signals: AD [15:0] 8. I OL3 and I OH3 apply to the following signals: A [15:0],D [31:0],H P [3:0],M D [31:0],M P [3:0] 9. The output buffers for A [15:0],D [31:0] and HP [3:0] are powered with V CC3 and therefore drive 3.3V signal levels.
4.4 82433LX AC Characteristics The AC specifications given in this section consist of propagation delays, valid delays, input setup require- ments, input hold requirements, output float delays, output enable delays, clock high and low times and clock period specifications. Figure 13 through Figure 21 define these specifications. Sections 4.3.1 through 4.3.3 list the AC Specifications. In Figure 13 through Figure 21 VT e1.5V for the fol- lowing signals: MD [31:0],M P [3:0],D [31:0], HP[3:0],A [15:0],A D [15:0], TRDY Ý, HCLK, PCLK, RESET, TEST. VT e 2.5V for the following signals: HIG [4:0], PIG[3:0], MIG [2:0], MDLE, DRVPCI, PPOUT, EOL.
4.4.1 HOST AND PCI CLOCK TIMING, 66 MHZ (82433LX)
Functional Operating Range: V CC e 4.9V to 5.25V; T CASE e 0§Ct o a70§C Symbol Parameter Min Max Figure Notes t1a HCLK Period 15 20 18 t1b HCLK High Time 5 18 t1c HCLK Low Time 5 18 t1d HCLK Rise Time 1.5 19 t1e HCLK Fall Time 1.5 19 t1f HCLK Period Stability g100 ps 1 t2a PCLK Period 30 18 t2b PCLK High Time 12 18 t2c PCLK Low Time 12 18 t2d PCLK Rise Time 3 19 t2e PCLK Fall Time 3 19 t3 HCLK to PCLK Skew b7.2 5.8 21 NOTE: 1. Measured on rising edge of adjacent clocks at 1.5 Volts.
4.4.2 COMMAND TIMING, 66 MHZ (82433LX)
Functional Operating Range: V CC e 4.9V to 5.25V; T CASE e 0§Ct o a70§C Symbol Parameter Min Max Figure Notes t10a HIG [4:0] Setup Time to HCLK Rising 5.4 15 t10b HIG [4:0] Hold Time from HCLK Rising 0 15 t11a MIG [2:0] Setup Time to HCLK Rising 5.4 15 t11b MIG [2:0] Hold Time from HCLK Rising 0 15 t12a PIG [3:0] Setup Time to PCLK Rising 15.6 15 t12b PIG [3:0] Hold Time from PCLK Rising b1.0 15 t13a MDLE Setup Time to HCLK Rising 5.7 15 t13b MDLE Hold Time to HCLK Rising b0.3 15 t14a DRVPCI Setup Time to PCLK Rising 6.5 15 t14b DRVPCI Hold Time from PCLK Rising b0.5 15 t15a RESET Setup Time to HCLK Rising 3.1 15 t15b RESET Hold Time from HCLK Rising 0.3 15
4.4.3 ADDRESS, DATA, TRDY Ý, EOL, TEST, TSCON AND PARITY TIMING, 66 MHz (82433LX)
Functional Operating Range: V CC e 4.9V to 5.25V; T CASE e 0§Ct o a70§C Symbol Parameter Min Max Figure Notes t20a AD [15:0] Output Enable Delay from PCLK Rising 2 17 t20b AD [15:0] Valid Delay from PCLK Rising 2 11 14 1 t20c AD [15:0] Setup Time to PCLK Rising 7 15 t20d AD [15:0] Hold Time from PCLK Rising 0 15 t20e AD [15:0] Float Delay from DRVPCI Falling 2 10 16 t21a TRDY Ý Setup Time to PCLK Rising 7 15 t21b TRDY Ý Hold Time from PCLK Rising 0 15 t22a D [31:0],H P [3:0] Output Enable Delay from HCLK Rising 0 7.7 17 2 t22b D [31:0],H P [3:0] Float Delay from HCLK Rising 3.1 15.5 16 t22c D [31:0],H P [3:0] Float Delay from MDLE Rising 2 11.0 16 3 t22d D [31:0],H P [3:0] Valid Delay from HCLK Rising 0 7.7 14 2 t22e D [31:0],H P [3:0] Setup Time to HCLK Rising 3.0 15 t22f D [31:0],H P [3:0] Hold Time from HCLK Rising 0.3 15 t23a HA [15:0] Output Enable Delay from HCLK Rising 0 15.2 17 t23b HA [15:0] Float Delay from HCLK Rising 0 15.2 16 t23c HA [15:0] Valid Delay from HCLK Rising 0 16 14 7 t23cc HA [15:0] Valid Delay from HCLK Rising 0 14.5 8 t23d HA [15:0] Setup Time to HCLK Rising 15 15 4 t23e HA [15:0] Setup Time to HCLK Rising 4.1 15 5 t23f HA [15:0] Hold Time from HCLK Rising 0.3 15 t24a MD [31:0],M P [3:0] Valid Delay from HCLK Rising 0 12.0 14 6 t24b MD [31:0],M P [3:0] Setup Time to HCLK Rising 4.0 15 t24c MD [31:0],M P [3:0] Hold Time from HCLK Rising 0.4 15 t25 EOL, PPOUT Valid Delay from PCLK Rising 2.3 17.2 14 2 t26a All Outputs Float Delay from TSCON Falling 0 30 16 t26b All Outputs Enable Delay from TSCON Rising 0 30 17 NOTES: 1. Min: 0 pF, Max: 50 pF 2 .0p F 3. When NOPC command sampled on previous rising HCLK on HIG [4:0] 4. CPU to PCI Transfers 5. When ADCPY command is sampled on HIG [4:0] 6. 50 pF 7. When DACPYL or DACPYH commands are sampled on HIG [4:0] 8. Inquire cycle
4.4.4 HOST AND PCI CLOCK TIMING, 60 MHz (82433LX)
Functional Operating Range: V CC e 4.75V to 5.25V; T CASE e 0§Ct o a85§C Symbol Parameter Min Max Figure Notes t1a HCLK Period 16.6 20 18 t1b HCLK High Time 5.5 18 t1c HCLK Low Time 5.5 18 t1d HCLK Rise Time 1.5 19 t1e HCLK Fall Time 1.5 19 t1f HCLK Period Stability g100 ps 1 t2a PCLK Period 33.33 18 t2b PCLK High Time 13 18 t2c PCLK Low Time 13 18 t2d PCLK Rise Time 3 19 t2e PCLK Fall Time 3 19 t3 PCLK to PCMC PCLKIN: Input to Input Skew b7.2 5.8 21 NOTES: 1. Measured on rising edge of adjacent clocks at 1.5 Volts
4.4.5 COMMAND TIMING, 60 MHZ (82433LX)
Functional Operating Range: V CC e 4.75V to 5.25V; T CASE e 0§Ct o a85§C Symbol Parameter Min Max Figure Notes t10a HIG [4:0] Setup Time to HCLK Rising 6.0 15 t10b HIG [4:0] Hold Time from HCLK Rising 0 15 t11a MIG [2:0] Setup Time to HCLK Rising 6.0 15 t11b MIG [2:0] Hold Time from HCLK Rising 0 15 t12a PIG [3:0] Setup Time to PCLK Rising 16.0 15 t12b PIG [3:0] Hold Time from PCLK Rising 0 15 t13a MDLE Setup Time to HCLK Rising 5.9 15 t13b MDLE Hold Time to HCLK Rising b0.3 15 t14a DRVPCI Setup Time to PCLK Rising 7.0 15 t14b DRVPCI Hold Time from PCLK Rising b0.5 15 t15a RESET Setup Time to HCLK Rising 3.4 15 t15b RESET Hold Time from HCLK Rising 0.4 15
4.4.6 ADDRESS, DATA, TRDY Ý, EOL, TEST, TSCON AND PARITY TIMING, 60 MHz (82433LX)
Functional Operating Range: V CC e 4.75V to 5.25V; T CASE e 0§Ct o a85§C Symbol Parameter Min Max Figure Notes t20a AD [15:0] Output Enable Delay from PCLK Rising 2 17 t20b AD [15:0] Valid Delay from PCLK Rising 2 11 14 1 t20c AD [15:0] Setup Time to PCLK Rising 7 15 t20d AD [15:0] Hold Time from PCLK Rising 0 15 t20e AD [15:0] Float Delay from DRVPCI Falling 2 10 16 t21a TRDY Ý Setup Time to PCLK Rising 7 15 t21b TRDY Ý Hold Time from PCLK Rising 0 15 t22a D [31:0],H P [3:0] Output Enable Delay from HCLK Rising 0 7.9 17 2 t22b D [31:0],H P [3:0] Float Delay from HCLK Rising 3.1 15.5 16 t22c D [31:0],H P [3:0] Float Delay from MDLE Rising 2 11.0 16 3 t22d D [31:0],H P [3:0] Valid Delay from HCLK Rising 0 7.8 14 2 t22e D [31:0],HP[3:0] Setup Time to HCLK Rising 3.4 15 t22f D [31:0],H P [3:0] Hold Time from HCLK Rising 0.3 15 t23a HA [15:0] Output Enable Delay from HCLK Rising 0 15.2 17 t23b HA [15:0] Float Delay from HCLK Rising 0 15.2 16 t23c HA [15:0] Valid Delay from HCLK Rising 0 18.5 14 7 t23cc HA [15:0] Valid Delay from HCLK Rising 0 15.5 8 t23d HA [15:0] Setup Time to HCLK Rising 15.0 15 4 t23e HA [15:0] Setup Time to HCLK Rising 4.1 15 5 t23f HA [15:0] Hold Time from HCLK Rising 0.3 15 t24a MD [31:0],M P [3:0] Valid Delay from HCLK Rising 0 12.0 14 6 t24b MD [31:0],M P [3:0] Setup Time to HCLK Rising 4.4 15 t24c MD [31:0],M P [3:0] Hold Time from HCLK Rising 1.0 15 t25 EOL, PPOUT Valid Delay from PCLK Rising 2.3 17.2 14 2 t26a All Outputs Float Delay from TSCON Falling 0 30 16 t26b All Outputs Enable Delay from TSCON Rising 0 30 17 NOTES: 1. Min: 0 pF, Max: 50 pF 2 .0p F 3. When NOPC command sampled on previous rising HCLK on HIG [4:0] 4. CPU to PCI Transfers 5. When ADCPY command is sampled on HIG [4:0] 6. 50 pF 7. When DACPYL or DACPYH commands are sampled on HIG [4:0] 8. Inquire cycle
4.4.7 TEST TIMING (82433LX)
Functional Operating Range: V CC e 4.75V to 5.25V; T CASE e 0§Ct o a85§C Symbol Parameter Min Max Figure Notes t30 All Test Signals Setup Time to 10.0 In PLL Bypass HCLK/PCLK Rising Mode t31 All Test Signals Hold Time to 12.0 In PLL Bypass HCLK/PCLK Rising Mode t32 Test Setup Time to HCLK/PCLK Rising 15.0 15 t33 Test Hold Time to HCLK/PCLK Rising 5.0 15 t34 PPOUT Valid Delay from PCLK Rising 0.0 500 15 In PLL Bypass Mode 4.5 82433NX AC Characteristics The AC specifications given in this section consist of propagation delays, valid delays, input setup require- ments, input hold requirements, output float delays, output enable delays, clock high and low times and clock period specifications. Figure 13 through Figure 21 define these specifications. Section 4.5 lists the AC Specifi- cations. In Figure 13 through Figure 21 VT e 1.5V for the following signals: MD [31:0],M P [3:0],D [31:0],H P [3:0], A[15:0],A D [15:0], TRDY Ý, HCLK, PCLK, RESET, TEST. VT e 2.5V for the following signals: HIG [4:0], PIG [3:0], MIG [2:0], MDLE, DRVPCI, PPOUT, EOL.
4.5.1 HOST AND PCI CLOCK TIMING, (82433NX)
Functional Operating Range: V CC e 4.75V to 5.25V; V CC3 e 3.135V to 3.465V, T CASE e 0§Ct o a85§C Symbol Parameter Min Max Figure Notes t1a HCLK Period 15 20 18 t1b HCLK High Time 5 18 t1c HCLK Low Time 5 18 t1d HCLK Rise Time 1.5 19 t1e HCLK Fall Time 1.5 19 t1f HCLK Period Stability g100 ps 1 t2a PCLK Period 30 18 t2b PCLK High Time 12 18 t2c PCLK Low Time 12 18 t2d PCLK Rise Time 3 19 t2e PCLK Fall Time 3 19 t3 HCLK to PCLK Skew b7.2 5.8 21 NOTE: 1. Measured on rising edge of adjacent clocks at 1.5 Volts.
4.5.2 COMMAND TIMING, (82433NX)
Functional Operating Range: V CC e 4.75V to 5.25V; V CC3 e 3.135V to 3.465V, T CASE e 0§Ct o a85§C Symbol Parameter Min Max Figure Notes t10a HIG [4:0] Setup Time to HCLK Rising 5.5 15 t10b HIG [4:0] Hold Time from HCLK Rising 0 15 t11a MIG [2:0] Setup Time to HCLK Rising 5.5 15 t11b MIG [2:0] Hold Time from HCLK Rising 0 15 t12a PIG [3:0] Setup Time to PCLK Rising 14.5 15 t12b PIG [3:0] Hold Time from PCLK Rising 0.0 15 t13a MDLE Setup Time to HCLK Rising 5.5 15 t13b MDLE Hold Time to HCLK Rising b0.3 15 t14a DRVPCI Setup Time to PCLK Rising 7.0 15 t14b DRVPCI Hold Time from PCLK Rising b0.5 15 t15a RESET Setup Time to HCLK Rising 3.4 15 t15b RESET Hold Time from HCLK Rising 0.4 15
4.5.3 ADDRESS, DATA, TRDY Ý, EOL, TEST, TSCON AND PARITY TIMING, (82433NX)
Functional Operating Range: V CC e 4.75V to 5.25V; V CC3 e 3.135V to 3.465V, T CASE e 0§Ct o a85§C Symbol Parameter Min Max Figure Notes t20a AD [15:0] Output Enable Delay from PCLK Rising 2 17 t20b AD [15:0] Valid Delay from PCLK Rising 2 11 14 1 t20c AD [15:0] Setup Time to PCLK Rising 7 15 t20d AD [15:0] Hold Time from PCLK Rising 0 15 t20e AD [15:0] Float Delay from DRVPCI Falling 2 10 16 t21a TRDY Ý Setup Time to PCLK Rising 7 15 t21b TRDY Ý Hold Time from PCLK Rising 0 15 t22a D [31:0],H P [3:0] Output Enable Delay from HCLK Rising 0 7.5 17 2 t22b D [31:0],H P [3:0] Float Delay from HCLK Rising 3.1 15.5 16 t22c D [31:0],H P [3:0] Float Delay from MDLE Rising 2 9.5 16 3 t22d D [31:0],H P [3:0] Valid Delay from HCLK Rising 0 7.5 14 2 t22e D [31:0],HP[3:0] Setup Time to HCLK Rising 3.1 15 t22f D [31:0],H P [3:0] Hold Time from HCLK Rising 0.3 15
Functional Operating Range: V CC e 4.75V to 5V; V CC3 e 3.135V to 3.465V, TCASE e 0§Ct o a85§C (Continued) Symbol Parameter Min Max Figure Notes t23a HA [15:0] Output Enable Delay from HCLK Rising 0 13.5 17 t23b HA [15:0] Float Delay from HCLK Rising 0 13.5 16 t23c HA [15:0] Valid Delay from HCLK Rising 0 17.5 14 7 t23cc HA [15:0] Valid Delay from HCLK Rising 0 13.5 8 t23d HA [15:0] Setup Time to HCLK Rising 15 15 4 t23e HA [15:0] Setup Time to HCLK Rising 4.2 15 5 t23f HA [15:0] Hold Time from HCLK Rising 0.3 15 t24a MD [31:0],M P [3:0] Valid Delay from HCLK Rising 0 12.0 14 6 t24b MD [31:0],M P [3:0] Setup Time to HCLK Rising 4.4 15 t24c MD [31:0],M P [3:0] Hold Time from HCLK Rising 1.0 15 t25 EOL, PPOUT Valid Delay from PCLK Rising 2.3 17.2 14 2 t26a All Outputs Float Delay from TSCON Falling 0 30 16 t26b All Outputs Enable Delay from TSCON Rising 0 30 17 NOTE: 1. Min: 0 pF, Max: 50 pF 2 .0p F 3. When NOPC command sampled on previous rising HCLK on HIG [4:0] 4. CPU to PCI Transfers 5. When ADCPY command is sampled on HIG [4:0] 6. 50 pF 7. When DACPYL or DACPYH commands are sampled on HIG [4:0] 8. Inquire cycle
4.5.4 TEST TIMING (82433NX)
Functional Operating Range: V CC e 4.75V to 5.25V; V CC3 e 3.135V to 3.465V, T CASE e 0§Ct o a85§C Symbol Parameter Min Max Figure Notes t30 All Test Signals Setup Time to HCLK/ 10.0 In PLL Bypass Mode PCLK Rising t31 All Test Signals Hold Time to HCLK/ 12.0 In PLL Bypass Mode PCLK Rising t32 Test Setup Time to HCLK/PCLK Rising 15.0 15 t33 Test Hold Time to HCLK/PCLK Rising 5.0 15 t34 PPOUT Valid Delay from PCLK Rising 0.0 500 15 In PLL Bypass Mode
4.5.5 TIMING DIAGRAMS
Figure 13. Propagation Delay Figure 14. Valid Delay from Rising Clock Edge Figure 15. Setup and Hold Times Figure 16. Float Delay Figure 17. Output Enable Delay
5.0 PINOUT AND PACKAGE INFORMATION
5.1 Pin Assignment
supply. All other VDD pins on the 82433NX must be connected to the 5V power supply. Figure 22. 82433LX and 82433NX Pin Assignment
Table 5. 82433LX and 82433NX Numerical Pin Assignment
Table 5. 82433LX and 82433NX Numerical Pin Assignment (Continued)
Table 6. 82433LX and 82433NX Alphabetical Pin Assignment List
Table 6. 82433LX and 82433NX Alphabetical Pin Assignment List (Continued)
5.2 Package Information
Figure 23. 82433LX and 82433NX 160-Pin QFP Package Table 7. 160-Pin QFP Package Values
6.0 TESTABILITY
6.1 NAND Tree
of each of the LBX signal pins. into PLL bypass mode and enable the NAND tree. PCLK or HCLK when in PLL bypass mode.
6.1.1 TEST VECTOR TABLE
mode and to enable NAND tree testing.
6.1.2 NAND TREE TABLE
NAND tree is driven on the PPOUT pin. Table 8. Test Vectors to put LBX Into PLL Bypass and Enable NAND Tree Testing
Table 9. NAND Tree Sequence
Table 9. NAND Tree Sequence (Continued)