8242AH

UPI-41AH INTEL | Alldatasheet

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Figure 3. Block Diagram eral software vendors’ keyboard controller firmware. Technologies Ltd., IBM, and Award Software Inc. for AT, PS/2, EISA, and PCI architectures. *Contact factory for current code revision available in all versions of the 8242 product lines.

Table 1. Pin Description synchronize the internal clock to PH1. See the Sync Mode Section. RESET 45 I RESET: Input used to reset status flip-flops and to set the program counter to zero. RESET is also used during EPROM programming and verification. program through each instruction (EPROM). This should be tied to a5V when not used. This pin is also used to put the device in Sync Mode by applying 12.5V to it. connected to a common data bus. ROM/EPROM verification. This pin should be tied low if unused. the OUTPUT DATA BUS BUFFER or status register. during program and verify operations. to the UPI INPUT DATA BUS BUFFER. microcomputer to an 8-bit master system data bus. (DRQ), and P 27 as DMA ACKnowledge (DACK ). PROG 25 28 I/O PROGRAM: Multifunction pin used as the program pulse input during PROM programming. During I/O expander access the PROG pin acts as an address/data strobe to the 8243. This pin should be tied high if unused. VCC 40 44 POWER: a5V main power supply pin. VSS 20 22 GROUND: Circuit ground potential.

UPI-41AH and UPI-42AH FEATURES 1. Two Data Bus Buffers, one for input and one for output. This allows a much cleaner Master/Slave protocol. 210393–4 2. 8 Bits of Status ST7 ST6 ST5 ST4 F1 F0 IBF OBF D7 D6 D5 D4 D3 D2 D1 D0 ST4 –ST7 are user definable status bits. These bits are defined by the ‘‘MOV STS, A’’ single byte, single cycle instruction. Bits 4–7 of the acccumu- lator are moved to bits 4–7 of the status register. Bits 0–3 of the status register are not affected. MOV STS, A Op Code: 90H 1 001000 0 D7 D0 3. RD and WR are edge triggered. IBF, OBF, F 1 and INT change internally after the trailing edge of RD or WR . 210393–6 During the time that the host CPU is reading the status register, the UPI is prevented from updat- ing this register or is ‘locked out.’ 4. P 24 and P 25 are port pins or Buffer Flag pins which can be used to interrupt a master proces- sor. These pins default to port pins on Reset. If the ‘‘EN FLAGS’’ instruction has been execut- ed, P 24 becomes the OBF (Output Buffer Full) pin. A ‘‘1’’ written to P 24 enables the OBF pin (the pin outputs the OBF Status Bit). A ‘‘0’’ written to P 24 disables the OBF pin (the pin remains low). This pin can be used to indicate that valid data is avail- able from the UPI (in Output Data Bus Buffer). If ‘‘EN FLAGS’’ has been executed, P 25 becomes the IBF (Input Buffer Full) pin. A ‘‘1’’ written to P 25 enables the IBF pin (the pin outputs the inverse of the IBF Status Bit. A ‘‘0’’ written to P 25 disables the IBF pin (the pin remains low). This pin can be used to indicate that the UPI is ready for data. 210393–5 Data Bus Buffer Interrupt Capability EN FLAGS Op Code: 0F5H 1 111010 1 D7 D0

Figure 8. UPI-41AH/42AH 80-Column be used to disable the programmer.

1. CS e 5V, V CC e 5V, V DD e 5V, RESET e 0V,

oscillator operating, BUS floating, PROG e 5V.

1. Insert 8741AH or 8742AH in programming socket
2. EA e 12.5V (active program mode)
3. V CC e 6V (programming supply)
4. V DD e 12.5V (programming power)
5. Address applied to BUS and P 20–22
6. RESET e 5V (latch address)
7. Read and verify data on BUS
8. Programmer should be at conditions of step 1

for proper programming procedure. for before the overprogram pulse is applied.

Figure 9. Programming Algorithm

The entire sequence of program pulses and byte verifications is performed at V CC e 6.0V and V DD e 12.5V. When the int eligent Programming cycle has been completed, all bytes should be compared to the original data with V CC e 5.0, V DD e 5V. Verify A verify should be performed on the programmed bits to determine that they have been correctly pro- grammed. The verify is performed with T0 e 5V, VDD e 5V, EA e 12.5V, SS e 5V, PROG e 5V, A0 e 0V, and CS e 5V. SECURITY BIT The security bit is a single EPROM cell outside the EPROM array. The user can program this bit with the appropriate access code and the normal program- ming procedure, to inhibit any external access to the EPROM contents. Thus the user’s resident program is protected. There is no direct external access to this bit. However, the security byte in the signature row has the same address and can be used to check indirectly whether the security bit has been programmed or not. The security bit has no effect on the signature mode, so the security byte can always be examined. SECURITY BIT PROGRAMMING/ VERIFICATION Programming a. Read the security byte of the signature mode. Make sure it is 00H. b. Apply access code to appropriate inputs to put the device into security mode. c. Apply high voltage to EA and V DD pins. d. Follow the programming procedure as per the inteligent Programming Algorithm with known data on the databus. Not only the security bit, but also the security byte of the signature row is pro- grammed. e. Verify that the security byte of the signature mode contains the same data as appeared on the data bus. (If DB0–DB7 e high, the security byte will contain FFH.) f. Read two consecutive known bytes from the EPROM array and verify that the wrong data are retrieved in at least one verification. If the EPROM can still be read, the security bit may have not been fully programmed though the se- curity byte in the signature mode has. Verification Since the security bit address overlaps the address of the security byte of the signature mode, it can be used to check indirectly whether the security bit has been programmed or not. Therefore, the security bit verification is a mere read operation of the security byte of the signature row (0FFH e security bit pro- grammed; 00H e security bit unprogrammed). Note that during the security bit programming, the reading of the security byte does not necessarily indicate that the security bit has been successfully pro- grammed. Thus, it is recommended that two consec- utive known bytes in the EPROM array be read and the wrong data should be read at least once, be- cause it is highly improbable that random data coin- cides with the correct ones twice.

The UPI-41AH/42AH has an additional 32 bytes of EPROM available for Intel and user signatures and miscellaneous purposes. The 32 bytes are parti- tioned as follows: A. Test code/checksumÐ This can accommodate up to 25 bytes of code for testing the internal nodes that are not testable by executing from the external memory. The test code/checksum is present on ROMs, and OTPs. B. Intel signature ÐThis allows the programmer to read from the UPI-41AH/42AH the manufacturer of the device and the exact product name. It fa- cilitates automatic device identification and will be present in the ROM and OTP versions. Loca- tion 10H contains the manufacturer code. For In- tel, it is 89H. Location 11H contains the device code. The code is 43H and 42H for the 8042AH and OTP 8742AH, and 41H and 40H for the 8041AH and OTP 8741AH, respectively. The code is 44H for any device with the security bit set by Intel. C. User signature ÐThe user signature memory is implemented in the EPROM and consists of 2 bytes for the customer to program his own signa- ture code (for identification purposes and quick sorting of previously programmed materials). D. Test signature ÐThis memory is used to store testing information such as: test data, bin num- ber, etc. (for use in quality and manufacturing control). E. Security byte ÐThis byte is used to check whether the security bit has been programmed (see the security bit section). The signature mode can be accessed by setting P10 e 0, P11–P17 e 1, and then following the programming and/or verification procedures. The location of the various address partitions are as follows: Address Device No. of Type Bytes Test Code/Checksum 0 0FH ROM/OTP 25 16H 1EH Intel Signature 10H 11H ROM/OTP 2 User Signature 12H 13H OTP 2 Test Signature 14H 15H ROM/OTP 2 Security Byte 1FH OTP 1

The Sync Mode is provided to ease the design of multiple controller circuits by allowing the designer to force the device into known phase and state time. The Sync Mode may also be utilized by automatic test equipment (ATE) for quick, easy, and efficient synchronizing between the tester and the DUT (de- vice under test). Sync Mode is enabled when SS pin is raised to high voltage level of a12 volts. To begin synchroniza- tion, T0 is raised to 5 volts at least four clock cycles after SS . T0 must be high for at least four X1 clock cycles to fully reset the prescaler and time state generators. T0 may then be brought down during low state of X1. Two clock cycles later, with the ris- ing edge of X1, the device enters into Time State 1, Phase 1. SS is then brought down to 5 volts 4 clocks later after T0. RESET is allowed to go high 5 tCY (75 clocks) later for normal execution of code. SYNC MODE TIMING DIAGRAMS 210393–28 Minimum Specifications SYNC Operation Time, t SYNC e 3.5 XTAL 1 Clock cycles. Reset Time, t RS e 4t CY. NOTE: The rising and falling edges of T0 should occur during low state of XTAL1 clock.

The following table summarizes the access codes required to invoke the Sync Mode, Signature Mode, and the Security Bit, respectively. Also, the programming and verification modes are included for comparison. Control Signals Data Bus Access Code Modes Port 2 Port 1 T0 RST SS EA PROG V DD VCC 01234567 0 1 2 0 1 23456 7 Programming 0 0 1 HV 1 V DDH VCC Address Addr a 0 a1 XXXXX X Mode 0 1 1 HV STB V DDH VCC Data In Addr Verification 0 0 1 HV 1 V CC VCC Address Addr a 0 a1 XXXXX X Mode 11 1 H V 1V CC VCC Data Out Addr Sync Mode STB 0 HV 0 X V CC VCC XXXXXXXX X X X X X XXXXX X High Signature Prog 0 0 1 HV 1 V DDH VCC Addr. (see Sig Mode Table) 0 0 0 0 1 1 1 1 X X 1 Mode 0 1 1 HV STB V DDH VCC Data In 0 0 0 Verify 0 0 1 HV 1 V CC VCC Addr. (see Sig Mode Table) 0 0 0 11 1 H V 1V CC VCC Data Out 0 0 0 Security Prog 0 0 1 HV 1 V DDH VCC Address 0 0 0 Bit/Byte 0 1 1 HV STB V DDH VCC Data In 0 0 0 Verify 0 0 1 HV 1 V CC VCC Address 0 0 0 11 1 H V 1V CC VCC Data Out 0 0 0 NOTES: 1. a 0 e 0o r1 ;a 1 e 0o r1 .a 0 must e a1. ABSOLUTE MAXIMUM RATINGS * Ambient Temperature Under Bias ÀÀÀÀ0 §Ct o a70§C Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b65§Ct o a150§C Voltage on Any Pin with Respect to GroundÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b0.5V to a7V Power Dissipation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5 W NOTICE: This is a production data sheet. The specifi- cations are subject to change without notice. *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability. D.C. CHARACTERISTICS TA e 0§Ct o a70§C, V CC e VDD ea 5V g10% Symbol Parameter UPI-41AH/42AH Units Notes Min Max VIL Input Low Voltage (Except XTAL1, XTAL2, RESET) b0.5 0.8 V VIL1 Input Low Voltage (XTAL1, XTAL2, RESET) b0.5 0.6 V VIH Input High Voltage (Except XTAL1, XTAL2, RESET) 2.0 V CC V VIH1 Input High Voltage (XTAL1, RESET) 3.5 V CC V VIH2 Input High Voltage (XTAL2) 2.2 V CC V VOL Output Low Voltage (D 0 –D7) 0.45 V I OL e 2.0 mA

D.C. CHARACTERISTICS TA e 0§Ct o a70§C, V CC e VDD ea 5V g10% (Continued) Symbol Parameter UPI-41AH/42AH Units Notes Min Max VOL1 Output Low Voltage (P 10P17,P 20P27, Sync) 0.45 V I OL e 1.6 mA VOL2 Output Low Voltage (PROG) 0.45 V I OL e 1.0 mA VOH Output High Voltage (D 0 –D7) 2.4 V I OH eb 400 mA VOH1 Output High Voltage (All Other Outputs) 2.4 I OH eb 50 mA IIL Input Leakage Current (T 0,T 1, RD, WR, CS, A 0, EA) g10 mAV SS s VIN s VCC IOFL Output Leakage Current (D 0 –D7, High Z State) g10 mAV SS a0.45 s VOUT s VCC ILI Low Input Load Current (P 10P17,P 20P27) 0.3 mA V IL e 0.8V ILI1 Low Input Load Current (RESET, SS) 0.2 mA V IL e 0.8V IDD VDD Supply Current 20 mA Typical e 8m A ICC a IDD Total Supply Current 135 mA Typical e 80 mA IDD Standby Power Down Supply Current 20 mA Typical e 8m A IIH Input Leakage Current (P 10 –P17,P 20 –P27) 100 mAV IN e VCC CIN Input Capacitance 10 pF T A e 25§C (1) CIO I/O Capacitance 20 pF T A e 25§C (1) NOTE: 1. Sampled, not 100% tested. D.C. CHARACTERISTICSÐPROGRAMMING TA e 25§C g5§C, V CC e 6V g0.25V, V DD e 12.5V g0.5V Symbol Parameter Min Max Units VDDH VDD Program Voltage High Level 12 13 V (1) VDDL VDD Voltage Low Level 4.75 5.25 V VPH PROG Program Voltage High Level 2.0 5.5 V VPL PROG Voltage Low Level b0.5 0.8 V VEAH Input High Voltage for EA 12.0 13.0 V (2) VEAL EA Voltage Low Level b0.5 5.25 V IDD VDD High Voltage Supply Current 50.0 mA IEA EA High Voltage Supply Current 1.0 mA NOTES: 1. Voltages over 13V applied to pin V DD will permanently damage the device. 2. V EAH must be applied to EA before V DDH and removed after V DDL. 3. V CC must be applied simultaneously or before V DD and must be removed simultaneously or after V DD.

A.C. CHARACTERISTICS TA e 0§Ct o a70§C, V SS e 0V, V CC e VDD ea 5V g10% DBB READ Symbol Parameter Min Max Units tAR CS, A 0 Setup to RD v 0n s tRA CS, A 0 Hold After RD u 0n s tRR RD Pulse Width 160 ns tAD CS, A 0 to Data Out Delay 130 ns tRD RDvto Data Out Delay 0 130 ns tDF RDuto Data Float Delay 85 ns DBB WRITE Symbol Parameter Min Max Units tAW CS, A 0 Setup to WR v 0n s tWA CS, A 0 Hold After WR u 0n s tWW WR Pulse Width 160 ns tDW Data Setup to WR u 130 ns tWD Data Hold After WR u 0n s CLOCK Symbol Parameter Min Max Units tCY (UPI-41AH/42AH) Cycle Time 1.2 9.20 ms(1) tCYC (UPI-41AH/42AH) Clock Period 80 613 ns tPWH Clock High Time 30 ns tPWL Clock Low Time 30 ns tR Clock Rise Time 10 ns tF Clock Fall Time 10 ns NOTE: 1. t CY e 15/f(XTAL) A.C. CHARACTERISTICS DMA Symbol Parameter Min Max Units tACC DACK to WR or RD 0 ns tCAC RD or WR to DACK 0 ns tACD DACK to Data ValidDACK to Data Valid 0 130 ns tCRQ RD or WR to DRQ Cleared 110 ns (1) NOTE: 1. C L e 150 pF.

A.C. CHARACTERISTICSÐPROGRAMMING TA e 25§C g5§C, V CC e 6V g0.25V, V DDL ea 5V g0.25V, V DDH e 12.5V g0.5V (8741AH/8742AH ONLY) Symbol Parameter Min Max Units tAW Address Setup Time to RESET u 4tCY tWA Address Hold Time After RESET u 4tCY tDW Data in Setup Time to PROG v 4tCY tWD Data in Hold Time After PROG u 4tCY tPW Initial Program Pulse Width 0.95 1.05 ms (1) tTW Test 0 Setup Time for Program Mode 4t CY tWT Test 0 Hold Time After Program Mode 4t CY tDO Test 0 to Data Out Delay 4t CY tWW RESET Pulse Width to Latch Address 4t CY tr,t f PROG Rise and Fall Times 0.5 100 ms tCY CPU Operation Cycle Time 2.5 3.75 ms tRE RESET Setup Time Before EA u 4tCY tOPW Overprogram Pulse Width 2.85 78.75 ms (2) tDE EA High to V DD High 1t CY NOTES: 1. Typical Initial Program Pulse width tolerance e 1m s g5%. 2. This variation is a function of the iteration counter value, X. 3. If TEST 0 is high, t DO can be triggered by RESET u. A.C. CHARACTERISTICS PORT 2 TA e 0§Ct o a70§C, V CC ea 5V g10% Symbol Parameter f(t CY)(3) Min Max Units tCP Port Control Setup Before Falling Edge of PROG 1/15 t CYb28 55 ns (1) tPC Port Control Hold After Falling Edge of PROG 1/10 t CY 125 ns (2) tPR PROG to Time P2 Input Must Be Valid 8/15 t CYb16 650 ns (1) tPF Input Data Hold Time 0 150 ns (2) tDP Output Data Setup Time 2/10 t CY 250 ns (1) tPD Output Data Hold Time 1/10 t CYb80 45 ns (2) tPP PROG Pulse Width 6/10 t CY 750 ns NOTES: 1. C L e 80 pF. 2. C L e 20 pF. 3. t CY e 1.25 ms.

A.C. TESTING INPUT/OUTPUT WAVEFORM INPUT/OUTPUT 210393–14 A.C. TESTING LOAD CIRCUIT 210393–15 DRIVING FROM EXTERNAL SOURCE-TWO OPTIONS l6 MHz 210393–16 210393–17 Rise and Fall Times Should Not Exceed 10 ns. Resis- tors to V CC are Needed to Ensure V IH e 3.5V if TTL Circuitry is Used. LC OSCILLATOR MODE L C NOMINAL f e 1 2q0LCÊ45 H 20 pF 5.2 MHz 120 H 20 pF 3.2 MHz CÊ e C a 3Cpp Cpp j 5–10 pF Pin-to-Pin Capacitance 210393–18 Each C Should be Approximately 20 pF, including Stray Capacitance. CRYSTAL OSCILLATOR MODE 210393–19 C1 5 pF (STRAY 5 pF) C2 (CRYSTAL a STRAY) 8 pF C3 20–30 pF INCLUDING STRAY Crystal Series Resistance Should be Less Than 30 X at 12.5 MHz.

READ OPERATIONÐDATA BUS BUFFER REGISTER 210393–20 WRITE OPERATIONÐDATA BUS BUFFER REGISTER 210393–21 CLOCK TIMING 210393–22

WAVEFORMS (Continued) COMBINATION PROGRAM/VERIFY MODE 210393–23 NOTES: 1. A 0 must be held low (0V) during program/verify modes. 2. For V IH,V IH1,V IL,V IL1,V DDH, and V DDL, please consult the D.C. Characteristics Table. 3. When programming the 8741AH/8742AH, a 0.1 mF capacitor is required across V DD and ground to suppress spurious voltage transients which can damage the device. VERIFY MODE 210393–29 NOTES: 1. PROG must float if EA is low. 2. PROG must float or e 5V when EA is high. 3. P 10 –P17 e 5V or must float. 4. P 24 –P27 e 5V or must float. 5. A 0 must be held low during programming/verify modes.

WAVEFORMS (Continued) DMA 210393–25 PORT 2 210393–26 PORT TIMING DURING EXTERNAL ACCESS (EA) 210393–27 On the Rising Edge of SYNC and EA is Enabled, Port Data is Valid and can be Strobed. On the Trailing Edge of Sync the Program Counter Contents are Available.

Table 2. UPI Instruction Set

Table 2. UPI Instruction Set (Continued)