82343

82343 INTEL | Alldatasheet

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intel’ ADVANCE INFORMATION 82343 SYSTEM CONTROLLER/DATA BUFFER The 82343 contains the system control and data The system controller handles system board refresh buffering functions in a 160-pin quad flatpack. directly and also controls the timing of slot bus re- fresh which is actually performed by the 82344 ISA The 82343's functions are highly programmable via Bus Controller. Refresh may be performed in cou- a set of internal configuration registers. Defaults on pled or decoupled mode. The former method is the reset for the configuration registers mimic the com- standard PC/AT-compatible mode where on- and patibility requirements of the original IBM PC/AT* as off-board refreshes are performed synchronously. In Closely as possible. The power-up defaults allow any decoupled mode, the timing of on- and off-board re- possible configuration of the system to boot at the _freshes is independent. Both may be programmed CPU's rated speed. However, operational capabili- for independent, slower than normal rates. This al- ties may be temporarily reduced until the configura- lows use of low power, slow refresh DRAMs. The : tion registers are set to mirror the true system con- 82343 controls all timing in both modes. In all cases, figuration. This normally occurs during BIOS power- _ refreshes are staggered to minimize power supply ‘on self-test in a manner completely transparent to loading and attendant noise on the Vpp and ground ‘the user. pins. In sleep mode, refresh switches to CAS # be- fore RAS# refresh for maximum power savings. The 82343 is designed to perform in systems run- ning up to 20 MHz. Builtsin page-mode operation, The physical banks of DRAM can be logically reor- two- of four-way interleaving, and fully programma- dered through one of the indexed configuration reg- ble memory timing allow the PC designer to maxi- isters. This DRAM remap option is useful in order to mize system performance using low cost DRAMs. map out bad DRAM banks allowing continued use of Programmable memory timing allows the system to a system until repairs are convenient. It also allows be setup to perfectly match the requirements of the DRAM bank combinations not in the supported chosen DRAMs; standard or custom. These adjust- memory maps to be logically moved into a support- ments can often be made without incurring the pen- __ed configuration without physically moving memory alty of additional wait states. components. This unique, programmable function alty of additional wat states. components. This uniave, programma Block Diagram = — _ ame ——j =| TT) = — Es nse (aS wet ee a hon — ae “ = —o a=] [exo] nave 3867 is a trademark of Intel Corporation. “IBM PC/AT® is a registered ‘trademark of International Business Machines Corporation. TBM PCIATS tea registered rademark of home ere ee Octobe 1990 1-12 Order Number: 240841-001

intel 92343 ADVANCE INFORMATION performs this task by switching the internal RAS# Shadowing features are supported on all 16k bound- and CAS signals between the external RAS# and aries between 640k and 1M. Simultaneous EMS CAS# pins. This allows internal row and column ad- _use, shadowed ROM, and direct system board ac- dresses generated for DRAM bank 0, for example, _cess is possible in non-overlapping fashion through- to be routed to any one of the four on-board DRAM _out this memory space. Control over four access op- banks. tions is provided. 1. Access ROM or slot bus for reads and writes. Full EEMS support is provided in hardware for the cess Or slot bus reads ant es. complete LIM EMS 4.0 standard, Seventy-two map- 2. Access system board DRAM for reads and ping registers provide a standard and an alternate writes. set of 36 registers each. The system allows backfill 3. Access system board DRAM for reads and slot down to 256k for EEMS support and provides 24 bus for writes. mapping registers covering this space. Twelve of the 4. Shadow setup mode. Read ROM or slot bus, 36 are page registers which cover the EMS space write system board DRAM from C0000h to E0000h. These twelve registers can alternatively be mapped in the AOO00-BFFFFh and these controls dden by EMS in segments 1D0000-DFFFFh range by changing a configuration am EMS In seg for which it is enabled. bit in the 82343. All registers are capable of translat- ing over the complete 32 Mbyte range of on-board DRAM. Users preferring an alternate plug-in EMS solution, can disable the on-board EMS system as well as system board DRAM, as required, down to 256k. READYIF im RASIO¥ BKRQ3-BKRQO, PHIT/MISS# an CASIO¥ M/10#,0/C#,W/RE BANK casity REFRESH# an CONTROL tte a ee {Es a csny MEMORY Om Rel {fs ss cnsug tt} eae [ casey CTT] wewory UI casise a el ae MEMORY casing CONTROL l 4 > o DRAMROY# 240841-2 Memory Controller Block Diagram 1-13

intel somg «ADVANCE INFORMATION we The System Controller is used to program the de- data can be converted from 8 bits wide to 16. The sired operational mode of the AT bus. Based on this data is latched for synchronization with the CPU. programming, it provides the bus clock and signal- Parity is generated for all data written to the D bus. ling interface to the Bus Controller. The bus may run The 82343 provides the data conversion necessary synchronously with the CPU's CLK2 or asynchro- for 16-bit writes to 8-bit devices on the XD or SD ously via an external oscillator. A programmable di- buses. vider conditions the selected BUSCLK source pro- viding divide by 1, 2, 3 or 4. Under the control of DMA or a bus master, the 82343 allows 8- or 16-bit data to be routed to and The 82343 also performs ail of the data buffering from the XD bus. The chip also is capable of per- functions required for a 386™SX-based PC/AT- forming high to low and low to high byte swaps on compatible system. Under the control of the CPU, the SD bus. For transfers between two peripherals the data buffer chip routes data to and from the ‘on the slot bus the outputs of the 82343 are dis- CPU’s D bus, XD bus, and slots (SD bus). The parity abled. The chip also provides the feature of a single is checked for D bus DRAM read operations. When input, TRI#, to disable all of its outputs for board reading from ROM, the XD bus or the SD bus, the level testability. my a snc = aes || A ran. 2 “ [ors-00_ sono owt son = = surinone fa a mon au oo mercn ROMCS# DATA cet he wear al ate “umey a] ube SOSWAPE toe one ot aces Data Buffer Functions Block Diagram 1-14

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intel 82343 ADVANCE INFORMATION Sa SIGNAL DESCRIPTIONS aE | Smatbeseinton | | Sarat | Signal Description A23-1 332-154] |-TTL | ADDRESS BITS 23 THROUGH 1: Driven by the CPU when the CPU is bus master. They are driven by the Bus Controller whenever HLDA is active, These bits allow direct access of up to 16 Mbytes of local memory. 165 | [TTL | BYTE HIGH ENABLE, ACTIVE LOW: This signal is driven by the CPU or the 82344. It is used to select the upper byte of a 16-bit wide memory location. BLE #/A0 156 | LTTL | BYTE LOWENABLE, ACTIVE LOW, OR AO: In 386SX mode this signal is BLE #, in 286 mode it is AO and is driven by the CPU or the Bus Controller. It is used to select the lower byte of a 16-bit wide memory location. wir#/so#| 157. | |-TPU | WRITE OR ACTIVE LOW READ ENABLE, OR SO: W/R ¢ is driven by the CPU in 386SX mode, SO # in 286 mode. This signal is decoded with the remaining CPU control signals to indicate the type of bus cycle requested. The bus cycle types include interrupt acknowledge, halt shutdown, 1/0 reads and writes, memory data reads and writes, and memory code reads. This pin is pulled up internally. D/G#/S1# I-TPU_| DATA OR ACTIVE LOW CODE ENABLE, OR S1: D/C# is driven by the CPU in 386SX mode or S1 # in 286 mode. This signal is decoded with the remaining CPU control signals to indicate the type of bus cycle requested. See W/R#/S0# definition for bus cycle types. This pin is pulled up internally. M/#/0 /-TPU_ | MEMORY OR ACTIVE LOW 1/0 ENABLE: Driven by the CPU, M/IO# is decoded with the remaining CPU control signals to indicate the type of bus cycle requested. See W/R #/S0# definition for bus cycle types. This pin is pulled up internally. ADS# 160 | -TPU | ADDRESS STROBE, ACTIVE LOW: This signal is driven by the 386SX as an indicator that the address and control signals currently supplied by the CPU are valid. Itis used internally to indicate that the data and command are valid and determine the beginning of a memory cycle. This pin is a no connect in 286 mode. An internal pull up resistor keeps it inactive during 286 mode. CLK2IN I-CMOS | This is the main clock input to the System Controller and it should be connected to the CLK2 signal that is output by the System Controller. This signal is used internally to clock the System Controller logic. TCLK2 7 I-TTL | This input is connected to a crystal oscillator whose frequency is equal to two times the system frequency. The TTL level oscillator output is. converted internally to CMOS levels and sent to the CLK2 output. cLK2 This output signal is CMOS level converted TCLK2 signal. It is output to the CPU and other on-board logic for synchronization. 1-16

intel 82343 ADVANCE INFORMATION SIGNAL DESCRIPTIONS (Continued) ‘Signal 5 | See | ner Type Stanal Description CPU INTERFACE SIGNALS (Continued) SLP #/MISS. As a “power on reset" default this bit is an output that reflects the inverse state of the SLEEP[7] configuration register bit. It is active low when sleep mode is active. Sleep mode is activated by setting SLEEPI[7] = 1. When configuration register CTRL1{0] = 1 this pin becomes a MISS output for use with a future product. READYO# 7 READY OUT, ACTIVE LOW: This signal is an indication that the current memory or I/O bus cycle is complete. It is generated from the internal DRAM controller or the synchronized version of CHREADY # for slot bus accesses. Outside the chip it is ORed with any other local bus |/O ‘or master. The culmination of these ORed READY signals is sent to the CPU ands also connected to the System Controller's READY! # input. READYI# |-TTL | READY INPUT, ACTIVE LOW: This signal is the ORed READY signals from the coprocessor or other optional add-in devices and from the 82343's READY # input. HLDA |-TTL | HOLD ACKNOWLEDGE, ACTIVE HIGH: This signal is issued by the CPU in response to the HRQ driven by the System Controller. It indicates that the CPU is floating its outputs to the high impedance state, so that another master can take control of the bus. When HLDA is active, the memory control is generated from CHS1 #/MR# and CHSO #/MW # rather than CPU status signals. HOLD REQUEST, ACTIVE HIGH: This output is driven by the System Controller to the CPU. It indicates that a master, such as a DMA or AT. channel master, is requesting control of the bus. HRQ is a result of the DMAHRO input or a coupled refresh cycle. It is synched to CLK2. RESCPU RESET CPU, ACTIVE HIGH: An output signal that is sent to the CPU by the System Controller. It is issued in response to the control bit for software reset located in the Port A register or a dummy read to IO port EFh. It is also issued in response to signals on the RSTORV or RC inputs and in response to System Controller's detection of a shutdown command. In all cases it is synched to CLK2. BUSYCPU# BUSY CPU, ACTIVE LOW: An output signal that is sent to the CPU. The state of BUSYNPX # is always passed through to BUSYCPU# indicating that the NPX is processing a command. ON occurrence of an ERRORNPX ¢# signal, it is latched and held active until occurrence of a write to ports F0h, F1h, or RESNPX. The former case is the normal mechanism used to reset the active latched signal. The latter two are resets. Since ERRORNPX # generates IRQ13 for PC/AT-compatibility, BUSYCPU ¢ is held active to prevent software access of the coprocessor until the interrupt service routine writes FOh. 1-17

intel 82343 ADVANCE INFORMATION SIGNAL DESCRIPTIONS (Continued) Signal [Soe [ wate | Type Signal Description CPU INTERFACE SIGNALS (Continued) PEREQCPU PROCESSOR EXTENSION REQUEST, ACTIVE HIGH: An output signal sent to the CPU in response to a PEREQNPX which is issued by the coprocessor to the System Controller. It indicates to the CPU that the coprocessor is requesting a data operand to be sent to or from memory by the CPU. For PC/AT-compatibility PEREQCPU is returned active on occurrence of ERRORNPX # after BUSYNPX # has gone. inactive. A write to FOh by the interrupt 13 handler returns control of the PEREQCPU signal to directly follow the PEREQNPX input. ON-BOARD MEMORY SYSTEM INTERFACE SIGNALS RAMW# RAM ACTIVE LOW WRITE/ ACTIVE HIGH READ: This output to the DRAM memory is to control the direction of data flow of the on-board memory. It is a resutt of the address and bus control decode. It is active during memory write cycles and high at all other times. MA10-MAO 33-35 MEMORY ADDRESSES 10 THROUGH 0: These address bits are the 37-40, tow and column addresses sent to on-board memory. They are 43-45, 47 buffered and multiplexed versions of the CPU bus addresses. They allow addressing of up to 8 Mbytes per DRAM bank. RASBK3 # — ROW ADDRESS BANK 0 THROUGH 3, ACTIVE LOW: These signals RASBKO# are sent to their respective RAM banks to strobe in the row address during on-board memory bus cycles. The active period for this signal is fully programmable. ' CAS7#- 49-54 COLUMN ADDRESS, STROBE, ACTIVE LOW: These signals are sent CASO# 56, 57 to their respective RAM banks to strobe in the column address during ‘on-board memory bus cycles. There is a CAS # signal for upper and lower bytes of each of the four 16-bit DRAM memory banks. The active period for this signal is completely programmable. For clarity, alternate names may also be used for these signals as shown in the following table where the digit in the “Alternate Name” indicates the DRAM bank the signal drives, L indicates it drives the low byte, and H indicates it drives the high byte. Standard Name Alternate Name CASO# CASOL # CAS1# CASOH# CAS2# CASIL# CAS3# CAS1H# CAS4# CAS2L# CASS # CAS2H# CAS6# CAS3L# CAS7# CAS3H # 1-18

intel 82343 ADVANCE INFORMATION a SIGNAL DESCRIPTIONS (Continued) Signal Signal ON-BOARD MEMORY SYSTEM INTERFACE SIGNALS (Continued) REFRESH# |-CMOS/ | REFRESH SIGNAL, ACTIVE LOW: This output is used by the 0-OD _| System Controller to initiate an off-board DRAM refresh operation in coupled refresh mode. in decoupled mode, the Bus Controller drives refresh active to indicate to the System Controller that it has decoded a refresh request command and is initiating an off-board refresh cycle. ROMCS# ROM CHIP SELECT: This output is active in CPU mode only 1 {CPUHLDA is negated). It is active anytime the address on the A bus selects the address range between FFO000h-FFFFFFh during amemory read cycle. It is also active 0E0000h-OFFFFFh and between FEO000-FEFFFF when RAMMAP(7] = 1, the default condition. When RAMMAP[7] = 0, accesses in these two regions are directed to the slot bus. “Holes” can be opened in this lower decode range by activation of shadow or EMS windows in this region; .e., when 16k shadow or EMS windows are activated in this region, ROMCS # is not generated. COPROCESSOR SIGNALS : PEREQNPX 68 COPROCESSOR EXTENSION REQUEST, ACTIVE HIGH: This input signal is driven by the coprocessor and indicates that it needs transfer of data operands to or from memory. For PC/AT- compatibility this signal is also gated with the internal ERROR/ BUSY control logic before being output to the CPU as PEREQCPU during NPX interrupts. ERRORNPX# L-TPU_ | ERROR COPROCESSOR, ACTIVE LOW: An input signal from the coprocessor indicating that an error has occurred in the previous instruction. This signal is internally gated and latched with BUSYNPX # to produce IRQ13. BUSYNPX# 70 LTPU_ | BUSY COPROCESSOR, ACTIVE LOW: An input signal that is driven by the coprocessor to indicate that it is currently executing a previous instruction and is not ready to accept another. This signal is decoded internally to produce 1RQ13 and to control PEREQCPU. RESNPX RESET COPROCESSOR: This output is connected to the coprocessor reset input. It is triggered through an internally generated system reset or via a write to port Fh. In the case of a system reset, the CPURESET signal is also activated. Write to port F1h only resets the coprocessor. A software FNINT signal must occur after an F1h generated reset in a 386SX system, otherwise the 387SX is not initialized to the same state that a 287 is placed in by a hardware reset alone. For compatibility, the F1 reset may be disabled by setting bit 6 of the MISCSET register to 1. IRQ13 INTERRUPT REQUEST, ACTIVE HIGH: This output is driven to the Bus Controller to indicate that an error has occurred within the coprocessor. This signal is decode of the BUSYNPX# and ERRORNPX # inputs. 1-19

intel 82343 ADVANCE INFORMATION SIGNAL DESCRIPTIONS (Continued) Signal nal Description COPROCESSOR SIGNALS (Continued) NPCS# 67 COPROCESSOR CHIP SELECT: Provides decoding of the 287 coprocessor's |/O space. This is the entire F8h to FFh region when Zenith Data Systems-Special Features are disabled. When ZDS-SF are enabled, only I/O accesses to F8h, FAh, FCh, and FEh cause NPCS # to be active. This signal is a don't care pin for 387SX operation since the 386SX provides this function using A23. BUS CONTROL SIGNALS CHREADY # |-CMOS | CHANNEL READY, ACTIVE LOW: An input issued by the Bus Controller as an indication that the current channel bus cycle is complete. This signal is synchronized internally then combined with ready signals from the coprocessor and DRAM controller to form the final version of READYO # which is sent to the CPU. CHSO#/MW# 10-TTL | CHANNEL SELECT 0 OR MEMORY WRITE, ACTIVE LOW: This signal is a decode of the CPU’s bus control signals and is sent to the Bus Controller. When combined with CHS1 # and CHM/|O# and decoded, the bus cycle type is defined for the Bus Controller. Activation of CPUHLDA reverses this signal to become an input from the Bus Controller, It is then a MEMW # signal for the DMA or bus master to access system memory. CHS1#/MR# 10-TTL | CHANNEL SELECT 1 OR MEMORY READ, ACTIVE LOW: This signal is a decode of the CPU's bus control signals and is sent to the Bus Controller. When combined with CHSO# and CHM/1O# and decoded, the bus cycle type is defined for the Bus Controller. Activation of CPUHLDA reverses this signal to become an input from the Bus Controller. It is then a MEMR # signal for the DMA or bus master to access system memory. CHM/IO# CHANNEL MEMORY 1/0: This signal is a decode of the M/IO# signal sent by the CPU to the System Controller. It is an indicator that the current bus cycle is a channel access, When combined with CHSO0#, and CHM/IO # and decoded, the bus cycle type is defined for the Bus Controller. BLKA20# BLOCK A20, ACTIVE LOW: An output driven to the Bus Controller to deactivate address bit 20. It is a decode of the AZ0GATE signal and Port A bit 1 indicating the dividing line of the 1 Mbyte memory boundary. Port A bit 1 may be directly written or set by a dummy read of I/O port EEh. BLKA20 # is forced high when HLDA is active. BUSOSC 73 |-TTL_ | BUS OSCILLATOR: This signal is supplied from an external oscillator. It is supplied to the Bus Controller when the System Controller's internal configuration registers are set for asynchronous slot bus mode. This signal is two times the AT bus clock speed (SYSCLK). BUSCLK 97 BUS CLOCK: This is the source clock used by the the Bus Controller to drive the slot bus. It is two times the AT bus clock (SYSCLK). It is programmable division from CLK2 or from an external oscillator when the System Controller is set up for a synchronous mode. 1-20

intel 82343 ADVANGE INFORMATION SIGNAL DESCRIPTIONS (Continued) Signal 5 [Set [ite | Se | hiiiiahaehdnel BUS CONTROL SIGNALS (Continued) DMAHRQ 83 |-CMOS | DMA HOLD REQUEST, ACTIVE HIGH: This signal is an input sent by the Bus Controller. It is internally synchronized by the System Controller before it is sent out to the CPU by the HRQ signal. Itis the indicator of the DMA controller or other bus master’s desire to control the bus. DMAHLDA | 98 DMA HOLD ACKNOWLEDGE: An output sent to the Bus Controller which indicates that the current hold acknowledge state is for the DMA . controller or other bus master. 1 BRDRAM# BOARD DRAM, ACTIVE LOW: An output to Bus Controller and Data Buffer to indicate that on-board DRAM is being addressed. EALE# 92 EARLY ADDRESS LATCH ENABLE, ACTIVE LOW: This output is sent to the Bus Controller in order latch the A23-A1 and byte enable signals. In 286 mode, this signal is generated internally by decode of the CPU status signals. In 386SX mode, the 82343’s ADS # input is gated directly to the EALE# output. ouTt 1-CMOS | Indicates a refresh request from the Bus Controller. This signal is provided by the 8254 megacell. PERIPHERAL INTERFACE SIGNALS A20GATE 75 |-TTL_ | ADDRESS 8IT 20 ENABLE: An input from the keyboard controller that is used internally along with Port A bit 1 to determine if address bit 20 from the CPU is true or gated low. It also determines the state of BLKAZ0# TURBO 76 |-TTL_ | TURBO, ACTIVE HIGH: This input to the System Controller determines the speed at which the system board operates. This input signal is normally the externally ANDed signal from the keyboard controller and a turbo switch. It is internally ANDed with a software settable latch. When high, operation is at full speed. When low, CLK2 is divided by the value coded in configuration register MISCSET. A range is provided that allows slow operation at, or below 8 MHz for any valid CPU speed. Siow speed takes precedence. When any one request for slow mode is present, slow mode is active. Turbo mode is active only when all TURBO requests are active. RC# 77 L-TTL | RESET CONTROL, ACTIVE LOW: The falling edge of this signal causes a RESCPU signal. RC # is generated by the keyboard controller and its inverse is ORed with Port A bit 0 to form RESCPU. BUS INTERFACE SIGNALS osc 72 I-TTL_ | OSCILLATOR: This is the buffered input of the external 14.318 MHz oscillator. loR# L-TTL | 1/0 READ, ACTIVE LOW: Driven by the Bus Controller to indicate to the System Controller that an |/O read cycle is occurring on the bus. Whenever an I/O cycle occurs, the memory interface signals are inactive. 1-21

intel 82343 ADVANCE INFORMATION oe SIGNAL DESCRIPTIONS (Continued) Signal 5 " [Sime | sate | S| Signal Description BUS INTERFACE SIGNALS (Continued) |-TTL | 1/0 WRITE, ACTIVE LOW: Driven by the Bus Controller to indicate to the System Controller than an I/O write cycle is occurring on the bus. Whenever an I/O cycle occurs, the memory interface signals are inactive. RSTDRV 87 |-TTL | RESET DRIVE, ACTIVE HIGH: This signal is output by the Bus Controller. It indicates that a hardware reset signal has been activated. This is the same signal which is output to the channel. This signal is used to reset internal logic and to derive the RESCPU : which is output by the System Controller. SDLH/HL# -TTL | SYSTEM DATA BUS LOW TO HIGH/HIGH TO LOW SWAP: This signal is driven by the Bus Controller. It is used to establish the direction of byte swaps. (Similar to DIR245 in the existing PC/AT- type chip sets.) \\-TTL | SYSTEM DATA BUS BYTE SWAP ENABLE: This signal is driven by the Bus Controller. It is the qualifying signal needed for SDLH/ HL#. (Used to be called GATE245 on the existing PC/AT-type chip sets.) XDREAD# L-TTL | PERIPHERAL DATA BUS (XD BUS) READ: This signal is driven by the Bus Controller and it determines the direction of the XD bus data flow. (Itis analogous to the XDATADIR control pin on the existing PC/AT-type chip sets). When this signal is high, the XD Bus is output enabled. LATLO# I-TTL | SD BUS LOW BYTE LATCH: This signal is needed to latch the SD bus low byte to the local data bus until the CPU is ready to sample the bus. This signal is driven by the Bus Controller. D15-Do 42-18, 20, | 10-TTL | CPU DATA BUS: This is the data bus directly connected to the 22-29 CPU. It is also referred to as the local data bus. 111-114, | IO-TTL | SYSTEM DATA BUS: This bus connects directly to the slots. Itis 116-119, used to transfer data to/from local and system devices. 122-125, 127-130 XD7-XDO 101-107, | |O-TTL | PERIPHERAL DATA BUS: This bus is connected to the Bus 109 Controller and the System Controller. These I/O's are used to read and write to on-board 8-bit peripherals. PAR1, PARO 1O-TTL | PARITY BIT BYTES 1 AND 0: These bits are generated by the parity generation circuitry. They are written to memory along with their corresponding bytes during memory write operations. During memory read operations, these bits become inputs and are used along with their respective data bytes to determine if a parity error has occurred. PARERROR # PARITY ERROR, ACTIVE LOW: This signal is the result of a parity check on the read from on-board memory. 286/386SX # 78 |-TPU | 286 OR 386SX MODE: Tied high or left open to allow internal logic to switch to 286/287 compatibility mode. If grounded, the 82343. ‘System Controller/Data Butfer switches into 386SX/387SX compatibility mode. 1-22

intel a2a13 -- ADVANCE INFORMATION SIGNAL DESCRIPTIONS (Continued) TRI# 79 THREE-STATE: This pin is used to drive all outputs to a high impedance state. When TRI # is low, all outputs and bidirectional pins are three- stated. TRI is internally pulled up. POWER AND GROUND PINS The power connections are split into an internal supply for the core-logic, and a pad-ring supply for the I/O drivers. Each supply should be individually bypassed with decoupling capacitors. voor | 1,32, 41, Pad-ring power connection, nominally + 5V. These pins along with the 1 110, 58, VSSR pins should be separately bypassed. 121 vssr | 19,31,36, | GND | Pad-ring ground connection, nominally OV. These pins along with the 42, 46, 55, VDDR pins should be separately bypassed. 81, 108, 115, 120, 126, 131 vool 74 Internal core-logie power connection, nominally + SV. This pin along with the VSSI pin should be separately bypassed. vss GND | internal core-logic ground connection, nominally OV. This pin along with the VDDI pin should be separately bypassed. SIGNAL TYPE LEGEND SignalCode|SignalType | Signal Code | Signal Type TIL Level Input [10-00 _| input or Open Drain, Slow Turn On Input with 30 kA Pull-Down Resistor] __| CMOS and TTL Level Compatible Output Input with 30 kA. Pull-Up Resistor TTL Level Output FTSPU__| Schmitt-Trigger Input ors Three-State Level Output with 30 k0 Pull-Up Resistor FoMOS | CMOSLevelinput_— [1 Input Used for Testing Purposes fom [rtttwetiewoupa eno |oroma THiLLevelinpu/Open Drain Ouput[Pwe [Power 4-23