8231A INTEL | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 13
Technical content
are used in the implementation of the APU algorithms. data and the stack. Results are then available to be retrieved from the stack. help coordinate program execution. Figure 1. Block Diagram
Table 1. Pin Description | Yvoo | 2 | | POWER: +5V power supply. 22 RESET: The active high reset signal provides initialization for the chip. and command registers are not affected (5 clock cycles). and enables communication with the data bus. from the 82314 if CS is low. written into the 82314 if CS is low. that is one clock period wide.
24 END: This active low, open-drain output indicates that execution of the
Next Command output to the device, or by RESET. command is complete (See READY Operation, p. 6). 8231A can drive the data bus only when CS and AD are low.
ing point format is specified. Bit 6 selects the preci: "emains low. Table 2. 32-Bit Floating Point Instructions
Table 3. 32-Bit Integer Instructions Table 4. 16-Bit Integer instructions
- In the hex code column, SVREQ is a 0.
- The stack initially is composed of four 32-bit numbers (A, B, C, D). A is equivalent to Top Of Stack (TOS) and B is Next
- The stack initially is composed of eight 16-bit numbers (Ay, AL, Bu, By, Cy, Ci, Dy, OL). Ay is the TOS and A, is NOS.
4, Nomenciature: Sign (S); Zero (Z); Overflow (O); Carry (C); Error Code Field (E).
intel. 8231A Double Precision Fixed Point Format fractional mantissa value between 0.5 and 1 multi- plied by 2 raised to an appropriate power. This is expressed as follows: PPTTITNR TTR TR VSTOVRPOTO TTA | value = mantissa x 2exponent 231305-5 For example, the value 100.5 expressed in this form is 0.1100 1001 x 27. The decimal equivalent of this The sign (positive or negative) of the operand is lo- Value may be computed by summing the compo- cated in the most significant bit (MSB). Positive val nents (powers of two) of the mantissa and then mul- ues are represented by a sign bit of zero (S = 0). __tiplying by the exponent as shown below: Negative values are represented by the two's com- _ p- 7 plement of the corresponding positive value with a vale = (2-4 + 2-2 + 275 + 2-8) x 27 sign bit equal to 1 (S = 1), The range of values that = 05 + 0.25 + 0.03125 + 0.00290625) x 128, may be accommodated by each of these formats is = 0.78515625 x 128 32,768 to +32,767 for single precision and = 1005 ~2,147,483,648 to + 2,147,483,647 for double pre- = 100. cision. Floating point binary values are represented ina for. FLOATING POINT FORMAT mat that permits arithmetic to be performed in @ The format for floating poit i . > to be ing point values in the 8231A is fashion analogous to operations with decimal values Given below. The mantissa is expressed as a 24-bit expressed in scientific notation. (fractional) value; the exponent is expressed as a . two’s complement 7-bit value having a range of —64 2 1) = x 9 (683 x 10% (8.16 x 101) = (4.76728 x 104) to +63. The most significant bit is the sign of the + mantissa (0 = positive, 1 = negative), for a total of In the decimal system, data may be expressed as ‘780 os | a 32 bits. The binary point is assumed to be the left of values between 0 and 10 times 10 raised to a power in S assu t that effectively shifts the implied decimal point right he most significant mantissa bit (bit 23). All floating or left the number of places necessary to express Point dala values must be normalized. Bit 23 must the result in conventional form (e.g., 47,5728). The Be equal to i except for the value zero, which is value-portion of the data is called the mantissa. The '°P" all zeros. exponent may be either negative or positive The concept of floating point notation has both a |] tenement —— gain and a loss associated with it. The gain is the [Sit ability to represent the significant digits of data with “e ap 231905-6 . values spanning a large dynamic range limited only - by the capacity of the exponent field. For example, in decimal notation in the exponent field is two digits The range of values that can be represented in this wide, and the mantissa is five digits, a range of val- format is +(2.7 x 10-20 to 9.2 x 1018) and zero. ues (positive or negative) from 1.0000 x 10-99 to 9.9999 x 10+99 can be accommodated. The loss is that only the significant digits of the value can be ~~ FUNCTIONAL DESCRIPTION represented. Thus there is no distinction in this rep- resentation between the values 123451 and 123452, for example since each would be expressed STACK CONTROL as: 1.2345 108. The sixth digit has been discard- F ed. In most applications where the dynamic range of The weer iiartace to meee includes access to values to be represented in large, the loss of signifi- gon feed int wide nds ne ie-tie ine ‘9 fh Pre ht cance, and hence accuracy of results, is a minor S10! val Point ene intained in the eat Wh i consideration. For greater precision a fixed point for- Such values may be maintained | ck. Whe mat could be chosen, although with a loss of poten- Sing double precision fixed point or floating point fial dynamic range. formats four values may be stored. The stack in ge. these two configurations can be visualized as shown The 8231A is a binary arithmetic processor and re. #!Ow: quires that floating point data be represented by a
intel. 82310 ee ister is cleared and the Service Request bit of the vs —-Ta aw] vos [x a arm] }} command register is checked. If it is a “1” the serv- wos [ez av] wos [ue ese!) ice request output level (SVREQ) is raised. END is a L_-——} |] cleared on receipt of an active low End Acknowl- ao = edge (EACK) pulse. Similarly, the service request b= | ‘231905-8 line is cleared by recognition of an active low Serv- [+ ice Acknowledge (SVACK) pulse. re
0 READY OPERATION
An active high ready (READY) is provided. This line Daa ae writen onto te sack, eight bis at aime, gh n ts quescon state ands pled ow by te in the order shown (A1, A2, A3, ... ). Data are re- nanan moved from the stack in reverse byte order (A4, A3, _t- A previouly initiated operation is in progress (de- multiples of the number of bytes appropriate to the ed. In this case, the READY line will be pulled low chosen data format. and remain low untit completion of the current command execution. It will then go high, permit- ting entry of the new command. DATA ENTRY 2. A previously initiated operation is in progress and Data entry is accomplished by bringing the chip se- stack access has been attempted. In this case, lect (CS), the command/data line (Ap), and WRiow, the READY line will be pulled low, will remain in as shown in the timing diagram. The entry of each that state until execution is complete, and will new data word “pushes down” the previously en- then be raised to permit completion of the stack tered data and places the new byte on the top of access. stack (TOS). Data on the bottom of the stack prior to 3. The 8231A is not busy, and data removal has a stack entry are lost. been requested. READY will be pulled low for the length of time necessary to transfer the byte from the top of stack to the interface latch, and will DATA REMOVAL then go high, indicating availability of the data. Data are removed from the stack in the 8231A by 4. The 8231A is not busy, and a data entry has been bringing chip select (CS), command/data (Ag), and requested. READY will be pulled tow for the RD low as shown in the timing diagram. The removal length of time required to ascertain if the preced- of each data world redefines TOS so that the next ing data byte, if any, has been written to the stack. successive byte to be removed becomes TOS. Data If so READY will immediately go high. If not, removed from the stack rotates to the bottom of the READY will remain low until the interface latch is stack. free and will then go high. 5. When a status read has been requested, READY COMMAND ENTRY will be pulled low for the length of time necessary After the appropriate number of bytes of data have well on be tae area nee te ang been entered onto the stack, a command may be status read. Status may be read whether or not issued to perform an operation on that data. Com- the 8231A is busy. mands which require two operands for execution (@.g., add) operate on the TOS and NOS values. Sin- When READY goes low, the APU expects the bus gle operand commands operate only on the TOS. control signals present at the time to remain stable Commands are issued to the 8231A by bringing the Unt! READY goes high. chip select (CS) line low, command data (Ag) line high, and WR line low as indicated by the timing dia- DEVICE STATUS fam. After a command is issued, the CPU can con- ; ; tne execution of its program concurrently with the pevice status 's provided by means oh ean internal 8231A command execution. Stalus register whose format is shown a COMMAND COMPLETION fuse om geno be ammo come = —- =} canny The 8231A signals the completion of each com- mand execution by lowering the End Execution line | * ° (END). Simultaneously, the busy bit in the status reg- 231905-9
stack is negative (1 = Negative) may be input by the CPU. 0100—Square root or log of negative en. Variations are data dependent. row). 7 use of chained calculations, etc. not busy the operation is complete and the other Corn, . Table 5. Command Execution Times
form is that it typically exhibits very large errors that for the logarithm and exponential functions. Ta(X) = Cos n8; wheren = 0.1, 2 (2) LOG, the absolute error is 2 x 10-7. ‘exponential functions according to the equation: tem speed. Figure 3. Minimum Configuration Example
intel. 8231A i ae de gk wo, Se e Tr or Bpesmeseas os 4 a2 32 8 ; iB) ik i lik LA a : 3 ik Figure 4, High Performance Configuration Example
intel. 8231A ABSOLUTE MAXIMUM RATINGS* NOTICE: This is a production data sheet. The specifi- -o cations are subject to change without notice. Storage Temperature sees eee ~ 65°C to + 150°C * WARNING: Stressing the device bey the te “Operating Conditions" is not recommended and ex- All Signal Voitages with Respect may affect device reliability. tOVES ee evveeeseeeeeesteesee “O.5V 10 +7.0V D.C. AND OPERATING CHARACTERISTICS Ta = 0°C to 70°C, Vgg = OV, Voc = +5V +10%, Vpp = +12V +10% [ Parameters | Description | min | Typ | Max | Units | Test Conditions OuiputiGH voltage | 37 | | |v | ton = =200nA OuiputLowvortage | || 04 |v | i = 3.2ma InputiGH voltage | 20 | | voc | wv [| Inputtowvottage | -o5 | | os | v | Inputtoad Current | || #10 | wa | Ves<Vin<Voc | Datasusteakage | | | 210 | uA_| Vas +0.45 = Vout < Voo OaoutCapostace | te | [or] WoCapacitance [| | 10 | | or | NOTE: 1, Sampled, not 100% tested. A.C. TESTING INPUT, OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT a rest Powes low asd oe ©, - 150 pF 251908-12 I AC. Testing: Inputs are driven at 3.7V for a logical “1” and 0.4V. for a logic “0”, Timing measurements are made at 2.0V for a logic = “1” and 0.8V for a logic “0”. 231905-13 310
intel. 8231A eee A.C. CHARACTERISTICS T, = 0°C to 70°C, Vsg = OV, Voc = +5V +10%, Vpop = +12V 10% READ OPERATION ae aa | force | nme ee [ta | Aa CSseupoA oo | | tay | READY J tromAB 4 Delay Woteay || 150 | | 100 | ns _| [ta | Rey teoMBt To To Tn | pow [te] [ey Te | tran READY Pulse Width (Note 3) +80 +60 epee [Pay + 50 +50 [toe | DataBusénabiotromABY Tso | [sons | | tony | Oatavaistoneary tT oT Tons [ior | DeteFatanerAOT | s0 | ao | 50] 100 | ne WRITE OPERATION re Pe | OM Smo! Prem a a [aw | Ao cSseuptowR To To | [twa | An CSHoidaterwA | eo | fas Tons | tw | READY J tromWA | Delay (Note2) [| 150 | [100 | ne _| [tw | reaoytowat fo Po ne | terw [READY Pulse wath Notes) [so Ts ne Wate inactive Time | Command | atoy | | atoy [| ne | Pm [aces Fee ete | tow | OatasouproWR | ts0 | 00 | ns Ltwo | datanoidanerwR [0 Tf Pos |
intel. 8231A OTHER TIMINGS Syne ream aa a] Oo | [toy | Cock Period | 480 | S000 | 260 | 2500 | ns _| Clock Pulse High Width | 200 [| too [| ns | Clock Pulse Low Width [ao [| wo [| | [tec | ENDPusowiatn woos) | 400 | | 200 | |e [Ciexe | EROR J ENO T Oouy || me || me EACK Pulse Width | wo ff so fs SVACK J osvAEG | Dey | | 300 [ [150 | ns | SVACK Pulse Wieth [oo ff mo Ts | NOTES: 1. Typical values are for Ta = 25°C, nominal supply voltages processing parameters. 2. READY is pulled tow for both command and data operations. 3. Minimum values shown assume no previously entered command is being executed for the data access. If a previously ‘entered command is being executed, READY low pulse width is the time to complete execution plus the time shown. Status may be read at any time without exceeding the time shown. 4. READY low pulse width is less than 50 ns when writing into the data port or the control port as long as the duty cycle requirement (tyy)) is observed and no previous command is being executed. twi may be safely violated as long as the extended tapw that results is observed. if a previously entered command is being executed, READY low pulse width is the time to complete execution plus the time shown. These timings refer specifically to the 8231. 5. END low pulse width is specified for EACK tied to VSS. Otherwise tea applies. 3-12
intel. 8231A WAVEFORMS READ OPERATION te sewrel Fron Mo, tan tra Li} : vam = pease woe om “ne a 251505-14 is WRITE OPERATION Ao. — ws READY | tow |p co a oo 25130815 INTERRUPT OPERATION tx —+ END es Ol ae Te EXCR en ll ae ‘se j-—tss—| SVECK sa1ms-16 3-13