82091AA

Intel Corporation

ADVANCED INTEGRATED PERIPHERAL (AIP)

Manufacturer: Intel Corporation

Document: 204 Pages / 1Mb

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82091AA INTEL | Alldatasheet

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4.1.13 SBCFG2ÐSERIAL PORT B POWER MANAGEMENT AND STATUS
4.1.13.1 Serial Port A/B Configuration Registers SxEN and SxDPDN Bits ÀÀÀÀÀÀÀÀÀÀÀÀÀ
4.1.14 IDECFGÐIDE CONFIGURATION REGISTER ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
4.2 Hardware Configuration ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
4.2.1 SELECTING THE HARDWARE CONFIGURATION MODE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
4.2.2 SELECTING HARDWARE CONFIGURATION MODE OPTIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
4.2.3 HARDWARE CONFIGURATION TIMING RELATIONSHIPS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
4.2.4 HARDWARE BASIC CONFIGURATION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
4.2.5 HARDWARE EXTENDED CONFIGURATION MODE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
4.2.6 SOFTWARE ADD-IN CONFIGURATION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
4.2.7 SOFTWARE MOTHERBOARD CONFIGURATION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
5.0 HOST INTERFACE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
6.0 PARALLEL PORT ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
6.1 Parallel Port Registers ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
6.1.1 ISA-COMPATIBLE AND PS/2-COMPATIBLE MODES ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
6.1.1.1 PDATAÐParallel Port Data Register (ISA-Compatible and PS/2-Compatible
6.1.1.2 PSTATÐStatus Register (ISA-Compatible and PS/2-Compatible Modes) ÀÀÀÀÀ
6.1.1.3 PCONÐControl Register (ISA-Compatible and PS/2-Compatible Mode) ÀÀÀÀÀÀ
6.1.2 EPP MODE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
6.1.2.1 PDATAÐParallel Port Data Register (EPP Mode) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
6.1.2.2 PSTATÐStatus Register (EPP Mode) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
6.1.2.3 PCONÐControl Register (EPP Mode) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
6.1.2.4 ADDSTRÐEPP Auto Address Strobe Register (EPP Mode) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
6.1.2.5 DATASTRÐAuto Data Strobe Register (EPP Mode) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
6.1.3 ECP MODE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
6.1.3.1 ECPAFIFOÐECP Address/RLE FIFO Register (ECP Mode) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
6.1.3.2 PSTATÐStatus Register (ECP Mode) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
6.1.3.3 PCONÐControl Register (ECP Mode) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
6.1.3.4 SDFIFOÐStandard Parallel Port Data FIFO ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
6.1.3.5 DFIFOÐData FIFO (ECP Mode) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
6.1.3.6 TFIFOÐECP Test FIFO Register (ECP Mode) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
6.1.3.7 ECPCFGAÐECP Configuration A Register (ECP Mode) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
6.1.3.8 ECPCFGBÐECP Configuration B Register (ECP Mode) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
6.1.3.9 ECR ECPÐExtended Control Register (ECP Mode) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
6.2 Parallel Port Operations ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
6.2.1 ISA-COMPATIBLE AND PS/2-COMPATIBLE MODES ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
6.2.2 EPP MODE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
6.2.3 ECP MODE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ

Datasheet sections

6.2.3.1 FIFO Operations ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
6.2.3.2 DMA Transfers ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
6.2.3.3 Reset FIFO and DMA Terminal Count Interrupt ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
6.2.3.4 Programmed I/O Transfers ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
6.2.3.5 Data Compression ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
6.2.4 PARALLEL PORT EXTERNAL BUFFER CONTROL ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
6.2.5 PARALLEL PORT SUMMARY ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
7.0 SERIAL PORT ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
7.1 Register Description ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
7.1.1 THR(A,B)ÐTRANSMITTER HOLDING REGISTER ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
7.1.2 RBR(A,B)ÐRECEIVER BUFFER REGISTER ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
7.1.3 DLL(A,B), DLM(A,B)ÐDIVISOR LATCHES (LSB AND MSB) REGISTERS ÀÀÀÀÀÀÀÀÀÀ
7.1.4 IER(A,B)ÐINTERRUPT ENABLE REGISTER ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
7.1.5 IIR(A,B)ÐINTERRUPT IDENTIFICATION REGISTER ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
7.1.6 FCR(A,B)ÐFIFO CONTROL REGISTER ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
7.1.7 LCR(A,B)ÐLINE CONTROL REGISTER ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
7.1.8 MCR(A,B)ÐMODEM CONTROL REGISTER ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
7.1.9 LSR(A,B)ÐLINE STATUS REGISTER ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
7.1.10 MSR(A,B)ÐMODEM STATUS REGISTER ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
7.1.11 SCR(A,B)ÐSCRATCHPAD REGISTER ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
7.2 FIFO Operations ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
7.2.1 FIFO INTERRUPT MODE OPERATION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
7.2.2 FIFO POLLED MODE OPERATION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.0 FLOPPY DISK CONTROLLER ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.1 Floppy Disk Controller Registers ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.1.1 SRBÐSTATUS REGISTER B (EREG EN e1) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.1.2 DORÐDIGITAL OUTPUT REGISTER ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.1.3 TDRÐENHANCED TAPE DRIVE REGISTER ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.1.4 MSRÐMAIN STATUS REGISTER ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.1.5 DSRÐDATA RATE SELECT REGISTER ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.1.6 FDCFIFOÐFDC FIFO (DATA) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.1.7 DIRÐDIGITAL INPUT REGISTER ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.1.8 CCRÐCONFIGURATION CONTROL REGISTER ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.2 Reset ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.2.1 HARD RESET AND CONFIGURATION REGISTER RESET ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.2.2 DOR RESET vs DSR RESET ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.3 DMA Transfers ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.4 Controller Phases ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.4.1 COMMAND PHASE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.4.2 EXECUTION PHASE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ

Datasheet sections

8.4.2.1 Non-DMA Mode Transfers from the FIFO to the Host ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.4.2.2 Non-DMA Mode Transfers from the Host to the FIFO ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.4.2.3 DMA Mode Transfers from the FIFO to the Host ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.4.2.4 DMA Mode Transfers from the Host to the FIFO ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.4.3 DATA TRANSFER TERMINATION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.5 Command Set/Descriptions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.5.1 STATUS REGISTER ENCODING ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.5.1.1 Status Register 0 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.5.1.2 Status Register 1 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.5.1.3 Status Register 2 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.5.1.4 Status Register 3 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.5.2 DATA TRANSFER COMMANDS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.5.2.1 Read Data ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.5.2.2 Read Deleted Data ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.5.2.3 Read Track ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.5.2.4 Write Data ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.5.2.5 Verify ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.5.2.6 Format Track ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.5.2.7 Format Field ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.5.3 CONTROL COMMANDS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.5.3.1 READ ID Command ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.5.3.2 RECALIBRATE Command ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.5.3.3 DRIVE SPECIFICATION Command ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.5.3.4 SEEK Command ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.5.3.5 SENSE INTERRUPT STATUS Command ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.5.3.6 SENSE DRIVE STATUS Command ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.5.3.7 SPECIFY Command ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.5.3.8 CONFIGURE Command ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.5.3.9 VERSION Command ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.5.3.10 RELATIVE SEEK Command ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.5.3.11 DUMPREG Command ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.5.3.12 PERPENDICULAR MODE Command ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.5.3.13 POWERDOWN MODE Command ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.5.3.14 PART ID Command ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.5.3.15 OPTION Command ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.5.3.16 SAVE Command ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.5.3.17 RESTORE Command ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
8.5.3.18 FORMAT AND WRITE Command ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ

Datasheet sections

9.0 IDE INTERFACE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
9.1 IDE Registers ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
9.2 IDE Interface Operation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
10.0 POWER MANAGEMENT ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
10.1 Power Management Registers ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
10.2 Clock Power Management ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
10.3 FDC Power Management ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
10.4 Serial Port Power Management ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
10.5 Parallel Port Power Management ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
11.0 ELECTRICAL CHARACTERISTICS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
11.1 Absolute Maximum Ratings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
11.2 DC Characteristics ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
11.3 Oscillator ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
11.4 AC Characteristics ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
11.4.1 CLOCK TIMINGS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
11.4.2 HOST TIMINGS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
11.4.3 FDC TIMINGS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
11.4.4 PARALLEL PORT TIMINGS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
11.4.5 IDE TIMINGS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
11.4.6 GAME PORT TIMINGS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
11.4.7 SERIAL PORT TIMINGS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
12.0 PINOUT AND PACKAGE INFORMATION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
12.1 Pin Assignment ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
12.2 Package Characteristics ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
13.0 DATA SEPARATOR CHARACTERISTICS FOR FLOPPY DISK MODE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
13.1 Write Data Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
13.2 Drive Control ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
13.3 Internal PLL ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ

*Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. December 1995COPYRIGHT © INTEL CORPORATION, 1996 Order Number: 290486-003 82091AA ADVANCED INTEGRATED PERIPHERAL (AIP) Y Single-Chip PC Compatible I/O Solution for Notebook and Desktop Platforms: Ð 82078 Floppy Disk Controller Core Ð Two 16550 Compatible UARTs Ð One Multi-Function Parallel Port Ð IDE Interface Ð Integrated Back Power Protection Ð Integrated Game Port Chip Select Ð 5V or 3.3V Supply Operation with 5V Tolerant Drive Interface Ð Full Power Management Support Ð Supports Type F DMA Transfers for Faster I/O Performance Ð No Wait-State Host I/O Interface Ð Programmable Interrupt Interfaces Ð Single Crystal/Oscillator Clock (24 MHz) Ð Software Detectable Device ID Ð Comprehensive Powerup Configuration Y The 82091AA is 100 Percent Compatible with EISA, ISA and AT Y Host Interface Features Ð 8-Bit Zero Wait-State ISA Bus Interface Ð DMA with Type F Transfers Ð Five Programmable ISA Interrupt Lines Ð Internal Address Decoder Y Parallel Port Features Ð All IEEE Standard 1284 Protocols Supported (Compatibility, Nibble, Byte, EPP, and ECP) Ð Peak Bi-Directional Transfer Rate of

2 MB/sec

Ð Provides Interface for Low-Cost Engineless Laser Printer Ð 16-Byte FIFO for ECP Ð Interface Backpower Protection Y Floppy Disk Controller Features Ð 100 Percent Software Compatible with Industry Standard 82077SL and 82078 Ð Integrated Analog Data Separator 250K, 300K, 500K, and 1 MBits/sec Ð Programmable Powerdown Command Ð Auto Powerdown and Wakeup Modes Ð Integrated Tape Drive Support Ð Perpendicular Recording Support for

4 MB Drives

Ð Programmable Write Pre- Compensation Delays Ð 256 Track Direct Address, Unlimited Track Support Ð 16-Byte FIFO Ð Supports 2 or 4 Drives Y 16550 Compatible UART Features Ð Two Independent Serial Ports Ð Software Compatible with 8250 and

16450 UARTs

Ð 16-Byte FIFO per Serial Port Ð Two UART Clock Sources, Supports MIDI Baud Rate Y IDE Interface Features Ð Generates Chip Selects for IDE Drives Ð Integrated Buffer Control Logic Ð Dual IDE Interface Support Y Power Management Features Ð Transparent to Operating Systems and Applications Programs Ð Independent Power Control for Each Integrated Device Y 100-Pin QFP Package (See Packaging Spec. 240800) The 82091AA Advanced Integrated Peripheral (AIP) is an integrated I/O solution containing a floppy disk controller, 2 serial ports, a multi-function parallel port, an IDE interface, and a game port on a single chip. The integration of these I/O devices results in a minimization of form factor, cost and power consumption. The

notebooks. The 82091AA supports both motherboard and add-in card configurations. Figure 1. 82091AA Advanced Integrated Peripheral Block Diagram

ADVANCED INTEGRATED PERIPHERAL (AIP) CONTENTS PAGE

1.0 OVERVIEW ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8

1.1 3.3/5V Operating Modes ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 11

2.0 SIGNAL DESCRIPTION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 11

2.1 Host Interface Signals ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 13

2.2 Floppy Disk Controller Interface ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 15

2.3 Serial Port Interface ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 17

2.4 IDE Interface ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 18

2.5 Parallel Port External Buffer Control/Game Port ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 19

2.6 Parallel Port Interface ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 20

2.6.1 COMPATIBILITY PROTOCOL SIGNAL DESCRIPTION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 21

2.6.2 NIBBLE PROTOCOL SIGNAL DESCRIPTION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22

2.6.3 BYTE MODE SIGNAL DESCRIPTION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 23

2.6.4 ENHANCED PARALLEL PORT (EPP) PROTOCOL SIGNAL DESCRIPTION ÀÀÀÀÀÀÀ 24

2.6.5 EXTENDED CAPABILITIES PORT (ECP) PROTOCOL SIGNAL DESCRIPTION ÀÀÀÀ 24

2.7 Hard Reset Signal Conditions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 26

2.8 Power And Ground ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 27

3.0 I/O ADDRESS ASSIGNMENTS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 27

4.0 AIP CONFIGURATION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 29

4.1 Configuration Registers ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 29

4.1.1 CFGINDX, CFGTRGTÐCONFIGURATION INDEX REGISTER AND TARGET

PORT ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 30

4.1.2 AIPIDÐAIP IDENTIFICATION REGISTER ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 32

4.1.3 AIPREVÐAIP REVISION IDENTIFICATION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 32

4.1.4 AIPCFG1ÐAIP CONFIGURATION 1 REGISTER ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 33

4.1.5 AIPCFG2ÐAIP CONFIGURATION 2 REGISTER ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 34

4.1.6 FCFG1ÐFDC CONFIGURATION REGISTER ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 36

4.1.7 FCFG2ÐFDC POWER MANAGEMENT AND STATUS REGISTER ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 37

4.1.8 PCFG1ÐPARALLEL PORT CONFIGURATION REGISTER ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 38

4.1.9 PCFG2ÐPARALLEL PORT POWER MANAGEMENT AND STATUS

4.1.10 SACFG1ÐSERIAL PORT A CONFIGURATION REGISTER ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 42

4.1.11 SACFG2ÐSERIAL PORT A POWER MANAGEMENT AND STATUS

4.1.12 SBCFG1ÐSERIAL PORT B CONFIGURATION REGISTER ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 46

The 82091AA’s enhanced floppy disk controller (FDC) incorporates several new features allowing for easy implementation in both the portable and desk- top markets. It provides a low cost, small form factor solution targeted for 5.0V and 3.3V platforms. The FDC supports up to four drives. The 82091AA’s FDC implements these new features while remaining functionally compatible with 82078/ 82077SL/82077AA/8272A floppy disk controllers. Together, with a 24-MHz crystal, a resistor package and a device chip select, these devices allow for the most integrated solution available. The integrated analog PLL data separator has better performance than most board level discrete PLL implementations and can be operated at 1 Mbps/500 Kbps/ 300 Kbps/250 Kbps. A 16-byte FIFO substantially improves system performance and is ideal for multi- master systems (e.g., EISA). Serial Ports The 82091AA contains two independent serial ports that provide asynchronous communications that are equivalent to two 16550 UARTs. The serial ports have identical circuitry and provide the serial com- munication interface to a peripheral device or mo- dem via Serial Port A and Serial Port B. Each serial port can be configured for one of eight address as- signments. The standard PC/AT compatible logical address assignments for COM1, COM2, COM3, and COM4 are supported. The serial ports perform serial-to-parallel conversion on data characters received from a peripheral de- vice or modem, and parallel-to-serial conversion on data characters received from the host. The serial ports can operate in either FIFO mode or non-FIFO mode. In FIFO mode, a 16-byte transmit FIFO holds data from the host to be transmitted on the serial link and a 16-byte receive FIFO that buffers data from the serial link until read by the host. The serial ports contain programmable baud rate generators that divide the internal reference clock by divisors of 1 to (2 16 b 1), and produce a 16x clock for driving the transmitter and receiver logic. The internal reference clock can be programmed to support MIDI. The serial ports have complete mo- dem-control capability and a prioritized interrupt sys- tem. Parallel Port The 82091AA provides a multi-function parallel port that transfers information between the host and pe- ripheral device (e.g., printer). The parallel port inter- face contains nine control/status lines and an 8-bit data bus. The standard PC/AT compatible logical address assignments for LPT1, LPT2, and LPT3 are supported. The parallel port can be configured for one of four modes and supports the following IEEE Standard 1284 parallel interface protocol standards: Parallel Port Parallel Interface Mode Protocol ISA-Compatible Mode Compatibility, Nibble PS/2-Compatible Mode Byte EPP Mode EPP ECP Mode ECP For ISA-Compatible and PS/2-Compatible modes, software controls the handshake signals on the par- allel port interface to transfer data between the host and peripheral device. Status and Control registers permit software to monitor the state of the peripheral device and generate handshake sequences. The EPP parallel port interface protocol increases throughput by specifying an automatic handshake sequence. In EPP mode, the 82091AA parallel port automatically generates this handshake sequence in hardware to transfer data between the host and peripheral device.

In addition to a hardware handshake on the parallel port interface, the ECP protocol specification also defines DMA and FIFO capability. To minimize pro- cessor overhead data transfer to/from a peripheral device, the 82091AA parallel port, in ECP mode, provides a 16-byte FIFO with DMA capability. IDE Interface The 82091AA supports the IDE (Integrated Drive Electronics) interface by providing chip selects and lower data byte control. Two chip selects are used to access registers on the IDE device. Separate lower and upper byte data control signals are provided. With these control signals, minimal external logic is needed to implement 16-bit IDE I/O and DMA inter- faces. Game Port The 82091AA provides a game port chip select sig- nal for use when the 82091AA is in an add-in card application. This function is assigned to I/O address location 201h. Note that when the 82091AA is locat- ed on the motherboard, this feature is not available. Power Management 82091AA power management provides a mecha- nism for saving power when the device or a portion of the device is not being used. By programming the appropriate 82091AA registers, software can invoke power management to the entire 82091AA or select- ed modules within the 82091AA (e.g., floppy disk controller, serial port, or parallel port). There are two methods for applying power managementÐdirect powerdown or auto powerdown. Direct powerdown turns off the clock to a particular module immediate- ly placing that module into a powerdown state. This method removes the clock regardless of the activity or status of the module. When auto powerdown is invoked, the module enters a powerdown state (clock is turned off) after certain conditions are met and the module is in an idle state. 1.1. 3.3V/5V Operating Modes The 82091AA can operate at a power supply of 3.3V, 5V or a mix of 3.3V and 5V. The mixed power supply mode provides 5V interfaces for the floppy disk controller and parallel port while all other 82091AA interfaces and internal logic (including the floppy disk controller and parallel port internal cir- cuitry) operate at 3.3V. The mixed mode permits 5V floppy disk drives and parallel port peripherals to be used in a 3.3V system without external buffering. NOTE: 3.3V operation is available only in the 82091AA. 2.0. SIGNAL DESCRIPTION This section describes the 82091AA signals. The in- terface signals are shown in Figure 5 and described in the following tables. Signal descriptions are orga- nized by functional group. Note that the ‘‘ Ý’’ symbol at the end of a signal name indicates the active, or asserted, state occurs when the signal is at a low voltage level. When ‘‘ Ý’’ is not present after the signal name, the signal is asserted when at the high voltage level. The terms assertion and negation are used exten- sively. This is done to avoid confusion when working with a mixture of ‘‘active-low’’ and ‘‘active-high’’ sig- nals. The term assert,o r assertion, indicates that a signal is active, independent of whether that level is represented by a high or low voltage. The term ne- gate,o r negation, indicates that a signal is inactive. The following notations are used to describe pin types: I Input Pin O Output Pin I/O Bi-Directional Pin

Figure 5. 82091AA Signals

2.1 Host Interface Signals

Signal Type DescriptionName ISA SIGNALS SA[10:0] I SYSTEM ADDRESS BUS: The 82091AA decodes the standard ISA I/O address space using SA [9:0]. SA10 is used along with SA [9:0] to decode the extended register set of the ECP parallel port. SA [10:0] connects directly to the ISA system address bus. SD[7:0] I/O SYSTEM DATA BUS: SD[7:0] is a bi-directional data bus. Data is written to and read from the 82091AA on these signal lines. SD [7:0] connect directly to the ISA system data bus. IORCÝ I I/O READ COMMAND STROBE: IORCÝ is an I/O access read control signal. When a valid internal address is decoded by the 82091AA and IORC Ý is asserted, data at the decoded address location is driven onto the SD [7:0] signal lines. IOWCÝ I I/O WRITE COMMAND STROBE: IOWCÝ is an I/O access write control signal. When a valid internal address is decoded by the 82091AA and IOWC Ý is asserted, data on the SD [7:0] signal lines is written into the decoded address location at the rising edge of IOWC Ý. NOWSÝ O NO WAIT-STATES: End data transfer signal. The 82091AA asserts NOWS Ý when a valid internal address is decoded by the 82091AA and the IORC Ý or IOWC Ý signal is asserted. This reduces the total bus cycle time by eliminating the wait- states associated with the default 8-bit I/O cycles. NOWS Ý is not asserted for IDE accesses or DMA accesses. This is an open drain output pin. IOCHRDY O I/O CHANNEL READY: The 82091AA uses this signal for parallel port data transfers when the parallel port is in EPP mode. In this case, the 82091AA negates IOCHRDY to extend the cycle to allow for completion of transfers to/from the peripheral attached to the parallel port. When the parallel port is in EPP mode, the 82091AA negates IOCHRDY to lengthen the ISA Bus cycle if the parallel port BUSY signal is asserted. The 82091AA also uses IOCHRDY during hardware configuration time (see Section 4.0, AIP Configuration). If IOWC Ý/IORCÝ is asserted to the 82091AA during hardware configuration time, the 82091AA negates IOCHRDY until hardware configuration time is completed. This is an open drain output pin. AEN I ADDRESS ENABLE: AEN is used during DMA cycles to prevent the 82091AA from misinterpreting DMA cycles from valid I/O cycles. When negated, AEN indicates that the 82091AA may respond to address and I/O commands addressed to the 82091AA. When asserted, AEN informs the 82091AA that a DMA transfer is occurring. When AEN is asserted and a xDACK Ý signal is asserted, the 82091AA responds to the cycle as a DMA cycle. RSTDRV I RESET DRIVE: RSTDRV forces the 82091AA to a known state. All 82091AA registers are set to their default state. X1/OSC I CRYSTAL1/OSCILLATOR: Main clock input signal can be a 24 MHz crystal connected across X1 and X2 or a 24 MHz TTL level clock input connected to X1. X2 I CRYSTAL2: This signal pin is connected to one side of the crystal when a crystal oscillator is used to provide the main clock. If an external oscillator/clock is connected to X1, this pin is not used and left unconnected.

2.1 Host Interface Signals (Continued)

Signal Type DescriptionName DMA SIGNALS FDDREQ O FLOPPY DISK CONTROLLER DMA REQUEST: The 82091AA asserts FDDREQ to request service from a DMA controller for the FDC module. This signal is enabled/disabled by bit 3 of the Digital Output Register (DOR). When disabled, FDDREQ is tri-stated. FDDACKÝ I FLOPPY DISK CONTROLLER DMA ACKNOWLEDGE: The DMA controller asserts this signal to acknowledge the FDC DMA request. When asserted, the IORC Ý and IOWC Ý inputs are enabled during DMA transfers. This signal is enabled/disabled by bit 3 of the DOR. PPDREQ O PARALLEL PORT DMA REQUEST: Parallel port DMA service request to the system DMA controller. This signal is only used when the parallel port is in ECP hardware mode and is always negated when the parallel port is not in this mode. In ECP hardware mode DMA requests are enabled/disabled by bit 3 of the ECP Extended Control Register (ECR). When disabled, PPDREQ is tri-stated. PPDACKÝ I PARALLEL PORT DMA ACKNOWLEDGE: The DMA controller asserts this signal to acknowledge the parallel port DMA request. When asserted the IORC Ý and IOWCÝ inputs are enabled during DMA transfers. This signal is enabled/disabled by bit 3 of the ECR Register. TC I TERMINAL COUNT: The system DMA controller asserts TC to indicate it has reached the last programmed data transfer. TC is accepted only when FDDACK Ý or PPDACK Ý is asserted. INTERRUPT SIGNALS IRQ3, IRQ4 O INTERRUPT 3 AND 4: IRQ3 and IRQ4 are associated with the serial ports and can be programmed (via the AIPCFG2 Register) to be either active high or active low. These signals can be configured for a particular serial channel via hardware configuration (at powerup) or by software configuration. Under Hardware Configuration IRQ3 is used as a serial port interrupt if the serial port is configured at address locations 2F8h–2FFh or 2E8h–2EFh. IRQ4 is used as a serial port interrupt if the serial port is configured at address locations 3F8h–3FFh or 3E8h–3EFh. Under Software configuration IRQ3 and IRQ4 are independently configured (i.e., the IRQ does not automatically track the communication port address assignment). These interrupts are enabled/disabled globally via bit 3 of the serial port Modem Control Register (MCR) and for specific conditions via the Interrupt Enable Register (IER). IRQ3 and IRQ4 are tri-stated when not enabled. IRQ5, IRQ7 O INTERRUPT REQUEST 5: IRQ5 and IRQ7 are associated with the parallel port and can be programmed (via AIPCFG2 Register) to be either active high or active low. Either IRQ5 or IRQ7 is enabled/disabled via PCFG1 Register to signal a parallel port interrupt. The interrupt not selected is disabled and tri-stated. During hardware configuration (see Section 4.0, AIP Configuration), IRQ5 is used if the parallel port is assigned to 278h–27Fh and IRQ7 is used if the parallel port interrupt is assigned to either 3BCh–3BFh or 378h–37Fh.

Signal Type DescriptionName INTERRUPT SIGNALS (Continued) IRQ6 O INTERRUPT REQUEST 6: IRQ6 is associated with the floppy disk controller and can be programmed (via the AIPCFG2 Register) to be either active high or active low. In non-DMA mode this signal is asserted to signal when a data transfer is ready. IRQ6 is also asserted to signal the completion of the execution phase for certain FDC commands. This signal is enabled/disabled by the DMAGATE bit in the Digital Output Register of the FDC. The signal is tri-stated when disabled.

2.2 Floppy Disk Controller Interface

Signal Type DescriptionName RDDATAÝ I READ DATA: Serial data from the disk drive. WRDATAÝ O WRITE DATA: MFM serial data to the disk drive. Precompensation value is selectable through software. HDSEL O HEAD SELECT: Selects which side of a disk is to be accessed. When asserted (low), side 1 is selected. When negated (high), side 0 is selected. STEPÝ O STEP: STEPÝ supplies step pulses (asserted) to the drive to move the head between the tracks during a seek operation. DIRÝ O DIRECTION: Controls the direction the head moves when a step signal is present. The head moves toward the center when DIR Ý is asserted and away from the center when negated. WEÝ O WRITE ENABLE: WEÝ is a disk drive control signal. When asserted, WE Ý enables the head to write to the disk. TRK0Ý I TRACK0: The disk drive asserts this signal to indicate that the head is on track 0. INDXÝ I INDEX: The disk drive asserts this signal to indicate the beginning of the track. WPÝ I WRITE PROTECT: The disk drive asserts this signal to indicate that the disk drive is write-protected. DSKCHG I DISK CHANGE: The disk drive asserts this signal to indicate that the drive door has been opened. The state of this signal input is available in the Digital Input Register (DIR Ý). DRIVDEN0 O DRIVE DENSITY: These signals are used by the disk drive to configure the drive for the appropriate media density. These signals are controlled by the FDC’s DriveDRIVDEN1 Specification Command.

2.2 Floppy Disk Controller Interface (Continued)

Signal Type DescriptionName FDME1Ý/O FLOPPY DRIVE MOTOR ENABLE 1, IDLE, OR DRIVE SELECT ENABLE: This signal pin has two functions (1). FDME1 Ý is the motor enable for drive 1. FDME1 ÝDSENÝ(1) is directly controlled via the Digital Output Register (DOR) and is a function of the mapping based on the BOOTSEL bits in the Tape Drive Register (TDR). The Drive Select Enable (DSEN Ý) function is only used in a four floppy drive system (see Appendix A, FDC Four Drive Support). FDS1Ý/O FLOPPY DRIVE SELECT1, POWERDOWN, OR MOTOR DRIVE SELECT 1: This signal pin has two functions (1). FDS1 Ý is the floppy drive select for drive 1. FDS1 ÝMDS1(1) is controlled by the select bits in the DOR and is a function of the mapping based on the BOOTSEL bits in the TDR. The Motor Drive Select 1 (MDS1) function is only used in a four floppy drive system (see Appendix A, FDC Four Drive Support). FDME0Ý/O FLOPPY DRIVE MOTOR ENABLE 0 OR MOTOR ENABLE ENABLE: This signal pin has two functions (1). FDME0 Ý is the motor enable for drive 0. FDME0 Ý isMEENÝ(1) directly controlled via the Digital Output Register (DOR) and is a function of the mapping based on the BOOTSEL bits in the Tape Drive Register (TDR). The Motor Enable Enable (MEEN Ý) function is only used in a four floppy drive system (see Appendix A, FDC Four Drive Support). FDS0Ý/O FLOPPY DRIVE SELECT 0 OR MOTOR DRIVE SELECT 0: This signal pin has two functions(1). FDS0 Ý is the floppy drive select for drive 0. This output is controlledMDS0(1) by the drive select bits in the DOR and is a function of the mapping based on BOOTSEL bits in the TDR. The Motor Drive Select 0 (MDS0) function is only used in a four floppy drive system (see Appendix A, FDC Four Drive Support). NOTE: 1. The function selected for these pins is based on the FDDQTY bit in the FCFG1 Register as shown in the following table. Signal Pin 2 Drive System 4 Drive System (FDDQTYe0) (FDDQTY e1) FDME1Ý/DSENÝ FDME1Ý DSENÝ FDS1Ý/MDS1Ý FDS1Ý MDS1 FDME0Ý/MEENÝ FDME0Ý MEENÝ FDS0Ý/MDS0 FDS0 Ý MDS0 When FDDQTY e1, these signal pins are used to control an external decoder for a four floppy disk drive system as described in Appendix A, FDC Four Drive Support.

2.3 Serial Port Interface

Serial Port A signal names end in the letter A and Serial Port B signal names end in the letter B. Serial Port A and B signals have the same functionality. Signal Type DescriptionName CTSAÝ,I CLEAR TO SEND: When asserted, this signal indicates that the modem or data set is ready to exchange data. The CTS Ý signal is a modem status input whoseCTSBÝ condition the CPU can determine by reading the CTS bit in Modem Status Register (MSR) for the appropriate serial port. The CTS bit is the compliment of the CTS Ý signal. The DCTS bit in the MSR indicates whether the CTS Ý input has changed state since the previous reading of the MSR. CTS Ý has no effect on the transmitter. DCDAÝ,I DATA CARRIER DETECT: When asserted, this signal indicates that the data carrier has been detected by the modem or data set. The DCD Ý signal is aDCDBÝ modem status whose condition the CPU can determine by reading the DCD bit in the MSR for the appropriate serial port. The DCD bit is the compliment of the DCD Ý signal. The DDCD bit in the MSR indicates whether the DCD Ý input has changed state since the previous reading of the MSR. DCD Ý has no effect on the transmitter. DSRAÝ,I DATA SET READY: When asserted, this signal indicates that the modem or data set is ready to establish the communications link with the serial port module. TheDSRBÝ DSRÝ signal is a modem status whose condition the CPU can determine by reading the DSR bit in the MSR for the appropriate serial channel. The DSR bit is the compliment of the DSR Ý signal. The DSR bit in the MSR indicates whether the DSR Ý input has changed state since the previous reading of the MSR. DSR Ý has no effect on the transmitter. DTRAÝ, I/O DATA TERMINAL READY: DTRAÝ/DTRBÝ are outputs during normal system operations. When asserted, this signal indicates to the modem or data set thatDTRBÝ the serial port module is ready to establish a communications link. The DTR Ý signal can be asserted via the Modem Control Register (MCR). A hard reset negates this signal. Hardware Configuration These signals are only inputs during hardware configuration time (RSTDRV asserted and for a short time after RSTDRV is negated). (See Section 4.0, AIP Configuration.) RIAÝ, RIB Ý I RING INDICATOR: When asserted, this signal indicates that a telephone ringing signal has been received by the modem or data set. The RI Ý signal is a modem status input whose condition the CPU can determine by reading the RI bit in the MSR for the appropriate serial channel. The RI bit is the compliment of the RI Ý signal. The TERI bit in the MSR indicates whether the RI Ý input has changed from low to high since the previous reading of the MSR.

2.3 Serial Port Interface (Continued)

Signal Type DescriptionName RTSAÝ, I/O REQUEST TO SEND: RTSAÝ/RTSBÝ are outputs during normal system operations. When asserted, this signal informs the modem or data set that theRTSBÝ serial port module is ready to exchange data. The RTS Ý signal can be asserted via the RTS bit in the Modem Control Register. A hard reset negates this signal. Hardware Configuration These signals are only inputs during hardware configuration time (RSTDRV asserted and for a short time after RSTDRV is negated). (See Section 4.0, AIP Configuration.) SINA, SINB I SERIAL INPUT: Serial data input from the communications link. (Peripheral device, modem, or data set.) SOUTA, I/O SERIAL OUTPUT: SOUTA/SOUTB are serial data outputs to the communications link during normal system operations. (Peripheral device, modem, or data set.) TheSOUTB SOUT signal is set to a marking state (logic 1) after a hard reset. Test Mode In test mode (selected via the SACFG2 or SBCFG2 Registers), the baudout from the baud rate generator is output on SOUTx. Hardware Configuration These signals are only inputs during hardware configuration time (RSTDRV asserted and for a short time after RSTDRV is negated). (See Section 4.0, AIP Configuration.)

2.4 IDE Interface

Signal Type DescriptionName IO16Ý I 16-BIT I/O: This signal is driven by I/O devices on the ISA Bus to indicate support for 16-bit I/O bus cycles. The IDE interface asserts this signal to the 82091AA to indicate support for 16-bit transfers. For IDE transfers, the 82091AA asserts HEN Ý when IO16 Ý is asserted. IDECS[1:0]Ý I/O IDE CHIP SELECT: IDECS[1:0]Ý are outputs during normal system operation and are chip selects for the IDE interface. IDECS [1:0]Ý select the Command Block Registers of the IDE device and are decoded from SA [9:3] and AEN. Hardware Configuration These signals are only inputs during hardware configuration time (RSTDRV asserted). (See Section 4.0, AIP Configuration.)

2.4 IDE Interface (Continued)

Signal Type DescriptionName DENÝ I/O DATA ENABLE: DENÝ is an output during normal system operations and is a data enable for an external data buffer for all 82091AA and IDE accesses. The SD [7:0] signals can be connected directly to the ISA. In this case, the DEN Ý signal is not used. However, an external buffer can be used to isolate the SD [7:0] signals from the 240 pF loading of the ISA Bus. With an external buffer implementation, DEN Ý controls the external buffers for transfers to/from the ISA Bus. Hardware Configuration This signal is only an input during hardware configuration time (RSTDRV asserted). (See Section 4.0, AIP Configuration.) HENÝ I/O IDE UPPER DATA TRANSCEIVER ENABLE: HENÝ is an output during normal system operations and is a high byte data transceiver enable signal for the IDE hard disk drive interface. HEN Ý is asserted for I/O accesses to the IDE data register when the drive asserts IO16 Ý. Hardware Configuration This signal is only an input during hardware configuration time (RSTDRV asserted). (See Section 4.0, AIP Configuration.)

2.5 Parallel Port External Buffer Control/Game Port

Signal Type DescriptionName PPDIR/GCSÝ I/O PARALLEL PORT DIRECTION (PPDIR) or GAME PORT CHIP SELECT (GCSÝ): This signal is an output during normal operations and provides the PPDIR and GCS Ý functions as follows: PPDIR This signal pin functions as a parallel port direction control output when the 82091AA is configured for software motherboard mode (SWMB). For configuration details, see Section 4.0, AIP Configuration. If external buffers are used on PD [7:0], PPDIR can be used to control the buffer direction. The 82091AA drives this signal low when PD [7:0] are outputs and the 82091AA drives this signal high when PD [7:0] are inputs. Note that if a configuration mode other than SWMB is selected, this signal pin is a game port chip select and does not track the PD [7:0] signal direction. GCSÝ This signal pin functions as a game port chip select output when 82091AA configuration is set for Software Add-In (SWAI), Hardware Basic (HWB), or Hardware Extended (HWE) modes. When the host accesses I/O address 201h, GCS Ý is asserted. Hardware Configuration This signal is only an input during hardware configuration time (RSTDRV asserted). (See Section 4.0, AIP Configuration.)

2.6 Parallel Port Interface

port hardware mode selected and the protocol used. a signal description for the five interface protocols. via software and the peripheral device. Table 1. Parallel Port Signal Name Cross Reference Not all parallel port signal pins are used for certain parallel port interface protocols. These signals are labeled ‘‘Ð’’.

2.6.1 COMPATIBILITY PROTOCOL SIGNAL DESCRIPTION

Except for the data bus, the 82091AA and compatibility protocol signal names are the same. For the data bus, the 82091AA signal names PD [7:0] corresponds to the compatibility protocol signal names Data [8:1]. 82091AA Signal Type Compatibility Protocol Signal Name and Description Name STROBEÝ O STROBE: The host asserts STROBE Ý to latch data into the peripheral device’s input latch. This signal is controlled via the PCON Register. BUSY I BUSY: BUSY is asserted by the peripheral to indicate that the peripheral device is not ready to receive data. The status of this signal line is reported in the PSTAT Register. ACKÝ I ACKNOWLEDGE: The printer asserts this signal to indicate that it has received the data and is ready for new data. The status of this signal line is reported in the PSTAT Register. SELECT I SELECT: SELECT is asserted by the peripheral device to indicate that the device is on line. The status of this signal line is reported in the PSTAT Register. PERROR I PAPER ERROR: The peripheral device asserts PERROR to indicate that it has encountered an error in the paper path. The exact meaning varies from peripheral device to peripheral device. The status of this signal line is reported in the PSTAT Register. FAULTÝ I FAULT: FAULTÝ is asserted by the peripheral device to indicate that an error has occurred. The status of this signal line is reported in the PSTAT Register. INITÝ O INITIALIZE: The host asserts INIT Ý to issue a hardware reset to the peripheral device. This signal is controlled via the PCON Register. AUTOFDÝ O AUTO FEED: AUTOFDÝ is asserted by the host to put the peripheral device into auto-line feed mode. This means that when software asserts this signal, the printer is instructed to advance the paper one line for each carriage return encountered. This signal is controlled via the PCON Register. PD[7:0] O DATA: Forward channel data. SELECTINÝ O SELECT INPUT: SELECTINÝ is asserted by the host to select a peripheral device. This signal is controlled via the PCON Register.

2.6.2 NIBBLE PROTOCOL SIGNAL DESCRIPTION

The Nibble protocol assigns the following signal operation to the parallel port pins. The name in bold at the beginning of the signal description column is the Nibble protocol signal name. The terms assert and negate are used in accordance with the 82091AA signal name as described at the beginning of Section 2.0. For example, AUTOFD Ý (HostBusy) asserted refers to AUTOFD Ý (HostBusy) at a low level. 82091AA Signal Type Nibble Protocol Signal Name and Description Name STROBEÝ O STROBE: The host controls this signal via the PCON Register and STROBE Ý should be held negated by the host. BUSY I PRINTER BUSY (PtrBusy): The peripheral drives this signal to transfer data bits 3 and 7 sequentially. The status of this signal line is reported in the PSTAT Register. ACKÝ I PRINTER CLOCK (PtrClk): The peripheral device asserts ACK Ý (PtrClk) to indicate to the host that data is available. The signal is subsequently asserted to qualify data being sent to the host. The status of this signal line is reported in the PSTAT Register. If interrupts are enabled via the PCON Register, the assertion of this signal causes a host interrupt to be generated. SELECT I XFLAG: The peripheral device drives this signal to transfer data bits 1 and 5 sequentially. The status of this signal line is reported in the PSTAT Register. PERROR I ACKNOWLEDGE DATA REQUEST (AckDataReq): This signal is initially high. The peripheral device drives this signal low to acknowledge HostBusy assertion. PERROR is subsequently used to transfer data bits 2 and 6 sequentially. The status of this signal line is reported in the PSTAT Register. FAULTÝ I DATA AVAILABLE (DataAvail): The peripheral device asserts FAULT Ý (DataAvail) to indicate data availability. Subsequently used to transfer data bits 0 and 4 sequentially. The status of this signal line is reported in the PSTAT Register. INITÝ O INITIALIZE: The host controls this signal via the PCON Register. AUTOFDÝ O HOST BUSY (HostBusy): The host negates AUTOFD Ý (HostBusy) in response to ACK Ý being asserted. This signal is subsequently driven low to enable the peripheral to transfer data to the host. AUTOFD Ý is then driven high to acknowledge receipt of byte data. This signal is controlled via the PCON Register. PD[7:0] O DATA: This 8-bit output data path to the peripheral Host data is written to the peripheral attached to the parallel port interface on these signal lines. SELECTINÝ O SELECT INPUT: This signal is controlled by the PCON Register.

2.6.3 BYTE MODE SIGNAL DESCRIPTION

The Byte protocol assigns the following signal operation to the parallel port pins. The name in bold at the beginning of the signal description column is the Byte protocol signal name. The terms assert and negate are used in accordance with the 82091AA signal name as described at the beginning of Section 2.0. For example, STROBE Ý (HostClk) asserted refers to STROBE Ý (HostClk) at a low level. 82091AA Type Byte Protocol Signal Name and DescriptionSignal Name STROBEÝ O HOST CLOCK (HostClk): This signal is strobed low by the host to acknowledge receipt of data. Note that the peripheral must not interpret this as a latch strobe for forward channel data. BUSY I PRINTER BUSY (PtrBusy): The peripheral device asserts BUSY (PtrBusy) to provide forward channel peripheral busy status. The status of this signal line is reported in the PSTAT Register. ACKÝ I PRINTER CLOCK (PtrClk): The peripheral device asserts ACK Ý (PtrClk) to indicate to the host that data is available. The signal is subsequently asserted to qualify data being sent to the host. The status of this signal line is reported in the PSTAT Register. If interrupts are enabled via the PCON Register, the assertion of this signal causes a host interrupt to be generated. SELECT I XFLAG: SELECT (XFLAG) is asserted by the peripheral device to indicate that the device is on line. The status of this signal line is reported in the PSTAT Register. PERROR I ACKNOWLEDGE DATA REQUEST (AckDataReq): This signal is initially high. The peripheral device drives this signal low to acknowledge HostBusy assertion. The status of this signal line is reported in the PSTAT Register. FAULTÝ I DATA AVAILABILITY (DataAvail): The peripheral device asserts FAULT Ý (DataAvail) to indicate data availability. The status of this signal line is reported in the PSTAT Register. INITÝ O INITIALIZE: The host controls this signal via the PCON Register and INIT Ý should be held in the negated state. AUTOFDÝ O HOST BUSY (HostBusy): The host negates AUTOFD Ý (HostBusy) in response to ACK Ý being asserted.The signal is subsequently driven low to enable the peripheral to transfer data to the host. AUTOFD Ý is then driven high to acknowledge receipt of nibble data. This signal is controlled via the PCON Register. PD[7:0] O DATA: This 8-bit data bus is used for bi-directional data transfer. SELECTINÝ I/O SELECT INPUT: This signal is controlled by the PCON Register.

2.6.4 ENHANCED PARALLEL PORT (EPP) PROTOCOL SIGNAL DESCRIPTION

EPP protocol assigns the following signal operation to the parallel port pins. The name in bold at the beginning of the signal description column is the EPP mode signal name. The terms assert and negate are used in accordance with the 82091AA signal name as described at the beginning of Section 2.0. For example, BUSY (Wait Ý) asserted refers to BUSY (Wait Ý) being high. 82091AA Type EPP Protocol Signal Name and DescriptionSignal Name STROBEÝ O WRITE (Write Ý): STROBEÝ (WriteÝ) indicates an address or data read/write operation to the peripheral. The 82091AA drives this signal low for a write and high for a read. BUSY I WAIT (Wait Ý): The peripheral sets BUSY (Wait Ý) low to indicate that the device is not ready. When BUSY signal is low, the 82091AA negates IOCHRDY on the ISA Bus to lengthen the I/O cycles. The peripheral device sets BUSY (Wait Ý) high to indicate that transfer of data or address is completed. ACKÝ I INTERRUPT REQUEST (Intr): The peripheral asserts ACK Ý (Intr) to generate an interrupt the host. When this signal is low and interrupts are enabled via bit 4 of the PCON Register, the 82091AA generates an interrupt request (via either IRQ5 or IRQ7) to the host. SELECT I SELECT: SELECT is asserted by the peripheral device to indicate that the device is on line. The status of this signal line is reported in the PSTAT Register. PERROR I PAPER ERROR: The peripheral device asserts PERROR to indicate that it has encountered an error in the paper path. The exact meaning varies from peripheral device to peripheral device. The status of this signal line is reported in the PSTAT Register. FAULTÝ I FAULT: FAULTÝ is asserted by the peripheral device to indicate that an error has occurred. The status of this signal line is reported in the PSTAT Register. INITÝ O INITIALIZE: The host asserts INIT Ý to issue a hardware reset to the peripheral device. This signal is controlled via the PCON Register. AUTOFDÝ O DATA STROBE (DStrb Ý): The 82091AA asserts AUTOFD Ý (DStrbÝ)t o indicate that valid data is present on PD [7:0] and is used by the peripheral to latch data during write cycles. For reads, the 82091AA reads in data from PD[7:0] when this signal is asserted. PD[7:0] I/O DATA: This 8-bit bi-directional bus provides addresses or data during the write cycles and supplies addresses or data to the 82091AA during the read cycles. SELECTINÝ O ADDRESS STROBE (AStrb Ý): The 82091AA asserts SELECTIN Ý (AStrbÝ)t o indicate that a valid address is present on PD [7:0] and is used by the peripheral to latch addresses during write cycles. For reads, the 82091AA reads in an address from PD [7:0] when this signal is asserted.

2.6.5 EXTENDED CAPABILITIES PORT (ECP) PROTOCOL SIGNAL DESCRIPTION

ECP protocol assigns the following signal operation to the parallel port pins. The name in bold at the beginning of the signal description column is the ECP protocol signal name. The terms assert and negate are used in accordance with the 82091AA signal name as described at the beginning of Section 2.0. For example, STROBE Ý (HostClk) asserted refers to STROBE Ý (HostClk) being low.

Signal Type ECP Protocol Signal Name and Description Name STROBEÝ O HOST CLOCK (HostClk): In the forward direction, the 82091AA asserts STROBEÝ (HostClk) to instruct the peripheral to latch the data on PD [7:0]. During write operations, the peripheral should latch data on the rising edge of STROBE Ý (HostClk). STROBE Ý (HostClk) handshakes with BUSY (PeriphAck) during write operations and is negated after the 82091AA detects BUSY (PeriphAck) asserted. STROBE Ý (HostClk) is not asserted by the 82091AA again until BUSY (PeriphAck) is detected negated. For read operations (reverse direction), STROBE Ý (HostClk) is not used. BUSY I PERIPHERAL ACKNOWLEDGE (PeriphAck): The peripheral device asserts this signal during a host write operation to acknowledge receipt of data. The peripheral device then negates the signal after STROBE Ý is detected high to terminate the transfer. For host write operations (forward direction), this signal handshakes with STROBE Ý (HostClk). During a host read operation (reverse direction), BUSY (PeriphAck) is normally low and is driven high by the peripheral to identify Run Length Encoded (RLE) data. ACKÝ I PERIPHERAL CLOCK (PeriphClk): During a peripheral to host transfer (reverse direction), ACK Ý (PeriphClk) is asserted by the peripheral to indicate data is valid on the data bus and then negated after AUTOFD Ý is detected high. This signal handshakes with AUTOFD Ý to transfer data. SELECT I XFLAG (Xflag): This signal is asserted by the peripheral to indicate that it is on- line. The status of this signal line is reported in the PSTAT Register. PERROR I ACKNOWLEDGE REVERSE (AckReverse Ý): PERROR (AckReverse Ý)i s driven low by the peripheral to acknowledge a reverse transfer request by the host. This signal handshakes with INIT Ý (ReverseRequestÝ). The status of this signal line is reported in the PSTAT Register. FAULTÝ I PERIPHERAL REQUEST (PeriphRequest Ý): The peripheral asserts FAULT Ý (PeriphRequestÝ) to request a reverse transfer. The status of this signal line is reported in the PSTAT Register. INITÝ O REVERSE REQUEST (ReverseRequest Ý): The host controls this signal via the PCON Register to indicate the transfer direction. The host asserts this signal to request a reverse transfer direction and negates the signal for a forward transfer direction. AUTOFDÝ O HOST ACKNOWLEDGE (HostAck): The 82091AA asserts AUTOFD Ý (HostAck) to request data from the peripheral (reverse direction). This signal handshakes with ACK Ý (PeriphClk). AUTOFD Ý (HostAck) is negated when the peripheral indicates valid state of the data bus (i.e., ACK Ý is detected asserted). In the forward direction, AUTOFD Ý (HostAck) indicates whether PD [7:0] contain an address/RLE or data. The 82091AA asserts this signal to identify an address/ RLE transfer and negates it to identify a data transfer. PD[7:0] I/O DATA: PD[7:0] is a bi-directional data bus that transfers data, addresses, or RLE data. SELECTINÝ O ECP MODE (ECPmode): The host (via the PCON Register) negates this signal during ECP mode operation.

2.7 Hard Reset Signal Conditions

Table 1 shows the state of all 82091AA output and bi-directional signals during hard reset (RSTDRV asserted). Table 2. Output and I/O Signal States During a Hard Reset

During and immediately after a hard reset, this signal is an input for hardware configuration. After the hardware configura-

tion time, these signals go to the state specified in the table.

If IORC Ý or IOWC Ý is asserted, IOCHRDY will be asserted by the IOCHRDY.
Dashes represent input signals.

2.8 Power And Ground

Signal Type DescriptionName VSS I GROUND: The ground reference for the 82091AA. VCC I POWER: The 5V/3.3V (1) modes are selected via strapping options at power-up (see Section 4.2, hardware Configuration). When strapping options (V SEL) are set to 5V, the VCC pins must be connected to 5V. When strapping options are set to 3.3V, the V CC pins must be connected to 3.3V. VCCF I POWER: The 5V/3.3V (1) power supply for the 82091AA. In 5V or 3.3V power supply modes (non-mixed mode), the voltage applied to V CCF is the same voltage as applied to V CC. For mixed mode operations, 5V is applied to V CCF. This voltage provides 5V reference for the parallel port and floppy disk controller interfaces. Note that in mixed mode, 3.3V is applied to V CC. NOTE: 1. 3.3V operation is available only in the 82091AA.

3.0 I/O ADDRESS ASSIGNMENTS

The 82091AA assigns CPU I/O address locations to its game port chip select, IDE interface, serial ports, parallel port, floppy disk controller, and the 82091AA configuration registers as indicated in Table 3. Ex- cept for the game port chip select (address 201h), address assignments are configurable. For example, the serial port can be assigned to one of eight ad- dress blocks. The parallel port can be assigned to one of three address blocks, and the IDE interface and floppy disk controller can be assigned to one of two address blocks. These address assign- ments are made during 82091AA configuration (ei- ther hardware configuration at powerup or a hard reset, or software configuration by programming the 82091AA configuration registers). In addition, the 82091AA configuration registers can be located at one of two address blocks during hardware configu- ration. All of the 82091AA address locations are located in the host I/O address space. The address block as- signments are shown in Table 3. The first hex ad- dress in the Address Block column represents the base address for that particular block.

Table 3. AIP Address Assignments

The 82091AA does not contain IDE registers. However, the 82091AA provides the address block assignments for access-

ing the IDE registers that are located in the IDE device.

The standard PC/AT * compatible logical I/O address assignments are supported. For example, COM1 (3F8–3FFh) and

(278–27Fh) are part of the parallel port assignments. *Other brands and names are the property of their respective owners.

4.0 AIP CONFIGURATION

82091AA configuration consists of setting up overall device operations along with certain functions pertaining to the individual 82091AA modules (parallel port, serial ports, floppy disk controller, and IDE interface). Overall device operations include selecting the clock frequency, power supply voltage, and address assignment for the configuration registers. Overall device operations also enable/ disable access to the configuration registers and provide interrupt signal level control. For the individual modules, 82091AA configuration includes module address assignment, interrupt control, module enable/disable, powerdown control, test mode control, module reset, and certain functions specific to each module. The remainder of the functions unique to each module are handled via the individual module registers. Two methods are provided for configuring the 82091AAÐhardware configuration via strapping op- tions at powerup (or whenever RSTDRV is asserted) and software configuration by programming the con- figuration registers. (For information on hardware configuration, see Section 4.2, Hardware Configura- tion. For information on software configuration, see Section 4.1, Configuration Registers.) NOTE: 1. There are four hardware configuration modesÐSWMB (Software Motherboard), SWAI (Software Add-In), HWB (Hardware Basic), and HWE (Hardware Extended). Some of these modes can be used without the need for programming the 82091AA configuration registers. Other modes use both hardware configuration strapping op- tions and programming the configuration registers to set up the 82091AA. 2. The 82091AA’s operating power supply voltage level, 82091AA clock frequency, and address assignment for the 82091AA configuration registers can only be config- ured by hardware configuration.

4.1 Configuration Registers

82091AA Configuration Space contains 13 configu- ration registers. Four of the registers (Product and Revision Identification Registers and the 82091AA Configuration 1 and 2 Registers) provide control and status information for the entire chip. In addition, two registers each for the floppy disk controller, parallel port, serial port A, and serial port B and one register for the IDE interface provide certain module status and control information. The 82091AA configuration registers are indirectly addressed by first writing to the 82091AA Configuration Index Register as de- scribed in Section 4.1.1. Thus, the 13 configuration registers occupy two address locations in the host’s I/O address spaceÐone for indirectly selecting the specific configuration register and the other for transfering register data. All 82091AA configuration registers are 8-bits wide and are accessed as byte quantities. Some of the 82091AA Configuration registers de- scribed in this section contain reserved bits. These bits are labeled ‘‘R’’. Software must deal correctly with fields that are reserved. On reads, software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particu- lar value. On writes, software must ensure that the values of reserved bit positions are preserved. That is, the value of reserved bit positions must first be read, merged with the new values for other bit posi- tions, and then written back. In addition to reserved bits within a register, the 82091AA configuration space contains address lo- cations that are labeled ‘‘Reserved’’ (Table 5). While the 82091AA responds to accesses to these I/O ad- dresses by completing the host cycle, writing to a reserved I/O address can result in unintended de- vice operations. Values read from a reserved I/O address should not be used to permit future expan- sion and upgrades. During a hard reset (RSTDRV asserted), the 82091AA sets its configuration registers to pre-de- termined default states. The default values are indi- cated in the individual register descriptions. The fol- lowing nomenclature is used for register access at- tributes: RO Read Only. If a register is read only, writes have no effect. R/W Read/Write. A register with this attribute can be read and written. Note that individual bits in some read/write registers may be read only.

4.1.1 CFGINDX, CFGTRGTÐCONFIGURATION INDEX REGISTER AND TARGET PORT

Table 4. Configuration Register Access Addresses register. The register descriptions are arranged in the order that they appear in Table 5. 7:0 82091AA Configuration Register Address Index: Bits[7:0] correspond to SD [7:0].

Table 5. AIP Configuration Registers Writing to a reserved I/O address should not be attempted and can result in unintended device operations.

4.1.2 AIPIDÐAIP IDENTIFICATION REGISTER

combined with the 82091AA Revision Identification Register uniquely identifies the device.

4.1.3 AIPREVÐAIP REVISION IDENTIFICATION

incremented for every stepping, even if change is invisible to software. Figure 6. AIP Revision Identification Register 7:4 STEP NUMBER: Contains the hexadecimal representation of the device stepping.

4.1.4 AIPCFG1ÐAIP CONFIGURATION 1 REGISTER

address assignment for the configuration registers (address locations of the INDEX and TARGET Registers). *3.3V operation is available only in the 82091AA. XeValue is determined by hardware strapping options as described in Section 4.2, Hardware Configuration. Figure 7. AIP Configuration 1 Register

7 NOT USED: Always write to 0. 6 VOLTAGE SELECT (VSEL): This bit indicates whether 3.3V or 5V has been selected for the operating power supply voltage during hardware configuration . A 1 indicates that 3.3V is selected and a 0 indicates that 5V is selected. This bit is read only and writes have no effect. NOTE: 3.3V operation is available only in the 82091AA. 5:4 CONFIGURATION MODE SELECT (CFGMOD): These bits indicate the configuration mode for the 82091AA. After a hard reset, these bits reflect the mode selected by hardware configuration. If configuration register access is not locked out during hardware configuration, software can change the configuration mode by writing to this field. For configuration mode details, (see Section 4.2, Hardware Configuration). Bits[5:4] Configuration Mode 0 0 Software Motherboard (SWMB) 0 1 Software Add-in (SWAI) 1 0 Extended Hardware (HWE) 1 1 Basic Hardware (HWB)

3 CONFIGURATION ADDRESS SELECT (CFGADS): This read only bit indicates the address

assignment for the 82091AA configuration registers as selected by hardware configuration. Hardware configuration selects between primary addresses (22h/23h and 26Eh/26Fh) and secondary addresses (24h/25h and 398h/399h) for accessing the 82091AA configuration registers. When CFGADS e0, the primary addresses are selected and when CFGADS e1, the secondary addresses are selected.

2 RESERVED

1 RESERVED

0 CLOCK OFF (CLKOFF): The CLKOFF bit is used to implement clock circuitry power management. When CLKOFF e0, the main clock circuitry is powered on. When CLKOFF e1, the main clock circuitry is powered off. This capability is independent of the 82091AA’s powerdown state. Note that auto powerdown mode and powerdown have no effect over the power state of the clock circuitry.

4.1.5 AIPCFG2ÐAIP CONFIGURATION 2 REGISTER

Index Address: 03h Default Value: 0000 0RRR Attribute: Read/Write Size: 8 bits This register selects the active signal level for IRQ [7:3]. The interrupt signals can be individually programmed for either active high or active low drive characteristics. The active high mode is ISA (non-share) compatible and has tri-state drive characteristic. The active low mode is EISA (sharable) compatible and has an open collector drive characteristic.

Figure 8. AIP Configuration 2 Register 7 IRQ7 MODE SELECT (IRQ7MOD): When IRQ7MOD e0, IRQ7 is an active high tri-state drive signal. When IRQ7MOD e1, IRQ7 is an active low open collector drive signal. 6 IRQ6 MODE SELECT (IRQ6MOD): When IRQ6MOD e0, IRQ6 is an active high tri-state drive signal. When IRQ6MOD e1, IRQ6 is an active low open collector drive signal. 5 IRQ5 MODE SELECT (IRQ5MOD): When IRQ5MOD e0, IRQ5 is an active high tri-state drive signal. When IRQ5MOD e1, IRQ5 is an active low open collector drive signal. 4 IRQ4 MODE SELECT (IRQ4MOD): When IRQ4MOD e0, IRQ4 is an active high tri-state drive signal. When IRQ4MOD e1, IRQ4 is an active low open collector drive signal. 3 IRQ3 MODE SELECT (IRQ3MOD): When IRQ3MOD e0, IRQ3 is an active high tri-state drive signal. When IRQ3MOD e1, IRQ3 is an active low open collector drive signal.

4.1.6 FCFG1ÐFDC CONFIGURATION REGISTER

the FDC, and enables/disables the FDC. All bits in this register are read/write. hardware strapping options as described in Section 4.2, Hardware Configuration. determined by hardware strapping options as described in Section 4.2, Hardware Configuration. Figure 9. FDC Configuration Register

7 FLOPPY DISK DRIVE QUANTITY (FDDQTY): This bit selects between two and four floppy disk

external decoder. When FDDQTY e1, the PDEN feature in the powerdown command is disabled.

1 FLOPPY DISK CONTROLLER ADDRESS SELECT (FADS): When FADS e0, the primary FDC

and HWE hardware configuration modes, the default is determined by signal pin strapping options.

4.1.7 FCFG2ÐFDC POWER MANAGEMENT AND STATUS REGISTER

3 FLOPPY DISK AUTO POWERDOWN ENABLE (FAPDN): This bit is used to enable/disable auto

conditions are met. When FAPDN e0, FDC auto powerdown is disabled. FRESETe1, the FDC is reset (i.e., all programming and current state information is lost). e1) of 1.13 ms minimum is met.

1 FLOPPY DISK CONTROLLER IDLE STATUS (FIDLE): When the FDC is in the idle state, this bit is

set to 0. This bit is read only.

0 FLOPPY DISK CONTROLLER POWERDOWN (FDPDN): When FDPDN is set to 1, the FDC is

DOR or bit 7 of the FDC’s DSR). A hard reset via the RSTDRV pin also removes the FDC powerdown.

4.1.8 PCFG1ÐPARALLEL PORT CONFIGURATION REGISTER

parallel port interrupt. This register also selects the hardware operation mode for the parallel port. hardware configuration options as described in Section 4.2, Hardware Configuration. hardware configuration options as described in Section 4.2, Hardware Configuration. Figure 11. Parallel Port Configuration Register

7 PARALLEL PORT FIFO THRESHOLD SELECT (PTHRSEL): This bit controls the FIFO threshold

and only affects parallel port operations when the parallel port is in ECP mode or ISA-Compatible FIFO mode. When PTHRSEL e1, the FIFO threshhold is 1 in the forward direction and 15 in the reverse direction. When PTHRSEL e0, the FIFO threshold is 8 in both directions. This bit can only be programmed when the parallel port is in ISA-Compatible or PS/2-Compatible mode. These modes can be selected via bits [6:5] of this register or the ECP Extended Control Register (ECR). NOTE: In the reverse direction, a threshold of 15/8 means that a request (DMA or Interrupt is enabled) is generated when 15/8 bytes are in the FIFO. In the forward direction, a threshold of 1/8 means that a request is generated when 1/8 byte locations are available. 6:5 PARALLEL PORT HARDWARE MODE SELECT (PPHMOD): This field selects the parallel port hardware mode. The ISA-Compatible mode is for compatibility and nibble mode peripheral interface protocols. The PS/2-Compatible mode is for the byte mode peripheral interface protocol. The EPP and ECP modes are for the EPP and ECP mode peripheral interface protocols, respectively. This field can be configured by strapping options at powerup for hardware extended configuration (HWE) mode only. For all other hardware configuration modes (SWMB, SWAI, and HWB), the default is 00 (ISA-Compatible). Bits [6:5] Read Write 0 0 ISA-Compatible ISA-Compatible (1) 0 1 PS/2-Compatible PS/2-Compatible (1) 1 0 EPP EPP (1, 3) 1 1 ECP (2) Reserved; do not write (2) NOTES: 1. ISA-Compatible, PS/2-Compatible, and EPP modes are selected via this field or hardware configuration. In addition, ISA-Compatible and PS/2-Compatible modes can be selected via the ECP Extended Control Register (ECR). When the ECR is programmed for one of these two modes (ECR [7:5] e000, 001), this field is updated to match the selected mode. 2. ECP Mode can not be entered by programming this field. ECP Mode can only be selected through the ECR. When the ECR is programmed for ECP mode, the 82091AA sets this field to 11. 3. Parallel port interface signals controlled by the PCON Register (SELECTIN Ý, INIT Ý, AUTOFD Ý, and STROBE Ý) should be negated before entering EPP mode.

4 RESERVED

3 PARALLEL PORT IRQ SELECT (PIRQSEL): When PIRQSEL e1, IRQ7 is selected as the parallel

port interrupt. When PIRQSEL e0, IRQ5 is selected as the parallel port interrupt. This field can be configured by strapping options at powerup for HWB and HWE modes only. For all other hardware configuration modes (SWMB and SWAI), the default is 0 (IRQ5).

2:1 PARALLEL PORT ADDRESS SELECT (PADS): This field selects the address for the parallel port as follows: Bits[2:1] Address Parallel Port Hardware Mode 0 0 378–37F All 0 1 278–27F All 1 0 3BC–3BE All except EPP 1 1 Reserved None, do not write This field can be configured by strapping options at powerup for HWB and HWE modes only. For all other hardware configuration modes (SWMB and SWAI), the default is 00 (378h–37Fh). Note that the SWMB and SWAI default settings for PIRQSEL (bit 3) and PADS (bits [2,1]) do not match a standard PC/AT * combination for address assignment and interrupt setting. However, for SWMB and SWAI, the parallel port defaults to a disabled condition and this register must be programmed to enable the parallel port (i.e., bit 0 set to 1). At this time, the selections for interrupt and address assignments should be made. 0 PARALLEL PORT ENABLE (PEN): When PEN e0, the parallel port is disabled. When PEN e1, the parallel port is enabled. This bit can be configured by hardware strapping options at powerup for HWB and HWE modes only. For all other hardware configuration modes (SWMB and SWAI), the default is 0 (disabled). Note that when the parallel port is disabled, IRQ [7,5] and PPDREQ are tri- stated.

4.1.9 PCFG2ÐPARALLEL PORT POWER MANAGEMENT AND STATUS REGISTER

Index Address: 21h Default Value: RR0R 0000 Attribute: Read/Write Size: 8 bits This register enables/disables parallel port auto powerdown and can place the parallel port into a powerdown mode directly. The register also provides parallel port idle status, resets the parallel port, and reports FIFO underrun or overrun errors. *Other brands and names are the property of their respective owners.

Figure 12. Parallel Port Power Management and Status Register

5 PARALLEL PORT FIFO ERROR STATUS (PFERR): When PFERR e1, a FIFO underrun or overrun

condition has occurred. This bit is read only. Setting PRESET to 1 clears this bit to 0.

3 PARALLEL PORT AUTO POWERDOWN ENABLE (PAPDN): When PAPDN e1, the parallel port

and no activity on the parallel port interface. This bit is read only.

0 PARALLEL PORT DIRECT POWERDOWN (PDPDN): When PDPDN is set to 1, the parallel port

4.1.10 SACFG1ÐSERIAL PORT A CONFIGURATION REGISTER

Through programming of this register and the SBCFG1 Register, the 82091AA permits serial ports A

responding to interrupts correctly.

It is possible to enable and assign both serial ports to the same address through software. In this

mined by hardware strapping options as described in Section 4.2, Hardware Configuration. Figure 13. Serial Port A Configuration Register

7 MIDI CLOCK FOR SERIAL PORT A ENABLE (SAMIDI): When SAMIDI e1, the clock into Serial

Port A is changed from 1.8462 MHz–2 MHz. The 2 MHz clock is needed to generate the MIDI baud rate. When SAMIDI e0, the clock frequency is 1.8462 MHz. 6:5 RESERVED

4 SERIAL PORT A IRQ SELECT (SAIRQSEL): When SAIRQSEL e0, IRQ3 is selected for the Serial

Port A interrupt. When SAIRQSEL e1, IRQ4 is selected for the Serial Port A interrupt. This bit can be configured by strapping options at powerup for HWB and HWE modes only. For SWMB and SWAI hardware configuration modes, the default is 0 (IRQ3). Note that, while the default address and IRQ assignments for SWMB and SWAI modes are the same for both serial ports, the serial ports are disabled and programming of this register is required for operation. 3:1 SERIAL PORT A ADDRESS SELECT (SAADS): This field selects the ISA address range for Serial Port A as follows: Bits[3:1] ISA Address Range 0 0 0 3F8–3FFh 0 0 1 2F8–2FFh 0 1 0 220–227h 0 1 1 228–22Fh 1 0 0 238–23Fh 1 0 1 2E8–2EFh 1 1 0 338–33Fh 1 1 1 3E8–3EFh This field can be configured by strapping options at powerup for HWB and HWE modes only. For SWMB and SWAI hardware configuration modes, the default is 000 (3F8–3FFh). Note that, while the default address and IRQ assignments for SWMB and SWAI modes are the same for both serial ports, the serial ports are disabled and programming of this register is required for operation. 0 SERIAL PORT A ENABLE (SAEN): When SAEN e1, Serial Port A is enabled. When SAEN e0, Serial Port A is disabled. This bit can be configured by strapping options at powerup for HWB and HWE modes only. For SWMB and SWAI hardware configuration modes, the default is 0 (disabled).

4.1.11 SACFG2ÐSERIAL PORT A POWER MANAGEMENT AND STATUS REGISTER

Index Address: 31h Default Value: RRR0 00U0 Attribute: Read/Write Size: 8 bits This register enables/disables the Serial Port A module auto powerdown and can place the module into a direct powerdown mode. The register also provides Serial Port A idle status, resets the Serial Port A module, and places Serial Port A into test mode.

Figure 14. Serial Port A Power Management and Status Register

4 SERIAL PORT A TEST MODE (SATEST): The serial port test mode provides user access to the

e0, the Serial Port A test mode is disabled.

Figure 15. Test Mode Output (SOUTA and SOUTB)

3 SERIAL PORT A AUTO POWERDOWN ENABLE (SAAPDN): This bit enables/disables auto

e0, auto powerdown is disabled.

1 SERIAL PORT A IDLE STATUS (SAIDLE): When Serial Port A is in an idle state the 82091AA sets

and transmit FIFOs are empty. This bit is read only.

0 SERIAL PORT A DIRECT POWERDOWN (SADPDN): When SADPDN e1, Serial Port A is placed in

direct powerdown mode. Setting this bit to 0 brings Serial Port A out of direct powerdown mode. loss, the SAIDLE bit should be 1 before placing the serial port into direct powerdown.

4.1.12 SBCFG1ÐSERIAL PORT B CONFIGURATION REGISTER

Through programming of this register and the SBCFG1 Register, the 82091AA permits serial ports A

responding to interrupts correctly.

It is possible to enable and assign both serial ports to the same address through software. In this

determined by hardware strapping options as described in Section 4.2, Hardware Configuration. Figure 16. Serial Port B Configuration Register

7 MIDI CLOCK FOR SERIAL PORT B ENABLE (SBMIDI): When SBMIDI e1, the clock into Serial

Port B is changed from 1.8462 MHz to 2 MHz. The 2 MHz clock is needed to generate the MIDI baud rate. When SBMIDI e0, the clock frequency is 1.8462 MHz. The default value is 0. 6:4 RESERVED

4 SERIAL PORT B IRQ SELECT (SBIRQSEL): When SBIRQSEL e0, IRQ3 is selected for the Serial

Port B interrupt. When SBIRQSEL e1, IRQ4 is selected for the Serial Port B interrupt. The default value is 0. This bit can be configured by strapping options at powerup for HWB and HWE modes only. For SWMB and SWAI configuration modes, the default is 0 (IRQ3). Note that, while the default address and IRQ assignments for SWMB and SWAI modes are the same for both serial ports, the serial ports are disabled and programming of this register is required for operation. 3:1 SERIAL PORT B ADDRESS SELECT (SBADS): This field selects the ISA address range for Serial Port B as follows: Bits[3:1] ISA Address Range 0 0 0 3F8–3FFh 0 0 1 2F8–2FFh 0 1 0 220–227h 0 1 1 228–22Fh 1 0 0 238–23Fh 1 0 1 2E8–2EFh 1 1 0 338–33Fh 1 1 1 3E8–3EFh This field can be configured by strapping options at powerup for HWB and HWE modes only. For SWMB and SWAI configuration modes, the default is 000 (3F8–3FFh). Note that, while the default address and IRQ assignments for SWMB and SWAI modes are the same for both serial ports, the serial ports are disabled and programming of this register is required for operation. 0 SERIAL PORT B ENABLE (SBEN): When SBEN e1, Serial Port B is enabled. When SAEN e0, Serial Port B is disabled. This bit can be configured by strapping options at powerup for HWB and HWE modes only. For SWMB and SWAI configuration modes, the default is 0 (disabled).

4.1.13 SBCFG2ÐSERIAL PORT B POWER MANAGEMENT AND STATUS REGISTER

and enables/disables Serial Port B test mode. Figure 17. Serial Port B Power Management and Status Register

7:5 RESERVED

4 SERIAL PORT B TEST MODE (SBTEST): The serial port test mode provides user access to the

output of the baud out generator. When SBTEST e1 (and the DLAB bit is 1 in the LCR), the Serial Port B test mode is enabled and the baud rate clock is output on the SOUTB pin (Figure 15). When SBTEST e0, the Serial Port B test mode is disabled.

3 SERIAL PORT B AUTO POWERDOWN ENABLE (SBAPDN): This bit enables/disables auto

powerdown. When SBAPDN e1, Serial Port B can enter auto powerdown if the required conditions are met. The required conditions are that the transmit and receive FIFOs are empty and the timeout counter has expired. When SBAPDN e0, auto powerdown is disabled. 2 SERIAL PORT B RESET (SBRESET): When SBRESET e1, Serial Port B is reset (i.e., all programming and current state information is lost). This is the same state the module would be in after a hard reset (RSTDRV asserted). When resetting the serial port via this configuration bit, the software must toggle this bit and ensure the reset active time (SBRESET e1) of 1.13 ms minimum is met.

1 SERIAL PORT B IDLE STATUS (SBIDLE): When Serial Port B is in an idle state the 82091AA sets

this bit to 1. Serial Port B is in the idle state when the transmit and receive FIFOs are empty and the timeout counter has expired. Note that these are the same conditions that apply to entering auto powerdown. When serial port B is not in an idle state, the 82091AA sets this bit to 0. Direct powerdown does not affect this bit and in auto powerdown, this bit is only set t oa1i ft h e receive and transmit FIFOs are empty. This bit is read only. During a hard reset (RSTDRV asserted), the 82091AA sets this bit to 0. However, because the serial port is typically initialized by software before the idle conditions are met, the defaullt state is shown as undefined.

0 SERIAL PORT B DIRECT POWERDOWN (SBDPDN): When SBDPDN e1, Serial Port B is placed in

powerdown mode. Setting this bit to 0 brings the module out of direct powerdown mode. Setting bit 2 (SBRESET) of this register to 1 will also bring Serial Port B out of the direct powerdown mode. NOTE: Direct powerdown resets the receiver and transmitter portions of the serial port including the receive and transmit FIFOs. To ensure that the resetting of the FIFOs does not cause data loss, the SBIDLE bit should be 1 before placing the serial port into direct powerdown.

4.1.13.1 Serial Port A/B Configuration

Register’s SxEN and SxDPDN Bits The bits which enable the serial ports (bit 0 in both the SACFG1 and SBCFG1 registers) and the bits which provide for serial port direct powerdown (bit 0 in both the SACFG2 and SBCFG2 registers) are not mutually exclusive. The partial circuit and truth table for the two bits shows that it is possible to enable serial port A using SACFG1, for example, yet still read the serial port A SACFG2 direct powerdown bit as a ‘‘1’’. When the SxCFG1 register bit 0 (serial port x en- able) is written as a ‘‘1’’ (enable), the SxCFG2 regis- ter bit 0 (serial port x powerdown) does not change from a ‘‘1’’ (powerdown enable) to a ‘‘0’’ (power- down disable). As can be seen in the circuit diagram, the READ activity does not see the register directly. Instead, a MUXed output is seen by the READ activi- ty. The truth table for the two bits shows it is possi- ble to enable a serial port yet still read the power- down bit for that same port as a ‘‘1’’, or enabled. Truth Table for Reading the Enable/Powerdown Bit Status Write Activity Read Activity SxCFG1 SxCFG2 SxCFG1 SxCFG2 Enable Powerdown Enable Powerdown 0001 1010 1111 0101

4.1.14 IDECFGÐIDE CONFIGURATION REGISTER

the address for accessing the IDE. default is determined by hardware strapping options as described in Section 4.2, Hardware Configuration. ** Not hardware configurable. Figure 18. IDE Configuration Register

7:3 RESERVED

2 IDE DUAL SELECT (IDUAL): When IDUAL e0, the IDE address selection is determined by the

IADS bit. When IDUAL e1, both the primary and secondary IDE addresses are selected and the setting of the IADS bit does not affect IDE address selection.

1 IDE ADDRESS SELECT (IADS): When IADS e0, the primary IDE address is selected (1F0h–1F7h,

3F6h, 3F7h ). When IADS e1, the secondary IDE address is selected (1F0h–1F7h, 376h, 377h). For all hardware configuration modes (SWMB, SWAI, HWB, and HWE), the default is determined by signal pin strapping options. 0 IDE INTERFACE ENABLE (IEN): When IEN e0, the IDE interface is disabled (i.e., the IDE chip selects (IDECS [1:0]), DEN Ý, and HEN Ý are negated (remain inactive) for accesses to the IDE primary and secondary addresses). When IEN e1, the IDE interface is enabled. For all hardware configuration modes (SWMB, SWAI, HWB, and HWE), the default is determined by signal pin strapping options.

4.2 Hardware Configuration

Hardware configuration provides a mechanism for configuring certain 82091AA operations at powerup. Four hardware configuration modes provide different levels of configuration depending on the type of ap- plication and the degree of hardware/software con- figuration desired. The hardware configuration modes are: # Software Motherboard (SWMB) # Software Add-In (SWAI) # Hardware Extended (HWE) # Hardware Basic (HWB) These modes support a variety of system implemen- tations. For example, with Hardware Basic (HWB) and Hardware Extended (HWE) modes, an exten- sive set of 82091AA configuration options are avail- able for setting up the 82091AA at powerup. This permits the 82091AA to be used in systems without 82091AA software drivers. For many of these sys- tems, access to the 82091AA configuration registers may not be necessary. As such, access to these registers can be disabled via hardware configura- tion. This option could be used to prevent software from inadvertently re-configuring the 82091AA.

figuration changes as desired.

4.2.1 SELECTING THE HARDWARE

CFGMOD[1,0] Hardware Configuration Mode. tion modes as shown in Table 6. Basic mode is not selectable. Table 6. AIP Configuration Mode Register Address Assignment

4.2.2 SELECTING HARDWARE

modes, these signal pins have no effect. Table 7. FDC and IDE Enable/Disable signment for the 82091AA configuration registers. Table 8. Hardware Configuration Mode Option Matrix

HWEa and HWEb reference the switching banks shown in Figure 22.
The following mnemonics are used in the table: SPCFGx

ply voltage select, CFGADS e82091AA configuration register address assignment select.

Always tie this signal low with a 10K resistor.

Table 9. Serial Port Address and Interrupt Assignments

In this configuration, the two serial ports share the same interrupt line. Responding correctly to interrupts generated in this

configuration is the exclusive responsibility of software. Table 10. Parallel Port Address and Interrupt Assignments

Table 11. Parallel Port Hardware Mode Select

PPMODx hardware configuration is effective in HWE
ECP mode is not selectable via hardware configuration.
For EPP mode, address assignment must be either 278h

Table 12. AIP Clock Select Table 13. AIP Power Supply Voltage

VSEL hardware configuration is not available in HWB
To operate the 82091AA and all of the interfaces at 5V
3.3V operation is available only in the 82091AA.

Table 14. Floppy Drive Quantity Select

FDDQTY hardware configuration is effective in HWE
Four floppy drive support requires external logic to de-

4.2.3 HARDWARE CONFIGURATION TIMING

4.2.4 HARDWARE BASIC CONFIGURATION

changed to SWAI mode (refer to AIPCFG1 register). Figure 21. Hardware Basic Configuration

4.2.5 HARDWARE EXTENDED

the pins on the serial ports at two different times. signals are driven by HWEb pullup/down resistors. Figure 22. Hardware Extended Configuration

4.2.6 SOFTWARE ADD-IN CONFIGURATION

Figure 23. Software Add-In Configuration

4.2.7 SOFTWARE MOTHERBOARD

mits the 82091AA to be located on the motherboard. can be selected to be at either 22h/23h or 24h/25h. Figure 24. Software Motherboard Hardware Configuration

5.0 HOST INTERFACE

cessed by programmed I/O and/or DMA bus cycles. on the 82091AA require only 8-bit data accesses. strobes that attempt to shorten the bus cycle. can be completed in a total of 3 BCLK cycles. out any particular reference to ISA cycle timings. ble to accomplish a DMA transfer in 2 BCLKs. Figure 25. ISA Interface (with Optional Data Buffer)

6.0 PARALLEL PORT

The 82091AA parallel port can be configured for four parallel port modes. These parallel port modes and the associated parallel interface protocols are: Parallel Port Mode Parallel Interface Protocol ISA-Compatible Mode Compatibility, Nibble PS/2-Compatible Mode Byte EPP Mode EPP ECP ECP ISA-Compatible, PS/2-Compatible, and EPP modes are selected through 82091AA configuration (see Section 4.0, AIP Configuration). ECP is selected by programming the ECP Extended Control Register (ECR). In ISA-Compatible mode, the parallel port exactly emulates a standard ISA-style parallel port. The par- allel port data bus (PD [7:0]) is uni-directional. The compatibility protocol transfers data to the peripher- al device via PD [7:0] (forward direction). Note that the Nibble protocol permits data transfers from the peripheral device (reverse direction) by using four peripheral status signal lines to transfer 4 bits of data at a time. PS/2-Compatible mode differs from ISA-Compatible mode by providing bi-directional transfers on PD[7:0]. A bit is added to the PCON Register to al- low software control of the data transfer direction. For both the ISA-Compatible and PS/2-Compatible modes, the actual data transfer over the parallel port interface is accomplished by software handshake (i.e., automatic hardware handshake is not used). Software controls data transfer by monitoring hand- shake signal status from the peripheral device via the PSTAT Register and controlling handshake sig- nals to the peripheral device via the PCON Register. EPP mode provides bi-directional transfers on PD[7:0]. The 82091AA automatically generates the address and data strobes in hardware. ECP is a high performance peripheral interface mode. This mode uses an asynchronous automatic handshake to transfer data over the parallel port in- terface. In addition, the parallel port contains a FIFO for transferring data in ECP mode. The ECP register set contains an Extended Control Register (ECR) that provides a wide range of functions including the ability to operate the parallel port in either ECP, ISA- Compatible, or PS/2-Compatible modes. NOTE: In general, this document describes parallel port operations and functions in terms of how the 82091AA parallel port hardware op- erates. Detailed descriptions of the parallel interface protocols are beyond the scope of this document. Readers should refer to the proposed IEEE Standard 1284 for detailed descriptions of the Compatibility, Nibble, Byte, EPP, and ECP protocols. Special circuitry on the 82091 prevents it from being powered up or being damaged while a parallel port peripheral is powered on and the 82091 is powered off.

6.1 Parallel Port Registers

This section is organized into three sub-sectionsÐ ISA-Compatible and PS/2-Compatible Modes, EPP Mode, and ECP Mode. Since the register sets are similar for ISA-Compatible and PS/2-Compatible modes (differing by a direction control bit in the PCON Register) the register set descriptions are combined. The EPP mode and ECP mode register sets are described separately. Each register set de- scription contains the I/O address assignment and a complete description of the registers and register bits. Note that the PSTAT and PCON Registers are common to all modes and for completeness are re- peated in each sub-section. Any difference in bit op- erations for a particular mode is noted in that partic- ular register description. The registers provide parallel port control/status in- formation and data paths for transferring data be- tween the parallel port interface and the 8-bit host interface. All registers are accessed as byte quanti- ties. The base address is determined by hardware configuration at powerup (or a hard reset) or via soft- ware configuration by programming the 82091AA configuration registers as described in Section 4.0, AIP Configuration. The parallel port can be disabled or configured for a base address of 378h (all modes), 278h (all modes), or 3BCh (all modes ex- cept EPP and ECP). This provides the system de- signer with the option of using additional parallel ports on add-in cards that have fixed address de- coding.

individual register descriptions. no affect on parallel port operations. some read/write registers may be read only.

6.1.1 ISA-COMPATIBLE AND PS/2-

in the order that they appear in the table. Table 15. Parallel Port Register (ISA-Compatible and PS/2-Compatible) Parallel port base addresses are 278h, 378h and 3BCh.

6.1.1.1 PDATAÐParallel Port Data Register (ISA-Compatible and PS/2-Compatible Modes)

I/O Address: Base a00h Default Value: 00h Attribute: Read/Write Size: 8 bits ISA-Compatible Mode The PDATA Register is a uni-directional data port that transfers 8-bit data from the host to the peripheral device (forward transfer). A write to this register drives the written data onto PD [7:0]. Reads of this register should not be performed in ISA-Compatible mode. For a host read of this address location, the 82091AA completes the handshake on the ISA Bus and the value is the last value stored in the PDATA Register. PS/2-Compatible Mode The PDATA Register is a bi-directional data port that transfers 8-bit data between the peripheral device and host. The direction of transfer is determined by the DIR Ý bit in the PCON Register. If DIR Ýe0 (forward direction), and the host writes to this register, the data is stored in the PDATA Register and driven onto PD[7:0].I fD I R Ýe1 (reverse direction), a host read of this register returns the data on PD [7:0]. Note that read data is not stored in the PDATA Register. Bit Description 7:0 PARALLEL PORT DATA: Bits[7:0] correspond to parallel port data lines PD [7:0] and ISA Bus data lines SD [7:0].

6.1.1.2 PSTATÐStatus Register (ISA-Compatible and PS/2-Compatible Modes)

I/O Address: Base a01h Default Value: XXXX X1RR Attribute: Read Only Size: 8 bits The PSTAT Register provides the status of certain parallel port signals and whether a CPU interrupt has been generated by the parallel port. This register indicates the current state of the BUSY, ACK Ý, PERROR, SELECT, and FAULT Ý signals.

XeDefault value is determined by signal state at reset. Figure 26. Status Register (ISA-Compatible and PS/2-Compatible Modes)

5 PERROR STATUS (PERRS): This bit indicates the state of the parallel port interface PERROR

signal. This bit indicates when an error has occurred in the peripheral paper path (e.g., out of paper). When PERROR is asserted, PERRS e1, When PERROR is negated, PERRS e0. 4 SELECT STATUS (SELS): This bit indicates the state of the parallel port interface SELECT signal. When the SELECT signal is asserted, SELS e1, When the SELECT signal is negated, SELS e0.

3 FAULTÝ STATUS (FAULTS): This bit indicates the state of the parallel port interface FAULT Ý

signal being driven by the peripheral device. When the FAULT Ý signal is asserted, FAULTS e0. When the FAULT Ý signal is negated, FAULTS e1.

2 PARALLEL PORT INTERRUPT STATUS (PIRQ): This bit indicates a CPU interrupt by the parallel

port. PIRQ indicates that the printer has accepted the previous character and is ready for another. In ISA-Compatible mode, interrupt status is not reported in this register and this bit is always 1. In PS/2-Compatibile mode, if interrupts are enabled via the PCON Register and the ACK Ý signal is asserted (low-to-high transition), PIRQ is set t o a 0 (and an IRQ generated to the CPU). The 82091AA sets PIRQ to 1 when this register is read or by a hard reset. If interrupts are disabled via the PCON Register, this bit is never set to 0. 1:0 RESERVED

6.1.1.3 PCONÐControl Register (ISA-Compatible And PS/2-Compatible Mode)

Ý, AUTOFD Ý, INIT Ý, and SELECTIN Ý signals. For PS/2-Compatible mode, this register also controls the direction of transfer on PD [7:0]. Figure 27. Control Register (ISA-Compatible and PS/2-Compatible Modes)

7:6 RESERVED 5 RESERVED (ISA-COMPATIBLE MODE): Not used and undefined when read. Writes have no affect on parallel port operations. DIRECTION (DIR Ý) (PS/2-COMPATIBLE MODE): This bit is used to control the direction of data transfer on the parallel port data bus (PD [7:0]). When DIR Ýe0, PD [7:0] are outputs. When DIRÝe1, PD [7:0] are inputs.

4 ACKÝ INTERRUPT ENABLE (ACKINTEN): ACKINTEN enables CPU interrupts (via either IRQ5 or

IRQ7) to be generated when the ACK Ý signal on the parallel port interface is asserted. When ACKINTENe1, a CPU interrupt is generated when ACK Ý is asserted. When ACKINTEN e0, the ACKÝ interrupt is disabled. 3 SELECTINÝ CONTROL (SELINC): This bit controls the SELECTIN Ý signal. SELINC is set to 1 to select the printer. When SELINC e1, the SELECTIN Ý signal is asserted, When SELINC e0, the SELECTINÝ signal is negated. 2 INITÝ CONTROL (INITC): This bit controls the INIT Ý signal. When INITC e1, the INIT Ý signal is negated. When INITC e0, the INIT Ý signal is asserted. 1 AUTOFDÝ CONTROL (AUTOFDC): This bit controls the AUTOFD Ý signal. AUTOFDC is set to 1 to instruct the printer to advance the paper one line each time a carriage return is received. When AUTOFDC e1, the AUTOFD Ý signal is asserted. When AUTOFDC e0, the AUTOFD Ý signal is negated. 0 STROBEÝ CONTROL (STROBEC): This bit controls the STROBE Ý signal. The STROBE Ý signal is set active to instruct the printer to accept the character being presented on the data lines. When STROBEC e1, the STROBE Ý signal is asserted. When STROBEC e0, the STROBE Ý signal is negated.

6.1.2 EPP MODE

in Table 16 and the register descriptions are presented in the order that they appear in the table. Table 16. Parallel Port Registers (EPP Mode) Parallel port base addresses are 278h (LPT2) and 378h (LPT1). Base address 3BCh is not available in EPP or ECP modes.

6.1.2.1 PDATAÐParallel Port Data Register (EPP Mode)

data is not stored in the PDATA Register.

6.1.2.2 PSTATÐStatus Register (EPP Mode)

PERROR, SELECT, and FAULT Ý signals. XeDefault value is determined by signal state at reset. Figure 28. Status Register (EPP Mode)

7 BUSY STATUS (BUSYS): This bit indicates the state of the parallel port interface BUSY signal. When BUSY is asserted, BUSYS e0. When BUSY is negated, BUSYS e1. This bit is an inverted version of the parallel port BUSY signal. 6 ACKÝ STATUS (ACKS): This bit indicates the state of the parallel port interface ACK Ý signal. This bit indicates when the peripheral has received a data byte and is ready for another. When ACK Ý is asserted, ACKS e0. When ACK Ý is negated, ACKS e1. Note that if interrupts are enabled (via bit 4 of the PCON Register), the assertion of the ACK Ý signal generates an interrupt to the CPU. signal. This bit indicates when an error has occurred in the peripheral paper path (e.g., out of paper). When PERROR is asserted, PERRS e1. When PERROR is negated, PERRS e0. 4 SELECT STATUS (SELS): This bit indicates the state of the parallel port interface SELECT signal. When the SELECT signal is asserted, SELS e1. When the SELECT signal is negated, SELS e0. signal being driven by the peripheral device. When the FAULT Ý signal is asserted, FAULTS e0. When the FAULT Ý signal is negated, FAULTS e1.

2 PARALLEL PORT INTERRUPT (PIRQ): In EPP mode interrupt status is not reported in this register

and this bit is always 1. 1:0 RESERVED

6.1.2.3 PCONÐControl Register (EPP Mode)

are automatically generated by the parallel port and are not controlled by software. Figure 29. Control Register (EPP Mode)

7:6 RESERVED 5 DIRECTION (DIR Ý): This bit is used to control the direction of data transfer on the parallel port data bus (PD [7:0]). When DIR Ýe0 (forward direction), PD [7:0] are outputs. When DIR Ýe1 (reverse direction), PD [7:0] are inputs.

4 ACKÝ INTERRUPT ENABLE (ACKINTEN): ACKINTEN enables CPU interrupts (via IRQ5 or IRQ7)

to be generated when the ACK Ý signal on the parallel port interface is asserted. When ACKINTENe1, a CPU interrupt is generated when ACK Ý is asserted. When ACKINTEN e0, the ACKÝ interrupt is disabled. 3 SELECTINÝ CONTROL (SELINC): Write to 0 when programming this register. This bit must be 0 for the parallel port handshake to operate properly. 2 INITÝ CONTROL (INITC): This bit controls the INIT Ý signal. When INITC e1, the INIT Ý signal is negated. When INITC e0, the INIT Ý signal is asserted. 1 AUTOFDÝ CONTROL (AUTOFDC): Write to 0 when programming this register. 0 STROBEÝ CONTROL (STROBEC): Write to 0 when programming this register. This bit must be 0 for the parallel port handshake to operate properly.

6.1.2.4 ADDSTRÐEPP Auto Address Strobe Register (EPP Mode)

I/O Address: Base a03h Default Value: 00h Attribute: Read/Write Size: 8 bits The ADDSTR Register provides a peripheral address to the peripheral (via PD [7:0]) during a host address write operation and to the host (via PD [7:0]) during a host address read operation. An automatic address strobe is generated on the parallel port interface when data is read from or written to this register. Bit Description 7:0 EPP ADDRESS: Bits[7:0] correspond to SD [7:0] and PD [7:0].

6.1.2.5 DATASTRÐAuto Data Strobe Register (EPP Mode)

byte address locations are provided for transferring data. 7:0 EPP DATA: Bits[7:0] correspond to SD [7:0] and PD [7:0].

6.1.3 ECP MODE

Table 17. Parallel Port Registers (ECP Mode)

Parallel port base addresses are 278h, 378h, and 3BCh.
A register is accessible when the ECR [7:5] field contains the value specified in the ECR [7:5] column. The register is not

is accessible in all modes selected by ECR [7:5].

6.1.3.1 ECPAFIFOÐECP Address/RLE FIFO Register (ECP Mode)

Figure 30. ECP Address/RLE FIFO Register (ECP Mode)

6.1.3.2 PSTATÐStatus Register (ECP Mode)

SELECT, and FAULT Ý signals. XeDefault value is determined by the state of the corresponding signal pin at reset. Figure 31. Status Register (ECP Mode)

7 BUSY STATUS (BUSYS): This bit indicates the state of the parallel port interface BUSY signal. When BUSY is asserted, BUSYS e0. When BUSY is negated, BUSYS e1. This is an inverted version of the parallel port BUSY signal. Refer to Section 6.2.3 ECP Mode for more detail. 6 ACKÝ STATUS (ACKS): This bit indicates the state of the parallel port interface ACK Ý signal. This bit indicates when the peripheral has received a data byte and is ready for another. When ACK Ý is asserted, ACKS e0. When ACK Ý is negated, ACKS e1. Note that if interrupts are enabled (via bit 4 of the PCON Register), the assertion of the ACK Ý signal generates an interrupt to the CPU. Refer to Section 6.2.3 ECP Mode for more detail. signal. This bit indicates when an error has occurred in the peripheral paper path (e.g., out of paper). When PERROR is asserted, PERRS e1, When PERROR is negated, PERRS e0.

4 SELECT STATUS (SELS): This bit is used in all parallel port modes and indicates the state of the

parallel port interface SELECT signal. When the SELECT signal is asserted, SELS e1. When the SELECT signal is negated, SELS e0.

3 FAULTÝ STATUS (FAULTS): This bit is used in all parallel port modes and indicates the state of

the parallel port interface FAULT Ý signal being driven by the peripheral device. When the FAULT Ý signal is asserted, FAULTS e0. When the FAULT Ý signal is negated, FAULTS e1.

2 PARALLEL PORT INTERRUPT (PIRQ): In ECP mode, interrupt status is not reported in this register

and this bit is always 1. 1:0 RESERVED

6.1.3.3 PCONÐControl Register (ECP Mode)

Figure 32. Control Register (ECP Mode)

4 INTERRUPT ENABLE (ACK Ý) (IRQEN): IRQEN enables interrupts to the CPU to be generated

when the ACK Ý signal on the parallel port interface is asserted and is used in all parallel port interface modes. When IRQEN e1, a CPU interrupt is generated when ACK Ý is asserted. When IRQENe0, parallel port interrupts are disabled. 3 SELECTINÝ CONTROL (SELINC): This bit controls the SELECTIN Ý signal. SELINC is set to 1 to select the printer. When SELINC e1, the SELECTIN Ý signal is asserted, When SELINC e0, the SELECTINÝ signal is negated.

2 INITÝ CONTROL (INITC): This bit controls the INIT Ý signal When INITC e1, the INIT Ý signal is

negated. When INITC e0, the INIT Ý signal is asserted.

1 AUTOFDÝ CONTROL (AUTOFDC): In ECP mode or ISA-Compatible FIFO mode (ECR [7:5] e011,

010), this bit has no effect. Refer to Section 6.2.3 ECP Mode for more details.

0 STROBEÝ CONTROL (STROBEC): In ECP mode or ISA-Compatible FIFO mode (ECR [7:5] e011,

010), this bit has no effect. Refer to Section 6.2.3 ECP Mode for more details.

6.1.3.4 SDFIFOÐStandard Parallel Port Data FIFO

PCON Register must be set to 0 for a forward transfer direction. Figure 33. ECP ISA-Compatible Data FIFO 7:0 ECP STANDARD PARALLEL PORT DATA: Bits[7:0] correspond to SD [7:0] and PD [7:0].

6.1.3.5 DFIFOÐData FIFO (ECP Mode)

hardware handshakes on the parallel port interface using ECP parallel port interface handshake protocol. Figure 34. ECP Data FIFO (ECP Mode) return bytes of ECP data to the system. Bits [7:0] correspond to SD [7:0] and PD [7:0].

6.1.3.6 TFIFOÐECP Test FIFO Register (ECP Mode)

bits in the ECR always keep track of the correct FIFO state. The test FIFO transfers data at the maximum ISA rate so that software can generate performance metrics. Figure 35. ECP Test FIFO Register (ECP Mode) 7:0 ECP TEST FIFO Data: Bits [7:0] correspond to SD [7:0].

6.1.3.7 ECPCFGAÐECP Configuration A Register (ECP Mode)

Figure 36. ECP Configuration A Register (ECP Mode)

6.1.3.8 ECPCFGBÐECP Configuration B Register (ECP Mode)

Figure 37. ECP Extended Control Register (ECP Mode) 7 RESERVED: This bit always reads back as 0.

6 INTRVALUE (INTRV): This bit returns the value on the ISA IRQ line (IRQ5/IRQ7) to determine

e111] to allow the state of the selected parallel port interrupt line to be read back. 5:0 RESERVED: These bits always read back as 0.

6.1.3.9 ECR ECPÐExtended Control Register (ECP Mode)

and FIFO full status bits are also used to report FIFO overrun and underrun conditions. Figure 38. ECP Extended Control Register (ECP Mode)

7:5 ECP MODE SELECT: This field selects one of the following ECP Modes: Mode Operation 0 0 0 ISA-Compatible Mode. In this mode the parallel port operates in ISA-Compatible mode. The FIFO is reset and common collector drivers are used on the control lines (STROBE Ý, AUTOFDÝ, INIT Ý and SELECTIN Ý). Setting the direction bit to 1 in the PCON Register does not affect the parallel port interface. For register descriptions in this mode, See Section 6.1.1, ISA-Compatible and PS/2-Compatible Modes. 0 0 1 PS/2-Compatible Mode. In this mode the parallel port operates in PS/2-Compatible mode. The FIFO is reset and common collector drivers are used on the control lines (STROBE Ý, AUTOFD Ý, INIT Ý and SELECTIN Ý). Unlike mode 000 above, setting the direction bit to 1 in the PCON Register tri-states the data lines and reading the data register returns the value on the PD [7:0]. For register descriptions in this mode, see Section 6.1.1, ISA-Compatible and PS/2-Compatible Modes. 0 1 0 ISA-Compatible FIFO Mode. This mode is the same as mode 000 above, except that data is written or DMAed to the FIFO. FIFO data is automatically transmitted using the ISA- style protocol. For this mode, the direction control bit in the PCON register must be 0. 0 1 1 ECP Mode. In the forward direction, bytes written to the ECP DFIFO location and bytes written to the ECP AFIFO location are placed in the ECP FIFO and transmitted automatically to the peripheral using ECP protocol. In reverse direction bytes are transferred from PD [7:0] to the ECP FIFO. 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Test Mode. In this mode, the FIFO may be written and read, but the data will not be transmitted on PD [7:0]. 1 1 1 Configuration Mode. In this mode, the ECP Configuration A and B Registers are accessible. ECP Mode Switching Guidelines Software will execute P1284 negotiations and all operation prior to a data transfer phase under programmed I/O (using mode 000 or 001). Hardware provides an automatic control line handshake, moving data between the FIFO and the ECP port only in the data transfer phase (using modes 011 or 010). Setting the mode to 011 or 010 causes the hardware to initiate the data transfer. If the parallel port is in mode 000 or 001, the port can be switched to any other mode. If the parallel port is not in mode 000 or 001, the port can only be switched into mode 000 or 001. The direction and the FIFO threshold can only be changed in modes 000 or 001. Note that the FIFO, FIFO Error, and TC conditions are also reset when the mode is switched to 000 or 001. Once in an extended forward mode, the software should wait for the FIFO to be empty before switching back to mode 000 or 001. In this case, all control signals are negated before the mode switch. In an ECP reverse mode the software waits for all the data to be read from the FIFO before changing to mode 000 or 001.

4 ERROR INTERRUPT DISABLE (ERRINTREN): This bit enables error interrupts to the host. In ECP Mode, When ERRINTREN e1, interrupts are disabled. When ERRINTREN e0, interrupts are enabled. When enabled and a high-to-low transition occurs on the FAULT Ý signal (FAULT Ý asserted), an interrupt is generated to the host. Note that if this bit is written fro ma1t oa0 while FAULTÝ is asserted, an interrupt is generated to the host. 3 DMA ENABLE (DMAEN): This bit enables/disables DMA. When DMAEN e1, DMA is enabled and the host uses PPDREQ, PPDACK, and TC to transfer data. When DMAEN e0, DMA is disabled and the PPDREQ output is tri-stated. In this case, programmed I/O is used to transfer data between the host and the 82091AA FIFO. The Service Interrupt (bit 2) needs to be set to 0 to allow generation of a TC interrupt. This bit must be written to 0 to reset the TC interrupt. 2 SERVICE INTERRUPT (SERVICEINTR): This bit enables FIFO and TC service interrupts. When the CPU writes SERVICEINTR e1, FIFO request interrupts, FIFO error interrupts, and TC interrupts are disabled. Setting this bit t o a 0 enables interrupts for one of the four cases listed below. When enabled (set to 0) and one of the four conditions below occurs, the 82091AA sets SERVICEINTR to a 1 and generates an interrupt to the host. 1. During DMA operations (DMAEN e1), when terminal count is reached (TC asserted). To clear the TC interrupt, switch to ISA-Compatible or PS/2-Compatible mode (write ECR [7:5] to 000, 001) or set DMAEN to 0. 2. In the forward direction and DMAEN e0, when there is a threshold number of bytes in the FIFO to be written. 3. In the reverse direction and DMAEN e0, when there is a threshold number of bytes in the FIFO to be read. 4. In either DMA or programmed I/O mode when there is a FIFO overrun or underrun. Reading the SERVICEINTR bit indicates the presence of an active interrupt when this bit has been written t o a 0 prior to reading it back. To disable interrupts, the SERVICEINTR bit must be explicitly written to a 1. NOTE: The ACK Ý and FAULT Ý interrupts can be generated independent of the value of the SERVICEINTR bit. ACK Ý and FAULT Ý interrupts are enabled via the ACKINTREN bit in the PCON Register and the ERRINTREN bit in the ECR Registers, respectively. The parallel port IRQ output (IRQ5/IRQ7) is enabled when ACKINTREN e1 in the PCON Register or when ECR [7:5] e010, 011, or 110. Otherwise, the IRQ output is tri-stated. 1 FIFO FULL STATUS (FIFOFS): This bit indicates when the FIFO is full. When FIFOFS e1 (and FIFOESe0), the FIFO is full and cannot accept another byte of data. When FIFOFS e0, at least one byte location is free in the FIFO. This bit is read only and writes have no affect. When a FIFO overrun or underrun occurs, the 82091AA sets both FIFOES and FIFOFS to 1. To clear the FIFO error condition interrupt, swiitch the parallel port mode from ECP (011) to either ISA-Compatible or PS/2- Compatible modes (000 or 001). 0 FIFO EMPTY STATUS (FIFOES): This bit indicates when the FIFO is empty. When FIFOES e1 (and FIFOFSe0), the FIFO is empty. When FIFOES e0, the FIFO contains at least one byte. This bit is read only and writes have no affect. When a FIFO overrun or underrun occurs, the 82091AA sets both FIFOES and FIFOFS to 1. To clear the FIFO error condition interrupt, swiitch the parallel port mode from ECP (011) to either ISA-Compatible or PS/2-Compatible modes (000 or 001).

6.2 Parallel Port Operations

be changed by programming the PCFG1 Register. gramming the 82091AA configuration registers.

6.2.1 ISA-COMPATIBLE AND PS/2-

parallel port interface for ISA-Compatible mode. Figure 39. ISA-Compatible Mode

may not use the PERROR signal. serts BUSY when it is not ready to receive data. parallel port interface for PS/2-Compatible mode. Figure 40. PS/2-Compatible Mode

6.2.2 EPP MODE

41 shows the parallel port interface for EPP mode. shown in Figure 42 and Figure 43. Figure 41. EPP Mode Figure 42. EPP Mode Write Cycle

Figure 43. EPP Mode Read Cycle

6.2.3 ECP MODE

ming the Extended Control Register (ECR bits [7:5]). are not used for interfacing with a peripheral device. patible and PS/2-Compatible Modes. Figure 44. ECP Mode

16-byte FIFO (via the SDFIFO address location). case in standard ISA-Compatible mode. Figure 45. ISA-Compatible Timing

Test Mode (ECR [7:5] e110) and Configuration Mode (ECR7:5 ] e111) The test mode can be used to check the FIFO read and write interrupt thresholds as described in Sec- tion 6.1.3.7, TFIFOÐECP Test FIFO Register. Note that for the 82091AA parallel port, the read and write FIFO interrupt thresholds are the same. The FIFO threshold is set by programming the PCFG1 Regis- ter in the 82091AA configuration space. The config- uration mode is used to access the ECPCFGA and ECPCFGB Registers. This mode must first be set before the ECPCFGA and ECPCFGB Registers can be accessed.

6.2.3.1 FIFO Operations

The parallel port FIFO is used for ECP transfers (ECR[7:5] e011), ISA-Compatible FIFO transfers (ECR[7:5] e010), and Test mode (ECR [7:5] e110). Either DMA or programmed I/O can be used for transfers between the host and the parallel port. The FIFO threshold value is selected via the 82091AA configuration registers (PCFG1 Register). The threshold is set to either 1 (forward)/15 (re- verse) or 8 in both directions. A threshold setting of 1 (forward)/15 (reverse) results in longer periods of time between service request, but requires faster servicing of both read and write requests. A thresh- old setting of 8 results in more service requests, but tolerates slower servicing of the requests. In modes 010 and 011, an internal temporary hold- ing register is used in conjunction with the 16-byte FIFO to provide 17 bytes of storage for both forward and reverse transfers. Thus, in the forward direction if the peripheral asserts the BUSY signal during the filling of the FIFO, the host needs to write 17 bytes before the FIFO full flag in the ECR is set to 1. In Test mode (110) only the 16-byte FIFO is used and the temporary holding register is not used. The FIFO is reset by a hard reset (RSTDRV assert- ed) or whenever the parallel port is placed in ISA- Compatible or PS/2-Compatible modes. Note that the FIFO threshold can only be changed when the parallel port is in ISA-Compatible or PS/2-Compati- ble mode.

6.2.3.2 DMA Transfers

The 82091AA contains parallel port DMA request (PPDREQ) and acknowledge (PPDACK Ý) signals to communicate with a standard PC DMA controller. Before initiating a DMA transfer the direction bit in the PCON Register must be set to the proper direc- tion. To initiate DMA transfers, software sets the DMAEN bit to 1 and the SERVICEINTR bit to 0 in the ECR. The PPDREQ and PPDACK Ý signals will then be used to fill (forward direction) or empty (reverse direction) the FIFO. When the DMA controller reach- es terminal count and asserts the TC signal, an inter- rupt is generated and the SERVICEINTR bit is set to 1. To reset the TC interrupt, software can either switch the mode to 000 or 001 or write the DMAEN bit to 0. In DMA mode, if 32 consecutive reads or writes are performed to the FIFO and PPDREQ is still asserted, the 82091AA negates PPDREQ for the length of the last PPDACK Ý/command pulse to force an arbitra- tion cycle on the ISA Bus.

6.2.3.3 Reset FIFO and DMA Terminal Count

The following operations are used to reset the paral- lel port FIFO and TC interrupt Function Reset Operations FIFO -Changing to modes 000 or 001 -Hard reset FIFO Error -Changing to modes 000 or 001 -Hard reset TC Interrupt -Changing to modes 000 or 001 -Setting DMAEN to 0 in ECR -Hard reset

6.2.3.4 Programmed I/O Transfers

Programmed I/O (non-DMA) can also be used for transfers between the host and the parallel port FIFO. Software can determine the read/write FIFO thresholds and the FIFO depth by accessing the FIFO in Test mode. To use programmed I/O trans- fers software sets the direction bit in the PCON Reg- ister to the desired direction and sets the DMAEN bit to 0 and the SERVICEINTR bit to 0 in the ECR. The parallel port requests programmed I/O transfers from the host by asserting IRQ5/IRQ7. In the reverse direction an interrupt occurs when SERVICEINTR e0 either 8 or 15 bytes (depending on threshold setting) are in the FIFO. IRQ5/IRQ7 can be used in an interrupt-driven system. The host must respond to the interrupt request by reading data from the FIFO.

interrupt request by writing data to the FIFO.

6.2.3.5 Data Compression

address/RLE instead of data. received by the RLE count received on bits [6:0].

6.2.4 PARALLEL PORT EXTERNAL BUFFER

rectly transferred through the external buffer.

6.2.5 PARALLEL PORT SUMMARY

Table 18. Parallel Port Summary

The selected IRQ pin (IRQ5/IRQ7) is enabled if ACKINTEN is enabled in the PCON Register. Otherwise, the IRQ pin is
PPDREQ is enabled whenever the DMAEN bit is enabled in the ECR, independent of the parallel port mode.

7.0 SERIAL PORT

7.1 Register Description

tions follow in the order that they appear in the table. the Line Control Register (LCR). conditions on an 82091AA signal pin. access a different register. access a different register. write registers contain bits that are read only. Table 19. Serial Port Registers

Table 20. Serial Port Register Summary

0 Data Bit 0 Data Bit 0 Enable Received 0 if Interrupt FIFO Enable Word Length

1 Data Bit 1 Data Bit 1 Enable XMTR Interrupt ID Bit RCVR FIFO Word Length

2 Data Bit 2 Data Bit 2 Enable RCVR Interrupt ID Bit XMIT FIFO Number of Stop

3 Data Bit 3 Data Bit 3 Enable Modem Interrupt ID Bit DMA Mode Parity Enable

4 Data Bit 4 Data Bit 4 0 0 Reserved Event Parity Select

5 Data Bit 5 Data Bit 5 0 0 Reserved Stick Parity

6 Data Bit 6 Data Bit 6 0 FIFOs Enabled RCVR Trigger Set Break

7 Data Bit 7 Data Bit 7 0 FIFOs Enabled RCVR Trigger Divisor Latch

Table 20. Serial Port Register Summary (Continued)

0 Data Terminal Data Ready Delta Clear to Bit 0 Bit 0 Bit 8

1 Request to Overrun Error Delta Data Set Bit 1 Bit 1 Bit 9

2 Out 1 Bit Parity Error Trailing Edge Bit 2 Bit 2 Bit 10

3 IRQ Enable Framing Error Delta Data Bit 3 Bit 3 Bit 11

4 Loop Break Interrupt Clear to Send Bit 4 Bit 4 Bit 12

7.1.1 THR(A,B)ÐTRANSMITTER HOLDING REGISTER

I/O Address: Base a0h (DLAB e0) Default Value: 00h Attribute: Write Only Size: 8 bits The THR contains data to be transmitted out on the SOUT [A,B] signal line. Bit 0 is the least significant bit and is the first bit serially transmitted. If the serial word length is less than 8 bits (as selected in the LCR), the data word must be written to this register right-justified. Bit positions above the number of bits selected for the word size are discarded (not transmitted). Bit Description 7:0 Transmit Data: Bits[7:0] correspond to SD [7:0].

7.1.2 RBR(A,B)ÐRECEIVER BUFFER REGISTER

I/O Address: Base a0h (DLAB e0) Default Value: 00h Attribute: Read Only Size: 8 bits The RRB contains data received from the SIN [A,B] signal line. Bit 0 is the least significant bit and is the first bit serially received. If the serial word length is less than 8 bits (as selected in the LCR), the data word in this register is right-justified. Bit positions above the number of bits selected for the word size are 0. Bit Description 7:0 Receiver Data: Bits[7:0] correspond to SD [7:0].

7.1.3 DLL(A,B), DLM(A,B)ÐDIVISOR LATCHES (LSB AND MSB) REGISTERS

I/O Address: Base a0h,1h (DLAB e1) Default Value: 00h Attribute: Read/Write Size: 8 bits The 82091AA contains two independently programmable baud rate generators. The 24 MHz crystal oscillator frequency input is divided by 13, resulting in a frequency of 1.8462 MHz. This frequency is the input to each baud rate generator and is divided by the divisor of the associated serial port. The output frequency of the baud rate generator (BOUT [A,B]) is 16 x the baud rate. divisor Ýe(frequency input)/(baud rate x 16) The output of each baud rate generator drives the transmitter and receiver sections of the associated serial port. Two 8-bit latches per serial port store the divisor in a 16-bit binary format. These divisor latches must be loaded during initialization to ensure proper operation of the baud rate generator. Upon loading either of the divisor latches, a 16-bit baud counter is loaded. Table 21 provides decimal divisors to use with crystal frequen- cies of 24 MHz. Using a divisor of zero is not recommended.

Figure 48. Divisor Latches (LSB and MSB) Registers 7:0 Divisor Latch Data: Bits[7:0] correspond to SD [7:0]. Table 21. AIP Serial Port A and B Divisors, Baud Rates, and Clock Frequencies

7.1.4 IER(A,B)ÐINTERRUPT ENABLE REGISTER

an interrupt request (IRQ3 or IRQ4) will not be generated. Figure 49. Interrupt Enable Register MIEe0, the Modem Status Interrupt is disabled.

2 RECEIVER INTERRUPT ENABLE (RIE): When RIE e1, the Receiver Line Status interrupt is

enabled. When RIE e0, the receiver line status interrupt is disabled.

1 TRANSMITTER HOLDING REGISTER EMPTY INTERRUPT ENABLE (THEIE): When THREIE e1,

Holding Register Empty Interrupt is disabled.

0 RECEIVER DATA AVAILABLE INTERRUPT ENABLE AND TIMEOUT INTERRUPT ENABLE IN

enables the Timeout Interrupt when set to 1 and disables the Timeout Interrupt when set to 0.

7.1.5 IIR(A,B)ÐINTERRUPT IDENTIFICATION REGISTER

until the current access is complete. Figure 50. Interrupt Identification Register

mode (FIFOs disabled). The 82091AA never sets this field to either e01 or 10.

3 TIMEOUT INTERRUPT PENDING (TOUTIP)ÐFIFO MODE ONLY: In the non-FIFO mode, this bit is

In FIFO mode TOUTIP is set to 1 when no characters have been removed from or input to the

pending as indicated in Table 22.

0 INTERRUPT PENDING STATUS (IPS): This bit can be used in an interrupt environment to indicate

Table 22. Interrupt Priority

7.1.6 FCR(A,B)ÐFIFO CONTROL REGISTER

Figure 51. FIFO Control Register

7:6 INTERRUPT TRIGGER LEVEL (ITL): The ITL field indicates the interrupt trigger level. When the number of bytes in the receive FIFO equals the interrupt trigger level programmed into this field and the Received Data Available Interrupt enabled (via the IER), an interrupt will be generated and the appropriate bits set in the IIR. Bits [7:6] Trigger Level (Bytes) 0 0 01 (default) 01 0 4 10 0 8 11 1 4 5:4 RESERVED 3 NOT USED: Writing to this bit causes no change in serial port operations. The serial port does not support DMA operations. Note that the TXRDY Ý and RXRDY Ý pins are not available in the 82091AA.

2 RESET TRANSMITTER FIFO (RESETTF): When RESETTF is set to a 1, the FIFO counter is set to

The shift register is not cleared. When the FIFO is cleared, the 82091AA sets this bit to 0. 1 RESET RECEIVER FIFO (RESETRF): When RESETRF is set to a 1, the FIFO counter is set to 0. The shift register is not cleared. When the FIFO is cleared, the 82091AA sets this bit to 0.

0 TRANSMIT AND RECEIVE FIFO ENABLE (TRFIFOE): TRFIFOE enables/disables the transmit

and receive FIFOs. When TRFIFOE e1, both FIFOs are enabled (FIFO Mode). When TRFIFOE e0, the FIFOs are both disabled (non-FIFO MODE). Writin ga0t o this bit clears all bytes in both FIFOs. When changing from FIFO mode to non-FIFO mode and vice versa, data is automatically cleared from the FIFOs. This bit must be written wit h a 1 when other bits in this register are written or the other bits will not be programmed. 105

7.1.7 LCR(A,B)ÐLINE CONTROL REGISTER

Buffer Register, and Interrupt Enable Register. Figure 52. Line Control Register

7 DIVISOR LATCH ACCESS BIT (DLAB): DLAB controls access to the Baud Rate Generator Divisor

Latches (and to the Transmit Holding Register, Receiver Buffer Register and Interrupt Enable Register which are located at the same I/O addresses). When DLAB e1, access to the two Divisor Latches is selected and access to the THR, RBR, and IER is disabled. When DLAB e0, access to the two Divisor Latches is disabled and access to the THR, RBR, and IER is selected. During test mode operations, DLAB must be set to 1 for the BOUT signal to appear on the SOUT pin.

6 BREAK CONTROL (BRCON): When BRCON e1, a break condition is transmitted from the

82091AA serial port to the receiving device. When BRCON e1, the serial output (SOUT) is forced to the ‘spacing‘ state (logical 0). BRCON only affects the SOUT signal and has no effect on the transmitter logic. Note that this feature permits the CPU to alert a terminal. If the following sequence is used, no erroneous characters will be transmitted because of the break. 1. Wait for the transmitter to be idle (TEMT e1). 2. Set break (BRCON e1) for the appropriate amount of time. If the transmitter will be used to time the break duration, then check that TEMT e1 before clearing the BRCON. 3. Clear break (BRCON e0) when normal transmission has to be restored. During the break, the transmitter can be used as a character timer to accurately establish the break duration by sending characters and monitoring THRE and TEMT. 5 STICKY PARITY (STICPAR): STICPAR is the Stick Parity bit. When parity is enabled (PAREN e1) this bit is used in conjunction with EVENPAR to select ‘‘Mark’’ or ‘‘Space’’ Parity. When bits PAREN, EVENPAR and STICPAR are 1, the parity bit is transmitted and checked a s a 0 (Space Parity). If bits PAREN and STICPAR are 1 and EVENPAR is 0, the parity bit is transmitted and checked as a 1 (Mark Parity). When STICPAR e0, stick parity is disabled. 4 EVEN PARITY SELECT (EVENPAR): EVENPAR selects between even and odd parity. When parity is enabled (PAREN e1) and EVENPAR e0, an odd number of 1s is transmitted or checked in the data word bits and parity bit. When parity is enabled and EVENPAR e1, an even number of 1s is transmitted or checked. 3 PARITY ENABLE (PAREN): This bit enables/disables parity generation and checking. When PARENe1, a parity bit is generated (transmit data) or checked (receive data) between the last data bit and stop bit of the serial data. (The Parity bit is used to produce an even or odd number of 1s when the data bits and the Parity bit are summed.) When PAREN e0, parity generation and checking is disabled.

2 STOP BITS (STOPB): This bit specifies the number of stop bits transmitted with each serial

character. When STOPB e0, one stop bit is generated in the transmitted data. When STOPB e1 and a 5-bit data length is selected, one and a half stop bits are generated. When STOPB e1 and either a 6-, 7-, or 8-bit data length is selected, two stop bits are generated. The receiver checks the first Stop bit only, regardless of the number of Stop bits selected. 1:0 SERIAL DATA BITS (SERIALDB): This field specifies the number of data bits in each transmitted or received serial character as follows: Bits[1:0] Data Length 0 0 5 Bits - Default 0 1 6 Bits 1 0 7 Bits 1 1 8 Bits 107

7.1.8 MCR(A,B)ÐMODEM CONTROL REGISTER

This register controls the interface with the modem or data set (or a peripheral device emulating a modem). Figure 53. Modem Control Register

7:5 RESERVED

4 LOOPBACK MODE ENABLE (LME): LME provides a local loopback feature for diagnostic testing of

the serial port module. When LME e1, the following occurs: 1. The transmitter Serial Output (SOUT) is set to the Marking (logic 1) state. 2. The receiver Serial Input (SIN) is disconnected. 3. The output of the Transmitter Shift Register is ‘‘looped back’’(connected) to the Receiver Shift Register. 4. The four modem control inputs (DSR Ý, CTS Ý, RI and DCD Ý) are disconnected. 5. The DTRC, RTSC, OUT1C, IE bits in the MCR are internally connected to DSRS, CTSS, RIS, and DCDS in MSR, respectively. 6. The modem control output pins are forced to their high (inactive) state. 7. Data that is transmitted is immediately received. This feature allows the CPU to verify the transmit and received data paths of the serial port. In the loopback mode, the receiver and transmitter interrupts are fully operational. The modem status interrupts are fully operational. The modem status interrupts are also operational, but the interrupt sources are the lower four bits of MCR instead of the four modem control inputs. Writin ga1t oa n y of these 4 MCR bits (bits [3:0]) causes an interrupt. In Loopback Mode the interrupts are still controlled by the Interrupt Enable Register. The IRQ3 and IRQ4 signal pins are tri-stated in the loopback mode.

3 INTERRUPT ENABLE (IE): When IE e1, the associated interrupt is enabled (either IRQ3 or IRQ4 as

selected via the associated serial port configuration registe r-Ao rB ) .I n Local Loopback Mode, this bit controls bit 7 of the Modem Status Register. 2 OUT1 BIT CONTROL (OUT1C): This bit is the OUT1 bit. It does not have an output pin associated with it. It can be written to and read by the CPU. In Local Loopback Mode, this bit controls bit 6 of the Modem Status Register. 1 REQUEST TO SEND CONTROL (RTS): This bit controls the Request to Send (RTS Ý) output. When RTSC e1, the RTS Ý output is asserted. When RTSC e0, the RTS Ý output is negated. In Local Loopback Mode, this bit controls bit 4 of the Modem Status Register.

0 DATA TERMINAL READY CONTROL (DTRC): This bit controls the Data Terminal Ready (DTR Ý)

output. When DTRC e1, the DTR Ý output is asserted. When DTRC e0, the DTR Ý output is negated. In Local Loopback Mode, this bit controls bit 5 of the Modem Status Register. NOTE: The DTR Ý and RTS Ý outputs of the serial port may be applied to an EIA inverting line driver (such as the DS1488) to obtain the proper polarity input at the modem or data set.

7.1.9 LSR(A,B)ÐLINE STATUS REGISTER

I/O Address: Base a5h Default Value: 60h Attribute: Read/Write Size: 8 bits This 8-bit register provides data transfer status information to the CPU. Note that the Line Status Register is intended for read operations only. Writing to this register is not recommended and could result in unintended operations. For this reason, the figure shows these bits as RO (read only). 109

Figure 54. Line Status Register to 0 when the CPU reads the LSR, if there are no subsequent errors in the FIFO.

5 TRANSMITTER HOLDING REGISTER STATUS (THRE): This bit is the Transmitter Holding

Register Empty (THRE) indicator. THRE indicates that the serial port module is ready to accept a new character for transmission. In addition, this bit causes the serial port module to issue an interrupt to the CPU when the Transmit Holding Register Empty Interrupt enable is set to a 1. THRE is set to 1 when a character is transferred from the Transmitter Holding Register into the Transmitter Shift Register. THRE is set to 0 when the CPU loads the Transmitter Holding Register. In the FIFO mode, this bit is set t o a 1 when the transmit FIFO is empty, and is set to 0 when at least 1 byte is written to the transmit FIFO. 4 BREAK INTERRUPT STATUS (BI): This bit is the Break Interrupt (BI) indicator. BI is set t o a 1 when the received data input is held in the Spacing state (logic 0) for longer than a full word transmission time (that is, the total time of Start bit a data bits a Parity a Stop bits). When the CPU reads the contents of the Line Status Register, BI is set to 0. In FIFO mode, this error is associated with the particular character in the FIFO associated with the Break. BI is indicated to the CPU when its associated character is at the top of the FIFO. When break occurs only one character is loaded into the FIFO. Restarting after a break is received requires the SIN pin to be a logical 1 for at least (/2 bit times. NOTE: Bits[3:0] are the error conditions that produce a Receiver Line Status interrupt whenever any of the corresponding conditions are detected and that interrupt is enabled. 3 FRAMING ERROR STATUS (FE): This bit is the Framing Error (FE) indicator. FE indicates that the received character did not have a valid stop bit. FE is set t o a 1 when the stop bit following the last data bit or parity bit is 0 (spacing level). FE is set to 0 when the CPU reads the contents of the Line Status Register. In FIFO mode, this error is associated with the particular character in the FIFO that it applies to. This error is revealed to the CPU when its associated character is at the top of the FIFO. When a framing error is due to the next start bit, the serial port attempts to resynchronize. In this case, the serial port module samples this start bit twice and, if no FE exists, then the module takes in the rest of the bits. 2 PARITY ERROR STATUS (PE): This bit is the Parity Error (PE) indicator. PE indicates that the received data character does not have the correct even or odd parity, as selected by the EVENPAR bit in the Line Status Register. When a parity error is detected, PE is set to 1. PE is set to 0 when the CPU reads the contents of the Line Status Register. In the FIFO mode, this error is associated with the particular character in the FIFO that it applies to. This error is indicated to the CPU when its associated character is at the top of the FIFO.

1 OVERRUN ERROR STATUS (OE): OE indicates that data in the Receiver Buffer Register was not

read by the CPU before the next character was transferred into the Receiver Buffer Register. In this case, the previous character is overwritten. When an overrun is detected, OE is set to 1. when the CPU reads the Line Status Register, OE is set to 0. This bit is read only. If the FIFO mode data continues to fill the FIFO beyond the trigger level, an overrun error will occur only after the FIFO is completely full and the next character has been received in the shift register. OE is indicated to the CPU as soon as it happens. The character in the shift register is overwritten, but it is not transferred to the FIFO.

0 RECEIVER DATA READY STATUS (DR): DR is set to 1 when a complete incoming character has

been received and transferred into the Receiver Buffer Register or the FIFO. When the data in the Receiver Buffer Register or FIFO is read, DR is set to 0. This bit is read only. 111

7.1.10 MSR(A,B)ÐMODEM STATUS REGISTER

The MSR provides the current state of the control lines from the Modem (or peripheral device) to the CPU. XeValue determined by state of the corresponding modem control signal. Figure 55. Modem Status Register

7 DATA CARRIER DETECT STATUS: This bit is the compliment of the Data Carrier Detect (DCD Ý)

input. If bit 4 of the MCR is set to a 1, this bit is equivalent to IRQ ENABLE in the MCR. 6 RING INDICATOR STATUS: This bit is the compliment of the Ring Indicator (RI) input. If bit 4 of the MCR is set to a 1, this bit is equivalent to OUT1 in the MCR. 5 DATA SET READY STATUS: This bit is the compliment of the Data Set Ready (DSR Ý) input. If bit 4 of the MCR is set to a 1, this bit is equivalent to DTR in the MCR. 4 CLEAR TO SEND STATUS: This bit is the compliment of the Clear to Send (CTS Ý) input. If bit 4 of the MCR is set to a 1, this bit is equivalent to RTS in the MCR.

3 DELTA DATA CARRIER DETECT STATUS: This bit is the Delta Data Carrier Detect (DDCD)

indicator. Bit 3 indicates that the DCD Ý input to the chip has changed state. NOTE: Whenever bit 0, 1, 2, or 3 is set to logic 1, a Modem Status Interrupt is generated.

2 TRAILING EDGE OF RING INDICATOR STATUS: This bit is the Trailing Edge of Ring Indicator

(TERI) detector. Bit 2 indicates that the RI Ý input to the chip has changed from a low to a high state. 1 DELTA DATA SET READY STATUS: This bit is the Delta Data Set Ready (DDSR) indictor. Bit 1 indicates that the DSR Ý input to the chip has changed state since the last time it was read by the CPU. 0 DELTA CLEAR TO SEND STATUS: This bit is the Delta Clear to Send (DCTS) indicator. Bit 0 indicates that the CTS Ý input to the chip has changed state since the last time it was read by the CPU.

7.1.11 SCR(A,B)ÐSCRATCHPAD REGISTER

I/O Address: Base a7h Default Value: 00h Attribute: Read/Write Size: 8 bits This 8-bit read/write register does not control the serial port module in any way. It is intended as a scratchpad register to be used by the programmer to hold data temporarily. Bit Description 7:0 SCRATCHPAD DATA: Bits[7:0] of this register correspond to SD [7:0]. 113

7.2 FIFO Operations

This section describes the FIFO operations for inter- rupt and polled modes.

7.2.1 FIFO INTERRUPT MODE OPERATION

When the Receive FIFO and receiver interrupts are enabled (FCR0 e1 and IER0 e1), receiver interrupts occur as follows: 1. The receive data available interrupt is invoked when the FIFO has reached its programmed trig- ger level. The interrupt is cleared when the FIFO drops below the programmed trigger level. 2. The IIR receive data available indication also oc- curs when the FIFO trigger level is reached, and like the interrupt, the bits are cleared when the FIFO drops below the trigger level. 3. The receiver line status interrupt (IIR-06h), as be- fore, has higher priority than the received data available (IIR e04h) interrupt. 4. The data ready bit (LSR0) is set as soon as a character is transferred from the shift register to the receive FIFO. This bit is set to 0 when the FIFO is empty. When receiver FIFO and receiver interrupts are en- abled, receiver FIFO timeout interrupts occur as fol- lows: 1. A FIFO timeout interrupt occurs, if the following conditions exist: a. At least one character is in the FIFO. b. The most recent serial character received was longer than 4 continous character times ago (if 2 stop bits are programmed, the second one is included in this time delay). c. The most recent CPU read of the FIFO was longer than 4 continous character times ago. The maximum time between a received charac- ter and a timeout interrupt is 160 ms at 300 baud with a 12-bit receive character (i.e., 1 start, 8 data, 1 parity, and 2 stop bits). 2. Character times are calculated by using the RCLK input for a clock signal (this makes the delay pro- portional to the baud rate). 3. When a timeout interrupt occurs, it is cleared and the timer reset when the CPU reads one charac- ter from the receiver FIFO. 4. When a timeout interrupt does not occur, the timeout timer is reset after a new character is re- ceived or after the CPU reads the receiver FIFO. When the transmit FIFO and transmitter interrupts are enabled (FCR0 e1, IER1 e1), transmit interrupts occur as follows: 1. The transmitter holding register interrupt occurs when the transmit FIFO is empty. The interrupt is cleared as soon as the transmitter holding regis- ter is written (1 to 16 characters may be written to the transmit FIFO while servicing the interrupt) or the IIR is read. Character timeout and receiver FIFO trigger level in- terrupts have the same priority as the current re- ceived data available interrupt. Transmit FIFO empty has the same priority as the current transmitter hold- ing register empty interrupt.

7.2.2 FIFO POLLED MODE OPERATION

e1, setting IER [3:0] to all 0s puts the se- rial port in the FIFO polled mode of operation. Since the receiver and transmitter are controlled separate- ly, either one or both can be in the polled mode of operation. In this mode, software checks receiver and transmit- ter status via the LSR. As stated in the register de- scription: # LSR0 is set as long as there is one byte in the receiver FIFO. # LSR1 and LSR4 specify which error(s) has oc- curred. Character error status is handled the same way as interrupt mode. The IIR is not af- fected since IER2 e0. # LSR5 indicates when the transmitter FIFO is empty. # LSR6 indicates that both the transmitter FIFO and shift register are empty. # LSR7 indicates whether there are any errors in the receiver FIFO. 114

8.0 FLOPPY DISK CONTROLLER

The 82091AA’s Floppy Disk Controller (FDC) is functionally compatible with 82078/82077SL/ 82077AA/8272A floppy disk controllers. During 82091AA configuration, the FDC can be configured for either two drive support or four drive support via the FCFG1 Register. This section provides a com- plete description of the FDC when it is configured for two drive support. Additional information on four drive support is provided in Appendix A, FDC Four Drive Support. NOTE: For FDC compatibility and programming guidelines, refer to the 82078 Floppy Disk Controller Data sheet.

8.1 Floppy Disk Controller Registers

The FDC contains seven status, control, and data registers. Table 23 shows the I/O address assign- ments for the FDC registers and the individual regis- ter descriptions follow in the order that they appear in the table. The registers provide control/status information and data paths for transfering data be- tween the floppy disk controller interface and the 8-bit host interface. In some cases, two different reg- isters occupy the same I/O address. In these cases, one register is read only and the other is write only (i.e., a read to the I/O address accesses one regis- ter and a write accesses the other register). All registers are accessed as byte quantities. The base address is determined by hardware configura- tion at powerup (or a hard reset) or via software con- figuration by programming the 82091AA configura- tion registers as described in Section 4.0, AIP Con- figuration. During a hard reset (RSTDRV asserted), the 82091AA registers are set to pre-determined de- fault states. The default values are indicated in the individual register descriptions. Reserved bits in the FDC registers must be programmed to 0 when writ- ing the register and these bits are 0 when read. The following bit notation is used for default settings: X Default bit position value is determined by conditions on an 82091AA signal pin. The following nomenclature is used for register ac- cess attributes: RO Read Only. Note that for registers with read only attributes, writes to the I/O address have no affect on floppy disk operations. WO Write Only. Note that for all FDC registers with write only attributes, reads of the I/O ad- dress access a different register. R/W Read/Write. A register with this attribute can be read and written. Note that individual bits in some read/write registers may be read only. Table 23 lists the register accesses that bring the FDC out of a powerdown state. All other registers accesses are possible without waking the part from a powerdown state and reads from these registers reflects the true status as shown in the register de- scription. For writes that do not affect the power- down state, the FDC retains the data and will subse- quently reflect it when the FDC awakens. Note that for accesses that do not affect powerdown, the ac- cess may cause a temporary increase in FDC power consumption. The FDC reverts back to low power mode when the access has been completed. None of the extended registers effect the behavior of the powerdown mode. 115

Table 23. Floppy Disk Controller Registers (1)

The base address is 3F0h (primary address) or 370 (secondary address).
While writing to the DOR or DSR does not wake up the FDC, writing any of the motor enable bits in the DOR or invoking

a software reset (either via DOR or DSR reset bits) will wake up the FDC.

8.1.1 SRBÐSTATUS REGISTER B (EREG EN e1)

XeValue is determined by the state of the corresponding signal pin. Figure 56. Status Register B 1 when the FDC is in the idle state. When IDLE e0, the FDC is not in the idle state.

8.1.2 DORÐDIGITAL OUTPUT REGISTER

powerdown, writing to the DOR does not wake up the FDC, except for activating any of the motor enable bits. Setting the motor enable bits to 1 wakes up the FDC.

The descriptions in this section for DOR only apply when two-drive support is selected in the FCFG1
The drive motor can be enabled separately without selecting the drive. This permits the motor to

come up to speed before selecting the drive. Note also that only one drive can be selected at a time. Figure 57. Digital Output Register

7:6 RESERVED: For a two-drive system, these bits are not used and have no affect on FDC operation. For a four drive system, see Appendix A, FDC Four Drive Support. 5 MOTOR ENABLE 1 (ME1): This bit controls a motor drive enable signal. ME1 directly controls either the FDME1 Ý signal or FDME0 Ý signal, depending on the state of the BOOTSEL bit in the TDR. When ME1 e1, the selected motor enable signal (FDME1 Ý or FDME0 Ý) is asserted and when ME1e0, the selected motor enable signal is negated. 4 MOTOR ENABLE 0 (ME0): This bit controls a motor drive enable signal. ME1 directly controls either the FDME0 Ý signal or FDME1 Ý signal, depending on the state of the BOOTSEL bit in the TDR. When ME0 e1, the selected motor enable signal (FDME0 Ý or FDME1 Ý) is asserted and when ME0e0, the selected motor enable signal is negated. 3 DMA GATE (DMAGATE): This bit enables/disables DMA for the FDC. When DMAGATE e1, DMA for the FDC is enabled. In this mode, FDDREQ, TC, IRQ6, and FDDACK Ý are enabled. When DMAGATEe0, DMA for the FDC is disabled. In this mode the IRQ6, and DRQ outputs are tri-stated and the DACK Ý and TC inputs are disabled to the FDC. Note that the TC input is only disabled to the FDC module. Other functional units in the 82091AA (e.g., parallel port or IDE interface) can still use the TC input signal for DMA activities. 2 FDC RESET (DORRST): DORRST is a software reset for the FDC module. When DORRST is set to 0, the basic core of the FDC and the FIFO circuits are cleared conditioned by the LOCK bit in the CONFIGURE Command. This bit is set to 0 by software or a hard reset (RSTDRV asserted). The FDC remains in a reset state until software sets this bit to 1. This bit does not affect the DSR, CCR and other bits of the DOR. DORRST must be held active for at least 0.5 ms at 250 Kbps. This is less than a typical ISA I/O cycle time. Thus, in most systems consecutive writes to this register to toggle this bit allows sufficient time to reset the FDC. 1 RESERVED: For a two-drive system, this bit is not used and must be programmed to 0. For a four drive system, see Appendix A, FDC Four Drive Support.

0 DRIVE SELECT (DS): This selects the floppy drive by controlling the FDS0 Ý and FDS1 Ý output

signals. DS directly controls FDS1 and FDS0 as follows: Bit 0 Output Pin Status

0 FDS0 Ý asserted (FDS1 asserted if BOOTSEL e1)

1 FDS1 Ý asserted (FDS1 asserted if BOOTSEL e1)

8.1.3 TDRÐENHANCED TAPE DRIVE REGISTER

I/O Address: Base a3h Default Value: 00h Attribute: Read/Write Size: 8 bits This register allows the user to assign tape support to a particular drive during initialization. Any future refer- ences to that drive number automatically invokes tape support. A hardware reset sets all bits in this register to 0 making drive 0 not available for tape support. A software reset via bit 2 of the DOR does not affect this register. Drive 0 is reserved for the floppy boot drive. Bits [7:2] are only available when EREG EN e1; other- wise the bits are tri-stated. EREG EN is a bit in the POWERDOWN Command. 119

Figure 58. Enhanced Tape Drive Register

2 BOOT DRIVE SELECT (BOOTSEL): The BOOTSEL bit is used to remap the drive selects and

0 DS0 xFDS0, ME0 xFDME0 (default)

1 DS0 xDS1, ME0 xFDME1

four drive system, only drive 0 or drive 1 can be selected as the boot drive. drive system, see Appendix A, FDC Four Drive Support.

0 TAPE SELECT (TAPESEL): This bit is used by software to assign logical drive number 1 to be a

0 None (all are floppy disk drives)

8.1.4 MSRÐMAIN STATUS REGISTER

each byte is transferred to or from the FIFO. register value is 00h until the oscillator circuit has stabilized and the internal registers have been initialized. to report 80h (i.e., RQM is set to 1) is 2.5 ms after a hard or soft reset. # MSRe80H; The controller is ready to receive a command. # MSRe90H; executing a command or waiting for the host to read status bytes (assume DMA mode). # MSReD0H; waiting for the host to write status bytes. Figure 59. Main Status Register

7 REQUEST FOR MASTER (RQM): When RQM e1, the FDC is ready to send/receive data through

the FIFO (FDCFIFO Register). The FDC sets this bit to 0 after a byte transfer and then sets the bit to 1 when it is ready for the next byte. During non-DMA execution phase, RQM indicates the status of IRQ6. 6 DIRECTION I/O (DIO): When RQM e1, DIO indicates the direction of a data transfer. When DIOe1, the FDC is requesting a read of the FDCFIFO. When DIO e0, the FDC is requesting a write to the FDCFIFO. 5 NON-DMA (NONDMA): Non-DMA mode is selected via the SPECIFY Command. In this mode, the FDC sets this bit t o a 1 during the execution phase of a command. This bit is for polled data transfers and helps differentiate between the data transfer phase and the reading of result bytes. 4 COMMAND BUSY (CMDBUSY): CMDBUSY indicates when a command is in progress. When the first byte of the command phase is written, the FDC sets this bit to 1. CMDBUSY is set to 0 after the last byte of the result phase is read. If there is no result phase (e.g., SEEK or RECALIBRATE Commands), CMDBUSY is set to 0 after the last command byte is written. 3:2 RESERVED: For a two-drive system, these bits are not used and must be programmed to 0. For a four drive system, see Appendix A, FDC Four Drive Support.

1 DRIVE 1 BUSY (DRV1BUSY): The FDC module sets this bit to 1 after the last byte of the command

phase of a SEEK or RECALIBRATE Command is issued for drive 1. This bit is set to 0 after the host reads the first byte in the result phase of the SENSE INTERRUPT Command for this drive.

0 DRIVE 0 BUSY (DRV0BUSY): The FDC module sets this bit to 1 after the last byte of the command

phase of a SEEK or RECALIBRATE Command is issued for drive 0. This bit is set to 0 after the host reads the first byte in the result phase of the SENSE INTERRUPT Command for this drive.

8.1.5 DSRÐDATA RATE SELECT REGISTER

I/O Address: Base a4h Default Value: 02h Attribute: Write Only Size: 8 bits The DSR selects the data rate, amount of write precompenstion, invokes direct powerdown, and invokes a FDC software reset. This write only register ensures backward compatibility with the Intel series of floppy disk controllers. Changing the data rate changes the timings of the drive control signals. To ensure that drive timings are not violated when changing data rates, choose a drive timing such that the fastest data rate will not violate the timing. In the default state, the PDOSC bit is low and the oscillator is powered up. When this bit is programmed to a 1, the oscillator is shut off. Hardware reset sets this bit to a 0. Neither of the software resets (via DOR or DSR) have any effect on this bit. Note that PDOSC should only be set t o a 1 when the FDC module is in the powerdown state. Otherwise, the FDC will not function correctly and must be hardware reset once the oscilla- tor has turned back on and stabilized. Setting the PDOSC bit has no effect on the clock input to the FDC (the X1 pin). The clock input is separately disabled when the part is powered down. The Save Command checks the status of PDOSC. However the Restore Command will not restore this bit to a 1. Software resets do not affect the DRATE or PRECOMP bits. 122

Figure 60. Data Rate Select Register

7 SOFTWARE RESET (DSRRST): DSRRST operates the same as the DORRST bit in the DOR,

except that this bit is self clearing. 6 POWERDOWN (FPD): FPD provides direct powerdown for the FDC module. When FPD e1, the FDC module enters the powerdown state, regardless of the state of the module. The FDC module is internally reset and then put into powerdown. No status is saved and any operation in progress is aborted. A hardware or software reset causes the 82091AA to exit the FDC module powerdown state.

5 RESERVED

4:2 PRECOMPENSATION (PRECOMP): Bits[4:2] adjusts the WRDATA output to the disk to compensate for magnetic media phenomena known as bit shifting. The data patterns that are susceptible to bit shifting are well understood and the FDC compensates the data pattern as it is written to the disk. The amount of precompensation depends on the drive and media but in most cases the default value is acceptable. The FDC module starts pre-compensating the data pattern starting on Track 0. The CONFIGURE Command can change the track where pre-compensating originates. Bits[4:2] Precompensation Delays (ns) 0 0 0 Default mode 0 0 1 41.67 0 1 0 83.34 0 1 1 125.00 1 0 0 166.67 1 0 1 208.33 110 2 5 0 1 1 1 0.00 (disabled) The default precompensation delay mode provides the following delays: Data Rate Default Precompensation Delays (ns) 1 Mbps 41.67 0.5 Mbps 125.00 0.3 Mbps 125.00 0.25 Mbps 125.00 1:0 DATA RATE SELECT (DRATESEL): DRATESEL[1:0] select one of the four data rates as listed below. The default value is 250 Kbps. Bits[1:0] Date Rate 1 1 1 Mbps 0 0 500 Kbps 0 1 300 Kbps 1 0 250 Kbps - default 124

8.1.6 FDCFIFOÐFDC FIFO (DATA)

the transfer of data. Disk writes complete the current sector by generating a 00 pattern and valid CRC. Figure 61. FDC FIFO 7:0 FIFO DATA: Bits[7:0] correspond to SD [7:0].

8.1.7 DIRÐDIGITAL INPUT REGISTER

This register is read only in all modes. In PC-AT mode only bit 7 is driven and all other bits remain tri-stated. Figure 62. Digital Input Register the DSKCHG Ý signal on the floppy interface is negated. During powerdown, this bit is invalid. 6:0 NOT USED: These bits are tri-stated during a read.

8.1.8 CCRÐCONFIGURATION CONTROL REGISTER

This register sets the data rate. Figure 63. Configuration Control Register

8.2 Reset

There are four sources of FDC resetÐa hard reset via the RSTDRV signal and three software resets (via the FCFG2, DOR, and DSR Registers). At the end of the reset, the FDC comes out of the power- down state. Note that the DOR reset condition re- mains in effect until software programs the DORRST bit to 1 in the DOR. All operations are terminated and the FDC enters an idle state. Invoking a reset while a disk write activity is in progress will corrupt the data and CRC. On exiting the reset state, various internal registers are cleared, and the FDC waits for a new command. Drive polling will start unless dis- abled by a new CONFIGURE Command.

8.2.1 HARD RESET AND CONFIGURATION

A hard reset (asserting RSTDRV) and a software re- set through the FCFG2 Registers have the same af- fect on the FDC. These resets clear all FDC regis- ters, except those programmed by the SPECIFY command. The DOR reset bit is enabled and must be set to 0 by the host to exit the reset state.

8.2.2 DOR RESET vs DSR RESET

The DOR and DSR resets are functionally the same. The DSR reset is included to maintain 82072 com- patibility. Both reset the 8272 core, which affects drive status information. The FIFO circuits are also reset if the LOCK bit is a 0 (see definition of the LOCK bit). The DSR reset is self-clearing (exits the reset state automatically) while the DOR reset re- mains in the reset state until software writes the DOR reset bit to 0. DOR reset has precedence over the DSR reset. The DOR reset is set automatically when a hard reset or configuration reset occurs. Software must set the DOR reset bit to 0 to exit the reset state. The AC Specifications gives the minimum amount of time that the DOR reset must be held active. This amount of time that the DOR reset must be held active is dependent upon the data rate. FDC re- quires that the DOR reset bit must be held active for at least 0.5 ms at 250 Kbps. This is less than a typi- cal ISA I/O cycle time.

8.3 DMA Transfers

DMA transfers are enabled with the SPECIFY Com- mand. When enabled, The FDC initiates DMA trans- fers by asserting the FDDREQ signal during a data transfer command. The FIFO is enabled directly by asserting FDDACK Ý and addresses need not be valid.

8.4 Controller Phases

The FDC handles commands in three phasesÐ com- mand , execution and result . Each phase is de- scribed in the following sections. When not process- ing a command, the FDC can be in the idle , drive polling or powerdown state . This section describes the command, execute and result phases.

8.4.1 COMMAND PHASE

After a reset, the FDC enters the command phase and is ready to accept a command from the host. For each of the commands, a defined set of com- mand code bytes and parameter bytes must be writ- ten to the FDC (as described in Section 8.8, Com- mand Set Description) before the command phase is complete. These bytes of data must be trans- ferred in the order described. Before writing to the FDC, the host must examine the RQM and DIO bits of the Main Status Register. RQM must be 1 and DIO must be 0, before com- mand bytes may be written. The FDC sets RQM to 0 after each write cycle and keeps the bit at 0 until the received byte is processed. After processing the byte, the FDC sets RQM to 1 again to request the next parameter byte of the command, unless an ille- gal command condition is detected. After the last parameter byte is received, RQM remains 0, and the FDC automatically enters the next phase (execution or result phase) as defined by the command defini- tion. The FIFO is disabled during the command phase to retain compatibility with the 8272A, and to provide for the proper handling of the Invalid Command con- dition. 128

8.4.2 EXECUTION PHASE

The following paragraphs detail the operation of the FIFO flow control. In these descriptions, threshold is defined as the number of bytes available to the FDC when service is requested from the host, and ranges from 1 to 16. The FIFOTHR parameter, which the user programs, is one less and ranges from 0 to 15. A low threshold value (e.g., 2) results in longer peri- ods of time between service requests but requires faster servicing of the request for both read and write cases. The host reads (writes) from (to) the FIFO until empty (full), then the transfer request goes inactive. The host must be very responsive to the service request. This is the desired case for use with a ‘‘fast’’ system. A high value of threshold (e.g., 12) is used with a ‘‘sluggish’’ system by affording a long latency period after a service request, but results in more frequent service requests.

8.4.2.1 Non-DMA Mode Transfers from the FIFO

The IRQ6 pin and RQM bits in the Main Status Reg- ister are activated when the FIFO contains 16 (or set threshold) bytes, or the last bytes of a full sector transfer have been placed in the FIFO. The IRQ6 pin can be used for interrupt driven systems and RQM can be used for polled sytems. The host must re- spond to the request by reading data from the FIFO. This process is repeated until the last byte is trans- ferred out of the FIFO, then FDC negates the IRQ6 pin and RQM bit.

8.4.2.2 Non-DMA Mode Transfers from the Host

The IRQ6 pin and RQM bit in the Main Status Regis- ter are activated upon entering the execution phase of data transfer commands. The host must respond to the request by writing data into the FIFO. The IRQ6 pin and RQM bit remain true until the FIFO becomes full. They are set true again when the FIFO has (threshold) bytes remaining in the FIFO. The IRQ6 pin is also negated if TC and DACK Ý both go inactive. The FDC enters the result phase after the last byte is taken by the FDC from the FIFO (i.e. FIFO empty condition).

8.4.2.3 DMA Mode Transfers from the FIFO to

The FDC asserts the FDDREQ signal when the FIFO contains 16 (or set threshold) bytes or the last byte of a full sector transfer has been placed in the FIFO. The DMA controller must respond to the request by reading data from the FIFO. The FDC negates FDDREQ when the FIFO is empty. FDDREQ is neg- ated after FDDACK Ý is asserted for the last byte of a data transfer (or on the active edge of RD Ý,o n the last byte, if no edge is present on FDDACK Ý). NOTE: FDDACKÝ and TC must overlap for at least 50 ns for proper functionality. A data under- run may occur if FDDREQ is not removed in time to prevent an unwanted cycle.

8.4.2.4 DMA Mode Transfers from the Host to

The FDC asserts FDDREQ when entering the exe- cution phase of data transfer commands. The DMA controller must respond by asserting FDDACK Ý and WRÝ signals and placing data in the FIFO. FDDREQ remains asserted until the FIFO becomes full. FDDREQ is again asserted when the FIFO has (threshold) bytes remaining in the FIFO. The FDC also negates the FDDREQ when the FIFO becomes empty (qualified by DACK Ý and TC overlapping by 50 ns) indicating that no more data is required. FDDREQ is negated after FDDACK Ý is asserted for the last byte of a data transfer (or on the active edge of WR Ý of the last byte, if no edge is present on DACKÝ). A data overrun may occur if FDDREQ is not removed in time to prevent an unwanted cycle. 129

8.4.3 DATA TRANSFER TERMINATION

The FDC supports terminal count explicitly through the TC signal and implicitly through the underrun/ overrun and end-of-track (EOT) functions. For full sector transfers, the EOT parameter can define the last sector to be transferred in a single or multi-sec- tor transfer. If the last sector to be transferred is a partial sector, the host can stop transferring the data in mid-sector and the FDC will continue to complete the sector as if a hardware TC was received. The only difference between these implicit functions and TC is that they return ‘‘abnormal termination’’ result status. Such status indications can be ignored if they were expected. NOTE: When the host is sending data to the FIFO, the internal sector count will be complete when the FDC reads the last byte from its side of the FIFO. There may be a delay in the removal of the transfer request signal of up to the time taken for the FDC to read the last 16 bytes from the FIFO. The host must be able to tolerate this. In a DMA system, FDDREQ is removed (negated) as soon as TC is received indicating the termination of the transfer. The reception of TC also gener- ates an interrupt on IRQ6. However, in a non-DMA system the interrupt will not be generated until the FIFO is empty. The generation of IRQ6 determines the beginning of the result phase. For each of the commands, a de- fined set of result bytes has to be read from the FDC before the result phase is complete (refer to Section 8.5, Command Set/Descriptions). These bytes of data must be read out for another command to start. RQM and DIO must both be 1 before the result bytes may be read from the FIFO. After all the result bytes have been read, RQM e1, DIO e0, and CMDBU- SYe0 in the MSR. This indicates that the FDC is ready to accept the next command.

8.5 Command Set/Descriptions

Commands can be written whenever the FDC is in the command phase. Each command has a unique set of needed parameters and status results. The FDC checks to see that the first byte is a valid com- mand and, if valid, proceeds with the command. If it was invalid, the next time the RQM bit in the MSR register is 1 the DIO and CB bits will also be 1, indi- cating the FIFO must be read. A result byte of 80h will be read out of the FIFO, indicating an invalid command was issued. After reading the result byte from the FIFO, the FDC returns to the command phase. Table 23 shows the FDC Command set. 130

Table 24. FDC Command Set

Table 24. FDC Command Set (Continued)

AUTO PD AUTO POWERDOWN CONTROL: When AUTO PD e0, automatic powerdown is disabled. When AUTO PD e1, automatic powerdown is enabled. C CYLINDER ADDRESS: The currently selected cylinder address, 0 to 255. D0, D1 DRIVE SELECT 0-1: Designates which drives are Perpendicular drives . A 1 indicates Per- pendicular drive. D DATA PATTERN: The pattern to be written in each sector data field during formatting. DN DONE: This bit indicates that this is the last byte of the drive specification command. The FDC checks to see if this bit is 1 or 0. When DN e0, the FDC expects more bytes. DNe0 FDC expects more subsequent bytes. DNe1 Terminates the command phase and enters the results phase. An additional benefit is that by setting this bit to 1, a direct check of the current drive specifications can be done. DIR Ý DIRECTION CONTROL: When DIR Ýe0, the head steps out from the spindle during a relative seek. When DIR Ýe1, the head steps in toward the spindle. DS0, DS1 DISK DRIVE SELECT: DS1 DS0 Drive Slot 0 0 drive 0 0 1 drive 1 1 0 drive 2 * 1 1 drive 3 * *Available when FDDQTY e1 in the FCFG1 Register (see Appendix A, FDC Four Drive Support) DTL SPECIAL SECTOR SIZE: By setting N to zero (00), DTL may be used to control the number of bytes transferred in disk read/write commands. The sector size (N e0) is set to 128. If the actual sector (on the diskette) is larger than DTL, the remainder of the actual sector is read but is not passed to the host during read commands; during write commands, the remainder of the actual sector is written with all zero bytes. The CRC check code is calculated with the actual sector. When N is not zero, DTL has no meaning and should be set to FFh. DRATE[0:1] DATA RATE: Data rate values from the DSR register. 140

DRT0, DRT1 DATA RATE TABLE SELECT: These two bits select between the different data rate tables. The default is the conventional table. These also provide mapping of the data rates selected in the DSR and CCR. The table below shows this. Bits in DSR DRT1 DRT0 DRATE1 DRATE0 Data Rate Operation 1 1 1 Mbps Default 0 0 0 0 500 Kbps 0 1 300 Kbps 1 0 250 Kbps 0 1 RSVD RSVD RSVD RSVD 1 0 RSVD RSVD RSVD RSVD 1 1 1 Mbps Perpendicular mode FDDs 1 1 0 0 500 Kbps 0 1 Illegal 1 0 250 Kbps DT0,DT1 DRIVE DENSITY SELECT TYPE: These bits select the outputs on DRVDEN0 and DRVDEN1 (see DRIVE SPECIFICATION Command). EC ENABLE COUNT: When EC e1, the DTL parameter of the Verify Command becomes SC (Number of sectors per track). EFIFO Enable FIFO: When EFIFO e0, the FIFO is enabled. EFIFO e1 puts the FDC in the 8272A compatible mode where the FIFO is disabled. EIS ENABLE IMPLIED SEEK: When EIS e1, a seek operation is performed before executing any read or write command that requires the C parameter in the command phase. EIS e0 disables the implied seek. EOT END OF TRACK: The final sector number of the current track. EREG EN ENHANCED REGISTER ENABLE: When EREG EN e1, the TDR register is extended and SRB is made visible to the user. When EREG EN e0, the standard registers are used. FDI TRI FLOPPY DRIVE INTERFACE TRI-STATE: When FDI TRI e0, the output pins of the floppy disk drive interface are tri-stated. This is also the default state. When FDI TRI e1, the floppy disk drive interface remains unchanged. 141

FD0, FD1 FLOPPY DRIVE SELECT: These two bits select which physical drive is being specified. The FDn corresponds to FDSn and FDMEn on the floppy drive interface. The drive is selected independent of the BOOTSEL bit in the TDR. Refer to Section 8.1.3, TDRÐEnhanced Tape Drive Register, which explains the distinction between physical drives and their virtual map- ping as defined by the BOOTSEL bit. FD1 FD0 Drive slot 0 0 drive 0 1 0 drive 1 0 1 drive 2 * 1 1 drive 3 * *Available if the four floppy drive option is selected in the FCFG1 Register. GAP GAP: Alters Gap 2 length when using Perpendicular Mode. GPL GAP LENGTH: The gap 3 size. (Gap 3 is the space between sectors excluding the VCO synchronization field). H/HDS HEAD ADDRESS: Selected head: 0 or 1 (disk side 0 or 1) as encoded in the sector ID field. HLT HEAD LOAD TIME: The time interval that FDC waits after loading the head and before initiating a read or write operation. Refer to the SPECIFY Command for actual delays. HUT HEAD UNLOAD TIME: The time interval from the end of the execution phase (of a read or write command) until the head is unloaded. Refer to the SPECIFY Command for actual delays. ISO ISO FORMAT: When ISO e1, the ISO format is used for all data transfer commands. When ISOe0, the normal IBM system 34 and perpendicular is used. The default is ISO e0. LOCK LOCK: Lock defines whether EFIFO, FIFOTHR, and PRETRK parameters of the CONFIG- URE Command can be reset to their default values by a software reset (Reset made by setting the proper bit in the DSR or DOR registers). MFM MFM MODE: A one selects the double density (MFM) mode. A zero is reserved. 142

MIN DLY MINIMUM POWERUP TIME CONTROL: This bit is active only if AUTO PD bit is enabled. When MIN DLY e0, a 10 ms minimum powerup time is assigned and when MIN DLY e1, a 0.5 sec. minimum powerup time is assigned. MT MULTI-TRACK SELECTOR: When MT e1, the multi-track operating mode is selected. In this mode, the FDC treats a complete cylinder, under head 0 and 1, as a single track. The FDC operates as if this expanded track started at the first sector under head 0 and ended at the last sector under head 1. With this flag set, a multitrack read or write operation will automatically continue to the first sector under head 1 when the FDC finishes operating on the last sector under head 0. N SECTOR SIZE CODE: This specifies the number of bytes in a sector. When N e00h, the sector size is 128 bytes. The number of bytes transferred is determined by the DTL parame- ter. Otherwise the sector size is (2 raised to the ‘‘N’th’’ power) times 128. All values up to 07h are allowable. A value of 07h equals a sector size of 16 Kbytes. It is the users responsi- bility to not select combinations that are not possible with the drive. N Sector Size 00 128 bytes 01 256 bytes 02 512 bytes 03 1024 07 16 Kbytes NCN NEW CYLINDER NUMBER: The desired cylinder number. ND NON-DMA MODE FLAG: When ND e1, the FDC operates in the non-DMA mode. In this mode, the host is interrupted for each data transfer. When ND e0, the FDC operates in DMA mode and interfaces to a DMA controller by means of the DRQ and DACK Ý signals. NRP NO RESULTS PHASE: When NRP e1, the result phase is skipped. When NRP e0, the result phase is generated. OW OVERWRITTEN: The bits denoted D0 and D1 of the PERPENDICULAR MODE Command can only be overwritten when OW e1. 143

PCN PRESENT CYLINDER NUMBER: The current position of the head at the completion of SENSE INTERRUPT STATUS Command. PC2,PC1,PC0 PRECOMPENSATION VALUES: Precompensation values from the DSR register. PDOSC POWERDOWN OSCILLATOR: When this bit is set, the internal oscillator is turned off. PTS PRECOMPENSATION TABLE SELECT: This bit selects whether to enable the precompen- sation value programmed in the DSR or not. In the default state, the value programmed in DSR will be used. More information regarding the precompensation is available in Section 8.1.5. PTS e0 DSR programmed precompensation delays PTSe1 No precompensation delay is selected for the corresponding drive. POLL POLLING DISABLE: When POLL e1, the internal polling routine is disabled. When POLLe0, polling is enabled. PRETRK PRECOMPENSATION START TRACK NUMBER: Programmable from track 00 to FFh. R SECTOR ADDRESS: The sector number to be read or written. In multi-sector transfers, this parameter specifies the sector number of the first sector to be read or written. RCN RELATIVE CYLINDER NUMBER: Relative cylinder offset from present cylinder as used by the RELATIVE SEEK Command. SC NUMBER OF SECTORS: The number of sectors to be initialized by the FORMAT Command. The number of sectors to be verified during a Verify Command, when EC e1. SK SKIP FLAG: When SK e1, sectors containing a deleted data address mark will automatically be skipped during the execution of a READ DATA Command. If a READ DELETED DATA Command is executed, only sectors with a deleted address mark will be accessed. When SK e0, the sector is read or written the same as the read and write commands. SRT STEP RATE INTERVAL: The time interval between step pulses issued by the FDC. Pro- grammable from 0.5 ms to 8 ms, in increments of 0.5 ms at the 1 Mbit data rate. Refer to the SPECIFY Command for actual delays. ST0-3 STATUS REGISTERS 0-3. Registers within the FDC that store status information after a command has been executed. This status information is available to the host during the result phase after command execution. WGATE WRITE GATE: Write gate alters timing of WE, to allow for pre-erase loads in perpendicular drives.

8.5.1 STATUS REGISTER ENCODING

The contents of these registers are available only through a command sequence. 144

8.5.1.1 Status Register 0

BitÝ Symbol Name Description 7,6 IC Interrupt Code 00 Normal termination of command. The specified command was properly executed and completed without error. 01 Abnormal termination of command. Command execution was started, but was not successful completed. 10 Invalid command. The requested command could not be executed. 11 Abnormal termination caused by Polling.

5 SE Seek End The 82091AA completed a SEEK or RECALIBRATE command,

or a READ or WRITE with implied seek command.

4 EC Equipment Check The TRK pin failed to become a ‘‘1’’ after:

80 step pulses in the RECALIBRATE COMMAND. 2. The RELATIVE SEEK command causes the 82078 to step outward beyond Track 0. 3 Ð Ð Unused. This bit is always ‘‘0’’. 2 H Head Address The current head address. 1,0 DS1,0 Drive Select The current selected drive.

8.5.1.2 Status Register 1

BitÝ Symbol Name Description

7 EN End of Cylinder The 82078 tried to access a section beyond the final sector of

the track (255D). Will be set if TC is not issued after Read or Write Data Command. 6 Ð Ð Unused. This bit is always ‘‘0’’.

5 DE Data Error The 82078 detected a CRC error in either the ID field or the data

field of a sector.

4 OR Overrun/Underrun Becomes set if the 82078 does not receive CPU or DMA service

within the required time interval, resulting in data overrun or underrun. 3 Ð Ð Unused. Ths bit is always ‘‘0’’.

2 ND No Data Any one of the following:

READ DATA, READ DELETED DATA command, the 82091AA did not find the specified sector. 2. READ ID command, the 82091AA cannot read the ID field without an error. 3. READ TRACK command, the 82091AA cannot find the proper sector sequence.

1 NW Not Writable WP pin became a ‘‘1’’ while the 82091AA is executing a WRITE

DATA, WRITE DELETED DATA, or FORMAT TRACK command.

0 MA Missing Any one of the the following:

Address Mark 1. The 82091AA did not detect an ID address mark at the specified track after encountering the index pulse from the INDX Ý pin twice. 2. The 82091AA cannot detect a data address mark or a deleted data address mark on the specified track. 145

8.5.1.3 Status Register 2

BitÝ Symbol Name Description 7 Ð Ð Unused. This bit is always ‘‘0’’.

6 CM Control Mark Any one of the following:

READ DATA command, the 82078 encounters a deleted data address mark. 2. READ DELETED DATA command, the 82078 encountered a data address mark. 5 DD Data Error in The 82091AA detected a CRC error in the data field. Data Field

4 WC Wrong The track address from the sector ID field is different from the track

address maintained inside the 82091AA.Cylinder 3 Ð Ð Unused. This bit is always ‘‘0’’. 2 Ð Ð Unused. This bit is always ‘‘0’’.

1 BC Bad Cylinder The track address from the sector ID field is different from the track

address maintained inside the 82091AA and is equal to FF hex which indicates a bad track with a hard error according to the IBM soft-sectored format.

0 MD Missing Data The 82091AA cannot detect a data address mark or a deleted data

address mark.Address Mark

8.5.1.4 Status Register 3

Bit Ý Symbol Name Description 7 Ð Ð Unused. This bit is always ‘‘0’’. 6 WP Write Protected Indicates the status of the WP pin. 5 Ð Ð Unused. This bit is always ‘‘0’’. 4 T0 Track 0 Indicates the status of the TRK0 pin. 3 Ð Ð Unused. This bit is always ‘‘0’’. 2 HD Head Address Indicates the status of the HDSEL pin. 1,0 DS1,0 Drive Select Indicates the status of the DS1, DS0 pins. 146

8.5.2 DATA TRANSFER COMMANDS

ence being the coding of bits [4:0] in the first byte.

8.5.2.1 Read Data

and begins reading ID address marks and ID fields. transfers the data to the FIFO. terminate the READ DATA Command. 25). If N is set to zero, the sector size is set to 128. transfers the specified number of bytes to the host. impact on the number of bytes transferred. Table 25. Sector Sizes track) and N (Number of bytes/sector). Table 26. Effects of MT and N Bits to Table 29. The termination must be normal. be saved between subsequent reads.

READ DATA command execution and results.

8.5.2.2 Read Deleted Data

Table 27. Skip Bit vs READ DATA Command

0 Normal Data Yes No Normal Termination

1 Normal Data Yes No Normal Termination

1 Deleted Data No Yes Normal Termination Sector Not Read

Table 28. Skip Bit vs READ DELETED DATA Command

0 Normal Data Yes Yes Normal Termination

1 Normal Data No Yes Normal Termination Sector Not Read

1 Deleted Data Yes No Normal Termination

Table 29. Result Phase

0 Less than EOT NC NC R a1N C

0 Equal to EOT C a1N C 0 1 N C

1 Less than EOT NC NC R a1N C

1 Equal to EOT NC LSB 01 NC

NC eno change; the same value as the one at the beginning of command execution.
LSB eleast significant bit; the LSB of H is complemented.

8.5.2.3 Read Track

8.5.2.4 Write Data

remainder of the data field is filled with zeros.

8.5.2.5 Verify

signal cannot be used to terminate this command. e0, DTL/SC should be programmed to 0FFh. Table 30. Verify Command Result Phase

00 S C eDTL Successful Termination

00 S C eDTL Unsuccessful Termination

01 S C s Ý Sectors Remaining Successful Termination

01 S C l Ý Sectors Remaining Unsuccessful Termination

10 S C eDTL Successful Termination

10 S C eDTL Unsuccessful Termination

11 S C s Ý Sectors Remaining Successful Termination

11 S C l Ý Sectors Remaining Unsuccessful Termination

8.5.2.6 Format Track

vary due to drive electronics. Table 31. Typical PC/AT Values for Formatting

360 KB 512 02 09 2A 50

2.88 MB 512 02 24 38 53

720 KB 512 02 09 1B 54

All values are in hex, except sector size.
Gap3 is programmable during reads, writes, and formats.
GPL2 esuggested Gap3 value in FORMAT TRACK Command.

8.5.2.7 Format Field

Figure 64. System 34, ISO and Perpendicular Formats

8.5.3 CONTROL COMMANDS

Control commands differ from the other commands in that no data transfer takes place. Three com- mands generate an interrupt when complete; READ ID, RECALIBRATE and SEEK. The other control commands do not generate an interrupt.

8.5.3.1 READ ID Command

The READ ID Command is used to find the present position of the recording heads. The FDC stores the values from the first ID field it is able to read into its registers. If the FDC does not find an ID address mark on the diskette after the second occurrence of a pulse on the INDEX Ý pin, it then sets the IC code in Status Register 0 to 01 (Abnormal termination), sets the MA bit in Status Register 1 to 1, and termi- nates the command. The following commands will generate an interrupt upon completion. They do not return any result bytes. It is recommended that control commands be followed by the SENSE INTERRUPT STATUS Com- mand. Otherwise, valuable interrupt status informa- tion will be lost.

8.5.3.2 RECALIBRATE Command

This command causes the read/write head within the FDC to retract to the track 0 position. The FDC clears the contents of the PCN counter, and checks the status of the TRK0 pin from the FDD. As long as the TRK0 pin is low, the DIR Ý pin remains 0 and step pulses are issued. When the TRK0 pin goes high, the SE bit in Status Register 0 is set to 1, and the command is terminated. If the TRK0 pin is still low after 79 step pulses have been issued, the FDC sets the SE and the EC bits of Status Register 0 to 1 and terminates the command. Disks capable of han- dling more than 80 tracks per side may require more than one RECALIBRATE Command to return the head back to physical Track 0. The RECALIBRATE Command does not have a re- sult phase. The SENSE INTERRUPT STATUS Com- mand must be issued after the RECALIBRATE Com- mand to effectively terminate it and to provide verifi- cation of the head position (PCN). During the com- mand phase of the recalibrate operation, the FDC is in the busy state, but during the execution phase it is in a non-busy state. At this time another RECALI- BRATE Command may be issued, and in this man- ner, parallel RECALIBRATE operations may be done on up to 2 drives simultaneously. After powerup, software must issue a RECALI- BRATE Command to properly initialize all drives and the controller.

8.5.3.3 DRIVE SPECIFICATION Command

The FDC uses two pins, DRVDEN0 and DRVDEN1 to select the density for modern drives. These sig- nals inform the drive of the type of diskette in the drive. The DRIVE SPECIFICATION Command speci- fies the polarity of the DRVDEN0 and DRVDEN1 pins. It also enables/disables DSR programmed pre- compensation. This command removes the need for a hardware work-around to accommodate differing specifica- tions among drives. By programming this command during BIOS’s POST routine, the floppy disk control- ler internally configures the correct values for DRVDEN0 and DRVDEN1 with corresponding pre- compensation value and data rate table enabled for the particular type of drive. This command is protected from software resets. Af- ter executing the DRIVE SPECIFICATION Com- mand, subsequent software resets will not clear the programmed parameters. Only another DRIVE SPECIFICATION Command or hard reset can reset it to default values. The 6 LSBs of the last byte of this command are reserved for future use. The DRATE0 and DRATE1 are values as pro- grammed in the DSR register. See Table 32 for pin decoding at different data rates. Table 32 describes the drives that are supported with the DT0, DT1 bits of the DRIVE SPECIFICA- TION Command: 153

Table 32. DRVDENn Polarities

1 Mbps 1 1

300 Kbps 1 0

250 Kbps 0 0

1 Mbps 1 0

300 Kbps 1 1

250 Kbps 0 1

300 Kbps 0 1

250 Kbps 1 0

8.5.3.4 SEEK Command

in), and issues step pulses. out), and issues step pulses.

SENSE INTERRUPT STATUS Command;
Issue READ/WRITE Command.

The SEEK Command does not have a result phase.

8.5.3.5 SENSE INTERRUPT STATUS Command

Upon entering the Result Phase of:
End of SEEK, RELATIVE SEEK or
FDC requires a data transfer during the execution

may effect the operation of the next command.

8.5.3.6 SENSE DRIVE STATUS Command

8.5.3.7 SPECIFY Command

speed selection and are documented in Table 34. Table 33. Interrupt Identification

Table 34. Drive Control Delays (ms)

1 M 500K 300K 250K 1 M 500K 300K 250K

Table 35. Head Load Time (ms) the IRQ6 pin to signal data transfers.

8.5.3.8 CONFIGURE Command

meets the system requirements. data transfers are asked for on a byte by byte basis. PRETRKÐPrecompensation start track number.

8.5.3.9 VERSION Command

The VERSION Command checks to see if the con- troller is an enhanced type (82077, 82077AA, 82077SL) or the older type (8272A/765A). A value of 90h is returned as the result byte, defining an en- hanced FDD controller is in use. No interrupts are generated.

8.5.3.10 RELATIVE SEEK Command

The RELATIVE SEEK Command is coded the same as for the SEEK Command, except for the MSB of the first byte and the DIR Ý bit. DIRÝ Head Step Direction Control DIRÝ ACTION

0 Step Head Out

1 Step Head In

RCN Relative Cylinder Number that determines how many tracks to step the head in or out from the current track number. The RELATIVE SEEK Command differs from the SEEK Command in that it steps the head the abso- lute number of tracks specified in the command in- stead of making a comparison against an internal register. The SEEK Command is good for drives that support a maximum of 256 tracks. RELATIVE SEEKs cannot be overlapped with other RELATIVE SEEKs. Only one RELATIVE SEEK can be active at a time. Bit 4 of Status Register 0 (EC) will be set to 1 if RELATIVE SEEK attempts to step outward beyond Track 0. As an example, assume that a floppy drive has 300 useable tracks and that the host needs to read track 300 and the head is on any track (0–255). If a SEEK Command is issued, the head stops at track 255. If a RELATIVE SEEK Command is issued, the FDC moves the head the specified number of tracks, re- gardless of the internal cylinder position register (but increments the register). If the head had been on track 40 (D), the maximum track that the FDC could position the head on using RELATIVE SEEK, is 296 (D), the initial track, a256 (D). The maximum count that the head can be moved with a single RELATIVE SEEK Command is 256 (D). The internal register, PCN, would overflow as the cylinder number crossed track 255 and would con- tain 40 (D). The resulting PCN value is thus (NCN a PCN) mod 256. Functionally, the FDC starts count- ing from 0 again as the track number goes above 255(D). It is the users responsibility to compensate FDC functions (precompensation track number) when accessing tracks greater than 255. The FDC does not keep track that it is working in an ‘‘extend- ed track area’’ (greater than 255). Any command is- sued uses the current PCN value, except for the RE- CALIBRATE Command that only looks for the TRACK0 signal. RECALIBRATE returns an error if the head is farther than 79 due to its limitation of issuing a maximum 80 step pulses. The user simply needs to issue a second RECALIBRATE Command. The SEEK Command and implied seeks function correctly within the 44 (D) track (299–255) area of the extended track area. It is the users responsibility not to issue a new track position that exceeds the maximum track that is present in the extended area. To return to the standard floppy range (0–255) of tracks, a RELATIVE SEEK is issued to cross the track 255 boundary. A RELATIVE SEEK Command can be used instead of the normal SEEK Command but the host is re- quired to calculate the difference between the cur- rent head location and the new (target) head loca- tion. This may require the host to issue a READ ID Command to ensure that the head is physically on the track that software assumes it to be. Different FDC commands return different cylinder results which may be difficult to keep track of with software without the READ ID Command.

8.5.3.11 DUMPREG Command

The DUMPREG Command is designed to support system run-time diagnostics and application soft- ware development and debug. The command re- turns pertinent information regarding the status of many of the programmed fields in the FDC. This can be used to verify the values initialized in the FDC.

8.5.3.12 PERPENDICULAR MODE Command

An added capability of the FDC is the ability to inter- face directly to perpendicular recording floppy drives. Perpendicular recording differs from the tradi- tional longitudinal method by orienting the magnetic bits vertically. This scheme packs in more data bits for the same area. The PERPENDICULAR MODE Command allows the system designers to designate specific drives as Perpendicular recording drives. Data transfers be- 157

for the PERPENDICULAR MODE Command.

If any of the new bits D0 and D1 are pro-
Any of the new bits (DO/D1) are programmed for
Bits D0 and D1 can only be over-written when
A software reset (Reset via DOR or DSR regis-
A hardware reset (Reset via pin 32) sets all bits

8.5.3.13 POWERDOWN MODE Command

and identify the values of the PD and IDLE status. satisfied before the FDC will enter auto powerdown. Table 36. Effects of WGATE and GAP Bits When either GAP or WGATE bit is set, the current value of precompensation in the DSR is used.

Any software reset will re-initialize the timer. The tim- er countdown is also extended by up to 10 ms if the data rate is changed during the timer’s countdown. Without this timer, the FDC would have been put to sleep immediately after FDC is idle. The minimum delay gives software a chance to interact with the FDC without incurring an additional overhead due to recovery time. The command also allows the output pins of the floppy disk drive interface to be tri-stated or left unal- tered during auto powerdown. This is done by the FDI TRI bit. In the default condition (FDI TRI e0) the output pins of the floppy disk drive are tri-stated. Setting this bit leaves the interface unchanged from the normal state. The results phase returns the values programmed for MIN DLY, FDI TRI and AUTO PD. The auto pow- erdown mode is disabled by a hardware reset. Soft- ware results have no effect on the POWERDOWN MODE Command parameters.

8.5.3.14 PART ID Command

This command can be used to identify the floppy disk controller as an enhanced controller. The first stepping of the FDC (all versions) will yield 0x02 in the result phase of this command. Any future en- hancements on these parts will be denoted by the 5 LSBs (0x01 to 0x1F).

8.5.3.15 OPTION Command

The standard IBM format includes an index address field consisting of 80 bytes of GAP 4a, 12 bytes of the sync field, four bytes identifying the IAM and 50 bytes of GAP 1. Under the ISO format most of this preamble is not used. The ISO format allows only 32 bytes of GAP 1 after the index mark. The ISO bit in this command allows the FDC to configure the data transfer commands to recognize this for- mat. The MSBs in this command are reserved for any other enhancements made available to the user in the future.

8.5.3.16 SAVE Command

The first byte corresponds to the values pro- grammed in the DSR with the exception of CLKSEL. The DRATE1, DRATE0 used here are unmapped. The second byte is used for configuring the bits from the OPTION Command. All future enhancements to the OPTION Command will be reflected in this byte as well. The next nine result bytes are explained in the Parameter Abbreviations section after the com- mand summary. The 13th byte is the value associat- ed with the POWERDOWN MODE Command. The disk status is used internally by the FDC. There are two reserved bytes at the end of this command for future use. This command is similar to the DUMPREG Com- mand but it additionally allows the user to read back the precompensation values as well as the pro- grammed data rate. It also allows the user to read the values programmed in the POWERDOWN MODE Command. The precompensation values will be returned as programmed in the DSR register. This command, used in conjunction with the RE- STORE Command, should prove very useful for SMM power management. This command reserves the last two bytes for future enhancements.

8.5.3.17 RESTORE Command

Using the RESTORE Command with the SAVE Command, allows the SMM power management to restore the FDC to its original state after a system powerdown. It also serves as a succinct way to pro- vide most of the initialization requirements normally handled by the system. The sequence of initializing the FDC after a reset occurred and assuming a SAVE Command was issued follows: # Issue the DRIVE SPECIFICATION Command (if the design utilizes this command) # Issue the RESTORE Command (pass the 16 bytes retrieved previously during SAVE) The RESTORE Command programs the data rate and precompensation value via the DSR. It then re- stores the values normally programmed through the CONFIGURE, SPECIFY, and PERPENDICULAR Commands. It also enables the previously selected values for the POWERDOWN Mode Command. The PCN values are set restored to their previous values and the user is responsible for issuing the SEEK and RECALIBRATE Commands to restore the head to the proper location. There are some drives that do not recalibrate in which case the RESTORE Com- mand restores the previous state completely. The PDOSC bit is retrievable using the SAVE Command, however, the system designer must set it correctly. The software must allow at least 20 ms to execute the RESTORE Command. When using the BOOT- SEL bits in the TDR, the user must restore or reini- tialize these bits to their proper values. 159

8.5.3.18 FORMAT AND WRITE Command

H, R, and N but also the data transfer of N bytes. can be done fast and efficiently with this command. to format and copy diskettes.

9.0 IDE INTERFACE

buffered interface is also supported.

9.1 IDE Registers

and is driven by the 82091AA. Table 37. IDE Register Set (Located in IDE Device)

9.2 IDE Interface Operation

primary and secondary I/O locations. Figure 65. IDE Interface Example (without DMA)

Figure 66. IDE Interface Example (with DMA)

10.0 POWER MANAGEMENT

The 82091AA provides power management capabili- ties for its primary functional modules (parallel port, floppy disk controller, serial port A, and serial port B). For each module, the 82091AA implements two types of power managementÐdirect powerdown and auto powerdown. Direct powerdown, enabled via control bits in the 82091AA configuration regis- ters, immediately places the module in a powerdown mode by turning off the clock to the associated mod- ule. Direct powerdown removes the clock regardless of the activity or status of the module. By contrast, when auto powerdown is enabled (via control bits in the 82091AA configuration registers), the associated module only enters a powerdown mode if it is in an idle state. NOTE: The entire 82091AA can be placed in direct powerdown by writing to the CLKOFF bit in the AIPCFG1 Register.

10.1 Power Management Registers

The floppy disk controller, parallel port, serial port A, and serial port B each have two 82091AA configura- tion registers. For each module, three configuration register bits control power managementÐxDPDN, xIDLE, and xAPDN. # xAPDN: auto-powerdown, shuts off the oscillator to the module when the module is idle. # xIDLE: idle status, a read only pin that indicates idle status. # xDPDN: direct powerdown, shuts off module os- cillator when active regardless of module status. The 82091AA exits any powerdown mode after a hardware reset (RSTDRV asserted) or reset via the xRESET bit in the 82091AA configuration registers. Direct powerdown can also be exited by writing the corresponding xPDN bit in the configuration register to 0. Auto powerdown is exited by events at the module (e.g., CPU read/write or module interface activity). NOTE: The configuration registers also contain the xEN bit. This bit is used to completely dis- able an unused module. Enabling a disabled module takes much longer than restoring a module from powerdown. Therefore, this bit is not recommend for temporarily disabling a module as a powerdown scheme.

10.2 Clock Power Management

The internal clock circuitry of the 82091AA can be turned on or off as part of a power management scheme. The clock circuitry is controlled via the CLKOFF bit in the AIPCFG1 Register. If an external clock source exists, the user may want to turn off the internal oscillator to save power and provide mini- mum recovery time. Auto powerdown and direct powerdown (in each module) have no effect on the state of internal oscil- lator.

10.3 FDC Power Management

This section describes the FDC direct and auto pow- erdown modes and recovery from the powerdown modes. Auto Powerdown Automatic powerdown (APDN) has an advantage over direct powerdown (PDN) since the register con- tents are not lost under APDN. Automatic power- down is invoked by either the Auto Powerdown com- mand, or by enabling the FAPDN bit in the FDC con- figuration register. There are four conditions required before the FDC will enter powerdown: 1. The motor enable pins ME [3:0] must be inactive. 2. The FDC must be in an idle state. FDC idle is indicated by MSR e80h and the IRQ6 signal is negated (IRQ6 may be asserted even if MSR e80h due to polling interrupt). 3. The head unload timer (HUT, explained in the SPECIFY Command) must have expired. 4. The auto powerdown timer must have timed out. An internal timer is initiated when the POWER- DOWN MODE Command is executed. The amount of time can be set by the user via the MIN DLY bits in the POWERDOWN MODE Command. The mod- ule is then powered down, provided all the remaining conditions are met. A software reset reinitializes the timer. When using the FDC FAPDN bit to enable the automatic powerdown feature, the MIN DLY bit is set to the default condition. Recovery from Auto Powerdown When the FDC is in auto powerdown, the module is awakened by a reset or access to the DOR, MSR or FIFO registers. The module remains in auto power- down mode after a software reset (i.e., it will power- 163

u 82091AA down again after being idle for the time specified by MIN DLY). However, the FDC does not remain in auto powerdown mode after a hardware reset or DSR reset. Direct Powerdown Direct powerdown is invoked via the Powerdown bit in the Data Rate Select Register (bit 6), or the FDPDN bit in the FCFG2 Register. Setting FDPDN to 1 will powerdown the FDC. All status is lost when this type of powerdown mode is used. The FDC exits powerdown mode after any hardware or software re- set. Direct powerdown overrides automatic power- down. Recovery from Direct Powerdown The FDC exits the direct powerdown state by setting the FDPDN bit to 0 followed by a software or hard- ware reset. After reset, the FDC goes through a normal se- quence. The drive status is initialized. The FIFO mode is set to default mode on a hardware or soft- ware reset if the LOCK Command has not blocked it. Finally, after a delay, the polling interrupt is issued.

10.4 Serial Port Power Management

This section describes the serial port direct and auto powerdown modes and recovery from the power- down modes. Auto Powerdown When auto powerdown is enabled in the SxCFG2 Register (SxAPDN bit is 1), the serial port enters auto powerdown based on monitoring line interface activity. During auto powerdown, the status of the serial port is maintained (the FIFO and registers are not reset). Access to any serial port register is al- lowed during auto powerdown. The transmitter and the receiver enter powerdown individually, depend- ing on certain conditions. When there are no charac- ters to transmit (TEMPTY e1 in the LSR), the trans- mitter clock is shut off placing the transmitter in auto powerdown. In the case of the receiver, when serial input signal is inactive for approximately 5 character times, indicating that no character is being received, the receiver goes into auto powerdown. Recovery from Auto Powerdown The serial port recovers from auto powerdown when either the transmitter or receiver are active. If data is written to the transmitter or data is present at the receiver, the serial port exits from auto powerdown. Direct Powerdown Direct Powerdown is invoked via the SxCFG2 Regis- ter (setting the SxDPDN bit to 1). When in direct powerdown, the clock to the module is shut off. All registers are accessible while in direct powerdown. A host read of the Receiver Buffer Register or a write to the Transmitter Holding Register should not be performed during powerdown. The SINx input should remain static. When direct powerdown is invoked, the transmit and receive sections of the serial port are reset, includ- ing the transmit and receive FIFOs. Thus, to prevent possible data loss when the FIFOs are reset, soft- ware should not invoke direct powerdown until the serial port is in the idle state as indicated by the SxIDLE bit in the SxCFG2 Register. Recovery from Direct Powerdown Recovery from direct powerdown is accomplished by writing the SxDPDN bit in the configuration regis- ter to 0 or by a module reset.

10.5 Parallel Port Power Management

Auto powerdown is enabled via the PAPDN bit in the PCFG2 Register. When enabled, the parallel port enters auto powerdown when the module is in an idle state. If the parallel port FIFO is being used to transfer data, the parallel port is in an idle state when the FIFO is empty. Recovery from Auto Powerdown Recovery from auto powerdown occurs when the FIFO is written or as a result of parallel port interface activity. Direct Powerdown Direct powerdown is invoked via the PCFG2 Regis- ter (setting the PDPDN bit to 1). When PDPDN e1, the clock to the printer state machine is disabled and the state machine goes into an idle state. Recovery from Direct Powerdown Recovery from direct powerdown is accomplished by setting the PDPDN bit to 0 or the PRESET bit to a 1 in the PCFG2 Register. An 82091AA hard reset (RSTDRV asserted) also brings the part out of direct powerdown. 164

11.0 ELECTRICAL

11.1 Absolute Maximum Ratings

Maximum Ratings’’ may cause permanent damage. may affect device reliability.

11.2 DC Characteristics

Table 38. DC Specifications (VCCe5V g10%, T amb e 0§Ct o7 0 §C)

Test Conditions: Only the data bus inputs may float. All outputs are open.
Test Conditions: Tested while reading a sync field of ‘‘00’’. Outputs not connected to DC loads. This specification reflects

the supply current when all modules within the 82091AA are active. ILeVSS,V IHeVCC; Outputs not connected to DC loads.

Test Conditions: Typical value with the oscillator off.
Test Conditions: All 82091AA modules are in their powerdown state.
Test Conditions: 10 mA( V
Test Conditions: 0V kVOHkVCC
Test Conditions: 0.45V kVOHkVCC
Test Conditions: Device in Circuit V CCe0V, V INe5.5V max.

Table 39. Capacitance Specifications (VCCe5V g10%, T ambe0§Ct o7 0 §C) All pins except pins under test are tied to AC ground. The following pin groupings are used in Table 40 and Table 41. Table 40. V OL Specifications (VCCe5V g10%, T ambe0§Ct o7 0 §C)

11.3 Oscillator

Figure 69. Crystal Connections Figure 70. Oscillator Connections

11.4 AC Characteristics

Table 42. AC Specifications (VCCe5V g 10%, T amb e 0§Ct o7 0 §C)

24 MHz

Clock input high level test points for clock high time and clock rise/fall times are 3.5V with V CC at 5V g10% and 2.0V

with V CC at 3.3V V CC g10%. Clock input low level test point for clock low time and clock rise/fall time is 0.8V.

Clock input test point for clock period is 0.8V.
Certain Floppy Disk Controller module timings are a function of the selected data rate. The nominal values for the internal

1 Mbps 125 ns

500 Kbps 250 ns

300 Kbps 420 ns

250 Kbps 500 ns

All information contained in ( ) in the following tables represents 3.3V specifications. Table 43. AC Specifications (VCCe 5V g 10%, or [3.3V g 0.3V] Tambe0§Ct o7 0 §C)

Table 43. AC Specifications (VCCe 5V g 10%, or (3.3V g 0.3V) T ambe0§Ct o7 0 §C) (Continued)

The FDC Status Register’s status bits which are not latched may be updated during a host read operation.
The timing t13b is specified for the FDC interrupt signal in the polling mode only. These timings in case of the result

phase of the read and write commands are microcode dependent.

This timing is for FDC FIFO threshold

subtract 1.5 ms. The value shown is for 1 Mbps, scales linearly with data rate.

This timing is a function of the internal clock period (t1e) and is given as ( )/3) t1e. The values of t1e are shown in Note 3.
If DACK Ý transitions before RD Ý, then this specification is ignored. If there is no transition on DACK Ý, then this be-

comes the DRQ inactive delay.

TC width is defined as the time that both TC and DACK Ý are active. Note that TC and DACK Ý must overlap at least

NOTES: (Continued) 7. Based on the internal clock period (t1e). For various data rates, the read and write data width minimum values are: Disk Drive 24 MHzData Rate

1 Mbps 150 ns

500 Kbps 360 ns

300 Kbps 615 ns

250 Kbps 740 ns

8.This timing is a function of the selected data rate as follows: Disk Drive TimingData Rate 1 Mbps 1.0 ms Min 500 Kbps 2.0 ms Min 300 Kbps 3.3 ms Min 250 Kbps 4.0 ms Min 9. This value can range from 0.5 ms to 8.0 ms and is dependent upon data rate and the Specify Command value. 10. The minimum MFM values for WE Ý to HDSEL Ý change for the various data rates are: Disk Drive Min MFM ValueData Rate 1 Mbps 0.5 ms a [8 c GPL] 500 Kbps 1.0 ms a [16 c GPL] 300 Kbps 1.6 ms a [26.66 c GPL] 250 Kbps 2.0 ms a [32 c GPL] GPL is the size of gap 3 defined in the sixth byte of a Write Command. 11. Based on internal clock period. 12. Jitter tolerance is defined as: (Maximum bit shift from nominal position d (/4 period of nominal data rate) c 100 percent is a measure of the allowable bit jitter that may be present and still be correctly detected. The data separator jitter tolerance is measured under dynamic conditions that jitters the bit stream according to a reverse precompensation algorithm. 13. The minimum reset active period for a software reset is dependent on the data rate, after the FDC module has been properly reset using the t10a spec. The minimum software reset period then becomes: Disk Drive Data Rate Minimum Software Reset Active Period

11.4.1 CLOCK TIMINGS

Figure 71. Clock Timing

11.4.2 HOST TIMINGS

Figure 72. Host Read

Figure 73. Host Write

Figure 76. Reset Timing (Hardware Extended Configuration Mode)

11.4.3 FDC TIMINGS

Figure 77. Write Data Timing Figure 78. FDC Drive Control/Timing

Figure 79. FDC Internal PLL Timing Figure 80. Floppy Disk Controller Interrupts

11.4.4 PARALLEL PORT TIMINGS

Figure 81. Parallel Port Interrupt Timing

11.4.5 IDE TIMINGS

Figure 88. IDE Timing

11.4.6 GAME PORT TIMINGS

Figure 89. Game Port Timing

11.4.7 SERIAL PORT TIMINGS

Figure 90. Serial Port Interrupt Timing Figure 91. Modem Control Timing

12.0 PINOUT AND PACKAGE INFORMATION

12.1 Pin Assignment

Figure 92. 82091AA Pin Diagram

Table 44. Alphabetical 82091AA Pin Assignment

Table 44. Alphabetical 82091AA Pin Assignment (Continued) Table 45. Numerical 82091AA Pin Assignment

1 SA0 I

2 SA1 I

3 SA2 I

4 SA3 I

5 SA4 I

7 SA5 I

8 SA6 I

9 IRQ3 O

10 SA7 I

11 IRQ4 O

12 SA8 I

13 IRQ5 O

14 V SS V

15 SA9 I

16 IRQ6 O

17 SA10 I

18 IRQ7 O

19 IORC Ý I

20 IOWC Ý I

21 AEN I

22 IOCHRDY O

23 NOWS Ý O

24 SD0 I/O

25 SD1 I/O

26 SD2 I/O

27 SD3 I/O

28 V SS V

29 SD4 I/O

30 SD5 I/O

Table 45. Numerical 82091AA Pin Assignment (Continued)

31 SD6 I/O

32 SD7 I/O

33 RSTDRV I

34 V CC V

35 DCDA Ý O

36 DSRA Ý I

37 SINA I

38 RTSA Ý I/O

39 SOUTA I/O

40 CTSA Ý I

41 DTRA Ý I/O

42 RIA Ý I

43 DCDB Ý O

44 DSRB Ý I

45 SINB I

46 RTSB Ý I/O

47 SOUTB I/O

48 CTSB Ý I

49 DTRB Ý I/O

50 RIB Ý I

51 SELECT I

52 PERROR I

53 BUSY I

54 ACK Ý I

55 PD7 I/O

56 PD6 I/O

57 PD5 I/O

58 PD4 I/O

59 V CCF V

60 PD3 I/O

61 SELECTIN Ý O

62 V SS V

63 X1/OSC I

64 X2 I

65 PD2 I/O

66 INIT Ý O

67 PD1 I/O

68 FAULT Ý I

69 PD0 I/O

70 AUTOFD Ý O

71 STROBE Ý O

72 PPDIR/GCS Ý I/O

73 V CCF V

74 DSKCHG Ý I

75 HDSEL O

76 RDDATA Ý I

77 WP Ý I

78 TRK0 Ý I

79 WE Ý O

80 WRDATA Ý O

81 STEP Ý O

82 DIR Ý O

83 FDME1 Ý/DSENÝ O

84 FDS0 Ý/MDS0 O

85 FDS1 Ý/MDS1 O

86 FDME0 Ý/MEENÝ O

87 INDX Ý I

88 V SS V

89 DRVDEN0 O

90 DRVDEN1 O

91 IDECS1 Ý I/O

92 IDECS0 Ý I/O

93 V CC I/O

94 HEN Ý V

95 DEN Ý I/O

96 IO16 Ý I

97 FDDACK Ý I

98 FDDREQ O

99 PPDACK Ý I

100 PPDREQ O

12.2 Package Characteristics

Figure 93. 100-Pin Quad Flat Pack (QFP) Dimensions

Minimum Nominal Maximum Notes A 3.15 A1 0.0 B 0.20 0.30 0.40 C 0.10 0.15 0.20 D 17.5 17.9 18.3 D1 14.0 E 23.5 23.9 24.3 E1 20.0 e1 0.53 0.65 0.77 L1 0.60 0.80 1.00 N 100 Rectangle T 0.00 10.0 Y 0.10 ISSUE JEDEC 191

13.0 DATA SEPARATOR CHARACTERISTICS FOR FLOPPY DISK MODE

Figure 94. Typical Jitter Tolerance vs Data Rate (Capture Range 250 Kbps) Figure 95. Typical Jitter Tolerance vs Data Rate (Capture Range 300 Kbps)

13.1 Write Data Timing

290486–98 NOTE: Invert high.

13.2 Drive Control

290486–99 NOTE: For overlapped seeks, only one step pulse per drive selection is issued. Non-overlapped seeks will issue all programmed step pulses. Invert high. 194

13.3 Internal PLL

290486–A0 NOTE: Invert high. 195

Section 8.0 of this document completely describes the FDC when the module is configured for two drive support. In addition, the FDC commands in Section 8.0 provide four drive support information. This appendix provides additional information concerning four drive support. The signal pins that are affected by four drive support are described in Section A.1. Note that the FDC signals not discussed in this appendix operate the same for both two and four drive systems. The following registers are described in this appendix; Digital Output Register (DOR), Enhanced Tape Drive Register (TDR), and the Main Status Register (MSR). Some bits in these registers operate differently in a four drive configuration than a two drive configuration. NOTES: # The descriptions in this appendix assume that four floppy drive support has been selected by setting FDDQTY to 1 in the AIPCFG1 Register. # Only drive 0 or drive 1 can be selected as the boot drive. A.1 Floppy Disk Controller Interface Signals These signal descriptions are for a four drive system (FDDQTY e1 in the AIPCFG1 Register). See Section 2.0 for two drive system signal descriptions. Signal Name Type Description FDME1Ý/DSENÝ(1) O FLOPPY DRIVE MOTOR ENABLE 1, or DRIVE SELECT ENABLE: In a four drive system, this signal functions as a drive select enable (DSEN Ý). When DSEN Ý is asserted, MDS1 and MDS0 reflect the selection of the drive. FDS1Ý/MDS1(1) O FLOPPY DRIVE SELECT1, or MOTOR DRIVE SELECT 1: In a four drive system, this signal functions as a motor drive select (MDS1). MDS1, together with MDS0, indicate which of the four drives is selected, as shown in note 1. FDME0Ý/MEENÝ(1) O FLOPPY DRIVE MOTOR ENABLE 0 or MOTOR ENABLE ENABLE: In a four drive system, this signal functions as a motor enable enable (MEEN Ý). MEEN Ý is asserted to enable the external decoding of MDS1 and MDS0 for the appropriate motor enable (see note 1). FDS0Ý/MDS0(1) O FLOPPY DRIVE SELECT 0 or MOTOR DRIVE SELECT 0: In a four drive system, this signal functions as motor drive select (MDS0). MDS0, together with MDS1, indicate which of the four drives is selected as shown in note 1. NOTE: 1. These signal pins are used to control an external decoder for four floppy disk drives as shown below. Refer to the DOR Register Description in Section A.2 for details. MDS1 MDS0 DSEN Ýe0 MEEN Ýe0 0 0 Drive 0 ME0 0 1 Drive 1 ME1 1 0 Drive 2 ME2 1 1 Drive 3 ME3 A-1

Ý and Drive Select bits are unchanged. Figure 98. Digital Output Register

7 Motor Enable 3 (ME3): This bit controls a motor drive enable output signal and provides the signal

output for the floppy drive 3 motor (via external decoding) as shown in Table 46.

6 Motor Enable 2 (ME2): This bit controls a motor drive enable output signal and provides the signal

output for the floppy drive 2 motor (via external decoding) as shown in Table 46.

5 Motor Enable 1 (ME1): This bit controls a motor drive enable signal and provides the signal output

for the floppy drive 1 motor (via external decoding) as shown in Table 46.

4 Motor Enable 0 (ME0): This bit controls a motor drive enable signal and provides the signal output

for the floppy drive 0 motor (via external decoding) as shown in Table 46. 3 DMA Gate (DMAGATE): This bit enables/disables DMA for the FDC. When DMAGATE e1, DMA for the FDC is enabled. In this mode FDDREQ, TC, IRQ6, and FDDACK Ý are enabled. When DMAGATEe0, DMA for the FDC is disabled. In this mode, the IRQ6 and DRQ outputs are tri-stated and the DACK Ý and TC inputs are disabled to the FDC. Note that the TC input is only disabled to the FDC module. Other functional units in the 82091AA (e.g., parallel port or IDE interface) can still use the TC input signal for DMA activities. 2 FDC Reset (DORRST): DORRST is a software reset for the FDC module. When DORRST is set to 0, the basic core of the 82091AA’s FDC and the FIFO circuits are cleared conditioned by the LOCK bit in the Configure Command. This bit is set to 0 by software or a hard reset (RSTDRV asserted). The FDC remains in a reset state until software sets this bit to 1. This bit does not affect the DSR, CCR and other bits of the DOR. DORRST must be held active for at least 0.5 ms at 250 Kbps. This is less than a typical ISA I/O cycle time. Thus, in most systems consecutive writes to this register to toggle this bit allows sufficient time to reset the FDC. 1:0 Drive Select (DS [1:0]): This field provides the output signals to select a particular floppy drive (via external decoding) as shown in Table 47. Note that the drive motor can be enabled separately without selecting the drive. This permits the motor to come up to speed before selecting the drive. Note also that only one drive can be selected at a time. However, the drive should not be selected without enabling the appropriate drive motor via bits [7:4] of this register. A-3

Table 46. Output Pin Status for Four Disk Drives while the drive remains de-selected, ME0 is set to 1 and DS [1:0] is set to 01, 10, or 11.

Figure 99. Example External Decoder (Four Drive System) wise the bits are tri-stated.

Figure 100. Enhanced Tape Drive Register

2 Boot Drive Select (BOOTSEL): The BOOTSEL bit is used to remap the drive selects and motor

Only drive 0 or drive 1 can be selected as the boot drive.

each byte is transferred to or from the FIFO. register value is 00h until the oscillator circuit has stabilized and the internal registers have been initialized. to report 80h (i.e., RQM is set to 1) is 2.5 ms after a hard or soft reset. # MSRe80H; The controller is ready to receive a command. # MSRe90H; Executing a command or waiting for the host to read status bytes (assume DMA mode). # MSReD0H; Waiting for the host to write status bytes. Figure 101. Main Status Register

7 Request For Master (RQM): When RQM e1, the FDC is ready to send/receive data through the

FIFO (FDCFIFO Register). The FDC sets this bit to 0 after a byte transfer and then sets the bit to 1 when it is ready for the next byte. During non-DMA execution phase, RQM indicates the status of IRQ6. 6 Direction I/O (DIO): When RQM e1, DIO indicates the direction of a data transfer. When DIO e1, the FDC is requesting a read of the FDCFIFO. When DIO e0, the FDC is requesting a write to the FDCFIFO. 5 NON-DMA (NONDMA): Non-DMA mode is selected via the SPECIFY Command. In this mode, the FDC sets this bit t o a 1 during the execution phase of a command. This bit is for polled data transfers and helps differentiate between the data transfer phase and the reading of result bytes. 4 Command Busy (CMDBUSY): CMDBUSY indicates when a command is in progress. When the first byte of the command phase is written, the FDC sets this bit to 1. CMDBUSY is set to 0 after the last byte of the result phase is read. If there is no result phase (e.g., SEEK or RECALIBRATE Commands), CMDBUSY is set to 0 after the last command byte is written.

3 Drive 3 Busy (DRV1BUSY): The FDC module sets this bit to 1 after the last byte of the command

phase of a SEEK or RECALIBRATE Command is issued for drive 3. This bit is set to 0 after the host reads the first byte in the result phase of the SENSE INTERRUPT Command for this drive.

2 Drive 2 Busy (DRV1BUSY): The FDC module sets this bit to 1 after the last byte of the command

phase of a SEEK or RECALIBRATE Command is issued for drive 2. This bit is set to 0 after the host reads the first byte in the result phase of the SENSE INTERRUPT Command for this drive. phase of a SEEK or RECALIBRATE Command is issued for drive 1. This bit is set to 0 after the host reads the first byte in the result phase of the SENSE INTERRUPT Command for this drive. phase of a SEEK or RECALIBRATE Command is issued for drive 0. This bit is set to 0 after the host reads the first byte in the result phase of the SENSE INTERRUPT Command for this drive. A-8

Product Information

82091AA specifications and overview.

Summary

ADVANCED INTEGRATED PERIPHERAL (AIP)

Description

ADVANCED INTEGRATED PERIPHERAL (AIP)

Source title 82091AA Datasheet(PDF) - Intel Corporation

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