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CHMOS Ill technology for decreased power consumption and increased reliability. Figure 1. Block Diagram

2.26 Order Number 250137-004

cuk/xt 9 21 avec ooTyx2cys 895° oy vce. Figure 2. PLCC Pinout Figure 3. DIP Pinout

82050 PINOUT DEFINITION

reset | 17 | |_| RESET: Ahigh on this input pin resets the 82050. address bus to select one of the internal registers for read or write. 25-28 allow transfer of bytes between the CPU and the 82050. the interrupt by reading the 82050 status registers. hardware reset. For more details refer to the system clock generation.

intel. 82050

82050 PINOUT DEFINITION (Continued)

Comme || | wenn TxD TRANSMIT DATA: Sorial data is transmitted via this output pin starting at the least significant bit. RECEIVE DATA: Serial data is received on this input pin starting at the least significant bit. RING INDICATION: RI - Ring indicator—input, active low. This is a general purpose input accessible by the CPU. BTR DTR—DATA TERMINAL READY: Output, active low. This is a general purpose output pin controlled by the CPU. During hardware reset, this pin is an input used to determine the system clock mode. (See System Clock Generation.) DSR vo DSR—DATA SET READY: Input, active low. This is a general purpose input pin accessible by the CPU. RTS—REQUEST TO SEND: Output, active low. This is a general purpose output pin controlled by the CPU. During hardware reset, this pin is an input used to determine the system clock mode. (See system clock generation) CTs CLEAR TO SEND: input active low. This is a general purpose input pin accessible by the CPU, vo DCD—DATA CARRIER DETECTED: Input, active low. This is a general purpose input pin accessible by the CPU. | vec | 21 | P| voc: Device power supply. Lvss [7 [ P| vssicouna SYSTEM INTERFACE CRYSTAL OSCILLATOR The 82050 has a simple demultiplexed bus interface which consists of a bidirectional, three-state, 8-bit rn data bus and a 3-bit address bus. The Reset, Chip L£ = | Select, Read, and Write pins, along with the Interrupt d pin, provide the remaining signals necessary to inter- = seoraya face to the CPU. The 82050's system clock can be . - generated externally and provided through the CLK feu Grystal Frog, Mex = 16.482 Miz pin; or its on-chip crystal oscillator can be used by attaching a crystal to the X1 and X2 pins. For com- Figure 4. Crystal Oscillator patibility with IBM PC software, a system clock of 18.432 MHz (with divide by two enabled) is recom- —_—_x2 pins. The oscillator frequency is divided by two mended. The 82050, along with a transceiver, ad- —_ before being inputted into the chip circuitry. If an dress decoder, and a crystal, complete the interface 18.432 MHz crystal is used, then the actual system to the IBM PC Bus. clock frequency of the 82050 will be 9.216 MHz. This_mode is configured via a strapping option on the RTS pin. SYSTEM CLOCK OPTIONS It is very important to distinguish between the clock The 82050 has two modes of system clock opera- frequency being supplied ‘to the 82050 and the tion. It can accept an externally generated clock, or system clock frequency. The term system clock re- use a crystal to internally generate its system clock fers to the clock frequency being supplied to the by using the on-chip oscillator. 82050 circuitry (divided or undivided). The following oo - examples delineate the three options for clock us- The 82050 has an on-chip oscillator which can be ag and their effect on the 62050 system clock as used to generate its system clock. The oscillator will well as on the BRG source frequency: take the input from a crystal attached to the X1 and 2-28

Figure 8. interrupt Structure

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intel. 82050 TRANSMIT DATA REGISTER (TXD) BRG DIVISOR LOW BYTE (BAL) This register holds the next data byte to be transmit- This register contains the least significant byte of the ted. When the transmit shift register becomes emp- Baud Rate Generator’s 16-bit divisor. This register is ty, the contents of the Transmit Data Register are accessible only when the DLAB bit is set in the LCR loaded into the shift register and the Transmit Data register. Register Empty condition becomes true. BOBOEEno BOBDBaRoO o7 to o7 do ps 1 D6 oO os D2 oS b2 De Ds D4 os 290137-10 290137-8 'BAL—BAG Divisor Low Byte ‘TXD—Transmit Data Register BRG DIVISOR HIGH BYTE (BAH) RECEIVE DATA REGISTER (RXD) ; ; ; This register contains the most significant byte of This register holds the last character received by the the Baud Rate Generator’s 16-bit divisor. This regis- RX Machine. The character is right justified and the ter is accessible ony when the DLAB bit is set in the leading bits are zeroed. Reading the register emp- LCR register. ties the register and resets the Received Character Available condition. Pe[sT+Es[2T fo] 07 ‘DO CE ETEEEE ” 7 vo os b2 06 oF pa ps 05 02 (290197-15 D4 Ds BAH—BRG Divisor High Byte 200197-8 RXD~Receive Data Register 2-32

intel. 82050 INTERRUPT ENABLE REGISTER (IER) This register enables four types of interrupts which independently activate the INT pin. Each of the four interrupt types can be disabled by resetting the appropriate bit of the IER register. Similarly by setting the appropriate bits, selected interrupts can be enabled. If all interrupts are disabled, then the interrupt requests are inhibited from the IIR register and the INT pin. All other functions, including Status Register and the Line Status Register bits continue to operate normally. RXDA= RX DATA INTERRUPT ENABLE RESERVED TXDE~ TXDATA EMPTY ENABLE RXIE~ RX INTERRUPT ENABLE MIE = MODEM INTERRUPT ENABLE 290137-12 IER—Interrupt Enable Register MIE—MODEM Interrupt Enable 2 RXIE—RX Machine Interrupt Enable TXDE—TX Data Register Empty RXDA—RX Data Available INTERRUPT IDENTIFICATION REGISTER (IIR) This register holds the highest priority enabled and active interrupt request. The source of the interrupt request can be identified by reading bits 2-1. BOBOEaaoO IPN~ INTERRUPT PENDING 80} active RESERVED = INTERRUPT RESERVED 200197-19 R—interrupt identification Register B1, BO—Interrupt Bits, 2-1. These two bits reflect the highest priority, enabled and pending interrupt request. 11: RX Error Condition (Highest Priority) 10: RX Character Available 01: TXD Register Empty 00: Modem Interrupt (Lowest Priority) {PN—interrupt Pending—This bit is active low, and indicates that there is an interrupt pending. The interrupt logic asserts the INT pin as soon as this bit goes active (NOTE: the IIR register is continuously updated; so while the user is serving one interrupt source, a new interrupt with higher priority may enter IIR and replace the older interrupt vector). 2-33

intel. 82050 LINE CONTROL REGISTER (LCR) This is a read/write register which defines the basic configuration of the serial link. Pists[«Ts{2{ Jo} LAB CLO | CHARACTER SBK~ SET BACK cus | LENGTH PM2 ‘SBLO- STOP BIT LENGTH PARITY | PMT pmo : 200137-14 LCR-Line Configure Register DLAB—Divisor Latch Access Bit—This bit, when set, allows access to the Divisor Count Registers BAL and BAH. SBK—Set Break—This will force the TXD pin low. The TXD pin will remain low until this bit is reset. PM2—PM0—Parity Mode Bits—These three bits are used to select the various parity modes of the 82050. °O x x No Parity 1 0 0 Odd Parity 1 0 1 Even Parity 1 1 0 High Parity 1 1 1 Low Parity SBL—Stop Bit Length—This bit defines the Stop Bit lengths for transmission. The RX Machine can identity 3/4 stop bit or more. [ sBL | Character Length | Stop Bit Length 0 x 1 1 5-Bit 11/2 1 (6, 7, or 8-Bit) 2 CLO—CL1—Character Length—These bits define the character length used on the serial link.

5 Bits

6 Bits

7 Bits

8 Bits

intel. 82050 oe LINE STATUS REGISTER (LSR) This register holds the status of the serial link. When read, all bits of the register are reset to zero. UTeTsT+TsT2T Jo) nesenveo XDA RX DATA AVAILABLE TXST= TX MACHINE STATUS OE OVERRUN ERROR TXDE = TXD EMPTY PE@ PARITY ERROR: BKD = BREAK DETECTED FE~ FRAMING ERROR mors7-18 LSR—Line Status Register RXDA—RX Data Available—This bit, indicates that the RXD register has data available for the CPU to read. OE—Overrun Error—Iindicates that a received character was lost because the RXD register was not empty. PE Parity Error—indicates that a received character had a parity error. FE—Framing Error—indicates that a received character had a framing error. BkD—Break Detected—This bit indicates that a break condition was detected, i.e., RxD input was held low for two character times. TXDE—TXD Empty—This indicates that the 82050 is ready to accept a new character for transmission. In addition, this bit causes an interrupt request to be generated if the TXD register Empty interrupt is enabled. TXST—TX Machine Status—When set, this bit indicates that the TX Machine is Empty, i.e., both the TXD register and the TX Shift Register are empty. MODEM CONTROL REGISTER (MCR) This register controls the modem output pins. All the outputs invert the data, i.e., their output will be the complement of the data written into this register. BORDER OTR neseRveD as RESERVED uc ouT2 seo197-18 MonHodem Cont Regater 2-35

intel. 82050 LC—Loopback Control—This bit puts the 82050 into a Local Loopback mode. OUT2—OUT2 Output—This bit controls the OUT2 pin. The output signal is the complement of this bit. NOTE: This bit is only effective when the 82050 is being used with an externally generated clock. RTS—RTS Output Bit—This bit controls the RTS pin. The output signal is the complement of this bit. DTR—DTR Output Bit—This bit controls the DTR pin. The output signal is the complement of this bit. MODEM STATUS REGISTER (MSR) This register holds the status of the modem input pins (CTS, DCD, DSR, Ril). It is the source of Modem interrupts (bits 3-0) when enabled in the IER register. If any of the above input pins change levels, then the appropriate bit in MSR is set. Reading MSR will clear the status bits. BOBO COMPLEMENT OCD STATE CHANGE CTS COMPLEMENT Ri STATE CHANGE DSR ‘COMPLEMENT OSR (==>) Ri COMPLEMENT CTS STATE CHANGE DCD 290137-17 MSR—Mode Status Register DCDC—DCD Complement—Holds the complement of the DCD pin. DRIC—RI Complement—Holds the complement of the Ail pin. DSRC—DSR Complement—Holds the complement of the DSR pin. CTSC—CTS Complement—Holds the complement of the CTS pin. DDCD—Delta DCD—indicates that the DCD pin has changed state since this register was last read. DRI—Delta Rl—Indicates that the Ri pin has changed state from high to low since this register was last read. DDSR—Delta DSR—Indicates that the DSR pin has changed state since this register was last read. DCTS—Delta CTS—indicates that the CTS pin has changed state since this register was last read. SCRATCHPAD REGISTER (SCR) The 8-bit Read/Write register does not control the ACC. It is intended as a scratch pad register for use by the programmer. 2-36

intel. 82050 SSS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Voltage on any Pin (wrt. Vgg . -0.5V to Voc + 0.5V D.C. CHARACTERISTICS (T, = 0° TO 70°C, Voc = 5V + 10%) input Low Voltage | wm [os [oe Tv +05 Output Low Voltage @o | | oa Tv | Output high votage [| @y | 24 |Tv | ImputLeakageCurent |) | Tet Tn S-StateLeakage Curent | 6) | | eto [na |_tonn | inputtightorota.ATS [wo [Toe [ma InputowtorDTRLATS | (i) | nT ma X1, X2 Load a lec Power Supply Current mA/MHz mA (max) Input Capacitance po ff to Pe VO Capacitance fom [foe 4. Xe Load re ee NOTES: 1. Does not apply to CLK/X1 pin, when configured as crystal oscillator input (X1). 2.@ ly = 2mA. 3. @ lon = —0.4 mA. 4.0 < Vin < Voc. 5. 0.45V < Vout < (Voc — 0.45). 7. Viq = 2.4V on RB and RXD pins. 8. Freq = 1 MHz. 9. Does not apply OUT2/X2 pin, when configured as crystal oscillator output (X2). 10. Input current for DTA, RTS pins during Reset for Clock Mode Configuration. 2-37

intel. 82050 A.C. SPECIFICATIONS SYSTEM CLOCK SPECIFICATIONS Testing Conditions: [_symboi | Parameter [Min] Max [Notes] * All AC output parameters are under output load —_| DIVIDE BY TWO OPTION—ACTIVE of 20 to 100 pF, unless otherwise specified. Toy/2 CLK Period [54] 250 | (2) | * AC testing inputs are driven at 2.4 for logic ‘1’, and 0.45V for logic ‘0’. Output timing measure- TCLCH | CLK Low Time [asf || ments are made at 1.5V for both a logical ‘0’ and TCHCL | CLK High Time [e{ | | * In the following tables, the units are ns, unless | TCH1CH2| CLK Rise Time [ [to | w | otherwise specified. Tovacit |cukFatime | | 10 | (1) | FXTAL _ | External Crystal 18.492 System Interface Specification—System Clock Frequency Rating MHz Specification: DIVIDE BY TWO OPTION—INACTIVE The 82050 system clock is supplied via the CLK pin Frey [oLK Period __| or generated by on-chip crystal oscillator. The clock | 1° CLK Period jroo] | is optionally divided by two. The CLK parameters are CiktowTime |s4{ | | given separately for intrmal dvide-bytwo option Frcicy [eK High Time | 44 | ACTIVE and INACTIVE. Tonot [eLkHightime | 44] 250 | | TCHICH2|CLKRise Time | | 15 | (1) | The system clock attr dison by two, if active) — Fe ci fouk airtime [18 [a | must be at least 16X the Tx or Ax baud rate (the [TCL2CL1 | CLK Fall Time 15 faster of the two). noTes: 1. Rise/fall times are measured between 0.8 and 2.0V. 2. Tey in ACTIVE divide by two option is TWICE the input clock period. RESET SPECIFICATION TRSHL Reset Width—CLK/X1 ConfiguredtocLk | Bt | «| t)_—i TTLRSL ATS/DTALOW Setup toResetinactve | GT | «| _—@)_—i ATS/DTR Low Holdafter Reset inactive | 0 | Toy - 20 RESET TRSHL TTLRSL. TRSLTX: OTR/ATS \\ y 290197-18 NOTES: 1. In case of CLK/X1 configured as X1, additional time is required to guarantee crystal oscillator wake-up. 2. RTS/OTR are internally driven HIGH during RESET active time. The pin should be either left OPEN or externally driven LOW during RESET according to the required configuration of the system clock. These parameters specity the timing requirements on these pins, in case they are externally driven LOW during RESET. The maximum spec on TRSLTX requires that the RTS/DTR pins not be forced later than TRSLTX maximum. 2-38

Product Information

82050 specifications and overview.

Summary

ASYNCHRONOUS COMMUICATIONS CONTROLLER

Description

ASYNCHRONOUS COMMUICATIONS CONTROLLER

Source title 82050 Datasheet(PDF) - Intel Corporation

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