8203

8203 INTEL | Alldatasheet

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@ Provides Address Multiplexing and 8203-1 and the 8203-3. Figure 1. 8203 Block Diagram

24 Orcier Number: 210444-006

Table 1. Pin Descriptions AH7 Mode. (Not available in 64K mode.) See Figure 5. inactive before cycle completion. [wa [a1 [1 | Memory waire REQUEST. mode selected by OP, (pin 25). ALE Read mode, selected by OP, (pin 25). Column Address into the Dynamic RAM array. out, operates as OUT? and pin 26 operates as the By bank select input. be used to latch valid data from the RAM array.

Table 1. Pin Descriptions (Continued) mode for the 8203-1 and the 8203-3 only). 23-26 change function based on the mode of operation. The 8203 provides a complete dynamic RAM con- CPU handshake signals SACK and K. The 8203 has two modes, one for 16K dynamic S1 to be used in place of the RD input. RAMs and one for 64Ks, controlled by pin 35. can also be generated via the REFRQ input. mm, Pending completion of a cycle in progress. Figure 3. Crystal Operation for open), the 8203 has two Bank Select inputs to se- dynamic RAMs can be used with external logic.

Figure 7. Hidden Refresh

3 Eternal (icon) areeh caused by the external refresh request, and the in-

(pin 34). External refresh control is not available ‘on pin 25. lion fet status to generate an external refresh re- mimi he it is . 8203 can complete the refresh cycle before the next as the cycle start reference. memory request is generated.

If a Read cycle is requested while a refresh cycle is designed to have a system error rate less than 1 in progress, then the 8203 will set the internal memory cycle every three years based on the full delayed-SACK latch. When the Read cycle is even- operating range of the 8203. tually started, the 8203 will delay the active SACK transition until XACK goes active, as shown in the A microprocessor system is concerned when the compensate for the CPU’s READY setup and hold order to calculate memory read access times, the times. The delayed-SACK latch is cleared after ev- dynamic RAM’s AS Specifications must be exam- ery READ cycle. ined, especially the access time (trac) and the CAS-access time (tcc). Most configurations will be Based on system requirements, either SACK or CAS-access limited; i.e., the data from the RAM will XACK can be used to generate the CPU READY be stable tec, max (8203) + tcac (RAM) after a mem- signal. XACK will normally be used; if the CPU can ory read cycie is started. Be sure to add any delays tolerate an advanced READY, then SACK can be (due to buffers, data latches, etc.) to calculate the used, but only if the CPU can tolerate the amount of overall read access time. advance provided by SACK, If SACK arrives too ear- ly to provide the appropriate number of WAIT states, Since the 8203 normally performs ‘“‘early-write” cy- then either XACK or a delayed form of SACK should cles, the data must be stable at the RAM data inputs be used. by the time CAS goes active, including the RAM's data setup time. If the system does not normally guarantee sufficient write data setup, you must _ei- Write Cycles ther delay the WR input signal or delay the 8203 WE. Write cycles are similar to Normal Read cycles, ex- cept for the WE output. WE is held inactive for Read Delaying the WA input wilt delay all 8203 timing, in- cycles, but goes active for Write cycles. All 8203 cluding the READY handshake signals, SACK and Write cycles are “early-write” cycles; WE goes ac- XACK, which may increase the number of WAIT tive before CAS goes active by an amount of time _ states generated by the CPU. sufficient to keep the dynamic RAM output buffers turned off. © \\ Sf General System Considerations i mo ; All memory requests (Normal Reads, Advanced y Reads, Writes) are qualified by the PCS input. PCS omn——{7 we — should be stable, either active or inactive, prior to fn ! the leading edge of RD, WR, or ALE Systoms which i use battery backup should pullup to prevent os VN if erroneous memory requests. u 1 teac t In order to minimize propagation delay, the 8203 ' " uses an inverting address multiptexer without latch- oS \\ 1 f es. The system must provide adequate address set- + up and hold times to guarantee RAS and CAS setup 210444-6 and hold times for the RAM. The tap A.C. parameter should be used for this system calculation. Figure 9. Read Access Time “Bei F - If the WE output is externally delayed beyond the That Hay ae pat lalched. Brand Be choad net'ea CAS activa transition, then the FAM will use the fall changed durin cle. si i ing edge of WE to strobe the write data into the 1g a memory cycle, since they directly RAM, This WE control which RAS output is activated. M. This WE ‘ransition should not occur too late during the CAS active transition, or else the WE to The 8203 uses a two-stage synchronizer for the CAS requirements of the RAM will not be met. memory request inputs (RD, WR, ALE), and a sepa- BEE rate two stage synchronizer for the external refresh The RASo-a, CAS, OUTo.7, and WE outputs con- input (REFRQ). As with any synchronizer, there is ‘ain on-chip series damping resistors (typically 200) always a finite probability of metastable states in- ‘© Minimize overshoot. ducing system errors. The 8203 synchronizer was

Noise immunity may be improved for these RAMs by RAMs do not require pull-up resistors. Figure 10. Typical 8088 System

Figure 11. 8086/256K Byte System

ABSOLUTE MAXIMUM RATINGS* *Notice: Stresses above those listed under “Abso- Jute Maximum Ratings” may cause permanent dam- Voltage On Any Pin other conditions above those indicated in the opera- noon posure to absolute maximum rating conditions for D.C. CHARACTERISTICS Ta = 0°C to 70°C; Voc = 5.0V +10% (5.0V +5% for 8203-3); GND = OV [ sympor [Parameter | in | Max [Unite [ TestConaitions | Input Clamp Voltage | =10 [ov [p= -sma | tco | PowersupplyCurent [| 200 | ma | te Forward Input Current CLK, 64K/16K Mode Seiect mA Ve = 0.45V All Other Inputs(3) BA Ve = 0.45V | ta__| Reverseinputcurent® [40 | wa [Va = Voth Voi Output Low Voltage SACK, XACK 0.45 v lol = 5mA All Other Outputs. 0.45 v lo. = 3mA Vou Output High Voltage Vit = 0.65V SACK, XACK v lon = —1mA All Other Outputs. Vv lon = —1mA Input Low Vottage [| foe fv | Voc = sove Input High Voltage [20 | voc | v [| voc=sov | ae a Cin Input Capacitance F = 1MHz(6) Veias = 2.5V, Voc = 5V NOTES: 1. Ip = 200 pA for pin 37 (CLK). 2. For test mode FO 8 WA must be held at GND. 3. Except for pin 36 in XTAL mode. 4, 8203-1 and 6203-3 support both OP; and OP2, 8203 only supports OP. +12 Vort SAK Ed - | Resistor Tolerance: + 5% 210444-3 5. Ip = 180 pA for pin 35 (Mode Select 16K/64K). 6. Sampled not 100% tested, Ta = 25°C. 2-9

A.C. CHARACTERISTICS H) = 0°C to 70°C; Veco = 5V colt HAS +5% for oR} GND =0V | jeasurements made with respect to —-RAS3, CAS, WE, OUT -OUT¢ are at 2.4V and 0.8V. Ail other pins are measured at 1.5V. All times are in ns. [_Sympot | Parameter | in Tax | Notes | [tw | CockPeog | Tc [tow | ExtemalGiockHightime | zo TT | to. | External Clock Low Time—Above(>y2omHe | tz | | [to | _Extemalclock Low Time—Below(<)zomHz [| 20 | || | tac | _Memorycycietime | tot 90 | tate || [_trer | Retresh Time (128eyotesy |i | aati || | tap | FASPrechargoTime | tego TT | usa | AddressSeuptoRAS | te 90 fT |_taan | AddrossHoidFromRAS | tet | Ts [twos | Wesewpotas | temo fT | twon | WEHoatercAS | Ste 85 | Tk | tes | RO.WRALE,REFRO Delay FromAAS | stp | | | wip | FOWRsewtoAAS | Ts [aus | REFROSeupoRB.WH——SS«d Sa SSC*dC [seue | REFROSeuptoRAS —————SS~dC a Cd | tos | PCSSowptoROwAae = ||| Pe Stseupome ds Pu | stHeremae Sw [ica | FO, WA, ALE WAREOeay ——SC~*d~Cw | TO | [tcc | FO. WR. ALE CAS Oey =i as | aes | 2 [isc | cwoseupioGox Sid was | FO. Wriseupionerna ———«+dP Ss | CC [tx | GAStoXACK Dey te 8 | ete || er | tox | SACK RACK Tun-orrotey | Ts [ca | Ow insciveHolsater SAKE | wef CdS 2-10

A.C. CHARACTERISTICS (Continued) Ty = 0°C to 70°C; Voc = 5V +10% (5.0V_ +5% for 8203-3); GND = OV Measurements made with respect to -RAS3, CAS, WE, ‘0-OUTg are at 2.4V and 0.8V. All other pins are measured at 1.5V. All times are in ns. feFRaPusowath [20 | CMD Hold Time [oP | teen | REFRQIORASDowy [| tip + 00 |} | ww | WR to WE Delay poo | so | «6 | [wo | cPuaddressbeay [oo | wo NOTES: 1. tsc is a reference point only. ALE, RD, WA, and REFROQ inputs do not have to be externally synchronized to 8203 clock. 2. If tag min and tps min are met then toa, tor, and tog are valid, otherwise tcg is valid. 3. tasp, tRaH, tasc, GAH, and tagy depend upon By-By and CPU address remaining stable throughout the memory cycle. The address inputs are not latched by the 8203. 4, For back-to-back refresh cycles, tac max = 13 tp. 5. tac max is valid only if tap min is met (READ, WRITE followed by REFRESH) or typ min is met (REFRESH followed by READ, WRITE). 6. taFR is valid only if tag min and tay min are met. 7. ty min applies ‘when RO, WR has already gone high. Otherwise XACK follows AD, WA. a We goes high according to "wor or yw, whichever occurs first. 9. ta applies only when in normal SACK mode. 10. tcs applies only when in delayed SACK mode. 11. tos must be met only to ensure a SACK active pulse when in delayed SACK mode. XACK will always be activated for at least txw (tp — 25 ns). Violating toys min does not otherwise affect device operation. WAVEFORMS Normal Read or Write Cycle wa ins, . | us mi ASS sen, ‘Ken: FAK tex. toa tes w 210444-9 2-11

WAVEFORMS (Continued) Advanced Read Mode Sy f i tal ta me tas 7 | | os | ‘gg {ss tack, ol eon —o} XK ACA’ 210444-10 Memory Compatibility Timing sio-ANe as i 210444-11 242

a WAVEFORMS (Continued) Write Cycle Timing wr ” =e, a b&- LF ™ fo sts wes. won ms mi Ki 210444-12 Read or Write Followed By External Refresh WO, WR wr w — s mS os s i . 21044413 213

WAVEFORMS (Continued) External Refresh Followed By Read or Write 1.0% |+— wus —e| = rerna he es | oR we ms we oe \\ 210444-14 Clock and System Timing en | cd wes: ‘96: WD. Wi we as oe 210444=15 2-14

Table 2. 8203 Output Loading. All specifications The typical rising and falling charactorste curves for FAS,-RASs Cr = 60 pF ‘on system capacitive load. TAS C, = 320 pF 64K Dynamic RAMs configured in 2 banks. .. RAS load = 80 pF + board capacitance. oevice CAS load = 160 pF + board capacitance. 210444-16 the falling edge timing is needed for tcp and tcc. CC; includes jig capacitance. test load; i.e., 68 pF for RAS and 330 pF for CAS. (max.) spec should be increased by about 2 ns.