80C152JA INTEL | Alldatasheet
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*Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. October 1989COPYRIGHT © INTEL CORPORATION, 1995 Order Number: 270431-003 8XC152JA/JB/JC/JD UNIVERSAL COMMUNICATION CONTROLLER 8-BIT MICROCONTROLLER X 8K Factory Mask Programmable ROM Available Y Superset of 80C51 Architecture Y Multi-Protocol Serial Communication I/O Port (2.048 Mbps/2.4 Mbps Max) Ð SDLC/HDLC Only Ð CSMA/CD and SDLC/HDLC Ð User Definable Protocols Y Full Duplex/Half Duplex Y MCSÉ-51 Compatible UART Y 16.5 MHz Maximum Clock Frequency Y Multiple Power Conservation Modes Y 64KB Program Memory Addressing Y 64KB Data Memory Addressing Y 256 Bytes On-Chip RAM Y Dual On-Chip DMA Channels Y Hold/Hold Acknowledge Y Two General Purpose Timer/Counters Y 5 or 7 I/O Ports Y 56 Special Function Registers Y 11 Interrupt Sources Y Available in 48 Pin Dual-in-Line Package and 68 Pin Surface Mount PLCC Package (See Packaging Spec. Order Ý231369) The 80C152, which is based on the MCS É-51 CPU, is a highly integrated single-chip 8-bit microcontroller designed for cost-sensitive, high-speed, serial communications. It is well suited for implementing Integrated Services Digital Networks (ISDN), emerging Local Area Networks, and user defined serial backplane applica- tions. In addition to the multi-protocol communication capability, the 80C152 offers traditional microcontroller features for peripheral I/O interface and control. Silicon implementations are much more cost effective than multi-wire cables found in board level parallel-to- serial and serial-to-parallel converters. The 83C152 contains, in silicon, all the features needed for the serial- to-parallel conversion. Other 83C152 benefits include: 1) better noise immunity through differential signaling or fiber optic connections, 2) data integrity utilizing the standard, designed in CRC checks, and 3) better modulari- ty of hardware and software designs. All of theseÐcost, network parameter and real estate improvementsÐ apply to 83C152 serial links between boards or systems and 83C152 serial links on a single board.
Figure 1. Connection Diagrams
Figure 2. Block Diagram
(EPROM bus Program Store ENable). EBEN selects the functionality of Port 5 and Port 6. external program memory for Port 5 and Port 6. skipped, which is the same as when using PSEN .
- The timing is the same as when using Ports 0 and
2 for external program memory operations. Table 1. Program Memory Fetches Table 2. 8XC152 Product Differences
Pin Ý Pin Description DIP PLCC (1) 48 2 VCCÐSupply voltage. 24 3,33 (2) VSSÐCircuit ground. 18-21, 27-30, Port 0 ÐPort 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin 25-28 34-37 can sink 8 LS TTL inputs. Port 0 pins that have 1s written to them float, and in that state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program memory if EBEN is pulled low. During accesses to external Data Memory, Port 0 always emits the low-order address byte and serves as the multiplexed data bus. In these applications it uses strong internal pullups when emitting 1s. Port 0 also outputs the code bytes during program verification. External pullups are required during program verification. 1-8 4-11 Port 1 ÐPort 1 is an 8-bit bidirectional I/O port with internal pullups. Port 1 pins that have 1s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (I IL, on the data sheet) because of the internal pullups. Port 1 also serves the functions of various special features of the 8XC152, as listed below: Pin Name Alternate Function P1.0 GRXD GSC data input pin P1.1 GTXD GSC data output pin P1.2 DEN GSC enable signal for an external driver P1.3 TXC GSC input pin for external transmit clock P1.4 RXC GSC input pin for external receive clock P1.5 HLD DMA hold input/output P1.6 HLDA DMA hold acknowledge input/output 29-36 41-48 Port 2 ÐPort 2 is an 8-bit bidirectional I/O port with internal pullups. Port 2 pins that have 1s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (I IL, on the data sheet) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external Program Memory if EBEN is pulled low. During accesses to external Data Memory that use 16- bit addresses (MOVX @ DPTR and DMA operations), Port 2 emits the high-order address byte. In these applications it uses strong internal pullups when emitting 1s. During accesses to external Data Memory that use 8-bit addresses (MOVX @ Ri), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits during program verification. 10- 17 14-16, Port 3 ÐPort 3 is an 8-bit bidirectional I/O port with internal pullups. Port 3 pins that 18, 19, have 1s written to them are pulled high by the internal pullups, and in that state can be 23-25 used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (I IL, on the data sheet) because of the pullups. Port 3 also serves the functions of various special features of the MCS-51 Family, as listed below: Pin Name Alternate Function P3.0 RXD Serial input line P3.1 TXD Serial output line P3.2 INT0 External Interrupt 0 P3.3 INT1 External Interrupt 1 P3.4 T0 Timer 0 external input P3.5 T1 Timer 1 external input P3.6 WR External Data Memory Write strobe P3.7 RD External Data Memory Read strobe
Pin Description (Continued) Pin Ý Pin Description 47-40 65-58 Port 4 ÐPort 4 is an 8-bit bidirectional I/O port with internal pullups. Port 4 pins that have 1s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 4 pins that are externally being pulled low will source current (I IL, on the data sheet) because of the internal pullups. In addition, Port 4 also receives the low-order address bytes during program verification. 91 3 RSTÐReset input. A logic low on this pin for three machine cycles while the oscillator is running resets the device. An internal pullup resistor permits a power-on reset to be generated using only an external capacitor to V SS. Although the GSC recognizes the reset after three machine cycles, data may continue to be transmitted for up to 4 machine cycles after Reset is first applied. 38 55 ALEÐAddress Latch Enable output signal for latching the low byte of the address during accesses to external memory. In normal operation ALE is emitted at a constant rate of (/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory. While in Reset, ALE remains at a constant high level. 37 54 PSENÐProgram Store Enable is the Read strobe to External Program Memory. When the 8XC152 is executing from external program memory, PSEN is active (low). When the device is executing code from External Program Memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to External Data Memory. While in Reset, PSEN remains at a constant high level. 39 56 EAÐExternal Access enable. EA must be externally pulled low in order to enable the 8XC152 to fetch code from External Program Memory locations 0000H to 0FFFH. EA must be connected to V CC for internal program execution. 23 32 XTAL1ÐInput to the inverting oscillator amplifier and input to the internal clock generating circuits. 22 31 XTAL2ÐOutput from the inverting oscillator amplifier. N/A 17, 20 Port 5 ÐPort 5 is an 8-bit bidirectional I/O port with internal pullups. Port 5 pins that 21, 22 have 1s written to them are pulled high by the internal pullups, and in that state can 38, 39 be used as inputs. As inputs, Port 5 pins that are externally being pulled low will 40, 49 source current (I IL, on the data sheet) because of the internal pullups. Port 5 is also the multiplexed low-order address and data bus during accesses to external program memory if EBEN is pulled high. In this application it uses strong pullups when emitting 1s. N/A 67, 66 Port 6 ÐPort 6 is an 8-bit bidirectional I/O port with internal pullups. Port 6 pins that 52, 57 have 1s written to them are pulled high by the internal pullups, and in that state can 50, 68 be used as inputs. As inputs, Port 6 pins that are externally pulled low will source 1, 51 current (I IL, on the data sheet) because of the internal pullups. Port 6 emits the high-order address byte during fetches from external Program Memory if EBEN is pulled high. In this application it uses strong pullups when emitting 1s. N/A 12 EBENÐE-Bus Enable input that designates whether program memory fetches take place via Ports 0 and 2 or Ports 5 and 6. Table 1 shows how the ports are used in conjunction with EBEN. N/A 53 EPSENÐE-bus Program Store Enable is the Read strobe to external program memory when EBEN is high. Table 2 shows when EPSEN is used relative to PSEN depending on the status of EBEN and EA .
ABSOLUTE MAXIMUM RATINGS * Ambient Temperature Under Bias ÀÀÀÀ0 §Ct o a70§C Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b65§Ct o a150§C Voltage on Any pin to V SS ÀÀb0.5V to (V CC a 0.5V) Voltage on V CC to VSSÀÀÀÀÀÀÀÀÀÀÀ b0.5V to a6.5V Power Dissipation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.0W (9) NOTICE: This data sheet contains preliminary infor- mation on new products in production. The specifica- tions are subject to change without notice. Verify with your local Intel Sales office that you have the latest data sheet before finalizing a design. *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability. D.C. CHARACTERISTICS (TA e 0§Ct o a70§C; V CC e 5V g10%; V SS e 0V) Symbol Parameter Min Typ Max Unit Test Conditions(Note 3) VIL Input Low Voltage b0.5 0.2V CCb0.1 V (All Except EA , EBEN) VIL1 Input Low Voltage b0.5 0.2V CCb0.3 V (EA, EBEN) VIH Input High Voltage 0.2V CCa0.9 V CCa0.5 V (Except XTAL1, RST ) VIH1 Input High Voltage 0.7V CC VCCa0.5 V (XTAL1, RST ) VOL Output Low Voltage 0.45 V I OL e 1.6 mA (Ports 1, 2, 3, 4, 5, 6) (Note 4) VOL1 Output Low Voltage 0.45 V I OL e 3.2 mA (Port 0, ALE, PSEN , EPSEN ) (Note 4) VOH Output High Voltage 2.4 V I OH eb 60 mA (Ports 1, 2, 3, 4, 5, 6 COMM9 V CC e 5V g10% ALE, PSEN , EPSEN ) 0.9VCC VI OH eb 10 mA VOH1 Output High Voltage 2.4 V I OH eb 400 mA (Port 0 in External V CC e 5V g10% Bus Mode) 0.9VCC VI OH eb 40 mA (Note 5) IIL Logical 0 Input b50 mAV IN e 0.45V Current (Ports 1, 2, 3, 4, 5, 6) ITL Logical 1 to 0 b650 mAV IN e 2V Transition Current ILI Input Leakage g10 mA 0.45 kVINkVCC (Port 0, EA ) RRST Reset Pullup Resistor 40 k X IIH Logical 1 Input Current (EBEN) a60 mA ICC Power Supply Current : Active (16.5 MHz) 31 41.1 mA (Note 6) Idle (16.5 MHz) 8 15.4 mA (Note 6) Power Down Mode 10 mAV CC e 2.0V to 5.5V
Figure 5. I CC vs Frequency I: Instruction (program memory contents). X: No longer a valid logic level. e Time for Address Valid to ALE Low. TLLPL e Time for ALE Low to PSEN Low.
A.C. CHARACTERISTICS (TA e 0§Ct o a70§C; V CC e 5V g10%; V SS e 0V; Load Capacitance for Port 0, ALE, and PSEN e 100 pF; Load Capacitance for All Other Outputs e 80 pF) EXTERNAL PROGRAM AND DATA MEMORY CHARACTERISTICS (Note 7, 10) Symbol Parameter 16.5 MHz Variable Oscillator Unit Min Max Min Max 1/TCLCL Oscillator Frequency 3.5 12 MHz 80C152JA/JC 83C152JA/JC 80C152JB/JD 80C152JA/JC-1 3.5 16.5 MHz 83C152JA/JC-1 80C152JB/JD-1 TLHLL ALE Pulse Width 81 2TCLCL-40 ns TAVLL Address Valid to ALE Low 5 TCLCL-55 ns TLLAX Address Hold After ALE Low 25 TCLCL-35 ns TLLIV ALE Low to Valid 142 4TCLCL-100 ns Instruction In TLLPL ALE Low to PSEN Low 20 TCLCL-40 ns TPLPH PSEN Pulse Width 137 3TCLCL-45 ns TPLIV PSEN Low to Valid 77 3TCLCL-105 ns Instruction In TPXIX Input Instruction 0 0 ns Hold After PSEN TPXIZ Input Instruction 35 TCLCL-25 ns Float After PSEN TAVIV Address to Valid 198 5TCLCL-105 ns Instruction In TPLAZ PSEN Low to Address 10 10 ns Float TRLRH RD Pulse Width 263 6TCLCL-100 ns TWLWH WR Pulse Width 263 6TCLCL-100 ns TRLDV RD Low to Valid 138 5TCLCL-165 ns Data In TRHDX Data Hold After RD 00 n s TRHDZ Data Float After RD 51 2TCLCL-70 ns TLLDV ALE Low to Valid 335 8TCLCL-150 ns Data In TAVDV Address to Valid 380 9TCLCL-165 ns Data In TLLWL ALE Low to RD or 132 232 3TCLCL-50 3TCLCL a50 ns WR Low TAVWL Address to RD or 112 4TCLCL-130 ns WR Low TQVWX(8) Data Valid to WR 196 6TCLCL-167 ns Transition TWHQX Data Hold After WR 10 TCLCL-50 ns TRLAZ RD Low to Address 0 0 ns Float TWHLH RD or WR High to 20 100 TCLCL-40 TCLCL a40 ns ALE High
EXTERNAL PROGRAM MEMORY READ CYCLE 270431–8 EXTERNAL DATA MEMORY READ CYCLE 270431–9
EXTERNAL DATA MEMORY WRITE CYCLE 270431–10 EXTERNAL CLOCK DRIVE Symbol Parameter Min Max Units 1/TCLCL Oscillator Frequency 3.5 16.5 MHz TCHCX High Time 20 ns TCLCX Low Time 20 ns TCLCH Rise Time 20 ns TCHCL Fall Time 20 ns EXTERNAL CLOCK DRIVE WAVEFORM 270431–11
LOCAL SERIAL CHANNEL TIMINGÐSHIFT REGISTER MODE Symbol Parameter 16.5 MHz Variable Oscillator Units Min Max Min Max TXLXL Serial Port Clock Cycle 727 12TCLCL ns Time TQVXH Output Data Setup to 473 10TCLCL-133 ns Clock Rising Edge TXHQX Output Data Hold After 4 2TCLCL-117 ns Clock Rising Edge TXHDX Input Data Hold After 0 0 ns Clock Rising Edge TXHDV Clock Rising Edge to 473 10TCLCL-133 ns Input Data Valid SHIFT REGISTER MODE TIMING WAVEFORMS 270431–12 A.C. TESTING: INPUT, OUTPUT WAVEFORMS 270431–13 AC Inputs During Testing are Driven at V CCb0.5 for a Logic ‘‘1’’ and 0.45V for a Logic ‘‘0’’. Timing Measurements are made at V IH Min for a Logic ‘‘1’’ and V IL Max for a Logic ‘‘0’’. FLOAT WAVEFORM 270431–14 For Timing Purposes a Port Pin is no Longer Floating when a 100 mV change from Load Voltage Occurs, and Begins to Float when a 100 mV change from the Loaded V OH/VOL Level occurs IOL/IOH t g20 mA.
GLOBAL SERIAL PORT TIMINGSÐInternal Baud Rate Generator Symbol Parameter 16.5 MHz (BAUD e 0) Variable Oscillator Unit Min Max Min Max HBTJR Allowable jitter on 0.0375 (0.125 c ms the Receiver for (/2 (BAUDa1)c bit time (Manchester 8TCLCL) encoding only) b25 ns FBTJR Allowable jitter on 0.10 (0.25 c ms the Receiver for one (BAUD a1)c full bit time (NRZI 8TCLCL) and Manchester) b25 ns HBTJT Jitter of data from g10 g10 ns Transmitter for (/2 bit time (Manchester encoding only) FBTJT Jitter of data from g10 g10 ns Transmitter for one full bit time (NRZI and Manchester) DRTR Data rise time for 20 20 ns Receiver(11) DFTR Data fall time for 20 20 ns Receiver(12) GSC RECEIVER TIMINGS (INTERNAL BAUD RATE GENERATOR) 270431–15
GSC TRANSMIT TIMINGS (INTERNAL BAUD RATE GENERATOR) 270431–16 GLOBAL SERIAL PORT TIMINGSÐExternal Clock Symbol Parameter 16.5 MHz Variable Oscillator Unit Min Max Min Max 1/ECBT GSC Frequency with an 2.4 0.009 F OSC c 0.145 MHz External Clock ECH External Clock High 170 2TCLCL ns a 45 ns ECL(13) External Clock Low 170 2TCLCL ns a 45 ns ECRT External Clock Rise 20 20 ns Time(11) ECFT External Clock Fall 20 20 ns Time(12) ECDVT External Clock to Data ns Valid Out - Transmit 150 150 (to External Clock Negative Edge) ECDHT External Clock Data ns Hold - Transmit 0 0 (to External Clock Negative Edge) ECDSR External Clock Data 45 45 ns Set-up - Receiver (to External Clock Positive Edge) ECDHR External Clock to Data 50 50 ns Hold - Receiver (to External Clock Positive Edge)
GSC TIMINGS (EXTERNAL CLOCK) 270431–17 NOTES: 1. N.C. pins on PLCC package may be connected to internal die and should not be used in customer applications. 2. It is recommended that both Pin 3 and Pin 33 be grounded for PLCC devices. 3. ‘‘Typicals’’ are based on samples taken from early manufacturing lots and are not guaranteed. The measurements were made with V CC e 5V at room temperature. 4. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the V OLs of ALE and Ports 1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1- to-0 transitions during bus operations. In the worst cases (capacitive loading l 100 pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. 5. Capacitive loading on Ports 0 and 2 may cause the V OH on ALE and PSEN to momentarily fall below the 0.9V CC specifi- cation when the address bits are stabilizing. 6. I CC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL e 5 ns, V IL e VSS a 0.5V, V IH e VCC b 0.5V; XTAL2 N.C.; Port 0 pins connected to V CC. ‘‘Operating’’ current is measured with EA connected to V CC and RST connected to V SS. ‘‘Idle’’ current is measured with EA connected to V SS, RST connected to V CC and GSC inactive. 7. The specifications relating to external data memory characteristics are also applicable to DMA operations. 8. TQVWX should not be confused with TQVWX as specified for 80C51BH. On 80C152, TQVWX is measured from data valid to rising edge of WR . On 80C51BH, TQVWX is measured from data valid to falling edge of WR . See timing diagrams. 9. This value is based on the maximum allowable die temperature and the thermal resistance of the package. 10. All specifications relating to external program memory characteristics are applicable to: EPSEN for PSEN Port 5 for Port 0 Port 6 for Port 2 when EBEN is at a Logical 1 on the 80C152JB/JD. 11. Same as TCLCH, use External Clock Drive Waveform. 12. Same as TCHCL, use External Clock Drive Waveform. 13. When using the same external clock to drive both the receiver and transmitter, the minimum ECL spec effectively becomes 195 ns at all frequencies (assuming 0 ns propagation delay) because ECDVT (150 ns) plus ECDSR (45 ns) re- quirements must also be met (150 a 45 e 195 ns). The 195 ns requirement would also increase to include the maximum propagation delay between receivers and transmitters.
Within the 8XC152 there exists a race condition that may set both the RDN and AE bits at the end of a valid reception. This will not cause a problem in the application as long as the following steps are followed: ÐNever give the receive error interrupt a higher priority than the valid reception interrupt ÐDo not leave the valid reception interrupt service routine when AE is set by using a RETI instruction until AE is cleared. To clear AE set the GREN bit, this enables the receiver. If the user desires that the receiver remain disabled, clear GREN after setting it before leaving the interrupt service routine. ÐIf the AE bit is checked by user software in response to a valid reception interrupt, the status of AE should be considered invalid. The race condition is dependent upon both the temperature that the device is currently operating at and the processing the device received during the wafer fabrication. When the idle mode is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. DATA SHEET REVISION SUMMARY The following represent the key differences between the ‘‘-003’’ and the ‘‘-002’’ version of the 80C152/83C152 data sheet. Please review this summary carefully. 1. Removed minimum GSC frequency spec when used with an external clock. 2. Change figure ‘‘External Program Memory Read Cycle’’ to show Port 0/Port 5 address floating after PSEN goes low. 3. Added design note on terminating idle with reset. 4. Added status of PSEN during Power Down mode to Table 3. 5. Moved all notes to back of data sheet. 6. Changed microcomputer to microcontroller. 7. Added External Oscillator start-up capacitance note. The following represent the key differences between the ‘‘-002’’ and the ‘‘-001’’ version of the 80C152/ 83C152 data sheet. Please review this summary carefully. 1. Status of data sheet changed from ‘‘ADVANCED’’ to ‘‘PRELIMINARY’’. 2. 80C152JC, 83C152JC, and 80C152JD were added. 3. Added AE/RDN design note. 4. This revision summary was added. 5. Note Ý13 was added (Effective ECL spec at higher clock rates). 6. Table Ý2 changed to Table Ý3 (Status of pins during Idle/Power Down). 8. Transmit jitter spec changed from g35 ns and g70 ns to g10 ns.