80960HA INTEL | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1.0 About This Document
- 2.0 Intel’s 80960Hx Processor
- 2.1 The i960® Processor Family
- 2.2 Key 80960Hx Features
- 2.2.1 Execution Architecture
- 2.2.2 Pipelined, Burst Bus
- 2.2.3 On-Chip Caches and Data RAM
- 2.2.4 Priority Interrupt Controller
- 2.2.5 Guarded Memory Unit
- 2.2.6 Dual Programmable Timers
- 2.2.7 Processor Self Test
- 2.3 Instruction Set Summary
- 3.0 Package Information
- 3.1 Pin Descriptions
- 3.3 Package Thermal Specifications
- 3.4 Heat Sink Adhesives
- 3.5 PowerQuad4 Plastic Package
- 3.6 Stepping Register Information
- 3.7 Sources for Accessories
- 4.0 Electrical Specifications
- 4.1 Absolute Maximum Ratings
- 4.2 Operating Conditions
- 4.3 Recommended Connections
- 4.4 VCC5 Pin Requirements (V
- 4.5 VCCPLL Pin Requirements
- 4.6 DC Specifications
- 4.7 AC Specifications
- 4.7.1 AC Test Conditions
- 4.8 AC Timing Waveforms
- 5.0 Bus Waveforms
- 5.2 Boundary Scan Description Language Example
80960HA/HD/HT 32-Bit High-Performance Superscalar Processor Data Sheet Advance Information Product Features n 32-Bit Parallel Architecture —Load/Store Architecture —Sixteen 32-Bit Global Registers —Sixteen 32-Bit Local Registers —1.28 Gbyte Internal Bandwidth (80 MHz) —On-Chip Register Cache n Processor Core Clock —80960HA is 1x Bus Clock —80960HD is 2x Bus Clock —80960HT is 3x Bus Clock n Binary Compatible with Other 80960 Processors n Issue Up To 150 Million Instructions per Second n High-Performance On-Chip Storage —16 Kbyte Four-Way Set-Associative Instruction Cache —8 Kbyte Four-Way Set-Associative Data Cache —2 Kbyte General Purpose RAM —Separate 128-Bit Internal Paths For Instructions/Data n 3.3 V Supply V oltage —5 V Tolerant Inputs —TTL Compatible Outputs n Guarded Memory Unit —Provides Memory Protection —User/Supervisor Read/Write/Execute n 32-Bit Demultiplexed Burst Bus —Per-Byte Parity Generation/Checking —Address Pipelining Option —Fully Programmable Wait State Generator —Supports 8-, 16- or 32-Bit Bus Widths —160 Mbyte/s External Bandwidth (40 MHz) n High-Speed Interrupt Controller —Up to 240 External Interrupts —31 Fully Programmable Priorities —Separate, Non-maskable Interrupt Pin n Dual On-Chip 32-Bit Timers —Auto Reload Capability and One-Shot —CLKIN Prescaling, ÷1, 2, 4 or 8 —JTAG Support - IEEE 1149.1 Compliant Order Number: 272495-007 July, 1998 Notice:This document contains information on products in the sampling and initial production phases of development. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.
Advance InformationDatasheet Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 80960HA/HD/HT may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © Intel Corporation, 1998 *Third-party brands and names are the property of their respective owners.
iv Advance InformationDatasheet Figures
14 NMI
16 Bus Backoff (BOFF
18 Input Setup and Hold Waveforms for T
28 Output Delay vs. V
31 Entering ONCE
47 Using External READY
Advance InformationDatasheet v 80960HA/HD/HT 50 BOFF Functional Timing. BOFFoccurs during a burst or
52 LOCK
12 Maximum T
14 Maximum T
1.0 About This Document
— are published in thei960® Hx Microprocessor User’s Guide(272484). In this document, “80960Hx” and “i960 Hx processor” refer to the products described inTable 1. Throughout this document, information that is specific to each is clearly indicated.
2.0 Intel’s 80960Hx Processor
differ in the ratio of core clock speed to external bus speed.
- The 80960Hx is not “drop-in” compatible in an 80960Cx-based system. Customers can design systems that accept either 80960Hx or Cx
Figure 1. 80960Hx Block Diagram
16 Kbyte, Four-Way Set-Associative
8 Kbyte, Four-Way Set-Associative
Table 1. 80960Hx Product Description *Processor inputs are 5 V tolerant.
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In addition to expanded clock frequency options, the 80960Hx provides essential enhancements for an emerging class of high-performance embedded applications. Features include a larger instruction cache, data cache, and data RAM than any other 80960 processor to date. It also boasts a 32-bit demultiplexed and pipelined burst bus, fast interrupt mechanism, guarded memory unit, wait state generator, dual programmable timers, ONCE and IEEE 1149.1-compliant boundary scan test and debug support, and new instructions.
2.1 The i960 ® Processor Family
The i960 processor family is a 32-bit RISC architecture created by Intel to serve the needs of embedded applications. The embedded market includes applications as diverse as industrial automation, avionics, image processing, graphics and communications. Because all members of the i960 processor family share a common core architecture, i960 applications are code-compatible. Each new processor in the family adds its own special set of functions to the core to satisfy the needs of a specific application or range of applications in the embedded market.
2.2 Key 80960Hx Features
2.2.1 Execution Architecture
Independent instruction paths inside the processor allow the execution of multiple, out-of-sequence instructions per clock. Register and resource scoreboarding interlocks maintain the logical integrity of sequential instructions that are being executed in parallel. To sustain execution of multiple instructions in each clock cycle, the processor decodes multiple instructions in parallel and simultaneously issues these instructions to parallel processing units. The various processing units are then able to independently access instruction operands in parallel from a common register set. Local Register Cache integrated on-chip provides automatic register management on call/return instructions. Upon a call instruction, the processor allocates a set of local registers for the called procedure, then stores the registers for the previous procedure in the on-chip register cache. As additional procedures are called, the cache stores the associated registers such that the most recently called procedure is the first available by the next return (ret) instruction. The processor can store up to fifteen register sets, after which the oldest sets are stored (spilled) into external memory. The 80960Hx supports the 80960 architecturally-defined branch prediction mechanism. This allows many branches to execute with no pipeline break. With the 80960Hx’s efficient pipeline, a branch can take as few as zero clocks to execute. The maximum penalty for an incorrect prediction is two core clocks.
2.2.2 Pipelined, Burst Bus
A 32-bit high performance bus controller interfaces the 80960Hx core to the external memory and peripherals. The Bus Control Unit features a maximum transfer rate of 160 Mbytes per second (at a 40 MHz external bus clock frequency). A key advantage of this design is its versatility. The user can independently program the physical and logical attributes of system memory. Physical attributes include wait state profile, bus width, and parity. Logical attributes include cacheability and Big or Little Endian byte order. Internally programmable wait states and 16 separately configurable physical memory regions allow the processor to interface with a variety of memory
Advance InformationDatasheet 3 subsystems with minimum system complexity. To reduce the effect of wait states, the bus design is decoupled from the core. This lets the processor execute instructions while the bus performs memory accesses independently. The Bus Controller’s key features include:
- Demultiplexed, Burst Bus to support most efficient DRAM access modes
- Address Pipelining to reduce memory cost while maintaining performance
- 32-, 16- and 8-bit modes to facilitate I/O interfacing
- Full internal wait state generation to reduce system cost
- Little and Big Endian support
- Unaligned Access support implemented in hardware
- Three-deep request queue to decouple the bus from the core
- Independent physical and logical address space characteristics
2.2.3 On-Chip Caches and Data RAM
As shown inFigure 1, the 80960Hx provides generous on-chip cache and storage features to decouple CPU execution from the external bus. The processor includes a 16 Kbyte instruction cache, an 8 Kbyte data cache and 2 Kbytes of Data RAM. The caches are organized as 4-way set associative. Stores that hit the data cache are written through to memory. The data cache performs write allocation on cache misses. A fifteen-set stack frame cache allows the processor to rapidly allocate and deallocate local registers. All of the on-chip RAM sustains a 4-word (128-bit) access every clock cycle.
2.2.4 Priority Interrupt Controller
The interrupt unit provides the mechanism for the low latency and high throughput interrupt service essential for embedded applications. A priority interrupt controller provides full programmability of 240 interrupt sources with a typical interrupt task switch (latency) time of 17 core clocks. The controller supports 31 priority levels. Interrupts are prioritized and signaled within 10 core clocks of the request. If the interrupt has a higher priority than the processor priority, the context switch to the interrupt routine would typically complete in another 7 bus clocks. External agents post interrupts via the 8-bit external interrupt port. The Interrupt unit also handles the two internal sources from the Timers. Interrupts can be level- or edge-triggered.
2.2.5 Guarded Memory Unit
The Guarded Memory Unit (GMU) provides memory protection without the address translation found in Memory Management Units. The GMU contains two memory protection schemes: one prevents illegal memory accesses, the other detects memory access violations. Both signal a fault to the processor. The programmable protection modes are: user read, write or execute; and supervisor read, write or execute.
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2.2.6 Dual Programmable Timers
to the processor’s interrupt controller.
2.2.7 Processor Self Test
pin is HIGH (logic “1”) before the detection of a System Error. from the internal Built-In Self-Test (BIST); when 0, the mask indicates other failures. Ignore reserved bits 0 and 1. Also ignore bits 5 and 6 when bit 7 is clear (=0). The mask is shown inTable 2and Table 3. Table 2. Fail Codes For BIST (bit 7 = 1) 6 On-chip Data-RAM failure detected by BIST. 5 Internal Microcode ROM failure detected by BIST. 4 Instruction cache failure detected by BIST. 3 Data cache failure detected by BIST. 2 Local-register cache or processor core failure detected by BIST. Table 3. Remaining Fail Codes (bit 7 = 0) 4 A data structure within the IMI is not aligned to a word boundary. 3 A System Error during normal operation has occurred. 2 The Bus Confidence test has failed.
2.3 Instruction Set Summary
Table 4summarizes the 80960Hx instruction set by logical groupings. Table 4. 80960Hx Instruction Set
- 80960Hx extensions to the 80960 core instruction set.
- 80960Hx extensions to the 80960Cx instruction set.
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3.0 Package Information
specifications and information, see the IntelPackagingHandbook (Order# 240800). CC = 3.3 V ± 0.15 V over a case temperature range of 0° to 85°C. Table 5. 80960HA/HD/HT Package Types and Speeds
25 A80960HA25 S L2GX
33 A80960HA33 S L2GY
40 A80960HA40 S L2GZ
25 FC80960HA25 S L2GU
33 FC80960HA33 S L2GV
40 FC80960HA40 S L2GW
3.1 Pin Descriptions
which can be driven active according to normal JTAG specifications. Table 6. Pin Description Nomenclature I/O Pin can be input or output.
- Pin must be connected as indicated for proper device functionality.
CLKIN to ensure proper operation of the processor. CLKIN to ensure proper operation of the processor. A(E) Asynchronous edge-sensitive input. A(L) Asynchronous level-sensitive input.
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Table 7. 80960Hx Processor Family Pin Descriptions (Sheet 1 of 4) increment to indicate successive addresses. configured for 8-bit data. When configured for 16-bit data, D15:0 are used. generation/checking is only performed for the size of the data accessed. PCHK indicates that the previous bus read access resulted in a parity check error. changes state when the next address is presented.
ADDRESS STROBE indicates a valid address and the start of a new bus access. is asserted for the first clock of a bus access. indicate that read data on the bus is valid, or that a write transfer has completed. wait states. WAITc a nb eu s e dt od e r i v eaw r i t ed a t as t r o b e . used with DENto provide control for data transceivers connected to the data bus. changes state when DENis high. used with DT/Rto provide control for data transceivers connected to the data bus. DEN remains asserted for sequential reads from pipelined memory regions. BUS LOCK indicates that an atomic read-modify-write operation is in progress. de-asserted when BLASTis deasserted in the last bus cycle. Table 7. 80960Hx Processor Family Pin Descriptions (Sheet 2 of 4)
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Completes the current bus request. Asserts HOLDA and floats the address, data, and control buses. reassumes control of the address, data, and control pins. HOLDA is never granted while LOCKis asserted. next clock cycle and the current access is aborted. See Figure 16 on page 40for BOFFtiming requirements. BUS REQUEST indicates that a bus request is pending in the bus controller. bus arbiter the processor’s bus ownership requirements. out of on-chip cache memory). pins are level sensitive in this mode. the vectored source are set to “010” internally. NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur. NMI is the highest priority interrupt source. NMIis falling edge triggered. Table 7. 80960Hx Processor Family Pin Descriptions (Sheet 3 of 4)
the processor boot sequence. processor to execute its built in self-test. pin asserts and the processor ceases execution. mode, the processor stops all clocks and floats all output pins except the TDO pin. DC Characteristics” on page 32. Pull this pin high when not in use. TEST DATA INPUT is the serial input pin for IEEE 1149.1 Boundary Scan testing. Characteristics” on page 32. testing. ONCE does not disable this pin. page 32. Pull this pin low when not in use. “80960Hx DC Characteristics” on page 32.
5 V REFERENCE VOLTAGE input is the reference voltage for the 5 V-tolerant I/O
all inputs are from 3.3 V components, connect this signal to 3.3 V. VCCPLL I PLL VOLTAGE is the +3.3 VDC analog input for the PLL. available only on the PGA version. Table 7. 80960Hx Processor Family Pin Descriptions (Sheet 4 of 4)
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Figure 2. 80960Hx 168-Pin PGA Pinout — View from Top (Pins Facing Down)
Figure 3. 80960Hx 168-Pin PGA Pinout — View from Bottom (Pins Facing Up)
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Table 8. 80960Hx 168-Pin PGA Pinout — Signal Name Order (Sheet 1 of 2)
Table 8. 80960Hx 168-Pin PGA Pinout — Signal Name Order (Sheet 2 of 2)
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Table 9. 80960Hx 168-Pin PGA Pinout — Pin Number Order (Sheet 1 of 2)
Table 9. 80960Hx 168-Pin PGA Pinout — Pin Number Order (Sheet 2 of 2)
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Figure 4. 80960Hx 208-Pin PQ4 Pinout
Table 10. 80960Hx PQ4 Pinout — Signal Name Order (Sheet 1 of 2)
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Table 10. 80960Hx PQ4 Pinout — Signal Name Order (Sheet 2 of 2)
Table 11. 80960Hx PQ4 Pinout — Pin Number Order (Sheet 1 of 2)
1 VCC 31 VCC 61 D28 91 BSTALL
2 VSS 32 VSS 62 D29 92 VCC
3 VSS 33 VCC 63 D30 93 VSS
4 VCC 34 D12 64 D31 94 VSS
5 FAIL 35 D13 65 VSS 95 VCC
6 ONCE 36 D14 66 VCC 96 D/C
7 VSS 37 D15 67 BTERM 97 SUP
8 VSS 38 VCC 68 READY 98 VSS
9 VCC 39 D16 69 HOLD 99 LOCK
10 BOFF 40 D17 70 VSS 100 BREQ
11 VCC 41 D18 71 VCC 101 VCC
12 D0 42 D19 72 HOLDA 102 VCC
13 D1 43 VSS 73 VSS 103 VSS
14 D2 44 VCC 74 VCC 104 A31
15 D3 45 D20 75 VSS 105 A30
16 VSS 46 VCC 76 VCC 106 A29
17 VCC 47 VSS 77 ADS 107 A28
18 VSS 48 VSS 78 BE3 108 VSS
19 VCC 49 VCC 79 BE2 109 VCC
20 D4 50 D21 80 VSS 110 A27
21 D5 51 D22 81 VCC 111 A26
22 D6 52 D23 82 BE1 112 A25
23 D7 53 VSS 83 BE0 113 A24
24 VSS 54 D24 84 BLAST 114 VSS
25 VCC 55 D25 85 DEN 115 VCC
26 D8 56 D26 86 VSS 116 VSS
27 D9 57 D27 87 VCC 117 VCC
28 D10 58 VSS 88 W/R 118 A23
29 D11 59 VCC 89 DT/R 119 A22
30 VSS 60 VCC 90 WAIT 120 A21
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121 A20 143 VCC 165 VCC 187 VCC
122 VSS 144 A7 166 XINT3 188 TDO
123 VCC 145 A6 167 XINT2 189 PCHK
124 A19 146 A5 168 XINT1 190 VSS
125 A18 147 A4 169 XINT0 191 TDI
126 A17 148 VSS 170 VSS 192 TMS
127 A16 149 VCC 171 VCC 193 TRST
128 VCC 150 A3 172 VSS 194 TCK
129 VSS 151 A2 173 VCC 195 VSS
130 VSS 152 VSS 174 RESET 196 VCC
131 VCC 153 VCC 175 CLKIN 197 VCC5
132 A15 154 VCC 176 VCC 198 VSS
133 A14 155 VSS 177 VCCPLL 199 VCC
134 A13 156 VSS 178 VSS 200 VSS
135 A12 157 VSS 179 VCC 201 VCC
136 VSS 158 VCC 180 CT3 202 DP3
137 VCC 159 NMI 181 CT2 203 DP2
138 A11 160 XINT7 182 CT1 204 VCC
139 A10 161 XINT6 183 CT0 205 VSS
140 A9 162 XINT5 184 VSS 206 DP0
141 A8 163 XINT4 185 VCC 207 DP1
142 VSS 164 VSS 186 VSS 208 STEST
Table 11. 80960Hx PQ4 Pinout — Pin Number Order (Sheet 2 of 2)
3.3 Package Thermal Specifications
opposite the pins. Refer toFigure 5. operating frequencies (fCLKIN ). Specifications” on page 32and VCC of 3.3 V . Figure 5. Measuring 80960Hx PGA Case Temperature
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Table 12. Maximum TA at Various Airflows in °C (PGA Package Only) *0.285” high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing). Table 13. 80960Hx 168-Pin PGA Package Thermal Characteristics
- This table applies to 80960Hx PGA plugged into socket or soldered directly to board.
*0.285” high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing).
Table 14. Maximum TA at Various Airflows in °C (PQ4 Package Only) *0.285” high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing). Table 15. 80960Hx 208-Pin PQ4 Package Thermal Characteristics
- This table applies to 80960Hx PQ4 plugged into socket or soldered directly to board.
*0.285” high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing).
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3.4 Heat Sink Adhesives
particular recommendation concerning the PQ4 package.
3.5 PowerQuad4 Plastic Package
to the SQFP package and the former PQ2 package, so the PQ4 fits into the same board footprint. expensive ceramic PGA package.
3.6 Stepping Register Information
value for device identification is compliant with the IEEE 1149.1 specification and Intel standards. Table 16describes the fields of the device ID. Figure 6. 80960Hx Device Identification Register
Table 16. Fields of 80960Hx Device ID Version See Table 18 Indicates major stepping changes. VCC 1 = 3.3 V device Indicates that a device is 3.3 V. (Indicates i960 CPU) Designates type of product. Generation Type 0010 = H-series Indicates the generation (or series) the product belongs to. (Indicates Intel) Manufacturer ID assigned by IEEE. Table 17. 80960Hx Device ID Model Types Table 18. Device ID Version Numbers for Different Steppings This data sheet applies to the B2 stepping.
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3.7 Sources for Accessories
The following is a list of suggested sources for 80960Hx accessories. This is neither an endorsement nor a warranty of the performance of any of the listed products and/or companies. Sockets
- 3M Textool Test and Interconnection Products 6801 River Place Blvd. MS 130-3N-29 Austin, TX 78726-9000 (800) 328-0411 FAX: (800) 932-9373
- Concept Mfg, Inc. (Decoupling Sockets) 400 Walnut St. Suite 609 Redwood City, CA 94063 (415) 365-1162 FAX: (415) 365-1164 Heatsinks/Fins
- Thermalloy, Inc.
2021 West Valley View Lane
Dallas, TX 75234-8993 (972) 243-4321 FAX: (972) 241-4656
- Wakefield Engineering, Inc.
60 Audubon Road
Wakefield, MA 01880 (617) 245-5900 FAX: (617) 246-0874
- Aavid Thermal Technologies, Inc. One Kool Path Laconia, NH 03247-0400 (603) 523-3400
4.0 Electrical Specifications
4.1 Absolute Maximum Ratings
4.2 Operating Conditions
data sheet before finalizing a design. “Operating Conditions” may affect device reliability. Table 19. Operating Conditions
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4.3 Recommended Connections
the ground plane. Pins identified as “NC” —no connect pins—must notbe connected in the system. power surges when its output buffers transition, particularly when connected to large capacitive loads. offer the lowest possible inductance. must always remain unconnected.
4.4 VCC5 Pin Requirements (V DIFF)
applies to power-up, power-down, and steady-state operation.Table 20outlines this requirement. VCC5 pin does not exceed the ICC5 specification. does not exceed the maximum rating for this pin. This resistor is not necessary in systems that can guarantee the VDIFF specification. pin directly to the 3.3 V VCC plane. Figure 7. VCC5 Current-Limiting Resistor Table 20. VDIFF Specification for Dual Power Supply Requirements (3.3 V, 5 V) power-up and power-down, or during steady-state operation.
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4.5 VCCPLL Pin Requirements
If the voltage on the VCCPLL power supply pin exceeds the VCC pin voltage by 0.5 V at any time, including the power up and power down sequences, excessive currents can permanently damage on-chip electrostatic discharge (ESD) protection diodes. The damage can accumulate over multiple episodes. Pragmatically, this problem only occurs when the VCCPLL and V CC pins are driven by separate power supplies or voltage regulators. Applications that use one power supply for VCCPLL and V CC are not typically at risk. Verify that your application does not allow the VCCPLL voltage to exceed VCC by 0.5 V. The VCCPL low-pass filter recommended in the Developer’s Manual does not promote this problem.
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4.6 DC Specifications
Table 21. 80960Hx DC Characteristics (Sheet 1 of 2) Per the conditions described inSection 4.3, “Recommended Connections” on page 30.
0.2 V IOL =3m A
- ICC Maximum is measured at worst case frequency, VCC , and temperature, with device operating and
outputs loaded to the test conditions described inSection 4.7.1, “AC Test Conditions” on page 37.
- ICC Typical is not tested.
- Output Capacitance is the capacitive load of a floating output.
- Measured with device operating and outputs loaded to the test conditions inFigure 8 “AC Test Load” on
- ICC Active (Power Supply) value is provided for selecting your system’s power supply. It is measured using
one of the worst case instruction mixes with VCC = 3.45 V. This parameter is characterized but not tested.
- ICC Active (Thermal) value is provided for your system’s thermal management. Typical ICC is measured with
VCC = 3.3 V and temperature = 25°C. This parameter is characterized but not tested.
- ICC Test (Power modes) refers to the ICC values that are tested when the 80960HA/HD/HT is in Reset mode
or ONCE mode with VCC =3 . 4 5V . 10.Pin capacitance is characterized, but not tested. Table 21. 80960Hx DC Characteristics (Sheet 2 of 2) Per the conditions described inSection 4.3, “Recommended Connections” on page 30.
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4.7 AC Specifications
Table 22. 80960Hx AC Characteristics (Sheet 1 of 2) Per conditions inSection 4.2, “Operating Conditions” on page 29and Section 4.7.1, “AC Test Conditions” on page 37. 3.3 V and 5 V inputs and I/Os. NOTE: See Table 23 “AC Characteristics Notes” on page 36for all notes related to AC specifications.
Table 22. 80960Hx AC Characteristics (Sheet 2 of 2) Per conditions inSection 4.2, “Operating Conditions” on page 29and Section 4.7.1, “AC Test Conditions” on page 37. NOTE: See Table 23 “AC Characteristics Notes” on page 36for all notes related to AC specifications.
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Table 23. AC Characteristics Notes
- SeeSection 4.8, “AC Timing Waveforms” on page 38for waveforms and definitions.
- SeeFigure 25 “Output Delay or Hold vs. Load Capacitance” on page 44for capacitive derating information
for output delays and hold times.
- SeeFigure 22 “Rise and Fall Time Derating at 85°C and Minimum VCC ” on page 43for capacitive derating
information for rise and fall times.
- Where N is the number of NRAD ,N RDD ,N WAD or NWDD wait states that are programmed in the Bus
Controller Region Table. WAITnever goes active when there are no wait states in an access.
- N = Number of wait states inserted with READY.
- These specifications are guaranteed by the processor.
- These specifications must be met by the system for proper operation of the processor.
must meet setup and hold times to the rising edge of the CLKIN.
- The interrupt pins are synchronized internally by the 80960Hx. They have no required setup or hold times
recognition at a particular clock edge, the setup and hold times shown must be met. 10.Relative Output timings are not tested. Table 24. 80960Hx Boundary Scan Test Signal Timings
4.7.1 AC Test Conditions
AC values are derived using the 50 pF load shown inFigure 8.F i g u r e2 5“ O u t p u tD e l a yo rH o l dv s . (except for CLKIN) are assumed to have a rise and fall time of£ 2n sf r o m0 . 8Vt o2 . 0V . Figure 8. AC Test Load
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4.8 AC Timing Waveforms
Figure 9. CLKIN Waveform Figure 10. Output Delay Waveform Figure 11. Output Delay Waveform
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Figure 15. Hold Acknowledge Timings Figure 16. Bus Backoff (BOFF) Timings TOV TOH — OUTPUT DELAY - The maximum output delay is referred to as the Output Valid Delay (TOV ). The minimum output delay is referred to as the Output Hold (TOH ). during which synchronous inputs must be stable for correct processor operation.
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Figure 19. Output Delay and Output Float for TBSOV1 and TBSOF1 Figure 20. Output Delay and Output Float Waveform for TBSOV2 and TBSOF2 Figure 21. Input Setup and Hold Waveform for TBSIS2 and TBSIH2
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Figure 24. ICC Active (Thermal) vs. Frequency Figure 25. Output Delay or Hold vs. Load Capacitance
5.5 V Input Signals
3.3 V Input Signals
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5.0 Bus Waveforms
Figure 29. Cold Reset Waveform
Figure 30. Warm Reset Waveform
16 CLKIN Periods 1C L K I N
16 CLKIN Periods
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Figure 31. Entering ONCEMode RESET high, minimum10,000 CLKIN Periods. CLKIN may neither float nor remain idle.
- ONCE mode may be entered prior to the rising edge of RESET: ONCE input is not latched until the rising
- The ONCE input may be removed after the processor enters ONCE mode.
Figure 32. Non-Burst, Non-Pipelined Requests without Wait States NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
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Figure 33. Non-Burst, Non-Pipelined Read Request with Wait States NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
Figure 34. Non-Burst, Non-Pipelined Write Request with Wait States NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
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Figure 35. Burst, Non-Pipelined Read Request without Wait States, 32-Bit Bus NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
Figure 36. Burst, Non-Pipelined Read Request with Wait States, 32-Bit Bus NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
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Figure 37. Burst, Non-Pipelined Write Request without Wait States, 32-Bit Bus NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
Figure 38. Burst, Non-Pipelined Write Request with Wait States, 32-Bit Bus NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
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Figure 39. Burst, Non-Pipelined Read Request with Wait States, 16-Bit Bus NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
Figure 40. Burst, Non-Pipelined Read Request with Wait States, 8-Bit Bus NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
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Figure 41. Non-Burst, Pipelined Read Request without Wait States, 32-Bit Bus
- Non-pipelined request concludes, pipelined reads begin.
- Pipelined reads conclude, non-pipelined requests begin.
1 Xxxxx
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
Figure 42. Non-Burst, Pipelined Read Request with Wait States, 32-Bit Bus
- Non-pipelined request concludes, pipelined reads begin
- Pipelined reads conclude, non-pipelined requests begin
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
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Figure 43. Burst, Pipelined Read Request without Wait States, 32-Bit Bus NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
- Non-pipelined request concludes, pipelined reads begin
- Pipelined reads conclude, non-pipelined requests begin
Figure 44. Burst, Pipelined Read Request with Wait States, 32-Bit Bus
- Non-pipelined request concludes, pipelined reads begin.
- Pipelined reads conclude, non-pipelined requests begin.
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
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Figure 45. Burst, Pipelined Read Request with Wait States, 8-Bit Bus
- Non-pipelined request concludes, pipelined reads begin
- Pipelined reads conclude, non-pipelined requests begin
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
Figure 46. Burst, Pipelined Read Request with Wait States, 16-Bit Bus NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
- Non-pipelined request concludes, pipelined reads begin
- Pipelined reads conclude, non-pipelined requests begin
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Figure 47. Using External READY NOTE: Pipelining must be disabled to use READY.
Figure 48. Terminating a Burst with BTERM the last (or only) data transfer of the bus access.
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The processor can stall (BSTALL asserted) even with an empty bus queue (BREQ deasserted). the processor in all stall cases, potentially degrading processor performance. is a “red light” indicating a stall in progress. Figure 49. BREQ and BSTALL Operation
Figure 50. BOFFFunctional Timing. BOFFoccurs during a burst or non-burst data cycle.
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Figure 51. HOLD Functional Timing
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Figure 54. A Summary of Aligned and Unaligned Transfers for 32-Bit Regions
- All requests that are less than a word in size and are cacheable will be promoted to a word to be cached. This causes
adjacent requests to occur for full words to the same address.
Figure 55. A Summary of Aligned and Unaligned Transfers for 32-Bit Regions(Continued)
8 Short Requests
- All requests that are less than a word in size and are cacheable will be promoted to a word to be cached. This causes
adjacent requests to occur for full words to the same address.
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Figure 56. A Summary of Aligned and Unaligned Transfers for 16-Bit Bus
Figure 57. A Summary of Aligned and Unaligned Transfers for 8-Bit Bus
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Figure 58. Idle Bus Operation
Figure 59. Bus States
- When the PMCON for the region has External Ready Control enabled, wait states are inserted as
- W aCNT is decremented during Taw
- W dCNT is decremented during Tdw
- W xCNT is decremented during Trw
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Table 25. 80960Hx Boundary Scan Chain (Sheet 1 of 4)
- Cell#1 connects to TDO and cell #112 connects to TDI.
- All outputs are three-state.
- In output and bidirectional signals, a logical “1” on the enable signal enables the output. A logical “0”
WRRDBAR Output Appears as WRBAR in BSDL file. DATACODBAR Output Appears as DCBAR in BSDL file. USERSUPBAR Output Appears as SUPBAR in BSDL file. Table 25. 80960Hx Boundary Scan Chain (Sheet 2 of 4)
- Cell#1 connects to TDO and cell #112 connects to TDI.
- All outputs are three-state.
- In output and bidirectional signals, a logical “1” on the enable signal enables the output. A logical “0”
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Table 25. 80960Hx Boundary Scan Chain (Sheet 3 of 4)
- Cell#1 connects to TDO and cell #112 connects to TDI.
- All outputs are three-state.
- In output and bidirectional signals, a logical “1” on the enable signal enables the output. A logical “0”
CT3 Output Appears as CT(3:0) in BSDL file. Table 25. 80960Hx Boundary Scan Chain (Sheet 4 of 4)
- Cell#1 connects to TDO and cell #112 connects to TDI.
- All outputs are three-state.
- In output and bidirectional signals, a logical “1” on the enable signal enables the output. A logical “0”
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5.2 Boundary Scan Description Language Example
Boundary-Scan Description Language (BSDL) example 14-2 meets the de facto standard means of describing essential features of ANSI/IEEE 1149.1-1993 compliant devices. Example 1. Boundary-Scan Description Language (BSDL) for PGA Package Example (Sheet 1 of 8) -- Copyright Intel Corp. 1995 - - Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein. - - Boundary-Scan Description Language (BSDL Version 0.0) is a de-facto standard means of describing essential features of ANSI/IEEE 1149.1-1990 compliant devices. This language is under consideration by the IEEE for formal inclusion within a supplement to the 1149.1-1990 standard. The generation of the supplement entails an extensive IEEE review and a formal acceptance balloting procedure which may change the resultant form of the language. Be aware that this process may extend well into 1993, and at this time the IEEE does not endorse or hold an opinion on the language. -- i960(R) Processor BSDL Model
Advance InformationDatasheet 81 -- Project code HA -- File NOT verified electrically -- Rev 0.7 18 Dec 1995 Updated for A-1 stepping. -- Rev 0.6 08 Dec 1994 -- Rev 0.5 21 Nov 1994 -- Rev 0.4 31 Oct 1994 -- Rev 0.3 26 July 1994 -- Rev 0.2 22 June 1994 -- Rev 0.1 16 Mar 1994 -- Rev 0.0 30 Aug 1993 entity Ha_Processor is generic(PHYSICAL_PIN_MAP : string:= “PGA”); port (A : out bit_vector(2 to 31); ADSBAR : out bit; BEBAR : out bit_vector(0 to 3); BLASTBAR : out bit; BOFFBAR : in bit; BREQ : out bit; BSTALL : out bit; BTERMBAR : in bit; CT : out bit_vector(0 to 3); CLKIN : in bit; D : inout bit_vector(0 to 31); DENBAR : out bit; DP : inout bit_vector(0 to 3); DTRBAR : out bit; DCBAR : out bit; FAILBAR : out bit; HOLD : in bit; HOLDA : out bit; LOCKBAR : out bit; NMIBAR : in bit; ONCEBAR : in bit; PCHKBAR : out bit; READYBAR : in bit; RESETBAR : in bit; STEST : in bit; Example 1. Boundary-Scan Description Language (BSDL) for PGA Package Example (Sheet 2 of 8)
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SUPBAR : out bit; TCK : in bit; TDI : in bit; TDO : out bit; TMS : in bit; TRST : in bit; WAITBAR : out bit; WRBAR : out bit; XINTBAR : in bit_vector(0 to 7); FIVEVREF : linkage bit; VCCPLL : linkage bit; VOLTDET : out bit; VCC1 : linkage bit_vector(0 to 23); VCC2 : linkage bit_vector(0 to 20); VSS1 : linkage bit_vector(0 to 25); VSS2 : linkage bit_vector(0 to 22); NC : linkage bit_vector(0 to 4) use STD_1149_1_1990.all; use i960ha_a.all; attribute PIN_MAP of Ha_Processor : entity is PHYSICAL_PIN_MAP; constant PGA:PIN_MAP_STRING := “ K17, L17, L16, M17, N17, N16, P17, Q17, P16,”& “ P15, Q16, R17, R16, Q15, S17, R15, S16, Q14, ”& “ R14, Q13, S15), “ADSBAR : R06,”& “BEBAR : (R09, S07, S06, S05),”& “BLASTBAR : S08,”& “BOFFBAR : B01,”& “BREQ : R13,”& “BSTALL : R12,”& “BTERMBAR : R04,”& “CLKIN : C13,”& Example 1. Boundary-Scan Description Language (BSDL) for PGA Package Example (Sheet 3 of 8)
Advance InformationDatasheet 83 “ G01, H02, H01, J01, K01, L02, L01, M01, N01,”& “ N02, P01, P02, Q01, P03, Q02, R01, S01, Q03,”& “DENBAR : S09,”& “DTRBAR : S11,”& “DCBAR : S13,”& “FAILBAR : A02,”& “HOLD : R05,”& “HOLDA : S04,”& “LOCKBAR : S14,”& “NMIBAR : D15,”& “ONCEBAR : C03,”& “PCHKBAR : B08,”& “READYBAR : S03,”& “RESETBAR : A16,”& “STEST : B02,”& “SUPBAR : Q12,”& “TCK : B05,”& “TDI : A07,”& “TDO : A08,”& “TMS : B06,”& “TRST : A06,”& “WAITBAR : S12,”& “WRBAR : S10,”& “ XINTBAR : (B15, A15, A17, B16, C15, B17, C16, C17),”& “FIVEVREF : C05,”& “VOLTDET : A05,”& “VCCPLL : B10,”& “ VCC1 : (M02, K02, J02, G02, N03, F03, C06, B07, B09, B11,”& “ B12, C14, E15, F16, H16, J16, K16, M16, N15, Q06,”& “ VSS1 : (G03, H03, J03, K03, L03, M03, C07, C08, C09, C10,”& “ C11, C12, Q07, Q08, Q09, Q10, Q11, F15, G15, H15,”& Example 1. Boundary-Scan Description Language (BSDL) for PGA Package Example (Sheet 4 of 8)
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attribute Tap_Scan_In of TDI : signal is true; attribute Tap_Scan_Mode of TMS : signal is true; attribute Tap_Scan_Out of TDO : signal is true; attribute Tap_Scan_Reset of TRST : signal is true; attribute Tap_Scan_Clock of TCK : signal is (66.0e6, BOTH); attribute Instruction_Length of Ha_Processor: entity is 4; attribute Instruction_Opcode of Ha_Processor: entity is “BYPASS (1111),” & “EXTEST (0000),” & “SAMPLE (0001),” & “IDCODE (0010),” & “RUBIST (0111),” & “CLAMP (0100),” & “HIGHZ (1000),” & “Reserved (1011, 1100)”; attribute Instruction_Capture of Ha_Processor: entity is “0001”; attribute Instruction_Private of Ha_Processor: entity is “Reserved” ; attribute Idcode_Register of Ha_Processor: entity is “0010” & --version, “1000100001000000” & --part number “00000001001” & --manufacturers identity “1”; --required by the standard attribute Register_Access of Ha_Processor: entity is “Runbist[32] (RUBIST),” & “Bypass (CLAMP, HIGHZ)”; { The first cell, cell 0, is closest to TDO } { BC_1:Control, Output3 CBSC_1:Bidir BC_4: Input, Clock } Example 1. Boundary-Scan Description Language (BSDL) for PGA Package Example (Sheet 5 of 8)
Advance InformationDatasheet 85 attribute Boundary_Cells of Ha_Processor: entity is “BC_4, BC_1, CBSC_1”; attribute Boundary_Length of Ha_Processor: entity is 112; attribute Boundary_Register of Ha_Processor: entity is “0 (CBSC_1, DP(3), bidir, X, 17, 1, Z),” & “1 (CBSC_1, DP(2), bidir, X, 17, 1, Z),” & “2 (CBSC_1, DP(0), bidir, X, 17, 1, Z),” & “3 (CBSC_1, DP(1), bidir, X, 17, 1, Z),” & “4 (BC_4, STEST, input, X),” & “5 (BC_1, FAILBAR, output3, X, 6, 1, Z),” & “6 (BC_1, *, control, 1),” & “7 (BC_4, ONCEBAR, input, X),” & “8 (BC_4, BOFFBAR, input, X),” & “9 (CBSC_1, D(0), bidir, X, 17, 1, Z),” & “10 (CBSC_1, D(1), bidir, X, 17, 1, Z),” & “11 (CBSC_1, D(2), bidir, X, 17, 1, Z),” & “12 (CBSC_1, D(3), bidir, X, 17, 1, Z),” & “13 (CBSC_1, D(4), bidir, X, 17, 1, Z),” & “14 (CBSC_1, D(5), bidir, X, 17, 1, Z),” & “15 (CBSC_1, D(6), bidir, X, 17, 1, Z),” & “16 (CBSC_1, D(7), bidir, X, 17, 1, Z),” & “17 (BC_1, *, control, 1),” & “18 (CBSC_1, D(8), bidir, X, 17, 1, Z),” & “19 (CBSC_1, D(9), bidir, X, 17, 1, Z),” & “20 (CBSC_1, D(10), bidir, X, 17, 1, Z),” & “21 (CBSC_1, D(11), bidir, X, 17, 1, Z),” & “22 (CBSC_1, D(12), bidir, X, 17, 1, Z),” & “23 (CBSC_1, D(13), bidir, X, 17, 1, Z),” & “24 (CBSC_1, D(14), bidir, X, 17, 1, Z),” & “25 (CBSC_1, D(15), bidir, X, 17, 1, Z),” & “26 (CBSC_1, D(16), bidir, X, 17, 1, Z),” & “27 (CBSC_1, D(17), bidir, X, 17, 1, Z),” & “28 (CBSC_1, D(18), bidir, X, 17, 1, Z),” & “29 (CBSC_1, D(19), bidir, X, 17, 1, Z),” & “30 (CBSC_1, D(20), bidir, X, 17, 1, Z),” & “31 (CBSC_1, D(21), bidir, X, 17, 1, Z),” & “32 (CBSC_1, D(22), bidir, X, 17, 1, Z),” & “33 (CBSC_1, D(23), bidir, X, 17, 1, Z),” & “34 (CBSC_1, D(24), bidir, X, 17, 1, Z),” & Example 1. Boundary-Scan Description Language (BSDL) for PGA Package Example (Sheet 6 of 8)
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“35 (CBSC_1, D(25), bidir, X, 17, 1, Z),” & “36 (CBSC_1, D(26), bidir, X, 17, 1, Z),” & “37 (CBSC_1, D(27), bidir, X, 17, 1, Z),” & “38 (CBSC_1, D(28), bidir, X, 17, 1, Z),” & “39 (CBSC_1, D(29), bidir, X, 17, 1, Z),” & “40 (CBSC_1, D(30), bidir, X, 17, 1, Z),” & “41 (CBSC_1, D(31), bidir, X, 17, 1, Z),” & “42 (BC_4, BTERMBAR, input, X),” & “43 (BC_4, READYBAR, input, X),” & “44 (BC_4, HOLD, input, X),” & “45 (BC_1, HOLDA, output3, X, 46, 1, Z),” & “46 (BC_1, *, control, 1),” & “47 (BC_1, ADSBAR, output3, X, 61, 1, Z),” & “48 (BC_1, BEBAR(3), output3, X, 61, 1, Z),” & “49 (BC_1, BEBAR(2), output3, X, 61, 1, Z),” & “50 (BC_1, BEBAR(1), output3, X, 61, 1, Z),” & “51 (BC_1, BEBAR(0), output3, X, 61, 1, Z),” & “52 (BC_1, BLASTBAR, output3, X, 61, 1, Z),” & “53 (BC_1, DENBAR, output3, X, 61, 1, Z),” & “54 (BC_1, WRBAR, output3, X, 61, 1, Z),” & “55 (BC_1, DTRBAR, output3, X, 56, 1, Z),” & “56 (BC_1, *, control, 1),” & “57 (BC_1, WAITBAR, output3, X, 61, 1, Z),” & “58 (BC_1, BSTALL, output3, X, 6, 1, Z),” & “59 (BC_1, DCBAR, output3, X, 61, 1, Z),” & “60 (BC_1, SUPBAR, output3, X, 61, 1, Z),” & “61 (BC_1, *, control, 1),” & “62 (BC_1, LOCKBAR, output3, X, 61, 1, Z),” & “63 (BC_1, BREQ, output3, X, 6, 1, Z),” & “64 (BC_1, A(31), output3, X, 80, 1, Z),” & “65 (BC_1, A(30), output3, X, 80, 1, Z),” & “66 (BC_1, A(29), output3, X, 80, 1, Z),” & “67 (BC_1, A(28), output3, X, 80, 1, Z),” & “68 (BC_1, A(27), output3, X, 80, 1, Z),” & “69 (BC_1, A(26), output3, X, 80, 1, Z),” & “70 (BC_1, A(25), output3, X, 80, 1, Z),” & “71 (BC_1, A(24), output3, X, 80, 1, Z),” & “72 (BC_1, A(23), output3, X, 80, 1, Z),” & “73 (BC_1, A(22), output3, X, 80, 1, Z),” & Example 1. Boundary-Scan Description Language (BSDL) for PGA Package Example (Sheet 7 of 8)
Advance InformationDatasheet 87 “74 (BC_1, A(21), output3, X, 80, 1, Z),” & “75 (BC_1, A(20), output3, X, 80, 1, Z),” & “76 (BC_1, A(19), output3, X, 80, 1, Z),” & “77 (BC_1, A(18), output3, X, 80, 1, Z),” & “78 (BC_1, A(17), output3, X, 80, 1, Z),” & “79 (BC_1, A(16), output3, X, 80, 1, Z),” & “80 (BC_1, *, control, 1),” & “81 (BC_1, A(15), output3, X, 80, 1, Z),” & “82 (BC_1, A(14), output3, X, 80, 1, Z),” & “83 (BC_1, A(13), output3, X, 80, 1, Z),” & “84 (BC_1, A(12), output3, X, 80, 1, Z),” & “85 (BC_1, A(11), output3, X, 80, 1, Z),” & “86 (BC_1, A(10), output3, X, 80, 1, Z),” & “87 (BC_1, A(9), output3, X, 80, 1, Z),” & “88 (BC_1, A(8), output3, X, 80, 1, Z),” & “89 (BC_1, A(7), output3, X, 80, 1, Z),” & “90 (BC_1, A(6), output3, X, 80, 1, Z),” & “91 (BC_1, A(5), output3, X, 80, 1, Z),” & “92 (BC_1, A(4), output3, X, 80, 1, Z),” & “93 (BC_1, A(3), output3, X, 80, 1, Z),” & “94 (BC_1, A(2), output3, X, 80, 1, Z),” & “95 (BC_4, NMIBAR, input, X),” & “96 (BC_4, XINTBAR(7), input, X),” & “97 (BC_4, XINTBAR(6), input, X),” & “98 (BC_4, XINTBAR(5), input, X),” & “99 (BC_4, XINTBAR(4), input, X),” & “100(BC_4, XINTBAR(3), input, X),” & “101(BC_4, XINTBAR(2), input, X),” & “102(BC_4, XINTBAR(1), input, X),” & “103(BC_4, XINTBAR(0), input, X),” & “104(BC_4, RESETBAR, input, X),” & “105(BC_4, CLKIN, input, X),” & “106(BC_1, CT(3), output3, X, 80, 1, Z),” & “107(BC_1, CT(2), output3, X, 80, 1, Z),” & “108(BC_1, CT(1), output3, X, 80, 1, Z),” & “109(BC_1, CT(0), output3, X, 80, 1, Z),” & “110(BC_1, PCHKBAR, output3, X, 111, 1, Z),” & “111(BC_1, *, control, 1)”; end Ha_Processor; Example 1. Boundary-Scan Description Language (BSDL) for PGA Package Example (Sheet 8 of 8)
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Example 2. Boundary-Scan Description Language (BSDL) for PQ2 Package Example (Sheet 1 of 8) -- Copyright Intel Corporation 1995, 1996 -- Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein. -- Boundary-Scan Description Language (BSDL Version 0.0) is a de-facto -- standard means of describing essential features of ANSI/IEEE 1149.1-1990 compliant devices. This language is under consideration by the IEEE for formal inclusion within a supplement to the 1149.1-1990 standard. The generation of the supplement entails an extensive IEEE review and a formal acceptance balloting procedure which may change the resultant form of the language. Be aware that this process may extend well into 1993, and at this time the IEEE does not endorse or hold an opinion on the language. -- i960(R) Processor BSDL Model -- Project code HA -- File NOT verified electrically -- Rev 0.8 4 Apr 1996 Changed for PQ2 Package -- Rev 0.7 18 Dec 1995 Updated for A-1 stepping. -- Rev 0.6 08 Dec 1994 -- Rev 0.5 21 Nov 1994 -- Rev 0.4 31 Oct 1994 -- Rev 0.3 26 July 1994 -- Rev 0.2 22 June 1994 -- Rev 0.1 16 Mar 1994 -- Rev 0.0 30 Aug 1993
Advance InformationDatasheet 89 entity Ha_Processor is generic(PHYSICAL_PIN_MAP : string:= “PQ2”); port (A : out bit_vector(2 to 31); ADSBAR : out bit; BEBAR : out bit_vector(0 to 3); BLASTBAR : out bit; BOFFBAR : in bit; BREQ : out bit; BSTALL : out bit; BTERMBAR : in bit; CT : out bit_vector(0 to 3); CLKIN : in bit; D : inout bit_vector(0 to 31); DENBAR : out bit; DP : inout bit_vector(0 to 3); DTRBAR : out bit; DCBAR : out bit; FAILBAR : out bit; HOLD : in bit; HOLDA : out bit; LOCKBAR : out bit; NMIBAR : in bit; ONCEBAR : in bit; PCHKBAR : out bit; READYBAR : in bit; RESETBAR : in bit; STEST : in bit; SUPBAR : out bit; TCK : in bit; TDI : in bit; TDO : out bit; TMS : in bit; TRST : in bit; WAITBAR : out bit; WRBAR : out bit; XINTBAR : in bit_vector(0 to 7); FIVEVREF : linkage bit; VCCPLL : linkage bit; Example 2. Boundary-Scan Description Language (BSDL) for PQ2 Package Example (Sheet 2 of 8)
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VCC1 : linkage bit_vector(0 to 23); VCC2 : linkage bit_vector(0 to 23); VSS1 : linkage bit_vector(0 to 23); VSS2 : linkage bit_vector(0 to 23) use STD_1149_1_1990.all; use i960ha_a.all; attribute PIN_MAP of Ha_Processor : entity is PHYSICAL_PIN_MAP; constant PQ2:PIN_MAP_STRING := “ 135, 134, 133, 132, 127, 126, 125, 124, 121, 120,”& “ADSBAR : 77,”& “BLASTBAR : 84,”& “BOFFBAR : 10,”& “BREQ : 100,”& “BSTALL : 91,”& “BTERMBAR : 67,”& “CLKIN : 175,”& “DENBAR : 85,”& “DTRBAR : 89,”& “DCBAR : 96,”& “FAILBAR : 5,”& “HOLD : 69,”& “HOLDA : 72,”& “LOCKBAR : 99,”& “NMIBAR : 159,”& Example 2. Boundary-Scan Description Language (BSDL) for PQ2 Package Example (Sheet 3 of 8)
Advance InformationDatasheet 91 “ONCEBAR : 6,”& “PCHKBAR : 189,”& “READYBAR : 68,”& “RESETBAR : 174,”& “STEST : 208,”& “SUPBAR : 97,”& “TCK : 194,”& “TDI : 191,”& “TDO : 188,”& “TMS : 192,”& “TRST : 193,”& “WAITBAR : 90,”& “WRBAR : 88,”& “FIVEVREF : 197,”& “VCCPLL : 177,”& “VCC2 : (102, 109, 115, 117, 123, 128, 131, 137, 143, 149,”& “ 153, 154, 158, 165, 171, 173, 176, 179, 185, 187,”& “VSS2 : (108, 114, 116, 122, 129, 130, 136, 142, 148, 152,”& “ 155, 156, 157, 164, 170, 172, 178, 184, 186, 190,”& attribute Tap_Scan_In of TDI : signal is true; attribute Tap_Scan_Mode of TMS : signal is true; attribute Tap_Scan_Out of TDO : signal is true; attribute Tap_Scan_Reset of TRST : signal is true; attribute Tap_Scan_Clock of TCK : signal is (66.0e6, BOTH); attribute Instruction_Length of Ha_Processor: entity is 4; attribute Instruction_Opcode of Ha_Processor: entity is Example 2. Boundary-Scan Description Language (BSDL) for PQ2 Package Example (Sheet 4 of 8)
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“BYPASS (1111),” & “EXTEST (0000),” & “SAMPLE (0001),” & “IDCODE (0010),” & “RUBIST (0111),” & “CLAMP (0100),” & “HIGHZ (1000),” & “Reserved (1011, 1100)”; attribute Instruction_Capture of Ha_Processor: entity is “0001”; attribute Instruction_Private of Ha_Processor: entity is “Reserved” ; attribute Idcode_Register of Ha_Processor: entity is “0001” & version, “1000100001000000” & part number “00000001001”& manufacturers identity “1”; required by the standard attribute Register_Access of Ha_Processor: entity is “Runbist[32] (RUBIST),” & “Bypass (CLAMP, HIGHZ)”; { The first cell, cell 0, is closest to TDO } { BC_1:Control, Output3 CBSC_1:Bidir BC_4: Input, Clock } attribute Boundary_Cells of Ha_Processor: entity is “BC_4, BC_1, CBSC_1”; attribute Boundary_Length of Ha_Processor: entity is 112; attribute Boundary_Register of Ha_Processor: entity is “0 (CBSC_1, DP(3), bidir, X, 17, 1, Z),” & “1 (CBSC_1, DP(2), bidir, X, 17, 1, Z),” & “2 (CBSC_1, DP(0), bidir, X, 17, 1, Z),” & “3 (CBSC_1, DP(1), bidir, X, 17, 1, Z),” & “4 (BC_4, STEST, input, X),” & “5 (BC_1, FAILBAR, output3, X, 6, 1, Z),” & Example 2. Boundary-Scan Description Language (BSDL) for PQ2 Package Example (Sheet 5 of 8)
Advance InformationDatasheet 93 “6 (BC_1, *, control, 1),” & “7 (BC_4, ONCEBAR, input, X),” & “8 (BC_4, BOFFBAR, input, X),” & “9 (CBSC_1, D(0), bidir, X, 17, 1, Z),” & “10 (CBSC_1, D(1), bidir, X, 17, 1, Z),” & “11 (CBSC_1, D(2), bidir, X, 17, 1, Z),” & “12 (CBSC_1, D(3), bidir, X, 17, 1, Z),” & “13 (CBSC_1, D(4), bidir, X, 17, 1, Z),” & “14 (CBSC_1, D(5), bidir, X, 17, 1, Z),” & “15 (CBSC_1, D(6), bidir, X, 17, 1, Z),” & “16 (CBSC_1, D(7), bidir, X, 17, 1, Z),” & “17 (BC_1, *, control, 1),” & “18 (CBSC_1, D(8), bidir, X, 17, 1, Z),” & “19 (CBSC_1, D(9), bidir, X, 17, 1, Z),” & “20 (CBSC_1, D(10), bidir, X, 17, 1, Z),” & “21 (CBSC_1, D(11), bidir, X, 17, 1, Z),” & “22 (CBSC_1, D(12), bidir, X, 17, 1, Z),” & “23 (CBSC_1, D(13), bidir, X, 17, 1, Z),” & “24 (CBSC_1, D(14), bidir, X, 17, 1, Z),” & “25 (CBSC_1, D(15), bidir, X, 17, 1, Z),” & “26 (CBSC_1, D(16), bidir, X, 17, 1, Z),” & “27 (CBSC_1, D(17), bidir, X, 17, 1, Z),” & “28 (CBSC_1, D(18), bidir, X, 17, 1, Z),” & “29 (CBSC_1, D(19), bidir, X, 17, 1, Z),” & “30 (CBSC_1, D(20), bidir, X, 17, 1, Z),” & “31 (CBSC_1, D(21), bidir, X, 17, 1, Z),” & “32 (CBSC_1, D(22), bidir, X, 17, 1, Z),” & “33 (CBSC_1, D(23), bidir, X, 17, 1, Z),” & “34 (CBSC_1, D(24), bidir, X, 17, 1, Z),” & “35 (CBSC_1, D(25), bidir, X, 17, 1, Z),” & “36 (CBSC_1, D(26), bidir, X, 17, 1, Z),” & “37 (CBSC_1, D(27), bidir, X, 17, 1, Z),” & “38 (CBSC_1, D(28), bidir, X, 17, 1, Z),” & “39 (CBSC_1, D(29), bidir, X, 17, 1, Z),” & “40 (CBSC_1, D(30), bidir, X, 17, 1, Z),” & Example 2. Boundary-Scan Description Language (BSDL) for PQ2 Package Example (Sheet 6 of 8)
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“41 (CBSC_1, D(31), bidir, X, 17, 1, Z),” & “42 (BC_4, BTERMBAR, input, X),” & “43 (BC_4, READYBAR, input, X),” & “44 (BC_4, HOLD, input, X),” & “45 (BC_1, HOLDA, output3, X, 46, 1, Z),” & “46 (BC_1, *, control, 1),” & “47 (BC_1, ADSBAR, output3, X, 61, 1, Z),” & “48 (BC_1, BEBAR(3), output3, X, 61, 1, Z),” & “49 (BC_1, BEBAR(2), output3, X, 61, 1, Z),” & “50 (BC_1, BEBAR(1), output3, X, 61, 1, Z),” & “51 (BC_1, BEBAR(0), output3, X, 61, 1, Z),” & “52 (BC_1, BLASTBAR, output3, X, 61, 1, Z),” & “53 (BC_1, DENBAR, output3, X, 61, 1, Z),” & “54 (BC_1, WRBAR, output3, X, 61, 1, Z),” & “55 (BC_1, DTRBAR, output3, X, 56, 1, Z),” & “56 (BC_1, *, control, 1),” & “57 (BC_1, WAITBAR, output3, X, 61, 1, Z),” & “58 (BC_1, BSTALL, output3, X, 6, 1, Z),” & “59 (BC_1, DCBAR, output3, X, 61, 1, Z),” & “60 (BC_1, SUPBAR, output3, X, 61, 1, Z),” & “61 (BC_1, *, control, 1),” & “62 (BC_1, LOCKBAR, output3, X, 61, 1, Z),” & “63 (BC_1, BREQ, output3, X, 6, 1, Z),” & “64 (BC_1, A(31), output3, X, 80, 1, Z),” & “65 (BC_1, A(30), output3, X, 80, 1, Z),” & “66 (BC_1, A(29), output3, X, 80, 1, Z),” & “67 (BC_1, A(28), output3, X, 80, 1, Z),” & “68 (BC_1, A(27), output3, X, 80, 1, Z),” & “69 (BC_1, A(26), output3, X, 80, 1, Z),” & “70 (BC_1, A(25), output3, X, 80, 1, Z),” & “71 (BC_1, A(24), output3, X, 80, 1, Z),” & “72 (BC_1, A(23), output3, X, 80, 1, Z),” & “73 (BC_1, A(22), output3, X, 80, 1, Z),” & “74 (BC_1, A(21), output3, X, 80, 1, Z),” & “75 (BC_1, A(20), output3, X, 80, 1, Z),” & Example 2. Boundary-Scan Description Language (BSDL) for PQ2 Package Example (Sheet 7 of 8)
Advance InformationDatasheet 95 “76 (BC_1, A(19), output3, X, 80, 1, Z),” & “77 (BC_1, A(18), output3, X, 80, 1, Z),” & “78 (BC_1, A(17), output3, X, 80, 1, Z),” & “79 (BC_1, A(16), output3, X, 80, 1, Z),” & “80 (BC_1, *, control, 1),” & “81 (BC_1, A(15), output3, X, 80, 1, Z),” & “82 (BC_1, A(14), output3, X, 80, 1, Z),” & “83 (BC_1, A(13), output3, X, 80, 1, Z),” & “84 (BC_1, A(12), output3, X, 80, 1, Z),” & “85 (BC_1, A(11), output3, X, 80, 1, Z),” & “86 (BC_1, A(10), output3, X, 80, 1, Z),” & “87 (BC_1, A(9), output3, X, 80, 1, Z),” & “88 (BC_1, A(8), output3, X, 80, 1, Z),” & “89 (BC_1, A(7), output3, X, 80, 1, Z),” & “90 (BC_1, A(6), output3, X, 80, 1, Z),” & “91 (BC_1, A(5), output3, X, 80, 1, Z),” & “92 (BC_1, A(4), output3, X, 80, 1, Z),” & “93 (BC_1, A(3), output3, X, 80, 1, Z),” & “94 (BC_1, A(2), output3, X, 80, 1, Z),” & “95 (BC_4, NMIBAR, input, X),” & “96 (BC_4, XINTBAR(7), input, X),” & “97 (BC_4, XINTBAR(6), input, X),” & “98 (BC_4, XINTBAR(5), input, X),” & “99 (BC_4, XINTBAR(4), input, X),” & “100(BC_4, XINTBAR(3), input, X),” & “101(BC_4, XINTBAR(2), input, X),” & “102(BC_4, XINTBAR(1), input, X),” & “103(BC_4, XINTBAR(0), input, X),” & “104(BC_4, RESETBAR, input, X),” & “105(BC_4, CLKIN, input, X),” & “106(BC_1, CT(3), output3, X, 80, 1, Z),” & “107(BC_1, CT(2), output3, X, 80, 1, Z),” & “108(BC_1, CT(1), output3, X, 80, 1, Z),” & “109(BC_1, CT(0), output3, X, 80, 1, Z),” & “110(BC_1, PCHKBAR, output3, X, 111,1, Z),” & “111(BC_1, *, control, 1)”; end Ha_Processor; Example 2. Boundary-Scan Description Language (BSDL) for PQ2 Package Example (Sheet 8 of 8)
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Table 26. Data Sheet Version -006 to -007 Revision History Entire data sheet Formatted in new template. Copyright Page Updated legal text. Section 3.0, “Package Information” on page 6 Added paaragraph two andTable 5. Corrected minor typeset and spacing errors. ONCE ; last sentence, changed “low” to “high”. Top (Pins Facing Down)” on page 12 Added insert package marking diagram. Figure 4 “80960Hx 208-Pin PQ4 Pinout” on page 18Added insert package marking diagram. Section 4.5, “VCCPLL Pin Requirements” on page 31Added section. Added footnote (10) to “CIN,C OUT and CI/O”p i n . Added overbars where required. on page 43 Changed “5” to “0” on “CLKIN Frequency” axis. Figure 49 “BREQ and BSTALL Operation” on page 66Added figure and following text.