80960CA-25 INTEL | Alldatasheet
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Datasheet sections
December 1994 Order Number: 271327-001 SPECIAL ENVIRONMENT 80960CA-25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR # Two Instructions/Clock Sustained Execution # Four 59 Mbytes/s DMA Channels with Data Chaining # Demultiplexed 32-bit Burst Bus with Pipelining Y 32-bit Parallel Architecture Ð Two Instructions/clock Execution Ð Load/Store Architecture Ð Sixteen 32-bit Global Registers Ð Sixteen 32-bit Local Registers Ð Manipulates 64-bit Bit Fields Ð 11 Addressing Modes Ð Full Parallel Fault Model Ð Supervisor Protection Model Y Fast Procedure Call/Return Model Ð Full Procedure Call in 4 Clocks Y On-Chip Register Cache Ð Caches Registers on Call/Ret Ð Minimum of 6 Frames Provided Ð Up to 15 Programmable Frames Y On-Chip instruction Cache Ð 1 Kbyte Two-Way Set Associative Ð 128-bit Path to instruction Sequencer Ð Cache-Lock Modes Ð Cache-Off Mode Y High Bandwidth On-Chip Data RAM Ð 1 Kbyte On-Chip Data RAM Ð Sustains 128 bits per Clock Access Y Four On-Chip DMA Channels Ð 59 Mbytes/s Fly-by Transfers Ð 32 Mbytes/s Two-Cycle Transfers Ð Data Chaining Ð Data Packing/Unpacking Ð Programmable Priority Method Y 32-Bit Demultiplexed Burst Bus Ð 128-bit internal Data Paths to and from Registers Ð Burst Bus for DRAM Interfacing Ð Address Pipelining Option Ð Fully Programmable Wait States Ð Supports 8-, 16- or 32-bit Bus Widths Ð Supports Unaligned Accesses Ð Supervisor Protection Pin Y Selectable Big or Little Endian Byte Ordering Y High-Speed Interrupt Controller Ð Up to 248 External interrupts Ð 32 Fully Programmable Priorities Ð Multi-mode 8-bit Interrupt Port Ð Four internal DMA Interrupts Ð Separate, Non-maskable interrupt Pin Ð Context Switch in 750 ns Typical Y Product Grades Available Ð SE3: b40§Ct o a110§C
SPECIAL ENVIRONMENT 80960CA-25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR CONTENTS PAGE
1.0 PURPOSE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5
2.0 80960CA OVERVIEW ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5
2.1 The C-Series Core ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6
2.2 Pipelined, Burst Bus ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6
2.3 Flexible DMA Controller ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6
2.4 Priority Interrupt Controller ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6
2.5 Instruction Set Summary ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7
3.0 PACKAGE INFORMATION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8
3.1 Package Introduction ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8
3.2 Pin Descriptions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8
3.3 80960CA Mechanical Data ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 15 3.3.1 80960CA PGA Pinout ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 15
3.4 Package Thermal Specifications ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 19
3.5 Stepping Register Information ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 21
3.6 Suggested Sources for 80960CA Accessories ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 21
4.0 ELECTRICAL SPECIFICATIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22
4.1 Absolute Maximum Ratings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22
4.2 Operating Conditions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22
4.3 Recommended Connections ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22
4.4 DC Specifications ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 23
4.5 AC Specifications ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 24
4.5.1 AC Test Conditions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 28
4.5.2 AC Timing Waveforms ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 28
4.5.3 Derating Curves ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 32
5.0 RESET, BACKOFF AND HOLD ACKNOWLEDGE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 34
6.0 BUS WAVEFORMS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 35
7.0 REVISION HISTORY ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 62
1.0 PURPOSE
80960 Core Architecture while including Special
64-bit operands and configure on-chip hardware. three instructions per clock. cost sensitive, main memory subsystem. Figure 1. 80960CA Block Diagram
SPECIAL ENVIRONMENT 80960CA-25, -16
2.1 The C-Series Core
The C-Series core is a very high performance micro- architectural implementation of the 80960 Core Ar- chitecture. The C-Series core can sustain execution of two instructions per clock (50 MIPs at 25 MHz). To achieve this level of performance, Intel has incor- porated state-of-the-art silicon technology and inno- vative microarchitectural constructs into the imple- mentation of the C-Series core. Factors that contrib- ute to the core’s performance include: # Parallel instruction decoding allows issuance of up to three instructions per clock # Single-clock execution of most instructions # Parallel instruction decode allows sustained, simultaneous execution of two single-clock in- structions every clock cycle # Efficient instruction pipeline minimizes pipeline break losses # Register and resource scoreboarding allow simul- taneous multi-clock instruction execution # Branch look-ahead and prediction allows many branches to execute with no pipeline break # Local Register Cache integrated on-chip caches Call/Return context # Two-way set associative, 1 Kbyte integrated in- struction cache # 1 Kbyte integrated Data RAM sustains a four- word (128-bit) access every clock cycle
2.2 Pipelined, Burst Bus
A 32-bit high performance bus controller interfaces the 80960CA to external memory and peripherals. The Bus Control Unit features a maximum transfer rate of 100 Mbytes per second (at 25 MHz). Internal- ly programmable wait states and 16 separately con- figurable memory regions allow the processor to in- terface with a variety of memory subsystems with a minimum of system complexity and a maximum of performance. The Bus Controller’s main features in- clude: # Demultiplexed, Burst Bus to exploit most efficient DRAM access modes # Address Pipelining to reduce memory cost while maintaining performance # 32-, 16- and 8-bit modes for I/O interfacing ease # Full internal wait state generation to reduce sys- tem cost # Little and Big Endian support to ease application development # Unaligned access support for code portability # Three-deep request queue to decouple the bus from the core
2.3 Flexible DMA Controller
A four-channel DMA controller provides high speed DMA control for data transfers involving peripherals and memory. The DMA provides advanced features such as data chaining, byte assembly and disassem- bly and a high performance fly-by mode capable of transfer speeds of up to 45 Mbytes per second at 25 MHz. The DMA controller features a performance and flexibility which is only possible by integrating the DMA controller and the 80960CA core.
2.4 Priority interrupt Controller
A programmable-priority interrupt controller man- ages up to 248 external sources through the 8-bit external interrupt port. The interrupt Unit also han- dles the four internal sources from the DMA control- ler and a single non-maskable interrupt input. The 8-bit interrupt port can also be configured to provide individual interrupt sources that are level or edge triggered. Interrupts in the 80960CA are prioritized and sig- naled within 270 ns of the request. If the interrupt is of higher priority than the processor priority, the con- text switch to the interrupt routine typically is com- plete in another 480 ns. The interrupt unit provides the mechanism for the low latency and high through- put interrupt service which is essential for embedded applications.
2.5 Instruction Set Summary
User’s Manual for a complete description of the instruction set. Table 1. 80960CA Instruction Set
3.0 PACKAGE INFORMATION
3.1 Package Introduction
Packaging Handbook (Order No. 240800).
3.2 Pin Descriptions
troller and Interrupt Unit are described in Table 5. Table 2. Pin Description Nomenclature
Table 3. 80960CA Pin DescriptionÐExternal Bus Signals indicate the selected byte in each word. During burst accesses, A3:2 increment toR(Z) indicate successive data cycles. D7:0 are used. For 16-bit data bus widths, D15:0 are used. For 32 bit bus widths theR(Z) full data bus is used. processor uses the BE3 , BE1 and BE0 pins as BHE , A1 and BLE respectively. processor uses the BE1 and BE0 pins as A1 and A0 respectively. ADS O ADDRESS STROBE indicates a valid address and the start of a new bus access.
Table 3. 80960CA Pin DescriptionÐExternal Bus Signals (Continued) states. The N XDA wait states cannot be extended. strobe. WAIT can also be thought of as a READY output that the processorR(1) provides when it is inserting wait states. READY or BTERM terminates the access. the processor receives data. Conversely, when deasserted, the processorR(0) sends data. DT/R changes only while DEN is high. performs DMA transfers while LOCK is active.
asserted, the state of the HOLDA pin is independent of the RESET pin. BREQ O BUS REQUEST is asserted when the bus controller has a request pending.
Table 4. 80960CA Pin DescriptionÐProcessor Control Signals clock division of the CLKIN pin. state, the processor bus will grant HOLDA and enter the Hold Acknowledge state. be disabled with the STEST pin. initialization. When deasserted, only the bus confidence tests are performed duringR(Z) initialization. and bring ONCE high prior to deasserting RESET . possible ONCE mode leakage current. installed processor transparent in the board.
Table 4. 80960CA Pin DescriptionÐProcessor Control Signals (Continued) CLKMODE I CLOCK MODE selects the division factor applied to the external clock input (CLKIN). processor will internally pull the CLKMODE pin low, enabling the 2-x clock mode. flexibility in the system’s allocation of capacitive loading on the clock. PCLK2:1 mayR(Q) also be connected at the processor to form a single clock signal. VSS Ð GROUND connections must be connected externally to a V SS board plane. VCC Ð POWER connections must be connected externally to a V CC board pane. VCCPLL Ð VCCPLL is a separate V CC supply pin for the phase lock loop used in 1-x clock mode. implemented starting with the D-stepping. See Table 13 for die stepping information. NC Ð NO CONNECT pins must not be connected in a system.
Table 5. 80960CA Pin DescriptionÐDMA and Interrupt Unit Control Signals simultaneously, the channel with the highest priority is serviced first. TheR(Z) channel priority mode is programmable. DACK3:0 O DMA ACKNOWLEDGE indicates that a DMA transfer is being executed. be level (low) or edge (falling) activated.
Table 6. 80960CA PGA PinoutÐIn Signal Order
Table 7. 80960CA PGA PinoutÐIn Pin Order
Figure 2. 80960CA PGA PinoutÐView from Top (Pins Facing Down)
Figure 3. 80960CA PGA PinoutÐView from Bottom (Pins Facing Up)
3.4 Package Thermal Specifications
the pins. Refer to Figure 4. Figure 4. Measuring 80960CA PGA Case Temperature Table 8. Maximum T A at Various Airflows in §C 0.285× high undirectional heatsink (Al alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing).
Table 9. 80960CA PGA Package Thermal Characteristics
- This table applies to 80960CA PGA plugged into socket or soldered directly to board.
*0.285× high unidirectional heatsink (Al alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing).
3.5 Stepping Register Information
Figure 5. Register g0 Table 10. Die Stepping Cross Reference
02 C-1
03 C-2,C-3
3.6 Suggested Sources for 80960CA
any of the listed products and/or companies.
- 3M Textool Test and Interconnection
33 Perry Avenue
- Concept Manufacturing, Inc.
41484 Christy Street
2021 West Valley View Lane
60 Audubon Road
4.0 ELECTRICAL SPECIFICATIONS
4.1 Absolute Maximum Ratings
cations are subject to change without notice. Maximum Ratings’’ may cause permanent damage. may affect device reliability.
4.2 Operating Conditions
Table 11. Operating Conditons (80960CA-25, -16)
- When in the 1-x input clock mode, CLKIN is an input to an internal phase-locked loop and must maintain a minimum
CLKIN restarts and has stabilized.
- Case temperatures are ‘‘instant on’’.
4.3 Recommended Connections
used input should be connected to ground. N.C. Number 270710) for more information.
4.4 DC Specifications
Table 12. DC Characteristics
- These pins have internal pullup resistors.
- These pins have internal pulldown resistors.
- Measured at worst case frequency, V
described in Section 4.5.1, AC Test Conditions .
- I CC Typical is not tested.
- Output Capacitance is the capacitive load of a floating output.
- CLKMODE pin has a pulldown resistor only when ONCE
4.5 AC Specifications
Table 13. 80960CA AC Characteristics (25 MHz)
Table 13. 80960CA AC Characteristics (25 MHz) (Continued)
- See Section 4.5.2, AC Timing Waveforms for waveforms and definitions.
- See Figure 16 for capacitive derating information for output delays and hold times.
- See Figure 17 for capacitive derating information for rise and fall times.
- Where N is the number of N
Table. WAIT never goes active when there are no wait states in an access.
- N e Number of wait states inserted with READY .
- Output Data and/or DT/R may be driven indefinitely following a cycle if there is no subsequent bus activity.
- Since asynchronous inputs are synchronized internally by the 80960CA, they have no required setup or hold times to be
edges to be seen by the processor.
- These specifications are guaranteed by the processor.
- These specifications must be met by the system for proper operation of the processor.
- This timing is dependent upon the loading of PCLK2:1. Use the derating curves of Section 4.5.3, Derating Curves to
adjust the timing for PCLK2:1 loading.
- In the 1-x input clock mode, the maximum input clock period is limited to 125 ns while the processor is operating. When
the processor is in reset, the input clock may stop even in 1-x mode.
- When in the 1-x input clock mode, these specifications assume a stable input clock with a period variation of less than
g0.1% between adjacent cycles.
- In 2-x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation.
and hold times to the falling edge of the CLKIN. (See Figure 21).
- In 1-x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation.
- The interrupt pins are synchronized internally by the 80960CA. They have no required setup or hold times for proper
edge, the setup and hold times shown must be met for two consecutive PCLK2:1 rising edges.
Table 14. 80960CA AC Characteristics (16 MHz)
Table 14. 80960CA AC Characteristics (16 MHz) (Continued)
- See Section 4.5.2, AC Timing Waveforms for waveforms and definitions.
- See Figure 16 for capacitive derating information for output delays and hold times.
- See Figure 17 for capacitive derating information for rise and fall times.
- Where N is the number of N
Table. WAIT never goes active when there are no wait states in an access.
- N e Number of wait states inserted with READY .
- Output Data and/or DT/R may be driven indefinitely following a cycle if there is no subsequent bus activity.
- Since asynchronous inputs are synchronized internally by the 80960CA, they have no required setup or hold times to be
edges to be seen by the processor.
- These specifications are guaranteed by the processor.
- These specifications must be met by the system for proper operation of the processor.
- This timing is dependent upon the loading of PCLK2:1. Use the derating curves of Section 4.5.3, Derating Curves to
adjust the timing for PCLK2:1 loading.
- In the 1-x input clock mode, the maximum input clock period is limited to 125 ns while the processor is operating. When
the processor is in reset, the input clock may stop even in 1-x mode.
- When in the 1-x input clock mode, these specifications assume a stable input clock with a period variation of less than
g0.1% between adjacent cycles.
- In 2-x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation.
and hold times to the falling edge of the CLKIN. (See Figure 21).
- In 1-x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation.
- The interrupt pins are synchronized internally by the 80960CA. They have no required setup or hold times for proper
edge, the setup and hold times shown must be met for two consecutive PCLK2:1 rising edges.
4.5.1 AC Test Conditions
how timings vary with load capacitance. Figure 6. AC Test Load
4.5.2 AC Timing Waveforms
Figure 7. Input and Output Clock Waveforms Figure 8. CLKIN Waveform
Figure 13. Bus Backoff BOFF Timings
Figure 14. Relative Timings Waveforms
4.5.3 Derating Curves
Figure 15. Output Delay or Hold vs Load Capacitance
5.0 RESET, BACKOFF AND HOLD
pin while RESET is asserted (low). Table 15. Reset Conditions
- With regard to bus output pin state only, the Hold Ac-
knowledge state takes precedence over the reset state. enter the Hold Acknowledge state even while in reset. among multiple processors sharing the same bus. pin while HOLDA is asserted (low). Table 16. Hold Acknowledge and Backoff
6.0 BUS WAVEFORMS
Figure 18. Cold Reset Waveform
Figure 19. Warm Reset Waveform
Figure 20. Entering the ONCE State
Figure 23. Non-Burst, Non-Pipelined Requests Without Wait States
Figure 24. Non-Burst, Non-Pipelined Read Request With Wait States
Figure 25. Non-Burst, Non-Pipelined Write Request With Wait States
Figure 26. Burst, Non-Pipelined Read Request Without Wait States, 32-Bit Bus
Figure 27. Burst, Non-Pipelined Read Request With Wait States, 32-Bit Bus
Figure 28. Burst, Non-Pipelined Write Request Without Wait States, 32-Bit Bus
Figure 29. Burst, Non-Pipelined Write Request With Wait States, 32-Bit Bus
Figure 30. Burst, Non-Pipelined Read Request With Wait States, 16-Bit Bus
Figure 31. Burst, Non-Pipelined Read Request With Wait States, 8-Bit Bus
Figure 32. Non-Burst, Pipelined Read Request Without Wait States, 32-Bit Bus
Figure 33. Non-Burst, Pipelined Read Request With Wait States, 32-Bit Bus
Figure 34. Burst, Pipelined Read Request Without Wait States, 32-Bit Bus
Figure 35. Burst, Pipelined Read Request With Wait States, 32-Bit Bus
Figure 36. Burst, Pipelined Read Request With Wait States, 16-Bit Bus
Figure 37. Burst, Pipelined Read Request With Wait States, 8-Bit Bus
Figure 38. Using External READY
signal will terminate a bus access if the signal is asserted during the last (or only) data transfer of the bus access. Figure 39. Terminating a Burst with BTERM
Figure 40. BOFF Functional Timing
Figure 41. HOLD Functional Timing
Figure 46. A Summary of Aligned and Unaligned Transfers for Little Endian Regions
Figure 47. A Summary of Aligned and Unaligned Transfers for Little Endian Regions (Continued)
Figure 48. Idle Bus Operation