80960JA INTEL | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1.0 Introduction
- 2.2 Burst Bus
- 2.3 Timer Unit
- 2.4 Priority Interrupt Controller
- 2.5 Instruction Set Summary
- 2.6 Faults and Debugging
- 2.7 Low Power Operation
- 2.8 Test Features
- 2.9 Memory-Mapped Control Registers
- 2.10 Data Types and Memory Addressing Modes
- 3.0 Package Information
- 3.1 Pin Descriptions
- 3.1.1 Functional Pin Definitions
- 3.2 Package Thermal Specifications
- 3.3 Thermal Management Accessories
- 3.3.1 Heatsinks
- 4.0 Electrical Specifications
- 4.1 Absolute Maximum Ratings
- 4.2 Operating Conditions
- 4.3 Connection Recommendations
- 4.4 VCC5 Pin Requirements (VDIFF)
- 4.5 VCCPLL Pin Requirements
- 4.6 DC Specifications
- 4.7 AC Specifications
- 4.7.1 AC Test Conditions and Derating Curves
- 4.7.2 AC Timing Waveforms
- 5.0 Bus Functional Waveforms
- 5.1 Basic Bus States
- 5.2 Boundary-Scan Register
- 6.0 Device Identification
- 7.0 Revision History
80960JA/JF/JD/JT 3.3 V EMBEDDED 32-BIT MICROPROCESSOR Advance Information Datasheet Product Features ■ Pin/Code Compatible with all 80960Jx Processors ■ High-Performance Embedded Architecture —One Instruction/Clock Execution —Core Clock Rate is: 80960JA/JF 1x the Bus Clock 80960JD 2x the Bus Clock 80960JT 3x the Bus Clock —Load/Store Programming Model —Sixteen 32-Bit Global Registers —Sixteen 32-Bit Local Registers (8 sets) —Nine Addressing Modes —User/Supervisor Protection Model ■ Two-Way Set Associative Instruction Cache —80960JA - 2 Kbyte —80960JF/JD - 4 Kbyte —80960JT - 16 Kbyte —Programmable Cache-Locking Mechanism ■ Direct Mapped Data Cache —80960JA - 1 Kbyte —80960JF/JD - 2 Kbyte —80960JT - 4 Kbyte —Write Through Operation ■ On-Chip Stack Frame Cache —Seven Register Sets Can Be Saved —Automatic Allocation on Call/Return —0-7 Frames Reserved for High-Priority Interrupts ■ On-Chip Data RAM —1 Kbyte Critical Variable Storage —Single-Cycle Access ■ 3.3 V Supply V oltage —5 V Tolerant Inputs —TTL Compatible Outputs ■ High Bandwidth Burst Bus —32-Bit Multiplexed Address/Data —Programmable Memory Configuration —Selectable 8-, 16-, 32-Bit Bus Widths —Supports Unaligned Accesses —Big or Little Endian Byte Ordering ■ High-Speed Interrupt Controller —31 Programmable Priorities —Eight Maskable Pins plus NMI —Up to 240 Vectors in Expanded Mode ■ Two On-Chip Timers —Independent 32-Bit Counting —Clock Prescaling by 1, 2, 4 or 8 —lnternal Interrupt Sources ■ Halt Mode for Low Power ■ IEEE 1149.1 (JTAG) Boundary Scan Compatibility ■ Packages —132-Lead Pin Grid Array (PGA) —132-Lead Plastic Quad Flat Pack (PQFP) —196-Ball Mini Plastic Ball Grid Array (MPBGA) Order Number: 273159-001 March, 1998 Notice: This document contains information on products in the sampling and initial production phases of development. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.
80960JA/JF/JD/JT 3.3 V Microprocessor Advance Information Datasheet Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 80960JA/JF/JD/JT 3.3 V Microprocessor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © Intel Corporation, 1998 *Third-party brands and names are the property of their respective owners.
80960JA/JF/JD/JT 3.3 V Microprocessor
4 Advance Information Datasheet
37 Burst Read and Write Transactions With 1, 0 Wait States and
38 Double Word Read Bus Request, Misaligned One Byte From
Advance Information Datasheet 5 80960JA/JF/JD/JT 3.3 V Microprocessor Tables
15 Maximum T
1.0 Introduction
- 80960JA — 3.3 V (5 V Tolerant), 2 Kbyte instruction cache, 1 Kbyte data cache
- 80960JF — 3.3 V (5 V Tolerant), 4 Kbyte instruction cache, 2 Kbyte data cache
- 80960JD — 3.3 V (5 V Tolerant), 4 Kbyte instruction cache, 2 Kbyte data cache and clock doubling
- 80960JT — 3.3 V (5 V Tolerant), 16 Kbyte instruction cache, 4 Kbyte data cache and clock tripling 2.0 80960Jx Overview The 80960Jx offers high performance to cost-sensitive 32-bit embedded applications. The 80960Jx is object code compatible with the 80960 Core Architecture and is capable of sustained execution at the rate of one instruction per clock. This processor’s features include generous instruction cache, data cache and data RAM. It also boasts a fast interrupt mechanism and dual-programmable timer units. The 80960Jx’s clock multiplication operates the processor core at two or three times the bus clock rate to improve execution performance without increasing the complexity of board designs. Memory subsystems for cost-sensitive embedded applications often impose substantial wait state penalties. The 80960Jx integrates considerable storage resources on-chip to decouple CPU execution from the external bus.
Figure 1. 80960Jx Microprocessor Package Options
80960JA/JF/JD/JT 3.3 V Microprocessor
8 Advance Information Datasheet
The 80960Jx rapidly allocates and deallocates local register sets during context switches. The processor needs to flush a register set to the stack only when it saves more than seven sets to its local register cache. A 32-bit multiplexed burst bus provides a high-speed interface to system memory and I/O. A full complement of control signals simplifies the connection of the 80960Jx to external components. The user programs physical and logical memory attributes through memory-mapped control registers (MMRs) — an extension not found on the i960 Kx, Sx or Cx processors. Physical and logical configuration registers enable the processor to operate with all combinations of bus width and data object alignment. The processor supports a homogeneous byte ordering model. This processor integrates two important peripherals: a timer unit, and an interrupt controller. These and other hardware resources are programmed through memory-mapped control registers, an extension to the familiar 80960 architecture. The timer unit (TU) offers two independent 32-bit timers for use as real-time system clocks and general-purpose system timing. These operate in either single-shot or auto-reload mode and can generate interrupts. The interrupt controller unit (ICU) provides a flexible, low-latency means for requesting interrupts. The ICU provides full programmability of up to 240 interrupt sources into 31 priority levels. The ICU takes advantage of a cached priority table and optional routine caching to minimize interrupt latency. Clock doubling reduces interrupt latency by 40% compared to the 80960JA/JF, and clock tripling reduces interrupt latency by 20% compared to the 80960JD. Local registers may be dedicated to high-priority interrupts to further reduce latency. Acting independently from the core, the ICU compares the priorities of posted interrupts with the current process priority, off-loading this task from the core. The ICU also supports the integrated timer interrupts. The 80960Jx features a Halt mode designed to support applications where low power consumption is critical. The halt instruction shuts down instruction execution, resulting in a power savings of up to 90 percent. The 80960Jx’s testability features, including ONCE (On-Circuit Emulation) mode and Boundary Scan (JTAG), provide a powerful environment for design debug and fault diagnosis. The Solutions960 ® program features a wide variety of development tools which support the i960 processor family. Many of these tools are developed by partner companies; some are developed by Intel, such as profile-driven optimizing compilers. For more information on these products, contact your local Intel representative.
- Core operates at the bus speed with the 80960JA/JF
- Core operates at two or three times the bus speed with the 80960JD and 80960JT respectively
- Single-clock execution of most instructions
- Independent Multiply/Divide Unit
- Efficient instruction pipeline minimizes pipeline break latency
- Register and resource scoreboarding allow overlapped instruction execution
- 128-bit register bus speeds local register caching
- Two-way set associative, integrated instruction cache
- Direct-mapped, integrated data cache
- 1 Kbyte integrated data RAM delivers zero wait state program data
Figure 2. 80960Jx Block Diagram
3 Independent 32-Bit SRC1, SRC2, and DEST Buses
80960JA/JF/JD/JT 3.3 V Microprocessor
10 Advance Information Datasheet
2.2 Burst Bus
A 32-bit high-performance Bus Controller Unit (BCU) interfaces the 80960Jx to external memory and peripherals. The BCU fetches instructions and transfers data at the rate of up to four 32-bit words per six clock cycles. The external address/data bus is multiplexed. Users may configure the 80960Jx’s bus controller to match an application’s fundamental memory organization. Physical bus width is register-programmed for up to eight regions. Byte ordering and data caching are programmed through a group of logical memory templates and a defaults register. The BCU’s features include:
- Multiplexed external bus to minimize pin count
- 32-, 16- and 8-bit bus widths to simplify I/O interfaces
- External ready control for address-to-data, data-to-data and data-to-next-address wait state types
- Support for big or little endian byte ordering to facilitate the porting of existing program code
- Unaligned bus accesses performed transparently
- Three-deep load/store queue to decouple the bus from the core Upon reset, the 80960Jx conducts an internal self-test. Then, before executing its first instruction, it performs an external bus confidence test by performing a checksum on the first words of the initialization boot record (IBR). The user may examine the contents of the caches by executing special cache control instructions.
2.3 Timer Unit
The timer unit (TU) contains two independent 32-bit timers that are capable of counting at several clock rates and generating interrupts. Each is programmed by use of the TU registers. These memory-mapped registers are addressable on 32-bit boundaries. The timers have a single-shot mode and auto-reload capabilities for continuous operation. Each timer has an independent interrupt request to the 80960Jx’s interrupt controller. The TU can generate a fault when unauthorized writes from user mode are detected. Clock prescaling is supported.
2.4 Priority Interrupt Controller
A programmable interrupt controller manages up to 240 external sources through an 8-bit external interrupt port. Alternatively, the interrupt inputs may be configured for individual edge- or level-triggered inputs. The interrupt unit (IU) also accepts interrupts from the two on-chip timer channels and a single Non-Maskable Interrupt (NMI ) pin. Interrupts are serviced according to their priority levels relative to the current process priority. Low interrupt latency is critical to many embedded applications. As part of its highly flexible interrupt mechanism, the 80960Jx exploits several techniques to minimize latency:
- Interrupt vectors and interrupt handler routines can be reserved on-chip
- Register frames for high-priority interrupt handlers can be cached on-chip
- The interrupt stack can be placed in cacheable memory space
- Interrupt microcode executes at two or three times the bus frequency for the 80960JD and 80960JT respectively
Advance Information Datasheet 11 80960JA/JF/JD/JT 3.3 V Microprocessor
2.5 Instruction Set Summary
The 80960Jx adds several new instructions to the i960 core architecture. The new instructions are:
- Conditional Move
- Conditional Add
- Conditional Subtract
- Byte Swap
- Halt
- Cache Control
- Interrupt Control Table 1 identifies the instructions that the 80960Jx supports. Refer to the i960® Jx Microprocessor Developer’ s Manual (272483) for a detailed description of each instruction.
2.6 Faults and Debugging
The 80960Jx employs a comprehensive fault model. The processor responds to faults by making implicit calls to a fault handling routine. Specific information collected for each fault allows the fault handler to diagnose exceptions and recover appropriately. The processor also has built-in debug capabilities. In software, the 80960Jx may be configured to detect as many as seven different trace event types. Alternatively, mark and fmark instructions can generate trace events explicitly in the instruction stream. Hardware breakpoint registers are also available to trap on execution and data addresses.
2.7 Low Power Operation
Intel fabricates the 80960Jx using an advanced sub-micron manufacturing process. The processor’s sub-micron topology provides the circuit density for optimal cache size and high operating speeds while dissipating modest power. The processor also uses dynamic power management to turn off clocks to unused circuits. Users may program the 80960Jx to enter Halt mode for maximum power savings. In Halt mode, the processor core stops completely while the integrated peripherals continue to function, reducing overall power requirements up to 90 percent. Processor execution resumes from internally or externally generated interrupts.
80960JA/JF/JD/JT 3.3 V Microprocessor
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2.8 Test Features
The 80960Jx incorporates numerous features which enhance the user’s ability to test both the processor and the system to which it is attached. These features include ONCE (On-Circuit Emulation) mode and Boundary Scan (JTAG). The 80960Jx provides testability features compatible with IEEE Standard Test Access Port and Boundary Scan Architecture (IEEE Std. 1149.1). One of the boundary scan instructions, HIGHZ, forces the processor to float all its output pins (ONCE mode). ONCE mode can also be initiated at reset without using the boundary scan mechanism. ONCE mode is useful for board-level testing. This feature allows a mounted 80960Jx to electrically “remove” itself from a circuit board. This allows for system-level testing where a remote tester — such as an in-circuit emulator — can exercise the processor system. The provided test logic does not interfere with component or circuit board behavior and ensures that components function correctly, connections between various components are correct, and various components interact correctly on the printed circuit board. The JTAG Boundary Scan feature is an attractive alternative to conventional “bed-of-nails” testing. It can examine connections which might otherwise be inaccessible to a test system.
2.9 Memory-Mapped Control Registers
The 80960Jx, though compliant with i960 series processor core, has the added advantage of memory-mapped, internal control registers not found on the i960 Kx, Sx or Cx processors. These give software the interface to easily read and modify internal control registers. Each of these registers is accessed as a memory-mapped, 32-bit register. Access is accomplished through regular memory-format instructions. The processor ensures that these accesses do not generate external bus cycles.
2.10 Data Types and Memory Addressing Modes
As with all i960 family processors, the 80960Jx instruction set supports several data types and formats:
- Bit
- Bit fields
- Integer (8-, 16-, 32-, 64-bit)
- Ordinal (8-, 16-, 32-, 64-bit unsigned integers)
- Triple word (96 bits)
- Quad word (128 bits) The 80960Jx provides a full set of addressing modes for C and assembly programming:
- Two Absolute modes
- Five Register Indirect modes
- Index with displacement
- IP with displacement
Table 1. 80960Jx Instruction Set Asterisk (*) denotes new 80960Jx instructions unavailable on 80960CA/CF, 80960KA/KB and 80960SA/SB implementations.
80960JA/JF/JD/JT 3.3 V Microprocessor
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3.0 Package Information
The 80960Jx is offered with four speeds and three package types. The 132-pin Pin Grid Array (PGA) device is specified for operation at VCC =3 .3 V ± 0.15 V over a case temperature range of 0° to 100°C:
- A80960JT-100 (100 MHz core, 33 MHz bus)
- A80960JT-75 (75 MHz core, 25 MHz bus)
- A80960JD-66 (66 MHz core, 33 MHz bus)
- A80960JD-50 (50 MHz core, 25 MHz bus)
- A80960JD-40 (40 MHz core, 20 MHz bus)
- A80960JD-33 (33 MHz core, 16 MHz bus)
- A80960JA/JF-33 (33 MHz)
- A80960JA/JF-25 (25 MHz)
- A80960JA/JF-16 (16 MHz) The 132-pin Plastic Quad Flatpack (PQFP) devices are specified for operation at V CC =3 . 3V ± 0.15 V over a case temperature range of 0° to 100°C:
- NG80960JT-100 (100 MHz core, 33 MHz bus)
- NG80960JT-75 (75 MHz core, 25 MHz bus)
- NG80960JD-66 (66 MHz core, 33 MHz bus)
- NG80960JD-50 (50 MHz core, 25 MHz bus)
- NG80960JD-40 (40 MHz core, 20 MHz bus)
- NG80960JD-33 (33 MHz core, 16 MHz bus)
- NG80960JA/JF-33 (33 MHz)
- NG80960JA/JF-25 (25 MHz)
- NG80960JA/JF-16 (16 MHz) An extended temperature 132-pin Plastic Quad Flatpack (PQFP) device is specified for operation at VCC = 3.3 V ± 0.15 V over a case temperature range of -40° to 100°C:
- TG80960JA-25 (25 MHz)
Advance Information Datasheet 15 80960JA/JF/JD/JT 3.3 V Microprocessor The 196-ball Mini Plastic Ball Grid Array (MPBGA) device is specified for operation at V CC = 3.3 V ± 0.15 V over a case temperature range of 0° to 100°C:
- GD80960JT-100 (100 MHz core, 33 MHz bus)
- GD80960JT-75 (75 MHz core, 25 MHz bus)
- GD80960JD-50 (50 MHz core, 25 MHz bus)
- GD80960JD-40 (40 MHz core, 20 MHz bus)
- GD80960JD-33 (33 MHz core, 16 MHz bus)
- GD80960JA/JF-33 (33 MHz)
- GD80960JA/JF-25 (25 MHz)
- GD80960JA/JF-16 (16 MHz) For package specifications and information, refer to Intel’s Packaging Handbook (240800).
16 Advance Information Datasheet
3.1 Pin Descriptions
3.1.1 Functional Pin Definitions
described in Table 4. Pins associated with the Interrupt Unit are described in Table 5. Table 2. Pin Description Nomenclature I/O Pin can be either an input or output. – Pin must be connected as described. Synchronous. Inputs must meet setup and hold times relative to CLKIN for proper operation. Asynchronous. Inputs may be asynchronous relative to CLKIN.
Table 3. Pin Description — External Bus Signals (Sheet 1 of 3) number of data transfers during the bus transaction.
- write — AD31:2 are driven with the last data value on the AD bus.
- read — AD31:4 are driven with the last address value on the AD bus; AD3:2 are driven with the value of A3:2 from the last data cycle. Typically, AD1:0 reflect the SIZE information of the last bus transaction (either instruction fetch or load/store) that was executed before entering Halt mode. ALE O R(0) H(Z) P(0) ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE is asserted during a Ta cycle and deasserted before the beginning of the Td state. It is active HIGH and floats to a high impedance state during a hold cycle (Th). ALE O R(1) H(Z) P(1) ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE is the inverted version of ALE. This signal gives the 80960Jx a high degree of compatibility with existing 80960Kx systems. ADS O R(1) H(Z) P(1) ADDRESS STROBE indicates a valid address and the start of a new bus access. The processor asserts ADS for the entire Ta cycle. External bus control logic typically samples ADS at the end of the cycle. A3:2 O R(X) H(Z) P(Q) ADDRESS3:2 comprise a partial demultiplexed address bus. 32-bit memory accesses: the processor asserts address bits A3:2 during Ta. The partial word address increments with each assertion of RDYRCV during a burst. 16-bit memory accesses: the processor asserts address bits A3:1 during Ta with A1 driven on the BE1 pin. The partial short word address increments with each assertion of RDYRCV during a burst. 8-bit memory accesses: the processor asserts address bits A3:0 during Ta, with A1:0 driven on BE1:0. The partial byte address increments with each assertion of RDYRCV during a burst.
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The processor asserts byte enables, byte high enable and byte low enable during Ta. conjunction with A3:2 described above. response to a HOLD request, regardless of prior operating state. access (0). D/C has the same timing as W/R. read (0). It is latched on-chip and remains valid during Td cycles. and Tw /Td cycles for a write. DT/R never changes state when DEN is asserted. Table 3. Pin Description — External Bus Signals (Sheet 2 of 3)
data transfer in a bus cycle. by inserting a wait state (Tw ). processor begins to drive address again. state, resuming control of the address/data and control lines. h state during reset and while halted as well as during regular operation. access to the bus; see i960® Jx Microprocessor Developer’s Manual (272483). should acquire/relinquish the bus. Table 3. Pin Description — External Bus Signals (Sheet 3 of 3)
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Table 4. Pin Description — Processor Control Signals, Test Signals and Power specified relative to a rising CLKIN edge. STEST is deasserted, the processor performs only the external bus confidence test.
- When self-test passes, the processor deasserts FAIL and begins operation from user code.
- When self-test fails, the processor asserts FAIL and then stops executing. 0 = self test failed 1 = self test passed TCK I TEST CLOCK is a CPU input which provides the clocking function for IEEE 1149.1 Boundary Scan Testing (JTAG). State information and data are clocked into the processor on the rising edge; data is clocked out of the processor on the falling edge. TDI I S(L) TEST DATA INPUT is the serial input pin for JTAG. TDI is sampled on the rising edge of TCK, during the SHIFT-IR and SHIFT-DR states of the Test Access Port. TDO O R(Q) HQ) P(Q) TEST DATA OUTPUT is the serial output pin for JTAG. TDO is driven on the falling edge of TCK during the SHIFT-IR and SHIFT-DR states of the Test Access Port. At other times, TDO floats. TDO does not float during ONCE mode. TRST I A(L) TEST RESET asynchronously resets the Test Access Port (TAP) controller function of IEEE 1149.1 Boundary Scan testing (JTAG). When using the Boundary Scan feature, connect a pulldown resistor between this pin and V SS . If TAP is not used, this pin must be connected to VSS ; however, no resistor is required. See Section 4.3, “Connection Recommendations” on page 40. TMS I S(L) TEST MODE SELECT is sampled at the rising edge of TCK to select the operation of the test logic for IEEE 1149.1 Boundary Scan testing. VCC – POWER pins intended for external connection to a VCC board plane. VCCPLL – PLL POWER is a separate VCC supply pin for the phase lock loop clock generator. It is intended for external connection to the VCC board plane. In noisy environments, add a simple bypass filter circuit to reduce noise-induced clock jitter and its effects on timing relationships. VCC5 –
5 V REFERENCE VOLTAGE input is the reference voltage for the 5 V-tolerant I/O
SS – GROUND pins intended for external connection to a VSS board plane. NC – NO CONNECT pins. Do not make any system connections to these pins.
Table 5. Pin Description — Interrupt Unit Signals can be programmed to be level (low) or edge (falling) sensitive. are level sensitive in this mode. Unused external interrupt pins should be connected to VCC . NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur. unused, it should be connected to VCC .
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Figure 3. 132-Lead Pin Grid Array Bottom View - Pins Facing Up
Figure 4. 132-Lead Pin Grid Array Top View - Pins Facing Down
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Table 6. 132-Lead PGA Pinout — In Signal Order NOTE: Do not connect any external logic to pins marked NC (no connect pins).
Table 7. 132-Lead PGA Pinout — In Pin Order NOTE: Do not connect any external logic to pins marked NC (no connect pins).
26 Advance Information Datasheet
Figure 5. 132-Lead PQFP - Top View
Table 8. 132-Lead PQFP Pinout — In Signal Order NOTE: Do not connect any external logic to pins marked NC (no connect pins).
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Table 9. 132-Lead PQFP Pinout — In Pin Order
1 TRST 34 BLAST 67 NC 100 AD8
2 TCK 35 D/C 68 AD26 101 AD7
3 TMS 36 ADS 69 AD25 102 AD6
4 HOLD 37 W/R 70 AD24 103 AD5
5 XINT0 38 VSS (Core) 71 VSS (I/O) 104 AD4
6 XINT1 39 VCC (Core) 72 VCC (I/O) 105 VCC (I/O)
7 XINT2 40 VSS (I/O) 73 VSS (Core) 106 VSS (I/O)
8 XINT3 41 VCC (I/O) 74 VCC (Core) 107 AD3
9 VCC (I/O) 42 DT/R 75 AD23 108 AD2
10 VSS (I/O) 43 DEN 76 AD22 109 AD1
11 XINT4 44 HOLDA 77 AD21 110 AD0
12 XINT5 45 ALE 78 AD20 111 VCC (I/O)
13 XINT6 46 VSS (Core) 79 VSS (I/O) 112 VSS (I/O)
14 XINT7 47 VCC (Core) 80 VCC (I/O) 113 VCC (Core)
15 NMI 48 VSS (I/O) 81 AD19 114 VSS (Core)
16 VCC (Core) 49 VCC (I/O) 82 AD18 115 VCC (Core)
17 VSS (Core) 50 LOCK /ONCE 83 AD17 116 VSS (Core)
18 NC 51 BSTAT 84 AD16 117 CLKIN
19 NC 52 BE0 85 VSS (I/O) 118 VSS (CLK)
20 VCC5 53 BE1 86 VCC (I/O) 119 VCCPLL
21 NC 54 BE2 87 AD15 120 VCC (CLK)
22 NC 55 BE3 88 AD14 121 NC
23 FAIL 56 VSS (I/O) 89 AD13 122 NC
24 ALE 57 VCC (I/O) 90 AD12 123 VCC (Core)
25 TDO 58 VSS (Core) 91 VSS (Core) 124 VSS (Core)
26 VCC (I/O) 59 VCC (Core) 92 VCC (Core) 125 RESET
27 VSS (I/O) 60 AD31 93 VSS (I/O) 126 NC
28 WIDTH/HLTD1 61 AD30 94 VCC (I/O) 127 NC
29 VCC (Core) 62 AD29 95 AD11 128 STEST
30 VSS (Core) 63 AD28 96 AD10 129 VCC (I/O)
31 WIDTH/HLTD0 64 VSS (I/O) 97 VSS (I/O) 130 TDI
32 A2 65 VCC (I/O) 98 VCC (I/O) 131 VSS (I/O)
33 A3 66 AD27 99 AD9 132 RDYRCV
NOTE: Do not connect any external logic to pins marked NC (no connect pins).
Figure 6. 196-Ball Mini Plastic Ball Grid Array Bottom View - Balls Facing Up
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Figure 7. 196-Ball Mini Plastic Ball Grid Array Top View - Balls Facing Down
Table 10. 196-Ball MPBGA Pinout — In Signal Order (Sheet 1 of 2) NOTE: Do not connect any external logic to pins marked NC (no connect pins).
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Table 10. 196-Ball MPBGA Pinout — In Signal Order (Sheet 2 of 2) NOTE: Do not connect any external logic to pins marked NC (no connect pins).
Table 11. 196-Ball MPBGA Pinout — In Pin Order (Sheet 1 of 2) NOTE: Do not connect any external logic to pins marked NC (no connect pins).
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3.2 Package Thermal Specifications
should be measured at the center of the top surface, opposite the pins. heatsink and/or by increasing airflow. Table 11. 196-Ball MPBGA Pinout — In Pin Order (Sheet 2 of 2) NOTE: Do not connect any external logic to pins marked NC (no connect pins).
Table 12. 132-Lead PGA Package Thermal Characteristics
- This table applies to a PGA device plugged into a socket or soldered directly into a board.
Table 13. 196-Ball MPBGA Package Thermal Characteristics
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Table 14. 132-Lead PQFP Package Thermal Characteristics
- This table applies to a PQFP device soldered directly into board.
Table 15. Maximum T A at Various Airflows in °C (80960JT) 1.0.248” high omnidirectional heatsink (AI alloy 6061, 41 mil fin width, 124 mil center-to-center fin spacing).
- 0.250” high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 146 mil center-to-center fin spacing).
Table 16. Maximum T A at Various Airflows in °C (80960JD) 1.0.248” high omnidirectional heatsink (AI alloy 6061, 41 mil fin width, 124 mil center-to-center fin spacing).
- 0.250” high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 146 mil center-to-center fin spacing).
Table 17. Maximum T A at Various Airflows in °C (80960JA/JF) 1.0.248” high omnidirectional heatsink (AI alloy 6061, 41 mil fin width, 124 mil center-to-center fin spacing).
- 0.250” high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 146 mil center-to-center fin spacing).
80960JA/JF/JD/JT 3.3 V Microprocessor
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3.3 Thermal Management Accessories
The following is a list of suggested sources for 80960Jx thermal solutions. This is neither an endorsement or a warranty of the performance of any of the listed products and/or companies.
3.3.1 Heatsinks
- Thermalloy, Inc.
2021 West Valley View Lane
Dallas, TX 75234-8993 (972) 243-4321 2. Wakefield Engineering
60 Audubon Road
Wakefield, MA 01880 (617) 245-5900 3. Aavid Thermal Technologies, Inc. One Kool Path Laconia, NH 03247-0400 (603) 528-3400
4.0 Electrical Specifications
4.1 Absolute Maximum Ratings
Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. and extended exposure beyond the “Operating Conditions” may affect device reliability. you have the latest data sheet before finalizing a design.
4.2 Operating Conditions
Table 19 indicates the operating conditions for the 80960Jx. Table 18. Absolute Maximum Ratings Table 19. 80960Jx Operating Conditions
- See Section 4.4, “VCC5 Pin Requirements (VDIFF)” on page 40.
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4.3 Connection Recommendations
For clean on-chip power distribution, VCC and VSS pins separately feed the device’s functional units. liberal decoupling capacitance near the 80960Jx, since the processor can cause transient power surges. Scan function will not be used (even for board-level testing), connect the TRST pin to VSS. Do not connect the TDI, TDO, and TCK pins if the TAP Controller will not be used. Note: Pins identified as NC must not be connected in the system.
4.4 VCC5 Pin Requirements (VDIFF)
pin directly to the 3.3 V VCC plane.
- Use a regulator that is designed to prevent the voltage differential from exceeding 2.25 V , or,
- As shown in Figure 8, place a 100Ω resistor in series with the VCC5 pin to limit the current through VCC5. If the regulator cannot prevent the 2.25 V differential, the addition of the resistor is a simple and reliable method for limiting current. The resistor can also prevent damage in the case of a power failure, where the 5 V supply remains on and the 3.3 V supply goes to zero.
Figure 8. VCC5 Current-Limiting Resistor Table 20. VDIFF Parameters
4.5 VCCPLL Pin Requirements
connecting VCCPLL must be as short as possible. Figure 9. VCCPLL Lowpass Filter
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4.6 DC Specifications
Table 21. 80960Jx DC Characteristics
- Typical is measured with VCC = 3.3 V and temperature = 25 °C.
Table 22. 80960Jx I CC Characteristics (Sheet 1 of 2)
- These pins have internal pullup devices. Typical leakage current is not tested.
- Measured with device operating and outputs loaded to the test condition in Figure 10 “AC Test Load” on
one of the worst case instruction mixes with VCC = 3.45 V. This parameter is characterized but not tested.
- ICC Active (Thermal) value is provided for your system’s thermal management. Typical ICC is measured with
VCC =3.3 V and temperature = 25°C. This parameter is characterized but not tested.
- ICC Test (Power modes) refers to the ICC values that are tested when the 80960JD is in Reset mode, Halt
mode or ONCE mode with VCC = 3.45 V. Table 22. 80960Jx I CC Characteristics (Sheet 2 of 2)
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4.7 AC Specifications
The 80960Jx AC timings are based upon device characterization. Table 23. 80960Jx AC Characteristics (Sheet 1 of 3) See Table 24 on page 47 for note definitions for this table.
Table 23. 80960Jx AC Characteristics (Sheet 2 of 3) See Table 24 on page 47 for note definitions for this table.
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Table 23. 80960Jx AC Characteristics (Sheet 3 of 3) See Table 24 on page 47 for note definitions for this table.
4.7.1 AC Test Conditions and Derating Curves
Table 24. Note Definitions for Table 23, 80960Jx AC Characteristics (pg. 44)
- To ensure a 1:1 relationship between the amplitude of the input jitter and the internal clock, the jitter
timings, refer to Relative Output Timings in this table.
- A float condition occurs when the output current becomes less than IOL . Float delay is not tested, but is
designed to be no longer than the valid delay.
- AD31:0 are synchronous inputs. Setup and hold times must be met for proper processor operation. NMI
minimum of two CLKIN periods to guarantee recognition.
- RDYRCV and HOLD are synchronous inputs. Setup and hold times must be met for proper processor
- RESET may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition at a
- ONCE and STEST must be stable at the rising edge of RESET for proper operation.
- Guaranteed by design. May not be 100% tested.
10.Relative to falling edge of TCK. Figure 10. AC Test Load
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Figure 11. Output Delay or Hold vs. Load Capacitance Figure 12. T LX vs. AD Bus Load Capacitance Rise and Fall times are identical. Rise and Fall times are identical.
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Figure 15. 80960JD ICC Active (Power Supply) vs. Frequency Figure 16. 80960JD ICC Active (Thermal) vs. Frequency
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4.7.2 AC Timing Waveforms
Figure 19. CLKIN Waveform Figure 20. T OV1 Output Delay Waveform
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Figure 24. T IS3 and TIH3 Input Setup and Hold Waveform Figure 25. T IS4 and TIH4 Input Setup and Hold Waveform
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Figure 28. TCK Waveform Figure 29. T BSIS1 and TBSIH1 Input Setup and Hold Waveforms Figure 30. T BSOV1 and TBSOF1 Output Delay and Output Float Waveform
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5.0 Bus Functional Waveforms
Figure 33. Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus
Figure 34. Burst Read and Write Transactions Without Wait States, 32-Bit Bus
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Figure 35. Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus
Figure 36. Burst Read and Write Transactions Without Wait States, 8-Bit Bus
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Figure 37. Burst Read and Write Transactions With 1, 0 Wait States and Extra Tr State on
Figure 38. Double Word Read Bus Request, Misaligned One Byte From
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Figure 39. HOLD/HOLDA Waveform For Bus Arbitration the processor deasserts HOLDA on the same edge in which it recognizes the deassertion of HOLD.
Figure 40. Cold Reset Waveform 10,000 CLKIN periods, for PLL stabilization.
- The processor asserts FAIL during built-in self-test. If self- test passes, the FAIL pin is deasserted.The processor also asserts FAIL
during the bus confidence test. If the bus confidence test passes, FAIL is deasserted and the processor begins user program execution.
- If the processor fails built-in self-test, it initiates one dummy load bus access. The load address indicates the point of self-test failure.
- Since the bus is idle, hold requests are honored during reset and built-in self-test.
- When selected, built-in self test requires approximately (in CLKIN periods): 393,000 for 80960JT, 207,000 for 80960JD, and 414,000
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Figure 41. Warm Reset Waveform
4 CLKIN Cycles
15 CLKIN Cycles
Figure 42. Entering the ONCE State
- ONCE mode may be entered prior to the rising edge of RESET: ONCE input is not latched until the rising edge of RESET.
CLKIN may not be allowed to float.
- The ONCE input may be removed after the processor enters ONCE Mode.
It must be driven high or low or continue to run.
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5.1 Basic Bus States
(Th). During system operation, the processor continuously enters and exits different bus states. asserted. When the processor needs to initiate a bus access, it enters the Ta state to transmit the address. not ready, the processor can wait as long as necessary for the memory or I/O device to respond. burst transaction, the bus exits the Td state and re-enters the Td/Tw state to transfer the next data word. transfer in a burst access (up to four), the bus enters the Tr state to allow devices on the bus to recover. bus enters the Ta state to transmit the new address. Figure 43. Bus States with Arbitration
5.2 Boundary-Scan Register
The Boundary-Scan register contains a cell for each pin as well as cells for control of I/O and HIGHZ pins. into the control cell, the associated pin(s) are HIGHZ or selected as input. Table 25. Boundary-Scan Register Bit Order
0 RDYRCV (TDI) I 24 DEN O 48 AD17 I/O
1 HOLD I 25 HOLDA O 49 AD16 I/O
10 NMI I 34 AD31 I/O 58 AD8 I/O
11 FAIL I 35 AD30 I/O 59 AD7 I/O
12 ALE O 36 AD29 I/O 60 AD6 I/O
13 WIDTH/HLTD1 O 37 AD28 I/O 61 AD5 I/O
14 WIDTH/HLTD0 O 38 AD27 I/O 62 AD4 I/O
15 A2 O 39 AD26 I/O 63 AD3 I/O
16 A3 O 40 AD25 I/O 64 AD2 I/O
17 CONTROL1 Enable cell
18 CONTROL2 Enable cell 1 42 AD23 I/O 66 AD0 I/O
19 BLAST O 43 AD22 I/O 67 CLKIN I
20 D/C O 44 AD21 I/O 68 RESET I
21 ADS O 45 AD20 I/O 69 STEST
22 W/R O 46 AD19 I/O
23 DT/R O 47 AD18 I/O
- Enable cells are active low.
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Table 26. Natural Boundaries for Load and Store Accesses Table 27. Summary of Byte Load and Store Accesses Table 28. Summary of Short Word Load and Store Accesses
Table 29. Summary of n-Word Load and Store Accesses (n = 1, 2, 3, 4)
- case n=1: burst of 2 short words
- case n=2: burst of 4 short words
- case n=3: burst of 4 short words burst of 2 short words
- case n=4: 2 bursts of 4 short words
- burst of n word(s) +1 (n =1, 2, 3, 4) +5 (n = 2, 3, 4) +9 (n = 3, 4) +13 (n = 3, 4)
- byte access
- burst of 2 bytes n-1 burst(s) of 4 bytes
- byte access
- byte access
- short-word access n-1 burst(s) of 2 short words
- byte access
- byte access
- short-word access n-1 word access(es)
- byte access +2 (n =1, 2, 3, 4) +6 (n = 2, 3, 4) +10 (n = 3, 4) +14 (n = 3, 4)
- burst of 2 bytes
- n-1 burst(s) of 4 bytes
- burst of 2 bytes
- short-word access
- n-1 burst(s) of 2 short words
- short-word access
- short-word access
- n-1 word access(es)
- short-word access +3 (n =1, 2, 3, 4) +7 (n = 2, 3, 4) +11 (n = 3, 4) +15 (n = 3, 4)
- byte access
- n-1 burst(s) of 4 bytes
- burst of 2 bytes
- byte access
- byte access n-1 burst(s) of 2 short words
- short-word access
- byte access
- byte access n-1 word access(es)
- short-word access
- byte access +4 ( n = 2, 3, 4) +8 (n = 3, 4) +12 (n = 3, 4)
- n burst(s) of 4 bytes •n burst(s) of 2 short words •n word access(es)
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Figure 44. Summary of Aligned and Unaligned Accesses (32-Bit Bus)
Figure 45. Summary of Aligned and Unaligned Accesses (32-Bit Bus) (Continued)
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6.0 Device Identification
- Upon reset, the identifier is placed into the g0 register.
- The identifier may be accessed from supervisor mode at any time by reading the DEVICEID register at address FF008710H.
- The IEEE Standard 1149.1 Test Access Port may select the DEVICE ID register through the IDCODE instruction.
- The device and stepping letter is also printed on the top side of the product package.
Table 30. 80960Jx Device Type and Stepping Reference Figure 46. 80960JT Device Identification Register
Table 31. Fields of 80960JT Device ID Version See Table 32 Indicates major stepping changes. VCC 0 = 3.3 V device Indicates that a device is 3.3 V. Manufacturer ID assigned by IEEE. Table 32. 80960JT Device ID Model Types Figure 47. 80960JD Device Identification Register
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Table 33. Fields of 80960JD Device ID Version See Table 30 Indicates major stepping changes. 1 = 5V device Indicates that a device is 3.3 V. (Indicates i960 CPU) Designates type of product. Generation Type 0001 = J-series Indicates the generation (or series) the product belongs to. Indicates member within a series and specific model information. (Indicates Intel) Manufacturer ID assigned by IEEE. Table 34. 80960JD Device ID Model Types Figure 48. 80960JA/JF Device Identification Register
7.0 Revision History
significant changes since the previous revisions. Table 35. Fields of 80960JA/JF Device ID Version See Table 36 Indicates major stepping changes. Indicates that a device is 3.3 V. Manufacturer ID assigned by IEEE. Table 36. 80960JA/JF Device ID Model Types Table 37. Data Sheet Revision History