8095BH

8095 INTEL | Alldatasheet

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multiply or 32/16 divide in 6.25 js. Instruction execution times average 1 to 2 us in typical applications. simultaneously perform software timer functions. Up to four 16-bit software timers can be in operation at once. available on the 8X95BHs and 8X97BHs, with the 8XS5BHs having 4 multiplexed analog inputs. Figure 1. 8X9XBH Block Diagram

With the commercial (standard) temperature option, STO-883, Method 1015. tended temperature range option, operationat char- ature and extended burn-in designators. the specifications are the same for both options. Figure 2. 8X9XBH Memory Map

Figure 3. 8X9X Packaging

68 PLOC

Figure 4. 8X9XBH Thermal Characteristics . 240800) for a description of Intel’s thermal impedance test methodology.

s 8X9XBH intel. EA <i)! 64|CT Vee ACH3/P0.3 SCJ] 2 63 | Ct Vss ACH1/P0.1 eI] 3 62 | [os xtatt ACHO/P0.0 <I] 4 61 | CO xTAL2 ACH2/P0.2 <I} 5 60 | [> ALE/ADV ACH6/PO.6/PMODE.2 eI] 6 59 | [D> RD ACH7/P0.7/PMODE.3 eCI}| 7 58 | [> A00/P3.0 ACHS/P0.5/PMODE.1 <I] 8 57 | [os ap1/P3.1 ACH4/P0.4/PMODE.O <j} 9 56 | [> A02/P3.2 ANGND <4] 10 55 | [> a3 /P3.3 Veer Cd] 11 54 | [> a04/P3.4 Vpp SJ] 12 53 | [> Ad5/P3.5 EXTINT/P2.2/PROG SCJ} 13 52 | [> A06/P3.6 . RESET Sd] 14 51 | [> A07/P3.7 RxD/P2.1/PALE eCI}] 15 50 | [> ans/P4.0 TxD/P2.0/PVER/SALE =I] 16 49 | [> ang/P4.1 P1.0 er} 17 48 | [> Ad10/P4.2 Pi.1 } 18 47 | [o> A011/P4.3 P1.4 Sq] 21 44 | [Oo A014/P4.6 HSI.0/SID.0 eI} | 22 43 | [> ap15/P4.7 HS1.1/SID.1 eX] 23 42 | oe T2cLK/P2.3 HSO.4/HSI.2/SID.2 SCI} | 24 41 | [oo READY HSO.5/HSI.3/SID.3 <I] 25 40 | [> T2RST/P2.4 HSO.0/PACT eX} 26 39 | [> BHE/WRH HSO.1 eI] 27 38 | [o> WR/WRL P1.5 ett]] 28 37 | [> pwM/P2.5/PD0/SPROG P1.6 <j] 29 36 | PO P2.7 P2.6 =I] 31 34} [D> Vss HSO.2 <I} 32 33 | Fo» Hs0.3 270090-56 Figure 5, 64-Pin Shrink-DiP Package

51 SO 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35

Figure 8. 68-Pin LCC Package

Figure 9. 68-Pin PLCC Package

Figure 10. 48-Pin DIP Package

symbol [SSS ad Fncton id Main supply voltage (6¥). Digital circuit ground (OV). There are two Vgg pins, both of which must be connected. Veo RAM standby supply voltage (SV). This voltage must be present during normal operation. Ina Power Down condition (i.e. Voc drops to zero), if FIESET is activated betore Voc drops below spec and Vpp continues to be held within spec., the top 16 bytes in the Register File will retain their contents. Ver Reference voltage for the A/D converter (5V). Vper is also the supply voltage to the analog portion of the A/D converter and the logic used to read Port 0. Must be connected to use A/D or Port 0. ANGND Reference ground for the A/D converter. Must be held at nominally the same potential as Vss. Vpp Programming voltage for the EPROM devices. It should be + 12.75V for programming and will float to 5V otherwise. The pin should not be above Voc for ROM and CPU devices. This pin must be left floating in the application circuit for EPROM devices. XTAL1 Input of the oscillator inverter and of the internal clock generator. XTAL2 Output of the oscillator inverter. CLKOUT*t Output of the internal clock generator. The frequency of CLKOUT is 1% the oscillator frequency. It has a 33% duty cycle. Reset input to the chip. Input low for a minimum 10 XTAL1 cycles to reset the chip. The 4 subsequent low-to-high transition re-synchronizes CLKOUT and commences a 10-state- time RESET sequence. BUSWIDTH"t | Input for bus width selection. If CCR bit 1 is a one, this pin selects the bus width for the bus cycle in progress. If BUSWIDTH is a 1, a 16-bit bus cycle ocours. if BUSWIDTH is a 0 an 8-bit cycle occurs. If CCR bit 1 is a 0, the bus is always an 8-bit bus. If this pin is left unconnected, it will rise to Voc. NMI*t A positive transition causes a vector to external memory location 0000H. INST*+ Output high during an external memory read indicates the read is an instruction fetch. INST is valid throughout the bus cycle. Input for memory select (External Access). EA equal to a TTL-high causes memory accesses to locations 2000H through 3FFFH to be directed to on-chip ROM/EPROM. EA equal to a TTL-low causes accesses to these locations to be directed to off-chip memory. EA equal to 12.75V causes the device to enter the Programming Mode. ALE/ADV ‘Address Latch Enable or Address Valid output, as selected by CCR. Both pin options provide a latch to demultiplex the address from the address/data bus. When the pin is ‘ADV, it goes high at the end of the bus cycle, ALE/ADV is activated only during external memory accesses. | Read signal output to external memory. RD is activated only during external memory reads. WA/WAL Write and Write Low output to external memory, as selected by the CCR. WR will go low for every external write, while WRL will go low only for external writes where an even byte is being written. WR/WAL is activated only during external memory writes. BHE/WRA Bus High Enable or Write High output to external memory, as selected by the CCR. BHE will go low for external writes to the high byte of the data bus. WRH will go low for ‘external writes where an odd byte is being written. BHE/WRH is activated only during external memory writes. PRELIMINARY 431 MM 4826475 044649 SOO mm

sx0xBH intel. PIN DESCRIPTIONS (Continued) READY Ready input to lengthen external memory cycles. If the pin is low prior to the falling edge of CLKOUT, the memory controller goes into a wait mode until the next positive transition of CLKOUT occurs with READY high. When the external memory is not being used, READY has no effect. Internal control of the number of wait states inserted into a bus cycle held not ready is available in the CCR. Inputs to High Speed Input Unit. Four HS! pins are available: HSI.0, HSI.1, HSI.2 and Outputs from High Speed Output Unit. Six HSO pins are available: HSO.0, HSO.1, HSO.2, Port ot 8.bit high impedance input-only port. These pins can be used as digital inputs and/or as analog inputs to the on-chip A/D converter. Port 1 8-bit quasi-bidirectional I/O port. Port 27 8-bit multi-functional port. Six of its pins are shared with other functions in the 8096BH, the remaining 2 are quasi-bidirectional. Ports 3. and 4 | 8-bit bidirectional |/O ports with open drain outputs. These pins are shared with the multiplexed address/data bus which has strong internal pullups. Ports 3 and 4 are also used as a command, address and data path by EPROM devices operating in the Programming Mode.* | PMODE _| Determines the EPROM programming mode. A low signal in Auto Programming Mode indicates that programming is in progress. A high signal indicates programming is complete. Allow signal in Auto Programming Mode indicates that the device programmed correctly. SALE A falling edge in Auto Programming Mode indicates that Ports 3 and 4 contain valid programming address/command information (output from master). A falling edge in Auto Programming Mode indicates that Ports 3 and 4 contain valid Programming data (output from master). [sid __| Assigns a pin of Ports 3 and 4 to each slave to pass programming verification. PALE falling edge in Slave Programming Mode and Auto Configuration Byte Programming Mode indicates that Ports 3 and 4 contain valid programming address/command information (input to slave). A falling edge in Slave Programming Mode indicates that Ports 3 and 4 contain valid programming data (input to slave). A high signal in Slave Programming Mode and Auto Configuration Byte Programming Mode indicates the byte programmed correctly. PVAL Anhigh signal in Slave Programming Mode indicates the device programmed correctly. PDO A low signal in Slave Programming Mode indicates that the PROG pulse was applied for longer than allowed. “Not available on Shrink-DIP package +Not available on 48-pin device +#Port 0.0.1.2.3 not available on 48-pin device 4-32 PRELIMINARY WM 4426175 O144b50 cee

ELECTRICAL CHARACTERISTICS NOTICE: This data sheet contains preliminary infor- ABSOLUTE MAXIMUM RATINGS* mation on new products in production. It is valid for the devices indicated in the revision history. The Ambient Temperature Under Bias ~55°C to +125°C _| specifications are subject to change without notice. Voltage from EX or Vpp Maximum Ratings” may cause permanent damage. - These are stress ratings only. Operation beyond the Voltage from Any Other Pin to tonded exposure beyond the “Operating Conditions” NOTES: 1. This includes Vpp and EA on ROM and CPU only devices. 2. Power dissipation is based on package heat transfer limitations, not device power consumption. OPERATING CONDITIONS (All characteristics in this data sheet apply to these operating conditions unless otherwise noted.) Ambient Temperature Under Bias Commercial Temp. | 0 | +70 | °C | Ambient Temperature Under Bias Extended Teno. | =40 | vas | =o] Power-Down Supply Voltage | aso | 550 | v | NOTE: ANGND and Vgg should be nominally at the same potential. DC CHARACTERISTICS [tcc ___|_ Voc Supply Current Commercial Temp. [|_| 240 | mA | AllOutputs | tcc | Voc Supply Current Extended Temp |_| ero _| ma _| Disconnected, [ tocr__|_Voc Supply Current (Ta > 70°C) [| 195 | ma_| Veo Supply Current Normal operation and Power-Down. PRELIMINARY 4-33 MH 4626175 0144651 169

? . @x9xBH intel DC CHARACTERISTICS (Continued) Vin Input High Voltage (Except RESET, Voc + 0.5 v NMI, XTAL1) Input high Voltage, RESET Rising | 24 | Voc+os| v [| | Vino Input High Voltage, RESET Falling 21 | Voct+05] Vv (Hysteresis) lu Input Leakage Current to each pin of +10 BA | Vin = Oto Veo HSI, P3, P4, and to P2.1. of PO ie Input Low Current to each pin of P1, 125 pA | Vy = 0.45V and to P2.6, P2.7 Commercial Temp. ie Input Low Current to each pin of P1, BA Vit = 0.45V and to P2.6, P2.7 Extended Temp. Input Low Current to RESET | -o25 | -2 | ma | Vu = 048v Ine Input Low Current P2.2, P2.3, P2.4, pA | Vi = 0.45V READY, BUSWIDTH Vou Output Low Voltage on Quasi- Vv | top = 0.8mA Bidirectional port pins and P3, P4 when (Note 1) used as ports Vou Output Low Voltage on Quasi- 0.75 Vv | lop = 20mA Bidirectional port pins and P3, P4 when (Notes 1, 2, 3) used as ports Vote __| Output Low Voltage on Standard 0.45 Vv | lop = 2.0mA Output pins, FRESE and Bus/Control (Notes 1, 2, 3) Pins Vou Output High Voitage on Quasi- 24 Vj lo = —20pA Bidirectional pins (Note 1) Vout Output High Voltage on Standard Vv | lon = 200 pA Output pins and Bus/Control pins (Note 1) [tows | Output high Curenton ESET | -s0 | | wa Von = 24v PinCapacitance(AryPintoVss) | | 10 |p| rest = 1.0 MHz NOTES: 1. Quasi-bidirectional pins include those on P1, for P2.6 and P2.7. Standard Output Pins include TXD, RXD (Mode 0 only), PWM, and HSO pins. Bus/Control pins include CLKOUT, ALE, BHE, RD, WA, INST and ADO-15. 2. Maximum current per pin must be externally limited to the following values if Voy is held above 0.45V. lo. on quasi-bidirectional pins and Ports 3 and 4 when used as ports: 4.0 mA Jo. On standard output pins and RESET: 8.0 mA lox on Bus/Control pins: 2.0 mA 3. During normal (non-transient) operation the following limits apply: Total Io, on Port 1 must not exceed 8.0 mA. Total Io, on P2.0, P2.6, RESET and all HSO pins must not exceed 15 mA. Total Io. on Port 3 must not exceed 10 mA. Total Io, on P2.5, P2.7, and Port 4 must not exceed 20 mA.

4.34 PRELIMINARY

Test Conditions: Load Capacitance on Output Pins = 80 pF TIMING REQUIREMENTS (The system must meet these specifications to work with the 8X9XBH.) Teux®9 [ READYHoidaterCLKOUTEdge [om [ns | Endl ALE/ADV READY ald |_| 8¥osn 78 | ve] ‘Address Validto input Datavaid | «|S Tosc— 1208) | ns | Address Validto BUSWIDTH Valid | | 2 Tosco - 125 | ns | NOTES: 1. If the 48-pin or 64-pin device is being used then this timing can be generated by assuming that the CLKOUT falling edge has occurred at 2 Togc + 55 (TLLCH(max) + TCHCL(max)) after the falling edge of ALE. 2. Pins not bonded out on 64-pin devices. 3. Pins not bonded out on 48-pin devices. 4, The term “Address Valid” applies to ADO-15, BHE and INST. 5. If wait states are used, add 3 Tog * N where N = number of wait states. PRELIMINARY 4-35 MH 4426175 0144653 73)

8X9XBH intel ° TIMING RESPONSES (MCS-96 devices meet these specs.) [ symbot [Parameter Twin [Max | Units [Fara _[OseitatorFrequency || 1.0 | Me | [Foss [OssiatorPoiod SSSC*dCSCti St | | [Toncn | XTALI Flsing Edge to Clockoutfisingédge | | a20 | ns | [Toon OLKOUT Perea «| Bosc) | Tosa) | ne | [Toneu'#) [cuxourHightime | Toso ~ 95 | Toso + 10 | ns | [Foun [CUKOUTLowioALEHigh S80 | [Tuc | ALE/ADVLowtoGLKOUTH@N®) | Toso 25 | Toso+ 45 | | [Tua [ALE/ADVHighTime | Tose 90 | Tose + 9809| ns | [Ta | Address SetuptoEnd ot ALE/ADV | Toso 50 | |__| [Truaz™ | RO or WRLow to Address Float Commercial Temp. | Typ. =o | 10 | ns | [Truaz | RD orWRLowtoAddressFloatextendedTemp | | 25 |_| [Tum [Endof ALE/ADVtoRDorWR Acie | Toso 40 [| ns | [Tun [AderossHoldaterEnd ot LEAD | Toso |_| vs | [Tw [WRPusewan LS Toso 950 | ne | [Tovwn | Output Data Valid to End of WA/WALAWAA | 3Tosc—60@| | ns | |Twuox | Output DataHoldatter WR/WAL/WRH | Toso 50 || ns | [Twin | Endot WA/WAL/WAH to ALE/ADVHigh | Toso 75 | |__| [Tau | FOPusowam Toso 200] id | [Twa [EndotRDio ALEADVHgh «| Tosca | —~*ds ie | [Tout | CLOOKOUT Low to ALE/ADVLow | Toso 40 | Toso? 5 | ve | [Thnx | FOHighioINSTO,BHE,ADB-15 inactive | Tosc~ 25 _[ Toso + 20 | ns | [Twuex'®) | WAHighto INST), BHE, ADE-15 inactive | Toso 60_| Tose + 100 | ns_| [Tau | WAL,WAR LowtoWAL WAR High | 2 Toso — 95 | 2Toso + 40|_ns_| [Tun _[ALE/ADV tow WAL, WAFLow | Toso = 20 | 2Tosc +85| | [Tovin [Output Datavaidto WAL WAR Low | Toso 60 | | ns | NOTES: 1. Pins not bonded out on 64-pin devices. 2. If more than one wait state is desired, add 3 Togc for each additional wait state. 3. CLKOUT is directly generated as a divide by 3 of the oscillator. The period will be 3 Togc + 10 ns if Tosc is constant and the rise and fall times on XTAL1 are less than 10 ns. 4. CLKOUT, INST, and BHE pins not bonded out on 48-pin and 64-pin devices. 5. Max spec applies only to ALE. Min spec applies to both ALE and ADV. 6. The term "Address Valid” applies to ADO-15, BHE and INST. 7. The term “ Address” in this definition applies to ADO-7 for 8-bit cycles, and ADO-15 for 16-bit cycles. 4-36 PRELIMINARY | MH 44626175 O144b54 976

WAVEFORM—SYSTEM BUS TIMINGS us TLELOLPLeLP Lem Toc Toner} + Tosc->| TuLcH’ LOCKOUT Tove

1 Toure

READY “VALID |,/| (3) vous Tow Tun ALE, ADV | Leni J < Tune. TLURLs 1, TRH RD ‘. Taye T RHO:

1 Tavov, TWHLH

TuuAL —— fe THU WR, WRL, WRH y= 7 TwHox eS a eT — NOTES: 1, 8-bit bus only. 2. 8-bit or 16-bit bus and write strobe mode selected. 3. When ADV selected. 4. 8- or 16-bit bus and no write strobe mode selected. WAVEFORM—BUSWIDTH* TIMINGS ww PLELPLOLe Lepper ‘CLKOUT / \\ / \\ / \\ Tavov seeceeece, Tusv ALE / ADV TuLex. TavL *Buswidth is not bonded out on 48- and 64-pin devices. PRELIMINARY 4.37 MH 4826175 O144655 804

8X9XBH intel ° EXTERNAL CLOCK DRIVE 17To.o. Osciator Frequency | | ta |e Touox High Time ee Tox | towtime Ps | Toon | Risetime TT tT | Fall Time ee ee EXTERNAL CLOCK DRIVE WAVEFORMS Tonox TouoH Tonou

25 Fr 7

‘Lox 08 08 D ‘LoL 270090-48 An external oscillator may encounter as much as a 100 pF load at XTAL1 when it starts up. This is due to interaction between the amplifier and its feedback capacitance. Once the external signal meets the Vi. and Vj specifications the capacitance will not exceed 20 pF. EXTERNAL CRYSTAL CONNECTIONS EXTERNAL CLOCK CONNECTIONS ce vat ss If = 8X9X t EXTERNAL EA c1ock inrut —[ >© MALI Quertz Crystal or clock driver ax9x Ceramic Reeonetor 270000-58 no connect =f XTALZ NOTE: Keep oscillator components close to chip and use 270090-59 ‘short, direct traces to XTAL1, XTAL2 and Vgs. When using crystals, C1 — 30 pF and C2 = 30 pF. When using ceramic resonators, consult manufacturerer for recommended capacitor values. ‘AC TESTING INPUT, OUTPUT WAVEFORMS AC TESTING FLOAT WAVEFORMS ous os os Yooug=020¥ yo.*020¥ 270080-49 270000-51 [AC Testing inputs are crvenat2.4V fora Logie “tan 0:46 for For Timing Purposes a Port Pin is no Longor Floating when 8 {Logi "O", Timing measurements are made at 2.0V fora Logie 200 mV change trom Load Voltage Occurs and Boge to Float “1” and 0.8V for a Logic “0”. when @ 200 mV change from the Loaded Vox/Vo, Level occurs tovllon = BA

4.38 PRELIMINARY

MINIMUM HARDWARE CONFIGURATION CIRCUITS Te} —onoar Tones Ex wer 4 baa yor pe fe —) re ae: vss? XTALY__XTALZ oF st TALL XTALZ Oona hour aor hour HLT rue PAT MF Soi F nue Ae" PE By,7 i i - 270090-52, = 270090-53 AC CHARACTERISTICS—SERIAL PORT—SHIFT REGISTER MODE SERIAL PORT TIMING—SHIFT REGISTER MODE Test Conditions: Load Capacitance = 80 pF [Symbol [Parameter | Min | Max Units | [Tau | SovalPonGuckPered Toss | ds | Taxi | Serial Port Glock Faling Edge to Rising Edge | 4Tosc- 60 | 4Tosc+50 | ns_| [ Toven | OutputData Setupto Clock Rising Edge | STosc | ns ["Toiox | Oubut Data Hod Afr Gock ising Esge | Tose -70 |__| [Teiow | Newt Oud Cate vaidARerClook sng Edge |__| Tose + 5 | no | [Tovxn | inputData Setupto Clock Rising Edge | 2 Toso +200 [| ns [Tivo | top Dato Afr GockRisngeage [0 | dro | [Txioz | LastGlock Rising to OutputFioat TTS Toso | ns WAVEFORM—Tripy ovr Su is Tine 35% 15% Yee { Sart Tae from Power Supply Kies to Externe! Output Low a, LV ee a A a PT ee a [asoness Houta} a00%ess | i Zor, coe | 2080 FIRST BUS FETCH CYCLE pal ermal RESET Lew to Pot Wo Te era. exon neser rue] 270090-60 PRELIMINARY 439 FA 4826175 O144b5? bo? Me

8X9XBH intel ° WAVEFORM—SERIAL PORT—SHIFT REGISTER MODE SERIAL PORT WAVEFORM—SHIFT REGISTER MODE Tova} Towel Toa] = Tox Tevaa~t r on <2 GED GEED GXED GEES GXED GaD> el tae (0 XK KKK NK KEK XK NY 270090-36 A/D CONVERTER SPECIFICATIONS A/D Converter operation is verified only on the 8097BH, 8397BH, 8095BH, 8395BH, 8797BH, 8795BH. The absolute conversion accuracy is dependent on the accuracy and stability of Vref. ‘See the MCS-96 A/D Converter Quick Reference for definitions of A/D Converter terms. [Parameter Typical" [Minimum | Maximum | Uniter> | Notes | Resolution 1024 Levels

10 Bits

Full Sale Eror Tosvosf +t ——~d=stss | id [-zeroOrsetero | sos | S| SSSSSCS~*d~( sd [Nontinearty iP Td tee TY Temperature Coefficients: Offset 0.009 LSB/°C Full Scale 0.009 LSB/°C Differential Non-Linearity 0.009 LsB/°C Ofisoaion ee Feedthrough a InpuiSeresResitance [| kK | dT a | | D1 put Leakage a Sample Dolay | J sieso 80 [Sos +60 [ns | 2 | Sample Time | 2 Tosc= 80 | t2Tosc+s0 [ns [| Sampling Capadior a a a NOTES: * These values are expected for most devices at 25°C. ** An “LSB”, as used here, is defined in the MCS-96 A/D Converter Quick Reference and has a value of approximately 5 mv. 1. DC to 100 KHz. 2. For starting the A/D with an HSO Command. ‘3. Multiplexer Break-Before-Make Guaranteed. 4. Resistance from device pin, through internal MUX, to sample capacitor. 4-40 PRELIMINARY WB 4826175 0144658 513

intel ° 8X9XBH EPROM SPECIFICATIONS EPROM PROGRAMMING OPERATING CONDITIONS [_symbot | Parameter Min Max | Units | [Tr ___| Ambient Temperature during Programming | 20 | 30 | c_| [Voc veo er | Supply Votages suing Programming ——~—=S=«d AB | 88 |__| | Vea Programming Mode Supply Votage | 8.0 | 180 | vem | | Vee | EPROM Programming Supply Voltage | 1260 | 130 | Ve | | Fosct___| Oscillator Frequency during Auto and Slave Programming | 6.0 | 6.0 | MHz | [Fosc2 | Oscilator Frequency during Run-Time Programming | 60 | 120 | Mrz | NOTES: 1. Voc. Vpp and Vagr should nominally be at the same voltage during programming. 2. Vea and Vp must never exceed the maximum voltage for any amount of time or the device may be damaged. 3. Vgg and ANGND should nominally be at the same voltage (OV) during programming. AC EPROM PROGRAMMING CHARACTERISTICS [_symbor [Parameter] win | Max ‘| Unis | [| Tavi | ADDRESS/COMMANDValdtoPALELow | 0 || Toso | [ Tune | ADORESS/COMMANOHotdaterPALELow | eo | | Tose | fi [Tover | OupuData Soup BetoroPROGLow | 0 | | ‘Tose | [Tro | Daa HowsAterPAOGraing «|_| «dt CTosc | [Tun | Parcrusewim Swf «dC | I ia ld

144 Tose

| Tew | PROGHightoNodPatetow | a0 || Toso | [Ttrwox | DataHoisAtorPAOG Hen | a0 | Toc | [teww | PROG High pvER/POOvaid | soo | ——'| Tose | [Tuy | PALELowioPVER/PDOHgnh ‘| 100 |__| Tose | [ Trio | PROG Low o VERIFICATION/DUMPOaiavaié | 100 | | Toso | [Trai | RESETHignoFretPALE Low rotshowe) | 2000 |__| Tosc_| DC EPROM PROGRAMMING CHARACTERISTICS [_svmbor [Parameter | min, | Max | Unite | [tee | Vee Supply Gurent(WhneneverProgamming) [| 100 | ma | PRELIMINARY 44 | BB 4826175 0144659 4ST mf

8X9XBH int el ° WAVEFORM—EPROM PROGRAMMING y Tove. Ae te Tux + Ie Truox PORTS 5,4 TpLPH —— TeHLL PROG Tayi, secce Tux Teupv TeHox ports 3,4 —{ AD) Ci warp buMe ic ee es “— | = PDO __VALID \\_vauio 270090-43 8X9XBH ERRATA occurs within 9 states after the first, the events will be entered separately with time-tags at least Devices covered by this data sheet (see Revision ‘one count apart. If the second event enters the History) have the following errata. FIFO coincident with the “skipped” time-tag situ- ation (see B above) the time tags will be at least two counts rt. 1. INDEXED, 3 OPERAND MULTIPLY apa The displacement portion of an indexed, three oper- 3. RESERVED LOCATION 2019H and (byte or word) multiply may not be in the range of 200H thru 17FFH inclusive. If you must use these The 1990 Architectural Overview recommended that displacements, execute an indexed, two operand address 2019H be loaded with OFFH. The recom- multiply and a move if necessary. mandation is now 20H. 2. HSI FIFO OPERATION 4, RESERVED LOCATION 201CH The High Speed Input (HSI) has three deviations Reading reserved location 201CH, either internally from the specifications. Note that “events” are de- or externally, will return “201” as data. fined as one or more pin transitions. “Entries” are defined as the recording of one or more events. 5, SERIAL PORT SECTION A. The resolution is nine states instead of eight states. Events occurring on the same pin more Serial Port Flags—Reading SP_STAT may not frequently than once every nine states may be —_clear the T! or RI flag if that flag was set within two lost. state times prior to the read. In addition, the parity B. A mismatch between the nine state HSI resolu. FOF bit (RPE/RB8) may not be correct if it is read tion and the eight state hardware timer causes _ Within two state times after RI is set. Use the follow- one time-lag value to be skipped every nine timer ing code to replace ORB sp_image, SP_STAT. counts. Events may receive a time-tag one count © SP_READ: LDB TEMP, SP_STAT later than expected. ORB SP_IMAGE, TEMP C. If the FIFO and Holding Register are empty, the JBS TEMP,5,SP_READ; if TI is first event will transfer into the Holding Register, set then read again leaving the FIFO empty again. The next event JBS TEMP,6,SP_READ; if RI is that occurs will be the first event loaded into the set then read again empty FIFO. If the first two events into an empty ANDB SP_IMAGE,#7FH; clear FIFO (not counting the Holding Register) occur false RB8/RPE coincident with each other, both are recorded as ORB SP_IMAGE, TEMP; load ‘one entry with one time-tag. If the second event correct RB8/RPE

442 PRELIMINARY

1. A bug was not documented in the -004 data DATA SHEET REVISION HISTORY sheet and was fixed before the -005 data sheet. This data sheet (270090-010) is valid for devices Information on the bug was added to the differ- marked with an "E” at the end of the topside track- ence between the -005 and -004 data sheets. ing number. Data sheets are changed as new device information becomes available. Verify with your local Differences between -006 and -005 data sheets. Intel sales office that you have the latest version 4. All EPROM programming mode information has before finalizing a design or ordering devices. ~ been deleted and moved to the Hardware Design The ditt between this data sheet (-010) and Information chapter. lifference bet nn this data sheet (-( an ‘ t the previous one (-008) is the Io./Ioy for float wave. 2 ‘Shrink-DIP package information has been added. form testing changed from +15 mA to +8 mA (this 3. Anew RESET timing specification has been add- data sheet). ed for clarity. 4. Software Reset pin timing information has been The following differences exist between (-009) data added. sheet and (-008). __, HSO Io, specifications have been improved so 1, The Exprose (extended temperature and burnin that all HSO pins have the same drive capability. options) were to this data sheet. The , i 6. Port 3 and Port 4 pin descriptions were clarified, SX9XBH Express data sheet (270433-004) is indicating the necessity of pullup if the pins are now obsolete. used as ports 2. Changes were made to the format of the data a sheet and the SFA descriptions were removed. 7° HSI FIFO overflow description added. No specification changes made. Differences between the -008 and the -004 data 3. Added Reserved Location 201CH errata. shoots. The following differences exist between the -008 "+ The, C05 data sheet covespande to devices data sheet and the -007 data sheet. tracking number. The -004 data sheet corre- 1. The -007 data sheet was valid for devices sponded to devices which are not marked with a marked with a “D” at the end of the top side “D". tracking number. 2. Much of the description of device functionality 2. The following errata were removed: RESET and has been deleted. All of this information is al- the Quasi-Bidirectional Ports, Software RESET ready in the MCS-96 Architectural Overview. Timing, and Using T2CLK as the source for Tim- the A/D converter specification for Differential ora, . ae Non-linearity has been changed to be a minimum. 3, Tho HS! FIFO Operation errata definition was of > 1 Isbs to a maximum of +2 LSBs. changed to match change in the HSI FIFO Oper- 4 g9xeH errata section. The JBS and JBC on ation. Port 0 errata has been fixed on the latest device The following differences exist between the -007 stepping. . data sheet and the -006 data sheet. 5. OXGXBH era section The orrata for the ed anged in = = levices has been fixed on the latest device step- * Toe i Mit trong Max ps Max ping.This errata caused the upper 8 bits on the ns to Min ‘ns, Mex J ‘Address/Data bus to be latched when resetting 2. Txax changed from Min = 2 Togc — 50 ns to into an 8-bit external memory system. Min = 2 Tosc ~ 70 ns. ; 6. 8X9XBH errata section. An errata existed which 3. ToLox changed from Min = 25 ns to Min = caused the device to be held in RESET for ex- 30 ns. tended periods of time with the internal RESET 4, An errata was added changing the recommenda- pin pulled down internally. The condition oc- tion for address 2019H from OFFH to 20H. cured who the XTAL inputs wore driven before , i icc was stable and within the data sheet speci 5. The power supply sequencing section has been cation. The condition was worse at cold, This er- deleted. The information is in the Hardware De- aaa rian not documented in the -004 data shoot . son lene siying th «change It has been fixed on the latest device stepping. * Tieator wae added to ine Uifferoneos between the 7» 8X9XBH errata section. Errata 3 and 4 have been cfcator was added to the differences between the added to the errata list. These errata exist for all . - steppings of the device. PRELIMINARY 4-43 MM 4826175 O144bb1 OOF Me

Differences between the -004 and the -003 data 7. The A/D Converter Specifications for Differential sheets. Non-Linearity has been corrected to be a maxi- 1. The bus control figures and bus timing diagrams mum of +2 LSB’s. were modified to more accurately describe their 8. The EPROM programming section figures were operation. In particular the 8-bit bus modes now corrected to indicate the correct interface to a reflect the use of Write Strobe Mode. 2764A-2. A reset circuit was added to these fig- 2. Additional text was added to the Analog/Digital ures and the signal PVAL (Port 3.X and Port 4.X) description of the conversion process to clarify its is now identified as the valid signal for program operation and usefulness, verification in the Auto Programming Mode. Text . was added to this section to reference the re- 3. Text was added to the interrupt description sec- quirement of using the Auto Configuration Byte tion to indicate the maximum transition speed of Programming Mode for 48-lead devices. Figure the Input signal relative to the CPU's state timing. 22A was edited for corrections to the text, and A figure was included to graphically demonstrate now indicates PVER (Port 2.0). The EPROM cir- the interrupt response timing. cuits were corrected to show 6 MHz operation 4. The pin descriptions were modified to indicate for programming devices from internal micro- that Vp must normally float in the application. code 5. The input low voltage specification (Vi.1) was de- 9. The protected memory section was edited to in- leted and is covered by the Vi. specification. dicate that the CPU will enter a “JUMP ON 6.A suggested minimum configuration circuit was SELF” condition when ROM/EPROM dump added to the material. mode is complete, 10. An 8X9XBH ERRATA section was added. 11. This REVISION HISTORY was added. 4-44 PRELIMINARY OP 4826175 O144bb2 T4H4