Microcontroller

8052AH

Intel Corporation

MCS 51 8-BIT CONTROL-ORIENTED MICROCONTROLLERS

Manufacturer: Intel Corporation

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intel. MCS® 51 8-BIT CONTROL-ORIENTED MICROCONTROLLERS Commercial/Express 8031AH/8051AH/8051AHP 8032AH/8052AH 8751H/8751H-8 8751BH/8752BH @ High Performance HMOS Process @ Boolean Processor @ Internal Timers/Event Counters m Bit-Addressable RAM @ 2-Level Interrupt Priority Structure @ Programmable Full Duplex Serial @ 32 1/0 Lines (Four 6-Bit Ports) Channel m 64K External Program Memory Space & 111 Instructions (64 Single-Cycle) m™ Security Feature Protects EPROM Parts 64K External Data Memory Space Against Software Piracy @ Extended Temperature Range 2 {—40°C to + 85°C) The MCS® 51 controllers are optimized for control applications. Byte-processing and numerical operations on small data structures are facilitated by a variety of fast addressing modes for accessing the internal RAM. The instruction set provides a convenient menu of 8-bit arithmetic instructions, including multiply and divide instruc- tions. Extensive on-chip support is provided for one-bit variables as @ separate data type, allowing direct bit manipulation and testing in control and logic systems that require Boolean Processing. The 8751H is an EPROM version of the 8051AH. It has 4 Kbytes of electrically programmable ROM which can be erased with ultraviolet light. It is fully compatible with the 8051AH but incorporates one additional feature: a Program Memory Security bit that can be used to protect the EPROM against unauthorized readout. The 8751H-8 is identical to the 8751H but only operates up to 8 MHz. The 8051AHP is identical to the 8051AH with the exception of the Protection Feature. To incorporate this Protection Feature, program verification has been disabled and external memory accesses have been limited to 4K. The 8052AH is an enhanced version of the 8051AH. It is backwards compatible with the 8051AH and is fabricated with HMOS I! technology. The 8052AH enhancements are listed in the table below. Also refer to this table for the ROM, ROMless and EPROM versions of each product. 8031AH none 128 x 8 RAM 2x 16-Bit 8051AH 4K x8 ROM 128 x 8 RAM 2x 16-Bit 8051AHP 4K x 8 ROM 128 x 8 RAM 2x 16-Bit 8751H 4K x 8 EPROM 128 x 8 RAM 2x 16-Bit 8751H-8 4K x 8 EPROM 128 x8 RAM 2x 16-Bit 8751BH 4K x 8 EPROM 128 x 8 RAM 2x 16-Bit 8032AH none 256 x 8 RAM 3x 16-Bit 8052AH 8K x 8 ROM 256 x 8 RAM 3x 16-Bit 8752BH 8K x 8 EPROM 256 x 8 RAM 3x 16-Bit October 1993 Order Number: 272318-001 2-21 www.chipinfo.ru Be sure to visit CHIPINFO web site for more information.

Figure 1. MCS® 51 Controller Block Diagram and 8752BH devices are manufactured on P422. www.chipinfo.ru Be sure to visit CHIPINFO web site for more information.

240800) for a description of Intel’s thermal impedance test methodology. **Do not connect reserved pins. Figure 2. MCS® 51 Controller Connections www.chipinfo.ru Be sure to visit CHIPINFO web site for more information.

® t, | MCS® 51 CONTROLLER in ° PIN DESCRIPTIONS Port 2 emits the high-order address byte during fetches from external Program Memory and during Vee: Supply voltage. accesses to external Data Memory that use 16-bit addresses (MOVX @DPTR). in this application it Vg: Circuit ground. uses strong internal pullups when emitting 1’s. Dur- ing accesses to external Data Memory that use 8-bit Port 0: Port 0 is an 8-bit open drain bidirectional 1/O addresses (MOVX @Ri), Port 2 emits the contents of port. As an output port each pin can sink 8 LS TTL the P2 Special Function Register. inputs. Port 2 also receives the high-order address bits dur- Port 0 pins that have 1’s written to them float, and in ing programming of the EPROM parts and during that state can be used as high-impedance inputs. program verification of the ROM and EPROM parts. Port 0 is also the multipiexed low-order address and The protection feature of the 8051AHP causes bits data bus during accesses to external Program and P2.4 through P2.7 to be forced to 0, effectively limit- Data Memory. In this application it uses strong inter- ing externa! Data and Code space to 4K each during nal pullups when emitting 1's and can source and external accesses. sink 8 LS TTL inputs. Port 3: Port 3 is an 8-bit bidirectional 1/O port with Port 0 also receives the code bytes during program- internal pullups. The Port 3 output buffers can sink/ ming of the EPROM parts, and outputs the code source 4 LS TTL inputs. Port 3 pins that have 1's bytes during program verification of the ROM and written to them are pulled high by the internal pull- EPROM parts. External pullups are required during ups, and in that state can be used as inputs. As program verification. inputs, Port 3 pins that are externally pulled low will source current (I; on the data sheet) because of the Port 1: Port 1 is an 8-bit bidirectional 1/O port with pullups. internal pullups. The Port 1 output buffers can sink/ source 4 LS TTL inputs. Port 4 pins that have 1's Port 3 also serves the functions of various special written to them are pulled high by the internal pull- features of the MCS 51 Family, as listed below: ups, and in that state can be used as inputs. As inputs, Port 1 pins that are externally pulled low will source current (Ij, on the data sheet) because of the Alternative Function internal pullups. P3.0 | RXD (serial input port) Port 1 also receives the low-order address bytes P31 TXD (serial output port) during programming of the EPROM parts and during P3.2 | INTO (external interrupt 0) program verification of the ROM and EPROM parts. P3.3 | INT? (external interrupt 1) in the 8032AH, 8052AH and 8752BH, Port 1 pins | P94 | TO (Timer 0 external input) P1.0 and P1.1 also serve the T2 and T2EX func- P3.5 | 71 (Timer 1 external input) tions, respectively. P3.6 WR (external data memory write strobe) P3.7 | AD (external data memory read strobe) | Ret | nematwerunction | RST: Reset input. A high on this pin for two machine cycles while the oscillator is running resets the de- Pt.0 T2 (Timer/Counter 2 External Input) vice. P14 T2EX (Timer/Counter 2 Capture/Reload Trigger) ALE/PROG: Address Latch Enable output pulse for latching the low byte of the address during accesses - s bidirearti 5 to external memory. This pin is also the program Port 2: Port 2 is an 8-bit bidirectional I/O port with A eno A . internal pullups. The Port 2 output butfers can sink/ BUS. input (PROG) during programming of the source 4 LS TTL inputs. Port 2 pins that have 1's Parts. written to them are pulled high by the internal pull- - . ups, and in that state can be used as inputs. As ere eet ALE is omitted at a constant inputs, Port 2 pins that are externally pulled low will é the oscillator frequency, lay be use source current (Ij_ on the data sheet) because of the for external timing or clocking purposes. Note, how- internal pullups. i ever, that one ALE pulse is skipped during each ac- ° cess to external Data Memory. 2-24 | www.chipinfo.ru Be sure to visit CHIPINFO web site for more information.

MCS® 51 CONTROLLER intel ; Table 1, EXPRESS Prefix identification [retin | Package Type Temperature Range | __ Burnin | pT Phastic | Commerciat | No ee pNP cc Commorciah | NO JT ort | toned TN | me | astic | Extended TN Jom Tuco Etonded =| NO [ae [resto [Commerc | ves ——| | oo ordi | ommercia | vos [oe Plastic toned =| Yos NOTE: Contact distributor or local sales office to match EXPRESS prefix with proper device. DESIAN CONSIDERATIONS * marie oe ae tee re © If an 8751BH or 8752BH is replacing an 8751H in + . a future design, the user should carefully com- following a oecuons shat use the Data Fointer pare both data sheets for DC or AC Characteris- only roa ‘e at address locations below tic differences. Note that the Vi, and Ii} specifi- . cations for the EA pin differ significantly between MOVX A,@DPTR the devices. oo MOVX @DPTR, A * Exposure to light when the EPROM device is in operation may cause logic errors. For this reason, When the Data Pointer contains an address it is suggested that an opaque label be placed above the 4K limit, those locations will not be ac- over the window when the die is exposed to am- cessed. bient light. To access Data Memory above 4K, the MOVX @Ri,A or MOVX A,@Ri instructions must be used. 2-26 | www.chipinfo.ru Be sure to visit CHIPINFO web site for more information.

intel ° MCS® 51 CONTROLLER ABSOLUTE MAXIMUM RATINGS* NOTICE: This is a production data sheet. It is valid for the devices indicated in the revision history. The Ambient Temperature Under Bias . ~ 40°C to + 85°C Specifications are subject to change without notice. Voltage on EA/Vpp Pin to Vss Maximum Ratings” may cause permanent damage. 8751H ~0.5Vto +21.5V These are stress ratings only. Operation beyond the vertetssesssesee sess: SONI : “Operating Conditions” is not recommended and ex- OPERATING CONDITIONS [ Symbot_ | Description [Min [Max units Ta Ambient Temperature Under Bias Commercial ) +70 °C Express -40 +85 °C Supply Voltage [45 | ss | vy | Oscillator Frequency a DC CHARACTERISTICS (Over Operating Conditions) _ All parameter values apply to all devices unless otherwise indicated Symbol| Parameter‘ Min | Wax | Unite | Test Gondltions Vit Input Low Voltage (Except EA Pin of Vv 8751H and 8751H-8) Vier Input Low Voltage to EA Pin of 0.7 Vv 8751H and 8751H-8 input High Votage ExceptxTALZ AS) | 20 [veo+os| v |] Input High Voltage to XTAL2, RST [ 25 | Voc + 05 XTAL1 = Vsg Vino input High Voltage to EA pin 5.5V of 8751BH and 8752BH Output Low Voltage (Ports 1, 2, 3)* [ [| o48 | Vv [ign =16mA Vout Output Low Voltage (Port 0, ALE, PSEN)* 8751H, 8751H-8 0.60 v lo. = 3.2mA 0.45 V jig. =24mA All Others 0.45 v lo. = 3.2mA Output High Voltage (Ports 1,2,3,ALE,PSEN) | 24 | | V_| low = —80nA Vou1 Output High Voltage (Port 0 in v loo = —400 pA External Bus Mode) Logical 0 Input Current (Ports 1,2,3,andRST) | | —500 | pA | Vin = 0.45V hu Logical 0 Input Current (EA) 8751H and 8751H-8 MA | Vin = 0.45V 8751BH mA | Vin = Vss 8752BH —10 mA | Vin = Vss mA | 2-27 www.chipinfo.ru Be sure to visit CHIPINFO web site for more information.

MCS® 51 CONTROLLER intel DC CHARACTERISTICS (Over Operating Conditions) All parameter values apply to all devices unless otherwise indicated (Continued) [Symbot | Parameter | Min | Max | Unite | Test Conditions [uz | Logical 0 Input Current (XTAL2) || -3.2 | ma_| Vin = 0.45v lu Input Leakage Current (Port 0) 8751H and 8751H-8 +100} pA | 0.45 < Vin < Voc All Others +10 | pA | 0.45 < Vin < Voc hy Logical 1 Input Current (EA) 8751H and 8751H-8 BA | Vin = 2.4V 8751BH/8752BH mA | 4.5V < Vin < 5.5V Input Current to RST to Activate Reset [ | 500 | pa | Vin < (Voc — 1.5V) loc Power Suppty Current: 8031AH/8051AH/8051AHP. 125 mA | All Outputs 8032AH/8052AH/8751BH/8752BH 175 mA | Disconnected; 8751H/8751H-8 250 mA_ | EA= Vcc Pin Capacitance | | 10 | pF | Testfreq = 1 MHz NOTES: 1. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the Vo,s ot ALE/PROG and Ports 1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make_1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100 pF), the noise pulse on the ALE/PROG pin may exceed 0.8V. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. 2. ALE/PROG refers to a pin on the 8751BH. ALE refers to a timing signal that is output on the ALE/PROG pin. 3. Under steady state (non-transient) conditions, Io, must be externally limited as follows: Maximum Io. per port pin: 10 mA Maximum Io, per 8-bit port - Port 0: 26 mA Ports 1, 2, and 3: 15mA Maximum total Ig. for all output pins: 71 mA If Io, exceeds the test condition, Vo, may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2-28 | www.chipinfo.ru Be sure to visit CHIPINFO web site for more information.

intel . MCS® 51 CONTROLLER EXPLANATION OF THE AC SYMBOLS bee Net LOW, oF ALE Each timing symbol has 5 characters. The first char- Q: Output data acter is always a ‘T’ (stands for time). The other R: RD signal characters, depending on their positions, stand ‘for T: Time the name of a signal or the logical status of that V: Valid signal. The following is a list of all the characters and W: WR signal what they stand for. X: No longer a valid logic level Z: Float A: Address C: Clock For example, D: Input Data H: Logic level HIGH TAVLL = Time from Address Valid to ALE Low. |: Instruction (program memory contents) TLLPL = Time from ALE Low to PSEN Low. AC CHARACTERISTICS (under Operating Conditions; Load Capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; Load Capacitance for All Other Outputs = 80 pF) EXTERNAL PROGRAM MEMORY CHARACTERISTICS 1/TCLCL | Oscillator Frequency pos 2.0 Me | TLHLL | ALE Pulse Width | va7 [| | arcucu-ao [Ts | TAVLL | AddressValidtoALELow | 43 | (| toici-4o | Sins | TLLAX | AddressHoldafterALELow| 48 | ——*(| ~totc.—35 | sss | TLLIV ALE Low to Valid Instr In 8751H 4TCLCL—150 | ns All Others 4TCLCL-100 | _ns TLLPL | ALELowtoPSENLow | s8_—| | TcicL-25 | ons TPLPH | PSEN Pulse Width 8751H 3TCLCL~60 Ail Others aTCLCL-35 TPLIV PSEN Low to Valid Instr In 8751H 100 3TCLCL-150 | ns All Others 125 3TCLCL-126 | ns inputinstrHoldafterPSEN | oo | | Tons | TPXIZ__| InputinstrFloatafterPSEN | ss || 63. | = sSS~*~=éd*«CirTCLCL—20 | rs‘ PSENtoAddress Vaid | 75 | | Touct-a [| ns | TAVIV Address to Valid Instr In 8751H 267 STCLCL - 150 All Others 302 STCLCL—115 PSENLowtoAddressFloat | | 20 [| 20s RO Pulse Width [400 | [etoucu-too[ | s_ TWLWH | WR Pulse Width | 400 [ [ercict-too[ sts ‘| TRLDV | RDLowtovalidDatain | ss || 252 |) SS=*«CSTCLCL—-165| ns | TRHOX _| Data Hold after RO a a Data Float after AD po ez TT ateuce=70 [ns ALE LowtoValidDatain | | siz [| arcucu—150| ns | | 2-29 www.chipinfo.ru Be sure to visit CHIPINFO web site for more information.

intel ° MCS® 51 CONTROLLER EXTERNAL PROGRAM MEMORY READ CYCLE TLHLL ALE ‘ TULPL TPLPH TAVLL TELIV PSEN [Fp TPL -TPXAV TPXIZ PORT 0 (_inste in TAVIV: PORT 2 (tsi) AB- AIS 272318-£ EXTERNAL DATA MEMORY READ CYCLE 2 | ALE PSEN TLLWL — TRLRH RO TAVLL TRLDV ‘TRHOZ . Port o {_A0-A7 FROM RIOR DPL_ KK) (ata) INSTR. IN TAVWL —— TAVDV PORT 2 AB“A15 FROM PCH 272318-6 EXTERNAL DATA MEMORY WRITE CYCLE ALE PSEN WR TAVLL TLLAX Javwx TWHOX PORTO fata our KX A0- a7 FROM POL {INSTR IN TAVWL PORT 2 AB~A1S FROM PCH 272318-7 | 2-31 www.chipinfo.ru Be sure to visit CHIPINFO web site for more information.

® 51 CONT MCS® 51 CONTROLLER intel . SERIAL PORT TIMING—SHIFT REGISTER MODE Test Conditions: Over Operating Conditions; Load Capacitance = 80 pF pee rem oe ee TXLXL [Serial Port Clock CycleTime | 10 | | rato | ‘| as | TQVXH | Output Data Setup to Clock Rising 700 JOTCLCL— 133 Edge TXHQX | Output Data Hold after Clock 2TCLCL—117 Rising Edge TXHDX | input Data Hold after Clock Rising Edge TXHDV | Clock Rising Edge to Input Data 700 JOTCLCL— 133 Valid SHIFT REGISTER MODE TIMING WAVEFORMS STRUCTION | © { 1 | 2 | 3 4 4 | 5S | 6 | F JY BY Po TXLxXl—y ot rnnox | OUTPUT DATA ED GD CD GE Gay, t | sel pe TXHOX 4 WRITE TO SBUF TXHOV r ami INPUT DATA CD DC DL) ND CT ED ZT) DCE ND CE) ED (ZED —— 4 CLEAR RI ‘SET RI 272318-8 2-32 | www.chipinfo.ru Be sure to visit CHIPINFO web site for more information.

intel > MCS® 51 CONTROLLER EXTERNAL CLOCK DRIVE [symbot [Parameter «win | Wax | one 4/TCLCL Oscillator Frequency (except 8751H-8) 12 MHz 8751H-8 8 MHz Toncx | Higntime Tm Td id EXTERNAL CLOCK DRIVE WAVEFORM TCHCX TCLCH —e—- TCHCL 2 25 25 25 os o8 TOLCX TCLCL 272318-9 AC TESTING INPUT, OUTPUT WAVEFORM a 20 20 oe os ous 272318-10 AC Testing: inputs are driven at 2.4V for a Logic 1" and 0.45V for a Logic “O". Timing measurements are made at 2.0V for a Logic “1" and 0.8V for a Logic “0”. | 2-33 www.chipinfo.ru Be sure to visit CHIPINFO web site for more information.

intel ° MCS® 51 CONTROLLER EPROM Security oy X = “DON'T CARE™ The security feature consists of a “locking” bit which Y when programmed denies electrical access by any vee external means to the on-chip Program Memory. Pp The bit is programmed as shown in Figure 7. The setup and procedure are the same as for normal P2.0- Po x EPROM programming, except that P2.6 is held at a x 23 eysay logic high. Port 0, Port 1 and pins P2.0-P2.3 may be in any state. The other pins should be held at the P24 ALE ALE PROG “Security” levels indicated in Table 3. P28 50 ma PULSE TO GNO P26 Once the Security Bit has been programmed, it can wt er nm tiver be cleared only by full erasure of the Program Mem- xm ory. While it is programmed, the internal Program ver Memory can not be read out, the device can not be a ‘3 RST further programmed, and it can not execute out of ie xTALy external program memory. Erasing the EPROM, vss PSEN 2 thus clearing the Security Bit, restores the device's 4 full functionality. It can then be reprogrammed. 27201813 a Figure 7. Programming the Security Bit Erasure Characteristics 3 09 9 rity Erasure of the EPROM begins to occur when the The recommended erasure procedure is exposure on i to light with lengths short to ultraviolet light (at 2537 Angstroms) to an integrat- device is exposed Sonpan wave so ss ‘i Pt ed dose of at least 15 W-sec/cm2. Exposing the ang ‘uorescen iting have wavelongihe w tg EPROM to an lave lamp of 12,000 Wome range, exposure te these light sources Over an ex- rating tor 20 to 30 mn tes, at @ distance of about tended time (about 1 week in sunlight, or 3 years in Vineh, should be sufficient. room-level fluorescent lighting) could cause inadver- a B tent erasure. If an application subjects the device to Erasure leaves the array in an all 1's state. this type of exposure, it is suggested that an opaque label be placed over the window. EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS Ta = 21°C to 27°C; VCC = 5V +10%; VSS = OV [symboi_ [Parameter [Min «| Ss Max—«—sunits Programming SupplyVottage | 205 [ats | | iep__ [Programming Supply Curent [| 80S mC 1/TCLOL Oscillator Frequency a TAVGL Address Setup to PROG Low astopch | CdCSC~—is*” TGHAX Address Hold after PROG arcane [| TCSs—s” TDVGL Data Setup to PROG Low astcich [| ti‘idE:C‘(<‘CO™C*d TEHSH P2.7 (ENABLE) High to VPP aetcrce [| t—é‘“~*T:S*é‘(‘CSNSC‘*d TSHGL VPP Setup to PROG Low ee es ee TGHSL VPP Hold atter PROG ee ee TGLGH PROG wiath Po as sms TAVQV Address to Data Valid [CSS SCOCT|SSCS~=i*d TELQV ENABLE Low to Data Valid [ T etccce f=” TEHOZ Data Float after ENABLE [ oo ~~ aetace Sf sid | 2-35 www.chipinfo.ru Be sure to visit CHIPINFO web site for more information.

MCS® 51 CONTROLLER intel EPROM PROGRAMMING AND VERIFICATION WAVEFORMS PROGRAMMING VERIFICATION pio-e17 ) 20-923 y ADDRESS || mm TOVGL A TAVGL ALE/PROG sr | Ex/ver TTL HIGH ‘TTL HIGH TTL HIGH TEHSH TELQV TEHQZ P27 (ENABLE) 272318-14 For programming conditions see Figure 5. For verification conditions see Figure 6. 2-36 | www.chipinfo.ru Be sure to visit CHIPINFO web site for more information.

tor needs to be running is that the internal bus is age on the EA/Vpp pin must be at the valid EA/Vpp. EPROM location to be programmed is applied to sections of this data sheet. EPROM location. The setup is shown in Figure 8. free of glitches. Figure 8. Programming the EPROM Table 4. EPROM Programming Modes for 875XBH www.chipinfo.ru Be sure to visit CHIPINFO web site for more information.

Figure 9. Then, the byte just programmed may be ly “unencrypt” the data during verity.) ming Lock features is that the Lock features cannot low read strobe. ming is by observing that their features are enabled.

25 PULSES

Figure 9. PROG Wavetorms Figure 10. Veritying the EPROM www.chipinfo.ru Be sure to visit CHIPINFO web site for more information.

intel ° MCS® 51 CONTROLLER . PROGRAM MEMORY LOCK Table 5. Lock Bits and their Features The two-level Program Lock system consists of 2 Lock Bits Logic Enabled Lock bits and a 32-byte Encryption Array which are | Bi | vez | used to protect the program memory against soft- — ware piracy. U U_—_|Minimum Program Lock features enabled. (Code Verify will still be encrypted by the Encryption ENCRYPTION ARRAY Array) Within the EPROM array are 32 bytes of Encryption u owe in progeny weno od rom Array that are initially unprogrammed (all 1s). Every disabled from fetching code bytes| time that a byte is addressed during a verify, 5 ad- from internal memory, EA is dress lines are used to select a byte of the Encryp- sampled and latched on reset tion Array. This byte is then exclusive-NORed and further programming of the (XNOR) with the code byte, creating an Encrypted EPROM is disabled Verify byte. The algorithm, with the array in the un- Programmed state (all 1s), will return the code in its ‘Same as above, but Verify is also original, unmodified form. disabled 2 It is recommended that whenever the Encryption Ar- Lv |p | Reserved for Future Definition fay is used, at least one of the Lock Bits be pro- P = Programmed grammed as well. U = Unprogrammed LOCK BITS READING THE SIGNATURE BYTES Also included in the EPROM Program Lock scheme The Sonature bytes sre read by the oon procecre two Lock Bits which functi shown in Tabl as a normal verification of locations an , B10 Mo Lock Bits which function as shown in Table SP that Pa.6 and 37 ned wo be pulled to a logic low. The values returned are: Erasing the EPROM also erases the Encryption Ar- (030H) = 89H indicates manufactured by Intel ray and meine returning the part to full un- (031H) = 51H indicates 8751BH , 52H indicates 8752BH To ensure proper functionality of the chip, the inter- nally latched value of the EA pin must agree with its external state. | 2.39 www.chipinfo.ru Be sure to visit CHIPINFO web site for more information.

MCS® 51 CONTROLLER ICS® 51 CONTRO intel ° ERASURE CHARACTERISTICS this type of exposure, it is suggested that an opaque label be placed over the window. Erasure of the EPROM begins to occur when the 8752BH is exposed to light with wavelengths shorter. © The recommended erasure procedure is exposure than approximately 4,000 Angstroms. Since sunlight to ultraviolet light (at 2537 Angstroms) to an integrat- and fluorescent lighting have wavelengths in this ed dose of at lease 15 W-sec/cm. Exposing the range, exposure to these light sources over an ex- EPROM to an ultraviolet lamp of 12,000 4.W/cm rat- tended time (about 1 week in sunlight, or 3 years in ing for 30 minutes, at a distance of about 1 inch, room-level fluorescent lighting) could cause inadver- should be sufficient. tent erasure. If an application subjects the device to Erasure leaves the array in an all 1s state. EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS (Ta = 21°C to 27°C, Vocg = 5.0V 410%, Vgg = OV) Programming Supply Votage | 125 | 190 «SV id [ise | Programming Supply Curent [<i so | ma TAVGL Address Setup to PROG Low acre «| t—“‘iYStstSCd TGHAX ‘Address Hold After PROG asrocce | t—‘“‘zTSt*~C;*;:SCSC*zd TDVGL Data Setup to PROG Low arora, «| t—‘“‘RSOS*;*S*C*z TGHDX Data Hold After PROG aerccche - || —t—‘“‘*LSCSC‘C‘i*zC TEHSH P2.7 (ENABLE) High to Vpp atoce [| || TSHGL Vpp Setup to PROG Low a TGHSL Vpp Hold After PROG ee TGLGH PROG Wiath [so tos TAVOV Address to Data Valid [i‘(asézCLC§Ctortcrce «S| si TELQV ENABLE Low to Data Valid | —Ss«d|saotcce | TEHQZ Data Float After ENABLE | o | «#racnc [| | TGHGL PROGHigh toPROGLow | 10 | Ts EPROM PROGRAMMING AND VERIFICATION WAVEFORMS PROGRAMMING VERIFICATION feoceea ADDRESS (scores) Tavay Port 0 Data Tovot s oxox | Tavot Pulses ToHAX ALE/PROG 5. TSHGL ToHst _ TOLGH TCHGL ee Ve EA/HIGH | | reHsH TeLay reHOz 2.7 272318-18 2-40 | www.chipinfo.ru Be sure to visit CHIPINFO web site for more information.

intel ° MCS® 51 CONTROLLER DATA SHEET REVISION HISTORY This datasheet (272318-001) replaces the following datasheets: MCS® 51 Controllers (270048-007) 8051AHP (270279-004) 8751BH (270248-005) 8751BH EXPRESS (270708-001) 8752BH (270429-004) 8752BH EXPRESS (270650-002) | 2-41 www.chipinfo.ru Be sure to visit CHIPINFO web site for more information.

Product Information

8052AH specifications and overview.

Summary

MCS 51 8-BIT CONTROL-ORIENTED MICROCONTROLLERS

Description

MCS 51 8-BIT CONTROL-ORIENTED MICROCONTROLLERS

Source title 8052AH Datasheet(PDF) - Intel Corporation

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