P8748H INTEL | Alldatasheet

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Figure 3. Pin Configuration Figure 4. Pad Configuration Table 1. Pin Description Output strobe for 8243 1/0 expander. Port 2 serve as a 4-bit I/O expander bus for 8243. BUS using the FID, WR strobes. The port can also be statically latched.

Table 1. Pin Description (Continued) designated the timer/counter input using the STRT CNT instruction. disabled after a reset. Also testable with conditional jump instruction. data onto the bus from an external device. Used as write strobe to external data memory. the processor through each instruction.

Table 2. Instruction Set

Table 2. Instruction Set (Continued)

moses intel. ABSOLUTE MAXIMUM RATINGS* NOTICE: This is a production data sheet. The specifi- c qT Bi c c cations are subject to change without notice. Voltage on any Pin with Respect These are stress ratings only. Operation beyond the D.C. CHARACTERISTICS T, = 0°C to +70°C; Voc = Von = 5V + 10%; Vsg = OV Vit Input Low Voltage (All Except RESET, X1, X2) Vius Input Low Voltage v All (RESET, x1, X2) Vin Input High Voltage Voc | V (All Except XTAL1, XTAL2, RESET) Vint Input High Voltage Veco | V (X1, X2, RESET) Vou Output Low Voltage 045 | Vv | lo = 20mA (Bus) Vou Output Low Voltage Vo] top = 1.8mA All (RD, WR, PSEN, ALE) Voz Output Low Voltage 045 | V_ | to = 1.0mA (PROG) Vous Output Low Voltage Vo | to = 1.6mA (All Other Outputs) Vou Output High Voltage Vs | lon = —400 pA (BUS) Vout Output High Voltage V | lon = —100 pA All (RD, WR, PSEN, ALE) Vou2 Output High Voltage V | lon = -40 nA (All Other Outputs) 1-32 |

intel Mose.4s D.C. CHARACTERISTICS T, = 0°C to +70°C; Voc = Vop = 5V + 10%; Vg = OV (Continued) fu Leakage Current BA | Vgg < Vin < Veo M1, INT) tut Input Leakage Current BA | Vsg + 0.45 < Vin < Voc All (P10-P17, P20-P27, EA, 5S) lua Input Leakage Current BA | Vg < Vin < 3.8 = 1 lo Leakage Current +10 | yA | Vsg < Vin $ Voc (BUS, TO) (High Impedance State) Vop Supply Current 8048AH (RAM Standby) 8035AHL 7 | ma 8049AH 8039AHL mA 8050AH 8040AHL Ipp + | Total Supply Current* mA 8048AH loc 8035AHL 70 | ma 8049AH 8039AHL mA 8050AH 8040AHL [ [so [soo [ma | iY ra | | [sof so [maf | Parson | Voo RAM Standby Voltage V_| Standby Mode Reset 8048AH sViut 8035AH v 8049AH 8039AH v 8050AH B040AHL “loc + loo are measured with all outputs in their high Impedance state, RESET low; 11 MHz crystal applied, INT. SS, and EA floating, | 1-33

wes intel. A.C. CHARACTERISTICS Ty = 0°C to + 70°C; Voc = Von = 5V + 10%; Vgg = OV [time | Conditions conet | tami | da | | te [Lt | cockrerog | tvtairog | 90.9 | 1000 | ns | iWote) _| [uc | averusowin | st-azo [to [| ns || [ta | Adarsowptoate | atta | 70 [| ns | notes | [ua | AdarHotatromace | ean 60 [ns [| | tccr | ControtPuise wietn (RO, WR) [761-200 | 40 | [ns [| | toce | Controtpuise wiatn (SEN) | et-200 | 350 | | ns | | tow | DataSetupbetrewn | st-200 | a0 | [ns | | wo | OataHodatterwR | 50 [ao | ns | [ton___| datatios(R.PsER) | tst-so | 0 [io [ns [| [aor | Fowoewn | aio | as | mm | [aoe | PSENoOewim =i ase | | ao | me |_| | tow | Adersewptown | st-ts0 [300 [| ns | | twor__| AddrSetupto Data (RO) | rost-2zo | [730 | ns | | [ase | Ade SeuptoOata SEH | 7st-200 | | «60 | me |_| [_tweor__| AddrFloattoRD,WA | at-ao | 140 | | ns | note) | L_twrce | AdcrFioattoPSEN | ost-ao_ | to | | ns | nota) | [waror | ALEtoConror(O.WR) | at-75_ | 200 | | ns | [karce | ALEto connor PSER) [sre | co | | me | | toa | Controtto ave (RO.WR,PROG) | tres | 25 | | ns | | [cs | ConoiioaLe sem | a7 | a0 | | we | [ice | Poncontoiseuptormos | s-e0 | so | |e | [ec | Poncenroinoistornos | —ai-a50 | 100 | | ve | [ten | ProGtorampuvaia | asi-veo | | os [me | [er | routdaaHosromends |r [| wo [me | [ior | Oupwonm seu | eas ae | re | [ee | PRocPuse wan | josi-aso| m0 | | re || [in| Ponavoseupio aie | at-a00 | veo | | me |_| [ue | Pon2vorodtoate | ost-zo_ | ts | | ns | | [ ev | Potouputtromace | astetoo | | 50 | ns | [tena | ToRepRate | tf avo | ns J [ov [owetme | tte [aso fe [id NOTES: 1. Control outputs: C, = 80 pF. BUS Outputs: C, = 150 pF. 2. BUS High Impedance Load 20 pF 3. f(t) assumes 50% duty cycle on X1, X2, Max clock period is for a 1 MHz crystal input. 1-34 |

INSTRUCTION FETCH FROM PROGRAM READ FROM EXTERNAL DATA MEMORY MEMORY = shuaresle— E sheet —| as [1 i cs we SI - Feet eas wr b-tcez =} teas " os wer) Ticoanmal [* afte —e ous rcoamma | _YoataFioatna wusnionmaX TX noame x Ynconvna) tra ba 1 [Bomess T- wo? =| INSTRUCTION 270053-5 270088-4 WRITE TO EXTERNAL DATA MEMORY INPUT AND OUTPUT FOR A.C. TESTS Freer =pteate 270083-7 ACC. testing inputs are driven at 2.4V for a logic 1" and 0.45V for we L_Jf a logic "0". Output timing measurements are made at 2.0V for a rooners _|towfecbe wo logic "1" and 0.8V tor a logic “0” ousrioarimeX XX ona Ronn iZ FLOATING tw 270053-6 PORT 1/PORT 2 TIMING seer a nof le poo 4 wt NPR she | | ' pur =e PORT 20-23 047A X_new rz0-23 para YXrox pe: T r 1 1 Pet PORT 26-27 PORT 10-17 ATA | ew PORT GaTA | | I ' fescas we — ezawoen Pa p-— tape af poetry ourrur TX vex‘ Xeonrananonra)( rons connenX| ournuronal | i in ' Vl sores | | [Lo be— 4 Fy mor ror )fonrmmonra)yfronrcéwrmox)X BR) ] i [rer afew | TI \\ “wo 270083-8 | 1-35

MCS®-48 intel ® CRYSTAL OSCILLATOR MODE CERAMIC RESONATOR MODE cS 2| xvas ¢ 2{ rans ! eo 1 H bane war ers. SS 01 = C2 = 33pF 5% i er oe ee Ce Pe) = wma CJ 2 oa 3 270053-8 (270053-10 C1 = 5 pF 4% pF + (STRAY < 5pF) C2 = (CRYSTAL + STAY) < 8 pF C3 = 20 pF £1 pF + (STRAY < § pF) Crystal series resistance should be ess than 301 at 11 MHz; loss than 75M at 6 Miz; less than 18081 at 3.6 Miz DRIVING FROM EXTERNAL SOURCE oon

2 ATALY

For XTALI and XTAL2 detine “high” as vottages above 1.6V and “low” as voltages below 1.6V. The duty cycle requirements for externally drving XTAL} and XTAL2 using the crcuis. shown above are as folows: XTALY must be high 35-65% of the period land XTAL2 must be high 35-65% ofthe penod. Rise and tal umes ‘must be faster than 20 ns. 1-36 |

@ a intel. Mese.4s PROGRAMMING AND VERIFYING THE WARNING: P6749H/48H PROGRAMMABLE ROM An attempt to program a missocketed P8749H/48H will result in severe damage to the part. An indication ve n of a properly socketed part is the appearance of the Programming Verificatio ALE clock output. The lack of this clock may be In brief, the programming process consists of: acti used to disable the programmer. vating the program mode, applying an address, ; latching the address, applying data, and applying a ‘The Program/Verify sequence is: Programming pulse. Each word is programmed com- 1, Va = SV, Clock applied or internal oscillator pletely before moving on to the next and is followed operating, RESET = OV, TO = 5V, EA = SV, by a verification step. The following is a list of the BUS and PROG floating. P10 and P11 must be pins used for programming and a description of their tied to ground. { functions: 2. Insert P8749H/48H in programming socket [pin [Function] a veut met Program mode) 4. EA = 18V (activate program mode) rats Clock Input (8 to 4.0 MH2) 5. Address applied to BUS and P20-22 FESET | initialization and Address Latching 8. RESET = SV (latch address) TO Selection of Program or Verifying Mode 7. Data applied to BUS EA Activation of Program/Verify Modes 8. Vpp = 21V (programming power) BUS | Address and Data Input 9. PROG = Voc or float followed by one 50 ms Data Output During Verify pulse to 18V DD = if PROG __| Program Pulse Input 11. TO = BV (verify mode) 12, Read and verify data on BUS 18. T0 = ov 14. RESET = OV and repeat from step 5 15. Programmer should be at conditions of step 1 when P8749H/48H is removed from socket. NOTE: Once programmed the P8749H/48H cannot be erased. | 1-37

moses intel. A.C. TIMING SPECIFICATION FOR PROGRAMMING P8748H/P8749H ONLY Ta = 25°C +5°C; Voc = 5V +5%; Vpp = 21 +0.5V [Symbol [Parameter Min_ | Max | Unit | TestConditions [taw | Address Setup Time to RESET [acy [OP [twa | Address Hold Time AtterRESET | atcy | | | [tow | Data in Setup Time to PROG [atey [ [two | Data in Hold Time After PROG [atcy | BESET Hold Time to Verity [Vatey [OT Vpp Hold Time Before PROG [To [io [ms [| Vpo Hold Time After PROG [oo [io [ms [| [_tpw | Program Pulse Width [so [eo [om [| TOSetup Time forProgamMode | 4toy | | | TOHoId Time After ProgramMode | 4toy || | [too | T0to Data Out Delay [OT atcy [OO [ww | RESET Pulse Width to Latch Address | atcy | [| Vpp and PROG Rise andFallTimes |" 0.5 | 100 | ps _| CPU Operation Cycle Time [avs [os [ous [| RESET Setup Time before EA [acy | NOTE: If Test 0 is high, tp can be triggered by RESET. D.C. CHARACTERISTICS FOR PROGRAMMING P8748H/P8749H ONLY Ta = 25°C +5°C; Voc = 5V +5%; Vpp = 21 +0.5V ["symboi [Parameter | Min’ | Max | Unit | Test Conditions Vo Program Voltage High Level [as fas {ov [| Vpp Voltage Low Level [avs [525 [ov [| PROG Program VoltageHighLevel | 175 | wes [| v | | Ve. PROG Voltage Low Level [40 [Voc [ov [| Vea EAProgram or Verity VoltageHighLevel | 175 | 185 | v |_| lop Vpp High Voltage Supply Current | 200 [ma [| prog ___| PROG High Voltage Supply Current [fo [om | ‘lea ____ |_EAHigh Voltage Supply Current [fio [im [Oo 1-38 |

intel. Mcse-4s SUGGESTED ROM VERIFICATION ALGORITHM FOR ROM DEVICE ONLY INITIAL ROM DUMP CYCLE SUBSEQUENT ROMDUMPCYCLES ace UU (ores) (OUTPUT) : ov ‘ : eA. I put) : oe L_*roness {rowers Lf sopness LY 52m | a i TONPUT) : 1 (NPT) : 270083-12 ae | 49H | son Veo = Voo = +5¥ Ato | “0 [aooa |"ApoR vss = OV NOTE: ALE is function of X1, X2 inputs. COMBINATION PROGRAM/VERIFY MODE (PROGRAMMABLE ROMS ONLY) ca VEAH ow! es f— ee vec veo iw ‘ To wer ww Voc. RESET | vu twat twa +100 DATA TO BE DD cwvonr _)--~ (GiPtRtS Monod ue) ~~ {Xs -- EX WEXT tvoow NDOH Yoo —--— ~r Yoo vec i | ven _ | wo 270059-13 | 1-39