80296SA INTEL | Alldatasheet

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Technical content

Datasheet sections

  • 1.0 Product Overview
  • 2.0 Nomenclature Overview
  • 3.0 Pinout
  • 4.0 Signals
  • 5.0 Address Map
  • 6.0 Electrical Characteristics
  • 6.1 DC Characteristics
  • 6.2 AC Characteristics
  • 6.2.1 Relationship of XTAL1 to CLKOUT
  • 6.2.2 Explanation of AC Symbols
  • 6.2.3 AC Characteristics — Multiplexed Bus Mode
  • 6.2.3.1 System Bus Timings, Multiplexed Bus
  • 6.2.3.2 READY Timing, Multiplexed Bus
  • 6.2.4 AC Characteristics — Demultiplexed Bus Mode
  • 6.2.4.1 System Bus Timings, Demultiplexed Bus
  • 6.2.4.2 READY Timing, Demultiplexed Bus
  • 6.2.5 HOLD#, HLDA# Timings
  • 6.2.6 AC Characteristics — Serial Port, Synchronous Mode
  • 6.2.7 External Clock Drive
  • 7.0 Thermal Characteristics
  • 9.0 Datasheet Revision History

Datasheet sections

COPYRIGHT © INTEL CORPORATION, 1997 January 1997 Order Number: 272748-003 80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER The 80296SA is a member of Intel’s 16-bit MCS® 96 microcontroller family. The 80296SA features 6 Mbytes of linear address space, a demultiplexed bus, and a chip-select unit. The external bus can dynamically switch between multiplexed and demultiplexed operation. The device has hardware and instructions to support various digital signal processing algorithms. NOTE This datasheet contains information on new products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. ■ 50 MHz Operation† ■ 6 Mbytes of Linear Address Space ■ 512 Bytes of Register RAM ■ 2 Kbytes of Code/Data RAM ■ Register-register Architecture ■ Footprint and Functionally Compatible Upgrade for the 8XC196NP and 80C196NU ■ Optional Phase-locked Loop (PLL) Circuitry with 2x or 4x Clock Multiplier ■ 32 I/O Port Pins ■ 19 Interrupt Sources, 14 with Programmable Priorities ■ 4 External Interrupt Pins and NMI Pin ■ 2 Flexible 16-bit Timer/Counters with Quadrature Counting Capability ■ 3 Pulse-width Modulator (PWM) Outputs with High Drive Capability ■ Full-duplex Serial Port with Dedicated Baud-rate Generator † 40 MHz standard; 50 MHz is Speed Premium ■ Chip-select Unit — 6 Chip-select Pins — Dynamic Demultiplexed/Multiplexed Address/Data Bus for Each Chip Select — Programmable Wait States (0–15) for Each Chip Select — Programmable Bus Width (8- or 16-bit) for Each Chip Select — Programmable Address Range for Each Chip Select ■ Event Processor Array (EPA) with

4 High-speed Capture/Compare

■ Multiply and Accumulate Executes in 80 ns Using the 40-bit Hardware Accumulator ■ 880 ns 32/16 Unsigned Division ■ 100-pin QFP Package ■ Complete System Development Support ■ High-speed CHMOS Technology

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel dis- claims any express or implied warranty, relating to sale and/or use of Intel products including liability or war- ranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel retains the right to make changes to specifications and product descriptions at any time, without notice. *Third-party brands and names are the property of their respective owners. Copies of documents which have an ordering number and are referenced in this document, or other Intel liter- ature, may be obtained from: Intel Corporation P.O. Box 7641 Mt. Prospect, IL 60056-7641 or call 1-800-548-4725

1.0 PRODUCT OVERVIEW

various digital signal processing algorithms. Figure 1. 80296SA Block Diagram

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2.0 NOMENCLATURE OVERVIEW

Figure 2. The 80296SA Family Nomenclature Table 1. Description of Product Nomenclature with Intel standard burn-in.

3.0 PINOUT

Figure 3. 80296SA 100-pin QFP Package

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Table 2. 80296SA 100-pin QFP Pin Assignment

5 NC (see Note) 30 V

11 A3 36 V CC 61 A13 86 AD13

13 A5 38 V

NOTE: For compatibility with future products, tie pin 5 to VCC and leave pins 2 and 27 unconnected.

Table 3. 80296SA 100-pin QFP Pin Assignment Arranged by Functional Categories

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4.0 SIGNALS

Table 4. Signal Descriptions cycle during both multiplexed and demultiplexed bus modes. addressing of the 1-Mbyte address space. FFFFFH). The microcontroller resets to FF2080H. A19:16 share package pins with EPORT.3:0. using ALE or ADV#. During the data phase, 8- or 16-bit data is transferred. AD7:0 share package pins with P3.7:0. AD15:8 share package pins with P4.7:0. bus; A19:0 for a demultiplexed bus). address/data bus in multiplexed mode. BHE# shares a package pin with WRH#. BHE# or as WRH#. CCR0.2 = 1 selects BHE#; CCR0.2 = 0 selects WRH#.

hold protocol is disabled (WSR.7 is cleared). HLDA#. Once it is asserted, BREQ# remains asserted until HOLD# is deasserted. BREQ# shares a package pin with P2.3. operating frequency (f). CLKOUT has a 50% duty cycle. CLKOUT shares a package pin with P2.7. configuration defaults to the CS5# values. CS5:0# share package pins with P3.5:0. EPA3:0 share package pins with P1.3:0. This is a standard 4-bit, bidirectional port. EPORT.3:0 share package pins with A19:16. Table 4. Signal Descriptions (Continued)

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whether a rising edge/high level or falling edge/low level activates the interrupt. hold protocol is disabled (WSR.7 is cleared). HLDA# shares a package pin with P2.6. An external device uses this active-low input signal to request control of the bus. HOLD# shares a package pin with P2.5. and chip configuration byte reads. INST is low during internal memory fetches.

In normal operating mode, a rising edge on NMI generates a nonmaskable interrupt. NMI has the highest priority of all interrupts except trap and unimplemented opcode. Assert NMI for greater than one state time to guarantee that it is recognized. and branch to the interrupt service routine. you can debug the system using a clip-on emulator. selectable special-function signals. selectable special-function signals. selectable special-function signals. Port 4 is a standard, 4-bit, bidirectional I/O port with high-current drive capability. and P4.2/PWM2. P4.3 has a dedicated package pin.

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frequency-pulse-widths are programmable. PWM2:0 share package pins with P4.2:0. zero and holding the READY pin low produces unpredictable results. down transistor connected to the RESET# pin for 16 state times. allow the PLL to stabilize before the internal CPU and peripheral clocks are enabled. After a reset, the first instruction fetch is from FF2080H.

Timing pin for the return-from-powerdown circuit. SS if either of the following conditions are true.

  • the internal oscillator is the clock source
  • the phase-locked loop (PLL) circuitry is enabled (see PLLEN2:1 signal description) The capacitor causes a delay (at least 2 ms) that enables the oscillator and PLL circuitry to stabilize before the internal CPU and peripheral clocks are enabled. Refer to the “Special Operating Modes” chapter of the 80296SA Microcontroller User’s Manual for details on selecting the capacitor. The capacitor is not required if your application uses powerdown mode and if both of the following conditions are true.
  • an external clock input is the clock source
  • the phase-locked loop circuitry is disabled If your application does not use powerdown mode, leave this pin unconnected. RXD I/O Receive Serial Data In modes 1, 2, and 3, RXD receives serial port input data. In mode 0, it functions as either an input or an open-drain output for data. RXD shares a package pin with P2.1. T1CLK I Timer 1 External Clock External clock for timer 1. Timer 1 increments (or decrements) on both rising and falling edges of T1CLK. Also used in conjunction with T1DIR for quadrature counting mode. and External clock for the serial I/O baud-rate generator input (program selectable). T1CLK shares a package pin with P1.4. T2CLK I Timer 2 External Clock External clock for timer 2. Timer 2 increments (or decrements) on both rising and falling edges of T2CLK. It is also used in conjunction with T2DIR for quadrature counting mode. T2CLK shares a package pin with P1.6. T1DIR I Timer 1 External Direction External direction (up/down) for timer 1. Timer 1 increments when T1DIR is high and decrements when it is low. Also used in conjunction with T1CLK for quadrature counting mode. T1DIR shares a package pin with P1.5. T2DIR I Timer 2 External Direction External direction (up/down) for timer 2. Timer 2 increments when T2DIR is high and decrements when it is low. It is also used in conjunction with T2CLK for quadrature counting mode. T2DIR shares a package pin with P1.7.

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TXD shares a package pin with P2.0. Connect each VCC pin to the digital supply voltage. through the lowest possible impedance path. asserted only during external memory writes. WR# shares a package pin with WRL#. WR# or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#. WRH# shares a package pin with BHE#. BHE# or WRH#. CCR0.2 = 1 selects BHE#; CCR0.2 = 0 selects WRH#. WRL# shares a package pin with WR#. WR# or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#. an external clock source instead of the on-chip oscillator.

5.0 ADDRESS MAP

Table 5. 80296SA Address Map

010000 External device (memory or I/O) connected to address/data bus Extended

64-Kbyte mode, code RAM is identically mapped into page FFH.

002000 External device (memory or I/O) connected to address/data bus Indirect, indexed, extended

000400 External device (memory or I/O) connected to address/data bus Indirect, indexed, extended

000200 Reserved (future register file expansion) —

000000 Lower register file (stack pointer and CPU SFRs) Direct

  1. Unless otherwise noted, write 0FFH to reserved memory locations and write 0 to reserved SFR bits.
  2. The contents or functions of reserved locations may change in future device revisions, in which case a

program that relies on one or more of these locations might not function properly.

  1. External memory occupies the boot memory partition, FF2080–FF7FFH. After reset, the default chip-

select line (CS0#) is active; the first instruction fetch is from FF2080H.

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6.0 ELECTRICAL CHARACTERISTICS

6.1 DC Characteristics

  1. This device is static and should operate below

1 Hz, but has been tested only down to 16 MHz.

  1. When the phase-locked loop (PLL) circuitry is
  2. Assumes an external clock. The maximum fre-

datasheet before finalizing a design. permanent damage. These are stress ratings only. “Operating Conditions” may affect device reliability. Table 6. DC Characteristics Over Specified Operating Conditions

  1. Typical values are based on a limited number of samples and are not guaranteed. The values listed

are at room temperature with VCC = 5.0 V.

  1. For temperatures below 100°C, typical is 10 µA.
  2. For all pins except P4.3:0, which have higher drive capability (see VOL 1).
  3. During normal (non-transient) conditions, the following maximum current limits apply for pin groups
  4. For all pins that were weakly pulled high during reset. This excludes ALE, INST, and NMI, which were

OL 2) and ONCE, which was pulled medium low (see VOL 3).

  1. Pin capacitance is not tested. This value is based on design simulations.

0.45 V I OL = 3 µA

0.45 V I OL = 30 µA

Table 6. DC Characteristics Over Specified Operating Conditions (Continued)

  1. Typical values are based on a limited number of samples and are not guaranteed. The values listed

are at room temperature with VCC = 5.0 V.

  1. For temperatures below 100°C, typical is 10 µA.
  2. For all pins except P4.3:0, which have higher drive capability (see VOL 1).
  3. During normal (non-transient) conditions, the following maximum current limits apply for pin groups
  4. For all pins that were weakly pulled high during reset. This excludes ALE, INST, and NMI, which were

OL 2) and ONCE, which was pulled medium low (see VOL 3).

  1. Pin capacitance is not tested. This value is based on design simulations.

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  1. Typical values are based on a limited number of samples and are not guaranteed. The values listed

are at room temperature with VCC = 5.0 V.

  1. For temperatures below 100°C, typical is 10 µA.
  2. For all pins except P4.3:0, which have higher drive capability (see VOL 1).
  3. During normal (non-transient) conditions, the following maximum current limits apply for pin groups
  4. For all pins that were weakly pulled high during reset. This excludes ALE, INST, and NMI, which were

OL 2) and ONCE, which was pulled medium low (see VOL 3).

  1. Pin capacitance is not tested. This value is based on design simulations.

Figure 4. ICC versus Frequency in Reset

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6.2 AC Characteristics

6.2.1 RELATIONSHIP OF XTAL1 TO CLKOUT

Figure 5. Effect of Clock Mode on CLKOUT

6.2.2 EXPLANATION OF AC SYMBOLS

and its condition, respectively. Symbols represent the time between the two signal/condition points. Table 7. AC Timing Symbol Definitions

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6.2.3 AC CHARACTERISTICS — MULTIPLEXED BUS MODE

Test Conditions: Capacitive load on all pins = 50 pF, Rise and Fall Times = 3 ns. Table 8. AC Characteristics the 80C296SA Will Meet, Multiplexed Bus Mode

  1. 25 MHz is the maximum input frequency when using an external crystal oscillator; however, 50 MHz

can be applied with an external clock source.

  1. When the phase-locked loop (PLL) circuitry is enabled, the minimum input frequency on XTAL1 is 8

MHz. The PLL cannot be run at frequencies lower than 16 MHz.

  1. If wait states are used, add 2t × n, where n = number of wait states.
  2. Assuming back-to-back bus cycles.

Table 9. AC Characteristics the External Memory System Must Meet, Multiplexed Bus Mode

  1. If using the READY signal to insert wait states, you must program at least one wait state in the

BUSCON x register because the first falling edge of READY is not synchronized with a CLKOUT edge.

  1. If using the BUSCONx register without the READY signal to insert wait states, add 2t × n, where n =
  2. If using the BUSCONx register to insert wait states, add 2t × (n–1), where n = number of wait states.
  3. Exceeding the maximum specification causes additional wait states.
  4. If you program two or more wait states in the BUSCON

x register, the TCH 1YX minimum does not apply. Table 8. AC Characteristics the 80C296SA Will Meet, Multiplexed Bus Mode (Continued)

  1. 25 MHz is the maximum input frequency when using an external crystal oscillator; however, 50 MHz

can be applied with an external clock source.

  1. When the phase-locked loop (PLL) circuitry is enabled, the minimum input frequency on XTAL1 is 8

MHz. The PLL cannot be run at frequencies lower than 16 MHz.

  1. If wait states are used, add 2t × n, where n = number of wait states.
  2. Assuming back-to-back bus cycles.

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6.2.3.1 System Bus Timings, Multiplexed Bus

Figure 6. System Bus Timings, Multiplexed Bus Mode

6.2.3.2 READY Timing, Multiplexed Bus

Figure 7. Example READY Timings at 50 MHz, Multiplexed Bus, BUSCONx = 1 Wait State

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6.2.4 AC CHARACTERISTICS — DEMULTIPLEXED BUS MODE

Test Conditions: Capacitive load on all pins = 50 pF, Rise and Fall Times = 3 ns. Table 10. AC Characteristics the 80C296SA Will Meet, Demultiplexed Bus Mode

  1. 25 MHz is the maximum input frequency when using an external crystal oscillator; however, 50 MHz

can be applied with an external clock source.

  1. When the phase-locked loop (PLL) circuitry is enabled, the minimum input frequency on XTAL1 is 8

MHz. The PLL cannot be run at frequencies lower than 16 MHz.

  1. If using either READY or BUSCONx to insert wait states, add 2t × n, where n = number of wait states.
  2. Assuming back-to-back bus cycles.

Table 11. AC Characteristics the External Memory System Must Meet, Demultiplexed Bus Mode

  1. If using the READY signal to insert wait states, you must program at least one wait state in the

BUSCON x register because the first falling edge of READY is not synchronized with a CLKOUT edge.

  1. If using the BUSCONx register without the READY signal to insert wait states, add 2t × n, where n =
  2. If CSx# changes or if a write cycle follows a read cycle, add 2t (1 state).
  3. If using the BUSCONx register to insert wait states, add (2t × n–1), where n = number of wait states.
  4. Exceeding the maximum specification causes additional wait states.
  5. If you program two or more wait states in the BUSCON

x register, the TCH 1YX minimum does not apply. Table 10. AC Characteristics the 80C296SA Will Meet, Demultiplexed Bus Mode (Continued)

  1. 25 MHz is the maximum input frequency when using an external crystal oscillator; however, 50 MHz

can be applied with an external clock source.

  1. When the phase-locked loop (PLL) circuitry is enabled, the minimum input frequency on XTAL1 is 8

MHz. The PLL cannot be run at frequencies lower than 16 MHz.

  1. If using either READY or BUSCONx to insert wait states, add 2t × n, where n = number of wait states.
  2. Assuming back-to-back bus cycles.

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6.2.4.1 System Bus Timings, Demultiplexed Bus

Figure 8. System Bus Timings, Demultiplexed Bus Mode

6.2.4.2 READY Timing, Demultiplexed Bus

Figure 9. Example READY Timings at 50 MHz, Demultiplexed Bus, BUSCONx = 1 Wait State

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occur in the first bus cycle following a chip-select change and in the first write cycle following a read cycle. delay (4t). The chip-select change in cycle 3, a read cycle, causes a 2t delay. Figure 10. Deferred Bus Mode Timing Diagram

6.2.5 HOLD#, HLDA# TIMINGS

Figure 11. HOLD#, HLDA# Timing Diagram Table 12. HOLD#, HLDA# Timings

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6.2.6 AC CHARACTERISTICS — SERIAL PORT, SYNCHRONOUS MODE 0

Figure 12. Serial Port Waveform — Synchronous Mode 0 Table 13. Serial Port Timing — Synchronous Mode 0 † The minimum baud-rate (SP_BAUD) register value is x002H for receptions and x001H for transmissions.

6.2.7 EXTERNAL CLOCK DRIVE

Figure 13. External Clock Drive Waveforms Table 14. External Clock Drive † Assumes an external clock; the maximum input frequency for an external crystal oscillator is 25 MHz.

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Figure 14. AC Testing Input and Output Waveforms During 5.0 Volt Testing Figure 15. Float Waveforms During 5.0 Volt Testing level occurs with IOL /IOH ≤15 mA.

7.0 THERMAL CHARACTERISTICS

Handbook (order number 210997) provides quality and reliability information. 80296SA’s behavior to deviate from published specifications are documented in a specification update.

9.0 DATASHEET REVISION HISTORY

the latest version before finalizing a design or ordering devices.

  1. All references to SQFP package were deleted.
  2. Reference to ROM option was removed from Table 1.
  3. The speed designation for 40 MHz was changed from “no mark” to “40” in Table 1.

RXDX specification was changed to 0 ns (from 2 ns) in Table 11 and Table 13.

  1. The T CHYX specification was replaced by TCH 1YX and TCH 2YX .
  2. The READY timing diagrams (Figures 8 and 10) were replaced by examples that reflect the new TCH 1YX
  3. The “Intel Confidential” designation was removed for publication.
  4. A heading was added for Section 1.0, “Product Overview,” and the remaining sections were renum-
  5. The errata list was replaced with a reference to the specification update document.
  6. Throughout the datasheet, the product name was changed to read “80296SA” instead of “80C296SA.”
  7. The feature list was clarified.
  8. A table of contents was added.
  9. The block diagram was changed.
  10. Several sections were rearranged and section numbers were assigned. “Thermal Characteristics” was

Table 15. Thermal Characteristics

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80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER tics” is Section 6.0; “Errata” is Section 8.0, and “Datasheet Revision History” is Section 9.0. 6. Table 2 was changed to Table 1 and the “process information” was corrected to show that “no mark” sig- nifies a CHMOS process. 7. Table 3 was changed to Table 7 and several clarifications were made. 8. Figure 3 was changed to correct the product name. Pin assignments did not change. 9. Table 4 was changed to Table 2 and pin 3 was changed from “no connection” to “tie to V CC .” 10. Figure 4 was changed to correct the product name. Pin assignments did not change. 11. Figure 5, “ICC versus Frequency in Reset,” was added. Remaining figure numbers were incremented. 12. Table 6 was changed to Table 4 and a note for handling the “no connection” pins was added. 13. Table 8 was changed to Table 6. The descriptions of BREQ#, HLDA#, and HOLD# were changed to reflect their operation during hold. The description of the ONCE signal was changed to reflect the correct states of READY, RESET#, and NMI during ONCE mode. The description of PLLEN2:1 was changed to show the correct pin states to achieve each phase-locked loop (PLL) clock multiplier mode. The descrip- tions of RPD and RESET# were changed to reflect system requirements when using the PLL. 14. Two notes were added to clarify the “Operating Conditions” in the “Electrical Characteristics” section. 15. Table 9 was changed to Table 8, the notes were re-ordered, and the following specifications were changed: CC max was changed to 150 mA (from 120 mA).

  • V OH min was changed to VCC –0.5 V (from VCC –0.3 V) at IOH = –200µA.
  • V OH min was changed to VCC –0.9 V (from VCC –0.7V) at IOH = –3.2 mA.
  • Test condition for VOL 1 max = 0.45 V was changed to IOL = 8 mA (from IOL = 10 mA).
  • R RST min and max were changed to 50 kΩ and 150 kΩ (from 9 kΩ and 95 kΩ ).
  • V OH 3 min specification was added. 16. Table 10 was divided into two tables: timing specifications that the microcontroller will meet (Table 10) and those that the external memory system must meet (Table 11). Note 7 was deleted and the remain- ing notes were re-ordered. The following specifications were changed or added in Table 10: XTAL 1 min for the PLL in 4x mode was changed to 8 MHz (from 4 MHz); a clarifying note was added.
  • T XHCH min was changed to 3 ns (from TBD).
  • T LLAX min was changed to 1 ns (from TBD).
  • T LLRL min was changed to 3 ns (from TBD)
  • T RHAX min was changed to t – 4 ns (from t).
  • T AVWL min (2t – 25) was added to Table 10.
  • T SLDV min (4t – 28) was added to Table 11. 17. Table 11 was divided into two tables: timing specifications that the microcontroller will meet (Table 12) and those that the external memory system must meet (Table 13). Note 7 was deleted and the remain- ing notes were re-ordered. The following specifications were changed: XTAL 1 min for the PLL in 4x mode was changed to 8 MHz (from 4 MHz); a clarifying note was added.
  • T WHQX min was changed to t – 5 ns (from t – 2 ns). 18. Figure 6 was changed to show the correct PLLEN2:1 values to select the 2x clock multiplier mode. 19. Table 13 was changed to Table 15 and a note was added. 20. Table 14 was changed to Table 16, 1/T XLXL specifications for each phase-locked loop (PLL) mode were added, and Note 2 was deleted.

80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER

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80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER