80186

80130 INTEL | Alldatasheet

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delay timer and a baud rate generator. Figure 1. iAPX 86/30, 88/30 Block Diagram

Figure 2. iAPX 86/30, 88/30 Pin Configuration

Table 1. 80130 Pin Description (Continued) CLK Clock: The system clock provides the basic timing for the processor and bus controller. : to interrupt the CPU by connecting it to INTR. HIGH level on an IR input (Level-Triggered Mode). _ andlor bus transceiver control. fetched by the CPU. AD}3~ADg are used to select the instruction. non-slave input or slave input programmed as being a local slave. Vss Ground: Vgg is the ground pin. DELAY [0 [| DELAY Timer: Output of timer 1. Reserved by Intel Corporation for future use. BAUD [9 | Baud Rate Generator: 8254 Mode 3 compatible output. Output of 80130 Timer 2.

. 80130/80130-2 intel iAPX 86/30, 88/30, 186/30, 188/30 PRELIMINARY eee proces anon anna nn - 8 > I 1 i er ' 4 —— pa 1 5 ' ‘1 PROGRAMMABLE i pL. mrganvet |) wrennuer mpurs | : -—— i | 1 wrennver out ! Stone \\ f 1 ' | sem Le srerew 1 jLL: “tc 1 { = ' H \\ i “| | > 1 1 [ T i i | | ' 1 | L wo : ' | lq i 1 | | 1 ' t \\ cx0ex avoness ee conto, — Les, wus connoe ADDRESS | waren i ‘DATA BUS | | LocaL \\ aeiuer ccomtnot uni er) CITI ST Figure 3, OSF Internal Block Diagram problem. Their goal is to simplify the design of multi- easy-to-use architectural extension to iAPX 86, 88 tasking application systems by providing a well- system designs. defined, fully debugged set of operating system primitives implemented directly in the hardware, thereby removing the burden of designing multitask- The OSP Approach ing operating system primitives from the application Programmer. The OSP system data types (SDTs) and primitive in- structions allocate, manage and share low-level pro- Both the 86/30 and the 88/30 OSPs are two-chip sets. cessor resources in an efficient manner. For Consisting of a main processor, an 8086 or 8088 CPU, _example, the OSP implements task context manage- and the Inte! 80130, Operating System Firmware ment (managing a task state image consisting of component (OSF) (see Figure 1). The 80130 provides both hardware register set and software control in- a set of multitasking kernel primitives, kernel contro! formation) for either the basic 86/10 context or the storage, and the additional support hardware, in- extended 86/20 (8086 +8087) numerics context. The cluding system timers and interrupt control, re- OSP manages the entire task state image both while quired by these primitives. From the application the task is actively executing and while it is inactive. programmer's viewpoint, the OSF extends the base Tasks can be created, put to sleep for specitied peri- iAPX 86, 88 architecture by providing 35 operating ods, suspended, executed to perform their func. system primitive instructions, and supporting five tions, and dynamically deleted when their functions new system data types, making the OSFalogicaland —_are complete. 3-201 210216-002

intel iAPX 86/30, 88/30, 186/30, 188/30 PRELIMINARY we The Operating System Processors support event- _(Table 4). A representative ASM86 sequence for call- oriented systems designs. Each event may be pro- ing a primitive is shown in Figure 4. In PL/M the OSP cessed by an individual responding task or along programmer uses a call to invoke the primitive. with other closely related events in a common task. External events and interrupts are processed by the OSP interrupt handler primitives using its built-in SAMPLE ASSEMBLY LANGUAGE PRIMITIVE CALL interrupt controller subsystem as they occur in real- | pusne, PUSH PARAMETER 1 time. The multiple tasks and the multiple events are Pus? PUSH PARAMETER 2 coordinated by the OSP integral scheduler whose preemptive, priority-based scheduling algorithm rus TSH ARAMET ER oy and system timers organize and monitor the process- Noversr ing of every task to guarantee that events are pro- LEA SRAEMUM_OYTER_PARAM - 20001 re TO PneT cessed as they occur in order of relative importance. [PARAMETER ON STACK The 86/30 also provides primitives for intertask com- wean TNT Come Oormrennurr COPE munication (by mailboxes) and for mutual exclusion 05° priniTive INVOKED (by regions), essential functions for multitasking Pree eyres. sop panawerens applications. ATES pani conta EXCEPTION CODES SL CONTAINS PARAMETER NUMBER ‘AT CAUSED EXCEPTION Programming Language Support | “ax conta WORD RETURN VALUE 2.grconrans romten REYORN VALLE Programs for the OSP can be written in ASM 86/88 or PI . ral 68 68 ystems standard system languages for Figure 4. ASM/86 OSP Calling Convention The Operating System Processor Support Package | (iOSP 86) provides an interface library for applica. | OSP Functional Description tion programs written in any model of PL/M-86. This library also provides 80130 configuration and in- Each major function of the OSP is described below. itialization support as well as complete user —_These are: documentation. Job and Task Management interrupt Management Free Memory Management OSF PROGRAMMING INTERFACE Intertask Communication The OSF provides 35 operating system kernel Intertask Synchronization primitives which implement multitasking, interrupt Environmental Control management, free memory management, intertask communication and synchronization. Table 4 shows The system data types (or SDTs) supported by the each primitive, and Table 5 gives the execution per- OSP are capitalized in the description. A short formance of typical primitives. description of each SDT appears in Table 2. OSP primitives are executed by a combination of OPU and OSF (80130) activity. When an OSP prim. VOB and TASK Management tive is called by an application program task, the Each OSP JOB is a controlled environment in which i et oN y tem data types reside. Each individual application application programs. program is normally a separate OSP JOB, whether it has one initial task (the minimum) or multiple tasks. OSP Primitive Calling Sequences JOBs partition the system memory into pools. Each memory pool provides the storage areas in which the A standard, stack-based, calling sequence is used to OSP will allocate TASK state images and other sys- invoke the OSF primitives. Before a primitive is tem data types created by the executing TASKs, and called, its operand parameters must be pushed on _ free memory for TASK working space. The OSP sup- the task stack. The SI register is loaded with the ports multiple executing TASKs within a JOB by offset of the last parameter on the stack. The entry _ managing the resources used by each, including the code for the primitive is loaded into AX. The primitive CPU registers, NPX registers, stacks, the system data invocation call is made with a CPU software interrupt _types, and the available free memory space pool. 3-202 210216-002

intel iAPX 86/30, 88/30, 186/30, 188/30 PRELIMINARY eee When a TASK is created, the OSP allocates memory _the OSP switches the control of the processor to the (from the free memory of its JOB environment) for higher priority TASK. First, the OSP saves the outgo- the TASK's stack and data area and initializes the ing (lower priority) TASK's state including CPU regis- additional TASK attributes such as the TASK priority __ter values in its TASK state image. Then, it restores level and its error handler location. (As an option, the the CPU registers from the TASK state image of the caller of CREATE TASK may assign previously incoming (higher priority) TASK. Finally it causes the defined stack and data areas to the TASK.) Task CPU to start or resume executing the higher priority Priorities are integers between 0 and 255 (the lower TASK the priority number the higher the scheduling Priority of the TASK). Generally, priorities up to 128 TASK scheduling is performed by the OSP. The OSP's will be assigned to TASKs which are to Process inter- Priority-oriented preemptive scheduler determines Tupts. Priorities above 128 do not cause interrupts to. which TASK executes by comparing their relative be disabled, these priorities (129 to 255) are appro- priorities. The scheduler insures that the highest priate for non-interrupt TASKs. If an 8087 Numerics _ priority TASK with a status of READY will execute, A Processor Extension is used, the error recovery inter- TASK will continue to execute until an interrupt with a Tupt level assigned to it will have a higher priority higher priority occurs, or until it requests unavailable than a TASK executing on it, so that error handling is resources, for which it is willing to wait, or until it performed correctly. makes specific resources available to a higher priority TASK waiting for those resources, EXECUTION STATUS vi ATASK has an execution status or execution state, TASKS can become READY by receiving a by tine The OSP provides five execution states: RUNNING, receiving control, receiving an interrupt, or by timing READY, ASLEEP, SUSPENDED, and ASLEEP. Sut. The OSP always monitors the status of all the SUSPENDED. ' TASKs (and interrupts) in the system. Preemptive ° . scheduling allows the system to be responsive to the — ATASK is RUNNING if it has control of the external environment while only devoting CPU re- Processor. sources to TASKs with work to be performed. — ATASK is READY if it is not asleep, suspended, or asleep-suspended. For a TASK to become the run- TIMED WAIT ning (executing) TASK, it must be the highest the OP timer hardware facilities support timed Priority TASK in the ready state. waits and timeouts. Thus, in many primitives, a TASK — ATASK is ASLEEP if it is waiting for a request to can specify the length of time it is prepared to wait be granted or a timer event to occur. A TASK may —_ for an event to occur, for the desired resources to Put itself into the ASLEEP state. become available or for a message to be received at a — ATASK is SUSPENDED if it is placed there by MAILBOX. The timing interval (or System Tick) can another TASK or if it suspends itself, ATASK may _ be adjusted, with a lower limit of 1 millisecond. have multiple suspensions, the count of suspen- sions is managed by the OSP as the TASK suspen- APPLICATION CONTROL OF TASK EXECUTION sion depth. Programs may alter TASK execution status and — ATASK is ASLEEP-SUSPENDED if it is both _ priority dynamically. One TASK may suspend its own waiting and suspended. execution or the execution of another TASK for a Period of time, then resume its execution later. Multi- TASK attributes, the CPU register values, and the ple suspensions are provided. A suspended TASK 8087 register values (if the 8087 is configured into may be suspended again. the application) are maintained by the OSP in the TASK state image. Each TASK will have a unique The eight OSP Job and TASK management primitives TASK state image. are: CREATE JOB Partitions system resources and SCHEDULING creates a TASK execution The OSP schedules the processor time among the environment. various TASKS on the basis of priority. ATASK hasan CREATE TASK Creates a TASK state image. execution priority relative to all other TASKs in the Specifies the location of the ‘system, which the OSP maintains for each TASK in its TASK code instruction stream, TASK state image. When a TASK of higher priority its execution priority, and the than the executing TASK becomes. ready to execute, other TASK attributes. +203 210216-002

intel iAPX 86/30, 88/30, 186/30, 188/30 PRELIMINARY Nw DELETE TASK Deletes the TASK state image, INTERRUPT HANDLER can queue for the INTER- removes the instruction stream RUPT TASK can be limited to the value specified in from execution and deallocates the SET INTERRUPT primitive. When the INTER- stack resources. Does not delete RUPT TASK is finished processing, it issues a WAIT INTERRUPT TASKS. INTERRUPT primitive, and is immediately ready to rocess the queue of interrupts that the INTERRUPT SUSPEND TASK Suspends the specified TASK or, HANDLER has built with repeated SIGNAL INTER- if already suspended, in- — RUPT primitives while the INTERRUPT TASK was crements its suspension depth —_ processing. If there were no interrupts at the level, . by one. Execute state is the queue is empty and the INTERRUPT TASK is SUSPEND. SUSPENDED. See the Example (Figure 5) and Fig- RESUME TASK —Decrements the TASK suspen- ures 6 and 7. sion depth by one. If the sus- OSP external INTERRUPT LEVELs are directly pension depth is then zero, related to internal TASK scheduling priorities. The the primitive changes the task © QSP maintains a single list of priorities including execution status to READY, both tasks and INTERRUPT LEVELs. The priority of or ASLEEP (if ASLEEP/ the executing TASK automatically determines which SUSPENDED). interrupts are masked. Interrupts are managed by i INTERRUPT LEVEL number. The OSP supports eight SLEEP Foe ne a ueetnG TASitiog _(evels directly and may be extended by means of specified number of System Ticks. (The S1aV@ 8259As to a total of 57. Tick interval can be configured The nine Interrupt Management OSP primitives are: lown to 1 millisecond.) DISABLE Disables an external INTER- SET PRIORITY Alters the priority of a TASK. RUPT LEVEL. ENABLE Enables an external INTER- Interrupt Management RUPT LEVEL. ENTER INTERRUPT — Gives an Interrupt Handler The OSP supports up to 256 interrupt levels or- its own data segment, sepa- ganized in an interrupt vector, and up to 57 external rate from the data segment interrupt sources of which one is the NMI (Non- of the interrupted task. Maskable Interrupt). The OSP manages each inter- EXITINTERRUPT —_—_—Performs an “END of INTER- rupt level independently. The OSF INTERRUPT RUPT” operation. Used by SUBSYSTEM provides two mechanisms for interrupt an INTERRUPT HANDLER management: INTERRUPT HANDLERs and INTER- which does not invoke an IN- RUPT TASKs. INTERRUPT HANDLERS disable all TERRUPT TASK. Reenables maskable interrupts and should be used only for interrupts, when the INTER- servicing interrupts that require little processing RUPT HANDLER gives up time. Within an INTERRUPT HANDLER only certain control. OSF Interrupt Management primitives (DISABLE, ENTER INTERRUPT, EXIT INTERRUPT, GET LeveL, OCT LEVEL Returns or eee Ne SIGNAL INTERRUPT) and basic CPU instructions TERRUPT HANDLER, can be used, other OSP primitives cannot be. The " INTERRUPT TASK approach permits all OSP _RESETINTERRUPT Cancels the previous as- primitives to be issued and masks only lower priority signment made to an interrupts. interrupt level by SET IN- TERRUPT primitive request. Work flow between an INTERRUPT HANDLER and an If an INTERRUPT TASK has INTERRUPT TASK assigned to the same level is been assigned, it is also regulated with the SIGNAL INTERRUPT and WAIT deleted. The interrupt level INTERRUPT primitives. The flow is asynchronous. is disabled. When an INTERRUPT HANDLER signals an INTER- SET INTERRUPT Assigns an INTERRUPT RUPT TASK, the INTERRUPT HANDLER becomes HANDLER to an interrupt immediately available to process another interrupt. level and, optionally, an IN- The number of interrupts (specified for the level) the TERRUPT TASK. 3-204 210216-002

Figure 7. Multiple Butter Example voke it. Ifa SIGNAL INTER: We Oot ent ize. memory pool which is allocated to each JOB for its Memory Pool. memory pool of the parent JOB.) The memory pool is to the JOB memory pool.

intel iAPX 86/30, 88/30, 186/30, 188/30 PRELIMINARY and the other of Messages. Four OSP primitives for There are five OSP primitives for mutual exclusion: intertask synchronization and communication are CREATE REGION Create a REGION (lock). Provided: , ; SEND CONTROL —_ Give up the REGION. OREATE MAILBOX Srereea erase mosse9° ACCEPT CONTROL Request the REGION, but do DELETE MAILBOX Deletes an intertask mes- not walt if itis not available. sage exchange. RECEIVE CONTROL Request a REGION, wait if , not immediately available. RECEIVE MESSAGE Calling TASK receives a més- sage from the MAILBOX. DELETE REGION _Delete a REGION. SEND MESSAGE Calling TASK sends a the osp also provides dynamic priority adjustment message to the MAILBOX. for TASKs within priority REGIONs: If a higher- riority TASK issues a RECEIVI ITROL primitive, The CREATE MAILBOX primitive allocates a MAIL- — Pinid, (lowerpriority) TASK Nesine ee the came BOX for use as an information exchange between REGION. the lower-priority TASK will be trans- TASKS. The OSP will post information at the MAIL: arentiy, and temporarily, elevated to the waiting BOX in a FIFO (First-In First-Out) manner when a Tag's Priority until it relinquishes the REGION via SEND MESSAGE instruction is issued. Similarily, a SEND CONTROL. At ther point, since it is no longer Rennes retrieved by the OSP if aTASK issues @ Using the critical resource, the TASK will have its RECEIVE MESSAGE primitive. The TASK which pom ay priority restored Creates the MAILBOX may make it available to other TASKs to use. OSP Control Facilities If no message is available, the TASK attempting to Continue exe nge May choose to wait for one or The OSP also includes system primitives that provide Continue executing. both control and customization capabilities to a mul- titasking system. These primitives are used to control The queue management method for the task queue the deletion of SDTs and the recovery of free memory (FIFO or PRIORITY) determines which TASK in the in a system, to allow interrogation of operating sys- * MAILBOX TASK queue will receive a message from tem status, and to provide uniform meare at adding the MAILBOX. The method is specified in the user SDTs and type managers. CREATE MAILBOX primitive. DELETION CONTROL Deletion of each OSP system data type is explicitly Intertask Synchronization and Mutual controlled by the applications programmer by set- Exclusion ting a deletion attribute for that structure. For exam- ple, if a SEGMENT is to be kept in memory until DMA Mutual exclusion is essential to multiprogramming —_activity is completed, its deletion attribute should be and multiprocessing systems. The REGION system disabled. Each TASK, MAILBOX, REGION, and SEG. data type implements mutual exclusion. A REGION is MENT SDT is created with its deletion attribute en. represented by a queue of TASKS waiting to use a _abled (i.e., they may be deleted). Two OSP primitives resource which must be accessed by only one TASK control the deletion attribute: ENABLE DELETION at_a time, The OSP provides primitives to use and DISABLE DELETION. REGIONs to manage mutually exclusive data and resources. Both critical code sections and shared © ENVIRONMENTAL CONTROL data structures can be protected by these primitives The OSP provides inquiry and control operations from simultaneous use by more than one task. which help the user interrogate the application envi. REGIONs support both FIFO (First-n First-Out) or ronment and implement flexible exception handling. Priority queueing disciplines for the TASKS seeking These features aid in run-time decision making and to enter the REGION. The REGION SDT can also be —_in application error processing and recovery. There used to implement software locks. are five OSP environmental contro! primitives. Multiple REGIONS are allowed, and are automatically OS EXTENSIONS exited in the reverse order of entry. While ina The OSP architecture is defined to allow new user REGION, a TASK cannot be suspended by itself or defined System Data Types and the primitives to ma, any other TASK, and thereby avoids deadlock. nipulate them to be added to OSP capabilities 3-207 210216-002

intel IAPX 86/30, 88/30, 186/30, 188/30 PRELIMINARY provided by the built-in System Data Types. The type _ allow the OSP primitives to report parameter errors managers created for the user-defined SDTs are _in primitive calls, and errors in primitive usage. Ex called user OS extensions and are installed in the ception handling procedures are flexible and can be system by the SET OS EXTENSION primitive. Once _ individually programmed by the application. In gen- installed, the functions of the type manager may be _eral, an exception handler if called will perform one invoked with user primitives conforming to the OSP__or more of the following functions: interface. For well-structured extended architec- —_L og the Error. tures, each OS extension should support aseparate —_pelete/Suspend the Task that caused the user-defined system data type, and every OS exten- ‘exception. sion should provide the same calling sequence and == __ignore the error, presumably because it is not program interface for the user as is provided for a rious. built-in SDT. The type manager for the extension would be written to suit the needs of the application. an EXCEPTION HANDLER is written as a procedure. OSP interrupt vector entries (224-255) are reserved If PLM/86 is used, the “compact,” “medium” or for user OS extensions and are not used by the OSP. large" model of computation should be specified for After assigning an interrupt number to theextension, the compilation of the program. The mode in which the extension user may then call it with the standard the EXCEPTION HANDLER operates may be speci- OSP call sequence (Figure 4), and the unique fie in the SET EXCEPTION HANDLER primitive. The software interrupt number assigned to the return information from a primitive call is shown in extension. Figure 4. CX is used to return standard system error conditions. Table 7 shows a list of these conditions, ENABLE DELETION Allows a specific SEGMENT, Alows 3 spec crmeaon = vanathe default EXCEPTION HANDLER of the OSP. SDT to be deleted. DISABLE DELETION Prevents a specific SEG- | HARDWARE DESCRIPTION MENT, TASK, MAILBOX, or REGION SDT from being _The 80130 operates in a closely coupled mode with deleted. the iAPX 86/10 or 88/10 CPU. The 80130 resides on GET TYPE Given a token fora nee eee es ayn congue for maximum mode baste ne babino tyP@, Operation. The 80130 automatically selects between * its 88/30 and 86/30 operating modes. GET TASK TOKENS Returns to the caller infor- mation about the current The 80130 used in the 86/30 configuration, as shown task environment. in Figure 8 (or a similar 88/30 configuration), GET EXCEPTION Returns information about operates at both 5 and 8 MHz without requiring pro- HANDLER the calling TASK’s current in- cessor wait states. Walt state memories are fully sup- formation handler: its ad- ported, however. The 80130 may be configured with dress, and when it is used. both an 8087 NPX and an 8089 IOP, and provides SET EXCEPTION Provides the address and {ull context control over the 6087. HANDLER sage of an exception the 80130 (shown in Figure 3) is internally divided ndler for a TASK. ' " < into a contro! unit (CU) and operating system unit SET OS EXTENSION Modifies one of the interrupt (OSU). The OSU contains facilities for OSP kernel vector entries reserved for support including the system timers for scheduling OS extensions (224-255) to and timing waits, and the interrupt controller for point to a user OS extension interrupt management support. procedure. SIGNAL EXCEPTION For use in OS extension er- _ IAPX 86/30, iAPX 88/30 System ror processing. Configuration The 80130 is both /O and memory mapped to the EXCEPTION HANDLING local CPU bus. The CPU's status SO/-S2/ is decoded along with 1OCS/ (with BHE and AD - The OSP supports exception handlers. These are ADs) or MEMCS/ (with AD;g-ADg). The pins are similar to CPU exception handlers such as OVER- internally latched. See Table 1 for the decoding of FLOW and ILLEGAL OPERATION. Their purpose is to these lines. 3-208 210216-002

intel iAPX 86/30, 88/30, 186/30, 188/30 PRELIMINARY Memory Mapping RAM Requirements Address lines Ayg~Ayq can be used to form MEMCS/ The OSP manages its own interrupt vector, which is since the 80130's memory-mapped portion is aligned _assigned to low RAM memory. Working RAM storage along a 16K-byte boundry. The 80130 can reside on _is required as stack space and data area. The any 16K-byte boundry excluding the highest memory space must be allocated in user RAM. (FCOOOH-FFFFFH) and lowest (00000H-003FFH). The 80130 control store code is position-independent ex: OSP interrupt vector memory locations OH~3FFH Cept as limited above, in order to make it compatible must be RAM based. The OSP requires 2 bytes of with many decoding logic designs. ADjg-ADg are allocated RAM. The processor working storage is decoded by the 80130's kernel control store. dynamically allocated from free memory. Approxi- mately 300 bytes of stack should be allocated for VO Mapping each OSP task. The /O-mapped portion of the 80130 must bealigned along a 16-byte boundry. Address lines Ais-Ag TYPICAL SYSTEM CONFIGURATION should be used to form IOCS/. Figure 8 shows the processing cluster of a “typical” System Performance iAPX 86/30 or iAPX 88/30 OSP system. Not shown are , subsystems likely to vary with the application. The The approximate porn of representitive OSP configuration includes an 8086 (or 8088) operating in for a typleal TAR Bon ress times are shown — asimum mode, an B2B4A elOk pencrony wean Me Thee eo mplementation with an 8 8288 system controller. Note that the 60130 is located ble to the execution times of similar functions in 0” the CPU side of any laches or transceivers. See é Intel Application Note 130 for further details on minicomputers (where available) and are an order of Inte’ Appli r ; iguration. magnitude faster than previous generation microprocessors. OSP Timers Initialization The OSP Timers are connected to the lower half of Both application system initialization and OSP- _the data bus and are addressed at even addresses. Specific initializatior/configuration are required to _The timers are read as two successive bytes, always + se the OSP. Configuration is based on a “database” LSB followed by MSB. The MSB is always latched on Provided by the user to the iOSP 86 support package. @ read operation and remains latched until read, The OSP-specific initialization and configuration in- Timers are not gatable. formation area is assigned to a user memory address adjacent to the 80130's memory-mapped location. Baud Rate Generator : (See Application Note 130 for further details.) The configuration data defines whether 8087 support is The baud rate generator is 8254 compatible (square Configured in the system, specifies if slave 82594 wave mode 3). Its output, BAUD, is intially high and interrupt controllers are used in addition to the remains high until the Count Register is loaded. The 80130, and sets the operating system time base (Tick __irst falling edge of the clock after the Count Register Interval). Also located in the configuration area are _is loaded causes the transfer of the internal counter the exception handler contro! Parameters, the ad- to the Count Register. The output stays high for N/2 dress location of the (separate) application system {(N+1)/2 if N is odd] and then goes low for N/2 Configuration area and the OSP extensions in use. __[(N-1)/2 if Nis odd]. On the falling edge of the clock The OSP application system configuration area may which signifies the final count for the output in low . be located anywhere in the user memory and must ‘state, the output returns to high state and the Count include the starting address of the application in- Register is transferred to the internal counter. The Struction code to be executed, plus the locations of whole process is then repeated. Baud Rates are the RAM memory blocks to be managed by the OSP__shown in Table 6. free memory manager. Complete application system ‘support and the required 80130 configuration sup- The baud rate generator is located at OCH (12), rela- ort are provided by the iAPX 86/30 and iAPX 88/30 _ tive to the 16-byte boundary in the /O space in which OPERATING SYSTEM PROCESSOR SUPPORT —_ the 80130 component is located (“OSF" in the follow, PACKAGE (iOSP 86). ing example), the timer control word is located at 3-209 210216-002

intel iAPX 86/30, 88/30, 186/30, 188/30 PRELIMINARY z _ “ __ CONTROL cox f coy a a = i an l ae vocal ira _Ab0 | —T 4 resources | | o | | zi | on k= : Do a cx Es “ose mens in ro feet ~~ renauer acouests Figure 8, Typical OSP Configuration relative address, OEH(14). Timers are addressed with —_Interrupt Controller IOCS=0. Timers 0 and 1 are assigned to the use by the OSP, and should not be altered by the user. The Programmable Interrupt Controller (PIC), is also an integral unit of the 80130. Its eight input pins For most baud-rate generator applications, the com- handle eight vectored priority interrupts. One of mand byte these pins must be used for the SYSTICK time func- oB6H Read/Write Baud-Rate Delay Val tion in timing waits, using an external connection as alrite Bau y Nate shown. During the 80130 initialization and configura- will be used. A typical sequence to set a baud rate tion sequence, each 80130 interrupt pin is individu- of 9600 using a count value of 52 follows (see ally programmed as either level or edge sensitive. Table 6): External slave 8259A interrupt controllers can be MOV AX,OB6H __;Prepare to Write Delay to used to expand the total number of OSP external ‘Timer 3. interrupts to 57. : rd, Nov oes iControl Wo In addition to standard PIC funtions, 80130 PIC unit " , has an LIR output signal, which when low indicates OUT OSF+12,AL ;LSB written first an interrupt acknowledge cycle. LIR=0 is provided to XCHG AL,AH control the 8289 Bus Arbiter SYSB/RESB pin. This OUT OSF+12,AL ;MSB written after. will avoid the need of requesting the system bus to acknowledge local bus non-siave interrupts. The The 80130 timers are subset compatible with 8254 user defines the interrupt system as part of the timers. configuration. 3-210 210216-002

intel IAPX 86/30, 88/30, 186/30, 188/30 PRELIMINARY INTERRUPT SEQUENCE signal which drives one of 80130 edge-triggered in- The OSP interrupt sequence is as follows: terrupt request pins once each A.C. cycle. The Inter- ; rupt Handler responds to the interrupts, keeping 1. One or more of the interrupts is set by a low-to- track of one second's AC. cycles. The interrupt Task high transition on edge-sensitive IR inputs or by a counts the seconds and after a day deletes itself. In high input on level-sensitive IR inputs. typical systems it might perform a data logging oper- ation once each day. The Interrupt Handler and Inter- baa eaadiee Cou tances andsendsan pt Task are written as separate modular programs 3. The CPU acknowledges the INT and responds The Interrupt Handler will actually service interrupt with an interrupt acknowledge cycle which is en- 59 when it occurs. It simply counts each interrupt, coded in 52-Sp. and at a count of 60 performs a SIGNAL INTERRUPT to notify the Interrupt Task that a second has elapsed. 4. Upon receiving the first interrupt acknowledge The Interrupt Handler (ACS HANDLER) was assigned from the CPU, the highest-priority interrupt is set _to this level by the SET INTERRUPT primitive. After by the 80130 and the corresponding edge detect doing this, the Interrupt Task performed the Primitive latch is reset. The 80130 does not drive the ad- RESUME TASK to resume the application task (INITS dress/data bus during this bus cycle but does TASKS TOKEN). acknowledge the cycle by making ACK=0 and sending the LIR value for the IR input being The main body of the task is the counting loop. The acknowledged. Interrupt Task is signaled by the SIGNAL INTERRUPT rimitive in the Ii Handler (at interr iT 5. The CPU will then initiate a second interrupt ac- Ses INTERRUPTS LEVEL} When'the task is i. knowledge cycle. During this cycle, the 80130 will nalied by the Interrupt Handler it will execute the supply the cascade address of the interrupting loop exactly one time, increasing the time count eater a Pulver nparsonmeainnts an oo variables. Then it will execute the WAIT INTERRUPT a primitive, and wait until awakened by the Interrupt read by the CPU. If the 80130 does supply the Handler. Normally, the task will now wait some period Pointer, then ACK will be low for the cycle. This of time for the next signal. However, since the inter- cycle also has the value LIR for the IR input being face between the Handler and the Task is asyn. acknowledged. chronous, the handler may have already queued the 6. This completes the interrupt cycle. The ISR bit __iMterrupt for servicing, the writer of the task does not remains set until an appropriate EXITINTERRUPT have fo worry about this possibility. The interrcpt Honalens (© called at the end of at the end of the day, the task will exit the loop and execute RESET INTERRUPT, which disables the in- terrupt level, and deletes the interrupt task. The OSP now reclaims the memory used by the Task and OSP APPLICATION EXAMPLE schedules another task. If an exception occurs, the coded value for the exception is available in TIMES Figure 5 shows an application of the OSP primitives EXCEPTS CODE after the execution of the primitive. to keep track of time of day in a simplified example. The system design uses a 60 Hz A.C. signal as a time A typical PL/M-86 calling sequence is illustrated by base. The power supply provides a TTL-compatible the call to RESET INTERRUPT shown in Figure 5 3-211 210216-002

Table 2. OSP System Data Type Summary may borrow memory from their parents. its execution state (asleep, suspended, ready, running, asleep/suspended). one or possibly both of two mailbox queues will be empty. mutually exclusive code or to access a shared data region, for example to update a file record. Tokens The OSP interface makes use of a 16-bit TOKEN data type to identify individual OSF data structures. TOKENs of the data structures on which it will operate.

Table 3. System Data Type Codes and Attributes Table 4. OSP Primitives .

1 ENABLE 184 0704H Level #, ExcptPtr

Table 4. OSP Primitives (Continued)

8 SEND MESSAGE 184 0302H MAILBOX,Message Response, ExcptPtr

5 DISABLE DELETION 184 } 0001H TOKEN, ExcptPtr

1 GET EXCEPTION

All parameters are pushed onto the OSP stack. Each parameter is one word. See Figure 3 for Call ‘Sequence.

Table 5. OSP Primitive Pertormance Examples

1 RECEIVE CONTROL, 205

"8 MHz iAPX 86/30 OSP Contiguation. Table 6. Baud Rate Count Values (16x)

intel iAPX 86/30, 88/30, 186/30, 188/30 PRELIMINARY Table 7a. Mnemonic Codes for Unavoidable Exceptions ESOK Exception CodeValue=0 SSS — the operation was successful ESTIME Exception Code Value = 1 the specified time limit expired before completion of the operations was possible ESMEM Exception Code Value = 2 insufficient nucleus memory is available to satisfy the request ESBUSY Exception CodeValue=3 ~ ‘specified region is currently busy ESUMIT Exception Code Value = 4 a attempted violation of a job, semaphore, or system limit ESCONTEXT Exception Code Value = 5 the primitive was called in an illegal context (e.g., call to enable for an already enabled interrupt) ESEXIST Exception Code Vaiue = 6 token argument does not currently refer to any object; note that the object could have been deleted at any time by its owner ESSTATE Exception Code Value = 7 attempted illegal state transition by a task ESNOTSCONFIGURED Exception Code Value = 8 the primitive called is not configured in this system ESINTERRUPTSSATURATION | Exception Code Vaiue- 9 ~ The interrupt task on the requested level has reached its user specified saturation point for interrupt service requests. No further interrupts will be allowed on the level until the interrupt task executes a WAITSINTERRUPT. (This error is only returned, in line, to interrupt handlers.) ESINTERRUPTSOVERFLOW | Exception CodeValue= 100 = ~~ The interrupt task on the requested level previously reached its saturation point and caused an ESINTERRUPTS$SATURATION condition. It subsequently executed an ENABLE allowing further interrupts to come in and has received another SIG- NALSINTERRUPTcall,, bringing it over its specified saturation point for interrupt service requests. (This error is only returned, in line, to interrupt handlers). . Table 7b. Mnemonic Codes for Avoidable Exceptions ESZEROSDIVIDE Exception Code Value = 8000H divide by zero interrupt occurred ESOVERFLOW Exception Code Value = 8001H overflow interrupt occurred ESTYPE Exception Code Value = 6002H ~ a token argument referred to an object tha was not of required type ES$BOUNDS Exception Code Value = 8003H an offset argument is out of segment bounds Exception Code Value = 80044 a (non-token,non-offset) argument has an illegal value ESBADSCALL Exception Code Value = 6005H an entry code for which there is no corresponding primitive was passed ESARRAYSBOUNDS = 8006H | Hardware or Language has detected an array overflow ESNDPSERROR Exception Code Value = 6007H an 8087 (Numeric data Processor) error has been detected; (the 8087 status information is contained in a parameter to the exception handler) 3-216 210216-002

i 80130/80130.2 ; UDA” intel iAPX 86/30, 88/30, 186/30, 188/30 RELIMINA! OO SS ABSOLUTE MAXIMUM RATINGS* “NOTICE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the Voitage on Any Pin With indicated in the operational sections of this specification D.C. CHARACTERISTICS | (1,=0°C to 70°C, Voc = 4.5 to 55V) [Symbol [Parameter [Min [ Max. Units [Test Conditions] |e | inpsttowvotage. [os [oe] OP SSS—~*&Y |___Viw | Input High Vottage {20 veces | ov [ TTOC~&Y Output Low Voltage a A De) | ua ogo eo ee Powe Sy Cue [ae a [ete Gonen 90 eg] TR Input Load Current uA | Vw= Veo uA Vin = © [a oni estage ara a a Glock puto a Glock ough a [en pst cassenee a [6H anastnes — eu Clock Input Leakage Current 70 uA | Vw= Veo 150 my Vy = 25V 10 uA_| Vm - Ov A.C. CHARACTERISTICS (1 -0-70° Voc - 45-55 Vol Veg - Groune aS | ee a a CLK Cycle Period [200 [ - [ow [ [os | [Taxon [CUR tow Time 90s fs ca [Yer | Sats acne smugness [Tong [Status inactive Hoistine [10 | = 0 | | Y Status Inactive Setup Time a Status Active Hold Time Le a Acres val Sup Tine | 8 |= 8} 7 a Cho Set Sup Ti ee Chip Select Hold Time po [= es Write Data Setup Time | Write Data Hold Time a [eta tine 0000 | Read Data Valid Delay [= Pao 05 [ns |G = 200 [ene [Reta toting ee Read Oso Feat A Cascade Atos boy Te [=| a8 [Js J 3-217 210216-002

intel \\APX 86/30, 88/30, 186/30, 188/30 PRELIMINARY oo A.C. CHARACTERISTICS (Continued) 0} | ep fp =] [=] | ows | Aetomtsge Hai tine 9] = | Yess oh Set t@ | Tescx | Stausto ACK 40] 140 [ns] ‘Address to ACK = 90 [ns | Timer Output Delay Time 200 200 [ns | ©, - 100pF [aor | tert Output ty Tine | =} 200 [200 | ne |e, i005 [tows PWT Output Deiay 200200] ns] a WAVEFORMS. AC. ux Se reoo DELAY avo ax | un nr = <— tam me el Le 3-218 210216-002

i 80130/80130-2 ~~ t ite! . iAPX 86/30, 88/30, 186/30, 188/30 PRELIMINARY WAVEFORMS AC. ——— ee CuK *) - rr - r~ a +4 _ Ps i Lh _ | y | | FS , | sesee. | ‘WEES, OES | ——— sovAbe Da) “Tr | 7 rH reir rein | owen | _ { | ra | Tae oe | rr] oe SH Toren 3-219 210216-002