80186

80186 INTEL | Alldatasheet

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*Other brands and names are the property of their respective owners. changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. Figure 1. Block Diagram

80186/80188 High-Integration 16-Bit Microprocessors CONTENTS PAGE FUNCTIONAL DESCRIPTION ÀÀÀÀÀÀÀÀÀÀÀÀÀ 9 Introduction ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 9 CLOCK GENERATOR ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 9 Oscillator ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 9 Clock Generator ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 9 READY Synchronization ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 9 RESET Logic ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 9 LOCAL BUS CONTROLLER ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 9 Memory/Peripheral Control ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 10 Local Bus Arbitration ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 10 Local Bus Controller and Reset ÀÀÀÀÀÀÀÀÀÀÀÀ 10 PERIPHERAL ARCHITECTURE ÀÀÀÀÀÀÀÀÀÀ 10 Chip-Select/Ready Generation Logic ÀÀÀÀÀÀ 10 DMA Channels ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 11 Timers ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 11 Interrupt Controller ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 12 CONTENTS PAGE ABSOLUTE MAXIMUM RATINGS ÀÀÀÀÀÀÀÀ 15 D.C. CHARACTERISTICS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 15 A.C. CHARACTERISTICS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 16 EXPLANATION OF THE AC SYMBOLS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 18 WAVEFORMS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 19 EXPRESS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 25 EXECUTION TIMINGS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 26 INSTRUCTION SET SUMMARY ÀÀÀÀÀÀÀÀÀÀ 27 FOOTNOTES ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 32 REVISION HISTORY ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 33

Figure 4. Plastic Leaded Chip Carrier Pin names in parentheses apply to the 80188.

Table 1. Pin Descriptions Symbol Pin Type Name and FunctionNo. VCC 9I SYSTEM POWER: a5 volt power supply. external clock may be applied to X1 while minimizing stray capacitance on X2. pin timings are specified relative to CLKOUT. generation via an RC network. are enabled while the processor is waiting for TEST , interrupts will be serviced. transitions are counted) and internally synchronized. clock. The Non-Maskable Interrupt cannot be avoided by programming. INT0 45 I Maskable Interrupt Requests can be requested by activating one of these pins. Controller section of this data sheet). Pin names in parentheses apply to the 80188.

Table 1. Pin Descriptions (Continued) Symbol Pin Type Name and FunctionNo. The status pins float during bus HOLD or RESET. 80188, S7 is high during normal operation. 1 as in the 8086. Note that ALE is never floated. Pin names in parentheses apply to the 80188.

Symbol Pin Type Name and FunctionNo. , and WR , or queue status information. falling edge of ARDY must be synchronized to the processor clock. Connecting ARDY HIGH will always assert the ready condition to the CPU. If this line is unused, it should be tied LOW to yield control to the SRDY pin. The status pins float during HOLD. may be used as a logical M/IO indicator, and S1 as a DT/R indicator. Pin names in parentheses apply to the 80188.

Symbol Pin Type Name and FunctionNo. reference is made to the defined upper portion (1K–256K block) of memory. will retain the previously latched value during HOLD. seventh peripheral chip select, or to provide an internally latched A2 signal. this pin will retain the previously latched value during HOLD. processsor. When HIGH, the processor places write data on the data bus. floated. DEN also floats during HOLD. Pin names in parentheses apply to the 80188.

functionally and register compatible. ready inputs, and reset circuitry. mended crystal configuration is shown in Figure 5. Figure 5. Recommended input of at least six clocks.

The processor provides ALE, RD , and WR bus con- trol signals. The RD and WR signals are used to strobe data from memory or I/O to the processor or to strobe data from the processor to memory or I/O. The ALE line provides a strobe to latch the address when it is valid. The local bus controller does not provide a memory/I/O signal. If this is required, use the S2 signal (which will require external latching), make the memory and I/O spaces nonoverlapping, or use only the integrated chip-select circuitry. Local Bus Arbitration The processor uses a HOLD/HLDA system of local bus exchange. This provides an asynchronous bus exchange mechanism. This means multiple masters utilizing the same bus can operate at separate clock frequencies. The processor provides a single HOLD/HLDA pair through which all other bus mas- ters may gain control of the local bus. External cir- cuitry must arbitrate which external device will gain control of the bus when there is more than one alter- nate local bus master. When the processor relin- quishes control of the local bus, it floats DEN ,R D , WR,S 0 –S2, LOCK , AD0–AD15 (AD0–AD7), A16–A19 (A8–A19), BHE (S7), and DT/R to allow another master to drive these lines directly. Local Bus Controller and Reset During RESET the local bus controller will perform the following action: # Drive DEN ,R D , and WR HIGH for one clock cy- cle, then float. NOTE: RD is also provided with an internal pull-up de- vice to prevent the processor from inadvertently entering Queue Status Mode during RESET. # Drive S0 –S2 to the inactive state (all HIGH) and then float. # Drive LOCK HIGH and then float. # Float AD0–15 (AD0–AD7), A16–19 (A8–A19), BHE (S7), DT/R . # Drive ALE LOW (ALE is never floated). # Drive HLDA LOW. PERIPHERAL ARCHITECTURE All of the integrated peripherals are controlled by 16-bit registers contained within an internal 256-byte control block. The control block may be mapped into either memory or I/O space. Internal logic will recog- nize control block addresses and respond to bus cy- cles. During bus cycles to internal registers, the bus controller will signal the operation externally (i.e., the RD ,W R , status, address, data, etc., lines will be driv- en as in a normal bus cycle), but D 15–0 (D7–0 ), SRDY, and ARDY will be ignored. The base address of the control block must be on an even 256-byte boundary (i.e., the lower 8 bits of the base address are all zeros). The control block base address is programmed by a 16-bit relocation register contained within the control block at offset FEH from the base address of the control block. It provides the upper 12 bits of the base address of the control block. In addition to providing relocation information for the control block, the relocation register contains bits which place the interrupt controller into Slave Mode, and cause the CPU to interrupt upon encountering ESC instructions. Chip-Select/Ready Generation Logic The processor contains logic which provides programmable chip-select generation for both mem- ories and peripherals. In addition, it can be pro- grammed to provide READY (or WAIT state) genera- tion. It can also provide latched address bits A1 and A2. The chip-select lines are active for all memory and I/O cycles in their programmed areas, whether they be generated by the CPU or by the integrated DMA unit. MEMORY CHIP SELECTS The processor provides 6 memory chip select out- puts for 3 address areas; upper memory, lower memory, and midrange memory. One each is provid- ed for upper memory and lower memory, while four are provided for midrange memory. UPPER MEMORY CS The processor provides a chip select, called UCS , for the top of memory. The top of memory is usually used as the system memory because after reset the processor begins executing at memory location FFFF0H. LOWER MEMORY CS The processor provides a chip select for low memo- ry called LCS . The bottom of memory contains the interrupt vector table, starting at location 00000H.

The lower limit of memory defined by this chip select is always 0H, while the upper limit is programmable. By programming the upper limit, the size of the memory block is defined. MID-RANGE MEMORY CS The processor provides four MCS lines which are active within a user-locatable memory block. This block can be located within the 1-Mbyte memory ad- dress space exclusive of the areas defined by UCS and LCS . Both the base address and size of this memory block are programmable. PERIPHERAL CHIP SELECTS The processor can generate chip selects for up to seven peripheral devices. These chip selects are ac- tive for seven contiguous blocks of 128 bytes above a programmable base address. The base address may be located in either memory or I/O space. Sev- en CS lines called PCS0 –6 are generated by the processor. PCS5 and PCS6 can also be pro- grammed to provide latched address bits A1 and A2. If so programmed, they cannot be used as peripher- al selects. These outputs can be connected directly to the A0 and A1 pins used for selecting internal registers of 8-bit peripheral chips. READY GENERATION LOGIC The processor can generate a READY signal inter- nally for each of the memory or peripheral CS lines. The number of WAIT states to be inserted for each peripheral or memory is programmable to provide 0–3 wait states for all accesses to the area for which the chip select is active. In addition, the proc- essor may be programmed to either ignore external READY for each chip-select range individually or to factor external READY with the integrated ready generator. CHIP SELECT/READY LOGIC AND RESET Upon RESET, the Chip-Select/Ready Logic will per- form the following actions: # All chip-select outputs will be driven HIGH. # Upon leaving RESET, the UCS line will be pro- grammed to provide chip selects to a 1K block with the accompanying READY control bits set at 011 to insert 3 wait states in conjunction with ex- ternal READY (i.e., UMCS resets to FFFBH). # No other chip select or READY control registers have any predefined values after RESET. They will not become active until the CPU accesses their control registers. Both the PACS and MPCS registers must be accessed before the PCS lines will become active. DMA Channels The DMA controller provides two independent DMA channels. Data transfers can occur between memo- ry and I/O spaces (e.g., Memory to I/O) or within the same space (e.g., Memory to Memory or I/O to I/O). Data can be transferred either in bytes or in words (80186 only) to or from even or odd addresses. Each DMA channel maintains both a 20-bit source and destination pointer which can be optionally in- cremented or decremented after each data transfer (by one or two depending on byte or word transfers). Each data transfer consumes 2 bus cycles (a mini- mum of 8 clocks), one cycle to fetch data and the other to store data. This provides a maximum data transfer rate of 1.25 Mword/sec or 2.5 Mbytes/sec at 10 MHz (half of this rate for the 80188). DMA CHANNELS AND RESET Upon RESET, the DMA channels will perform the following actions: # The Start/Stop bit for each channel will be reset to STOP. # Any transfer in progress is aborted. Timers The processor provides three internal 16-bit pro- grammable timers. Two of these are highly flexible and are connected to four external pins (2 per timer). They can be used to count external events, time ex- ternal events, generate nonrepetitive waveforms, etc. The third timer is not connected to any external pins, and is useful for real-time coding and time de- lay applications. In addition, the third timer can be used as a prescaler to the other two, or as a DMA request source.

Upon RESET, the Timers will perform the following actions: # All EN (Enable) bits are reset preventing timer counting. # For Timers 0 and 1, the RIU bits are reset to zero and the ALT bits are set to one. This results in the Timer Out pins going high. Interrupt Controller The processor can receive interrupts from a number of sources, both internal and external. The internal interrupt controller serves to merge these requests on a priority basis, for individual service by the CPU. Internal interrupt sources (Timers and DMA chan- nels) can be disabled by their own control registers or by mask bits within the interrupt controller. The interrupt controller has its own control register that sets the mode of operation for the controller. INTERRUPT CONTROLLER AND RESET Upon RESET, the interrupt controller will perform the following actions: # All SFNM bits reset to 0, implying Fully Nested Mode. # All PR bits in the various control registers set to 1. This places all sources at lowest priority (level 111). # All LTM bits reset to 0, resulting in edge-sense mode. # All Interrupt Service bits reset to 0. # All Interrupt Request bits reset to 0. # All MSK (Interrupt Mask) bits set to 1 (mask). # All C (Cascade) bits reset to 0 (non-Cascade). # All PRM (Priority Mask) bits set to 1, implying no levels masked. # Initialized to Master Mode.

Pin names in parenthesis apply to 80188. does not exist on the 80188, this is only required for a 16-bit data bus. Figure 6. Typical 80186/80188 Computer

Pin names in parentheses apply to 80188. (1) BHE does not exist on the 80188, this is only required for a 16-bit data bus. Figure 7. Typical 80186/80188 Multi-Master Bus Interface

ABSOLUTE MAXIMUM RATINGS * Ambient Temperature under Bias ÀÀÀÀÀÀ0 §Ct o7 0 §C Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b65§Ct o a150§C Voltage on any Pin with Respect to GroundÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b1.0V to a7V Power Dissipation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ3W NOTICE: This is a production data sheet. The specifi- cations are subject to change without notice. *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability. D.C. CHARACTERISTICS (TA e 0§Ct o a70§C, V CC e 5V g10%) Applicable to 8 MHz and 10 MHz devices. Symbol Parameter Min Max Units Test Conditions VIL Input Low Voltage b0.5 a0.8 V VIH Input High Voltage 2.0 V CC a 0.5 V (All except X1 and (RES ) VIH1 Input High Voltage (RES ) 3.0 V CC a 0.5 V VOL Output Low Voltage 0.45 V I a e 2.5 mA for S0 –S2 Ia e 2.0 mA for all other Outputs VOH Output High Voltage 2.4 V I oa eb 400 mA ICC Power Supply Current 600 * mA T A eb 40§C 550 mA T A e 0§C 415 mA T A ea 70§C ILI Input Leakage Current g10 mA0 V k VIN k VCC ILO Output Leakage Current g10 mA 0.45V k VOUT k VCC VCLO Clock Output Low 0.6 V I a e 4.0 mA VCHO Clock Output High 4.0 V I oa eb 200 mA VCLI Clock Input Low Voltage b0.5 0.6 V VCHI Clock Input High Voltage 3.9 V CC a 1.0 V CIN Input Capacitance 10 pF CIO I/O Capacitance 20 pF *For extended temperature parts only.

A.C. CHARACTERISTICS (TA e 0§Ct o a70§C, V CC e 5V g10%) Timing Requirements All Timings Measured At 1.5V Unless Otherwise Noted. Symbol Parameter

8 MHz 10 MHz

TDVCL Data in Setup (A/D) 20 15 ns TCLDX Data in Hold (A/D) 10 8 ns TARYHCH Asynchronous Ready 20 15 ns (ARDY) Active Setup Time(1) TARYLCL ARDY Inactive Setup Time 35 25 ns TCLARX ARDY Hold Time 15 15 ns TARYCHL Asynchronous Ready 15 15 ns Inactive Hold Time TSRYCL Synchronous Ready (SRDY) 20 20 ns Transition Setup Time (2) TCLSRY SRDY Transition Hold 15 15 ns Time (2) THVCL HOLD Setup (1) 25 20 ns TINVCH INTR, NMI, TEST , TIM IN, 25 25 ns Setup(1) TINVCL DRQ0, DRQ1, Setup (1) 25 20 ns Master Interface Timing Responses TCLAV Address Valid Delay 5 55 5 44 ns C L e 20 pF–200 pF all OutputsTCLAX Address Hold 10 10 ns (Except T CLTMV) @

8 MHz and 10 MHzTCLAZ Address Float Delay T CLAX 35 T CLAX 30 ns

TCHCZ Command Lines Float Delay 45 40 ns TCHCV Command Lines Valid Delay 55 45 ns (after Float) TLHLL ALE Width T CLCLb35 T CLCLb30 ns TCHLH ALE Active Delay 35 30 ns TCHLL ALE Inactive Delay 35 30 ns TLLAX Address Hold from ALE T CHCLb25 T CHCLb20 ns Inactive TCLDV Data Valid Delay 10 44 10 40 ns TCLDOX Data Hold Time 10 10 ns TWHDX Data Hold after WR T CLCLb40 T CLCLb34 ns TCVCTV Control Active Delay 1 5 50 5 40 ns TCHCTV Control Active Delay 2 10 55 10 44 ns TCVCTX Control Inactive Delay 5 55 5 44 ns TCVDEX DEN Inactive Delay 10 70 10 56 ns (Non-Write Cycle) 1. To guarantee recognition at next clock. 2. To guarantee proper operation.

A.C. CHARACTERISTICS (TA e 0§Ct o a70§C, V CC e 5V g10%) (Continued) Master Interface Timing Responses (Continued) Symbol Parameter TAZRL Address Float to RD Active 0 0 ns TCLRL RD Active Delay 10 70 10 56 ns TCLRH RD Inactive Delay 10 55 10 44 ns TRHAV RD Inactive to Address T CLCLb40 T CLCLb40 ns Active TCLHAV HLDA Valid Delay 5 50 5 40 ns TRLRH RD Width 2T CLCLb50 2T CLCLb46 ns TWLWH WR Width 2T CLCLb40 2T CLCLb34 ns TAVLL Address Valid to ALE Low T CLCHb25 T CLCHb19 ns TCHSV Status Active Delay 10 55 10 45 ns TCLSH Status Inactive Delay 10 65 10 50 ns TCLTMV Timer Output Delay 60 48 ns 100 pF max @ 8&1 0M H z TCLRO Reset Delay 60 48 ns TCHQSV Queue Status Delay 35 28 ns TCHDX Status Hold Time 10 10 ns TAVCH Address Valid to Clock High 10 10 ns TCLLV LOCK Valid/Invalid Delay 5 65 5 60 ns Chip-Select Timing Responses TCLCSV Chip-Select Active Delay 66 45 ns TCXCSX Chip-Select Hold from 35 35 ns Command Inactive TCHCSX Chip-Select Inactive Delay 5 35 5 32 ns CLKIN Requirements TCKIN CLKIN Period 62.5 250 50 250 ns TCKHL CLKIN Fall Time 10 10 ns 3.5 to 1.0V TCKLH CLKIN Rise Time 10 10 ns 1.0 to 3.5V TCLCK CLKIN Low Time 25 20 ns 1.5V TCHCK CLKIN High Time 25 20 ns 1.5V CLKOUT Timing (200 pF load) TCICO CLKIN to CLKOUT Skew 50 25 ns TCLCL CLKOUT Period 125 500 100 500 ns TCLCH CLKOUT Low Time (/2 TCLCLb7.5 (/2 TCLCLb6.0 ns 1.5V TCHCL CLKOUT High Time (/2 TCLCLb7.5 (/2 TCLCLb6.0 ns 1.5V TCH1CH2 CLKOUT Rise Time 15 12 ns 1.0 to 3.5V TCL2CL1 CLKOUT Fall Time 15 12 ns 3.5 to 1.0V

EXPLANATION OF THE AC SYMBOLS Each timing symbol has from 5 to 7 characters. The first character is always a ‘‘T’’ (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the charac- ters and what they stand for. A: Address ARY: Asynchronous Ready Input C: Clock Output CK: Clock Input CS: Chip Select CT: Control (DT/R , DEN ,...) D: Data Input DE: DEN H: Logic Level High IN: Input (DRQ0, TIM0, . . . ) L: Logic Level Low or ALE O: Output QS: Queue Status (QS1, QS2) R: RD signal, RESET signal S: Status (S0 ,S 1 ,S 2 ) SRY: Synchronous Ready Input V: Valid W: WR Signal X: No Longer a Valid Logic Level Z: Float Examples: T CLAV Ð Time from Clock low to Address valid TCHLH Ð Time from Clock high to ALE high TCLCSV Ð Time from Clock low to Chip Select valid

272430–8 NOTE: Pin names in parentheses apply to the 80188.

WAVEFORMS (Continued) MAJOR CYCLE TIMING (Continued) NOTES: 272430–9 1. INTA occurs one clock later in slave mode. 2. Status inactive just prior to T 4. 3. If latched A1 and A2 are selected instead of PCS5 and PCS6 , only T CLCSV is applicable. 4. Pin names in parentheses apply to the 80188.

WAVEFORMS (Continued) 272430–10 272430–11 272430–12

WAVEFORMS (Continued) 272430–13 272430–14

WAVEFORMS (Continued) READY TIMING 272430–15

272430–16 NOTE: Pin names in parentheses apply to the 80188.

the operational specifications of the microprocessor. exceed commercial standards. tended temperature range without burn-in. following guidelines in MIL-STD-883, Method 1015. for both commercial and EXPRESS parts. Table 2. Prefix Identification

A determination of program execution timing must consider the bus cycles necessary to prefetch in- structions as well as the number of execution unit cycles necessary to execute instructions. The fol- lowing instruction timings represent the minimum ex- ecution time in clock cycles for each instruction. The timings given are based on the following assump- tions: # The opcode, along with any data or displacement required for execution of a particular instruction, has been prefetched and resides in the queue at the time it is needed. # No wait states or bus HOLDS occur. # All word-data is located on even-address bound- aries. All instructions which involve memory accesses can also require one or two additional clocks above the minimum timings shown due to the asynchronous handshake between the bus interface unit (BIU) and execution unit. All jumps and calls include the time required to fetch the opcode of the next instruction at the destination address. The 80186 has sufficient bus performance to ensure that an adequate number of prefetched bytes will reside in the queue (6 bytes) most of the time. Therefore, actual program execution time will not be substantially greater than that derived from adding the instruction timings shown. The 80188 is noticeably limited in its performance relative to the execution unit. A sufficient number of prefetched bytes may not reside in the prefetch queue (4 bytes) much of the time. Therefore, actual program execution time may be substantially greater than that derived from adding the instruction timings shown.

Function Format Clock Clock Comments Cycles Cycles DATA TRANSFER MOV e Move: Register to Register/Memory 1000100w m o dr e g r / m 2/12 2/12 * Register/memory to register 1000101w m o dr e g r / m 2 / 9 2 / 9 * Immediate to register/memory 1100011w m o d0 0 0 r / m data data if w e1 12/13 12/13 8/16-bit Immediate to register 1011w r e g data data if w e1 3/4 3/4 8/16-bit Memory to accumulator 1010000w addr-low addr-high 8 8 * Accumulator to memory 1010001w addr-low addr-high 9 9 * Register/memory to segment register 10001110 m o d0r e g r / m 2 / 9 2/13 Segment register to register/memory 10001100 m o d0r e g r / m 2/11 2/15 PUSH e Push: Memory 11111111 m o d110 r / m 1 6 2 0 Register 01010 r e g 1 0 1 4 Segment register 000r e g110 9 1 3 Immediate 011010s0 data data if s e01 0 1 4 PUSHA e Push All 01100000 3 6 6 8 POP e Pop: Memory 10001111 m o d000 r / m 2 0 2 4 Register 01011 r e g 1 0 1 4 Segment register 000r e g111 (regi01) 8 12 POPA e P o pA l l 01100001 5 1 8 3 XCHG e Exchange: Register/memory with register 1000011w m o dr e g r / m 4/17 4/17 * Register with accumulator 10010 r e g 3 3 IN e Input from: Fixed port 1110010w port 10 10 * Variable port 1110110w 8 8 * OUT e Output to: Fixed port 1110011w port 9 9 * Variable port 1110111w 7 7 * XLAT e Translate byte to AL 11010111 1 1 1 5 LEA e Load EA to register 10001101 m o dr e g r / m 6 6 LDS e Load pointer to DS 11000101 m o dr e g r / m (modi11) 18 26 LES e Load pointer to ES 11000100 m o dr e g r / m (modi11) 18 26 LAHF e Load AH with flags 10011111 2 2 SAHF e Store AH into flags 10011110 3 3 PUSHF e Push flags 10011100 9 1 3 POPF e Pop flags 10011101 8 1 2 Shaded areas indicate instructions not available in 8086, 8088 microsystems. NOTE: *Clock cycles shown for byte transfers, for word operations, add 4 clock cycles for each memory transfer.

INSTRUCTION SET SUMMARY (Continued) 80186 80188 Function Format Clock Clock Comments Cycles Cycles DATA TRANSFER (Continued) SEGMENT e Segment Override: CS 00101110 2 2 SS 00110110 2 2 DS 00111110 2 2 ES 00100110 2 2 ARITHMETIC ADD e Add: Reg/memory with register to either 000000dw m o dr e g r / m 3/10 3/10 * Immediate to register/memory 100000sw m o d000 r / m data data if s w e01 4/16 4/16 * Immediate to accumulator 0000010w data data if w e1 3/4 3/4 8/16-bit ADC e Add with carry: Reg/memory with register to either 000100dw m o dr e g r / m 3/10 3/10 * Immediate to register/memory 100000sw m o d010 r / m data data if s w e01 4/16 4/16 * Immediate to accumulator 0001010w data data if w e1 3/4 3/4 8/16-bit INC e Increment: Register/memory 1111111w m o d000 r / m 3/15 3/15 * Register 01000 r e g 3 3 SUB e Subtract: Reg/memory and register to either 001010dw m o dr e g r / m 3/10 3/10 * Immediate from register/memory 100000sw m o d101 r / m data data if s w e01 4/16 4/16 * Immediate from accumulator 0010110w data data if w e1 3/4 3/4 8/16-bit SBB e Subtract with borrow: Reg/memory and register to either 000110dw m o dr e g r / m 3/10 3/10 * Immediate from register/memory 100000sw m o d011 r / m data data if s w e01 4/16 4/16 * Immediate from accumulator 0001110w data data if w e1 3/4 3/4 8/16-bit DEC e Decrement Register/memory 1111111w m o d001 r / m 3/15 3/15 * Register 01001 r e g 3 3 CMP e Compare: Register/memory with register 0011101w m o dr e g r / m 3/10 3/10 * Register with register/memory 0011100w m o dr e g r / m 3/10 3/10 * Immediate with register/memory 100000sw m o d111 r / m data data if s w e01 3/10 3/10 * Immediate with accumulator 0011110w data data if w e1 3/4 3/4 8/16-bit NEG e Change sign register/memory 1111011w m o d011 r / m 3/10 3/10 * AAA e ASCII adjust for add 00110111 8 8 DAA e Decimal adjust for add 00100111 4 4 AAS e ASCII adjust for subtract 00111111 7 7 DAS e Decimal adjust for subtract 00101111 4 4 MUL e Multiply (unsigned): 1111011w m o d1 0 0 r / m Register-Byte 26–28 26–28 Register-Word 35–37 35–37 Memory-Byte 32–34 32–34 Memory-Word 41–43 41–43 * Shaded areas indicate instructions not available in 8086, 8088 microsystems. NOTE: *Clock cycles shown for byte transfers, for word operations, add 4 clock cycles for each memory transfer.

INSTRUCTION SET SUMMARY (Continued) 80186 80188 Function Format Clock Clock Comments Cycles Cycles ARITHMETIC (Continued) IMUL e Integer multiply (signed): 1111011w m o d101 r / m Register-Byte 25–28 25–28 Register-Word 34–37 34–37 Memory-Byte 31–34 31–34 Memory-Word 40–43 40–43 * IMUL e Integer Immediate multiply 011010s1 m o dr e g r / m data data if s e0 22–25/ 22–25/ (signed) 29–32 29–32 DIV e Divide (unsigned): 1111011w m o d110 r / m Register-Byte 29 29 Register-Word 38 38 Memory-Byte 35 35 Memory-Word 44 44 * IDIV e Integer divide (signed): 1111011w m o d111 r / m Register-Byte 44–52 44–52 Register-Word 53–61 53–61 Memory-Byte 50–58 50–58 Memory-Word 59–67 59–67 * AAM e ASCII adjust for multiply 11010100 00001010 1 9 1 9 AAD e ASCII adjust for divide 11010101 00001010 1 5 1 5 CBW e Convert byte to word 10011000 2 2 CWD e Convert word to double word 10011001 4 4 LOGIC Shift/Rotate Instructions: Register/Memory by 1 1101000w m o dT T Tr / m 2/15 2/15 Register/Memory by CL 1101001w m o dT T Tr / m 5an/17an5 an/17an Register/Memory by Count 1100000w m o dT T Tr / m count 5an/17an5 an/17an TTT Instruction

000 R O L

001 R O R

010 R C L

011 R C R

101 S H R

111 S A R

AND e And: Reg/memory and register to either 001000dw m o dr e g r / m 3/10 3/10 * Immediate to register/memory 1000000w m o d100 r / m data data if w e1 4/16 4/16 * Immediate to accumulator 0010010w data data if w e1 3/4 3/4 8/16-bit TESTeAnd function to flags, no result: Register/memory and register 1000010w m o dr e g r / m 3/10 3/10 * Immediate data and register/memory 1111011w m o d000 r / m data data if w e1 4/10 4/10 * Immediate data and accumulator 1010100w data data if w e1 3/4 3/4 8/16-bit OReOr: Reg/memory and register to either 000010dw m o dr e g r / m 3/10 3/10 * Immediate to register/memory 1000000w m o d001 r / m data data if w e1 4/16 4/16 * Immediate to accumulator 0000110w data data if w e1 3/4 3/4 8/16-bit Shaded areas indicate instructions not available in 8086, 8088 microsystems. NOTE: *Clock cycles shown for byte transfers, for word operations, add 4 clock cycles for each memory transfer.

INSTRUCTION SET SUMMARY (Continued) 80186 80188 Function Format Clock Clock Comments Cycles Cycles LOGIC (Continued) XOR e Exclusive or: Reg/memory and register to either 001100dw m o dr e g r / m 3/10 3/10 * Immediate to register/memory 1000000w m o d110 r / m data data if w e1 4/16 4/16 * Immediate to accumulator 0011010w data data if w e1 3/4 3/4 8/16-bit NOT e Invert register/memory 1111011w m o d010 r / m 3/10 3/10 * STRING MANIPULATION MOVS e Move byte/word 1010010w 1 4 1 4 * CMPS e Compare byte/word 1010011w 2 2 2 2 * SCAS e Scan byte/word 1010111w 1 5 1 5 * LODS e Load byte/wd to AL/AX 1010110w 1 2 1 2 * STOS e Store byte/wd from AL/AX 1010101w 1 0 1 0 * INS e Input byte/wd from DX port 0110110w 1 4 1 4 OUTS e Output byte/wd to DX port 0110111w 1 4 1 4 Repeated by count in CX (REP/REPE/REPZ/REPNE/REPNZ) MOVS e Move string 11110010 1010010w 8 a8n 8 a8n* CMPS e Compare string 1111001z 1010011w 5 a22n 5 a22n* SCAS e Scan string 1111001z 1010111w 5 a15n 5 a15n* LODS e Load string 11110010 1010110w 6 a11n 6 a11n* STOS e Store string 11110010 1010101w 6 a9n 6 a9n* INS e Input string 11110010 0110110w 8 a8n 8 a8n* OUTS e Output string 11110010 0110111w 8 a8n 8 a8n* CONTROL TRANSFER CALL e Call: Direct within segment 11101000 disp-low disp-high 15 19 Register/memory 11111111 m o d010 r / m 13/19 17/27 indirect within segment Direct intersegment 10011010 segment offset 23 31 segment selector Indirect intersegment 11111111 m o d011 r / m (mod i 11) 38 54 JMP e Unconditional jump: Short/long 11101011 disp-low 14 14 Direct within segment 11101001 disp-low disp-high 14 14 Register/memory 11111111 m o d100 r / m 11/17 11/21 indirect within segment Direct intersegment 11101010 segment offset 14 14 segment selector Indirect intersegment 11111111 m o d101 r / m (mod i 11) 26 34 Shaded areas indicate instructions not available in 8086, 8088 microsystems. NOTE: *Clock cycles shown for byte transfers, for word operations, add 4 clock cycles for each memory transfer.

INSTRUCTION SET SUMMARY (Continued) 80186 80188 Function Format Clock Clock Comments Cycles Cycles CONTROL TRANSFER (Continued) RET e Return from CALL: Within segment 11000011 1 6 2 0 Within seg adding immed to SP 11000010 data-low data-high 18 22 Intersegment 11001011 2 2 3 0 Intersegment adding immediate to SP 11001010 data-low data-high 25 33 JE/JZ e Jump on equal/zero 01110100 disp 4/13 4/13 JMP not JL/JNGE e Jump on less/not greater or equal 01111100 disp 4/13 4/13 taken/JMP JLE/JNG e Jump on less or equal/not greater 01111110 disp 4/13 4/13 taken JB/JNAE e Jump on below/not above or equal 01110010 disp 4/13 4/13 JBE/JNA e Jump on below or equal/not above 01110110 disp 4/13 4/13 JP/JPE e Jump on parity/parity even 01111010 disp 4/13 4/13 JO e Jump on overflow 01110 000 disp 4/13 4/13 JS e Jump on sign 01111000 disp 4/13 4/13 JNE/JNZ e Jump on not equal/not zero 01110101 disp 4/13 4/13 JNL/JGE e Jump on not less/greater or equal 01111101 disp 4/13 4/13 JNLE/JG e Jump on not less or equal/greater 01111111 disp 4/13 4/13 JNB/JAE e Jump on not below/above or equal 01110011 disp 4/13 4/13 JNBE/JA e Jump on not below or equal/above 01110111 disp 4/13 4/13 JNP/JPO e Jump on not par/par odd 01111011 disp 4/13 4/13 JNO e Jump on not overflow 01110001 disp 4/13 4/13 JNS e Jump on not sign 01111001 disp 4/13 4/13 JCXZ e Jump on CX zero 11100011 disp 5/15 5/15 LOOP e Loop CX times 11100010 disp 6/16 6/16 LOOP not LOOPZ/LOOPE e Loop while zero/equal 11100001 disp 6/16 6/16 taken/LOOP LOOPNZ/LOOPNE e Loop while not zero/equal 11100000 disp 6/16 6/16 taken ENTER e Enter Procedure 11001000 data-low data-high L L e 0 15 19 L e 1 25 29 L l 1 22a16(nb1) 26 a20(nb1) LEAVE e Leave Procedure 11001001 8 8 INT e Interrupt: Type specified 11001101 type 47 47 Type 3 11001100 4 5 4 5 i f INT. taken/ INTO e Interrupt on overflow 11001110 48/4 48/4 if INT. not taken IRET e Interrupt return 11001111 2 8 2 8 BOUND e Detect value out of range 01100010 m o dr e g r / m 3 3 – 3 5 3 3 – 3 5 Shaded areas indicate instructions not available in 8086, 8088 microsystems. NOTE: *Clock cycles shown for byte transfers, for word operations, add 4 clock cycles for each memory transfer.

INSTRUCTION SET SUMMARY (Continued) 80186 80188 Function Format Clock Clock Comments Cycles Cycles PROCESSOR CONTROL CLC e Clear carry 11111000 2 2 CMC e Complement carry 11110101 2 2 STC e Set carry 11111001 2 2 CLD e Clear direction 11111100 2 2 STD e Set direction 11111101 2 2 CLI e Clear interrupt 11111010 2 2 STI e Set interrupt 11111011 2 2 HLT e Halt 11110100 2 2 WAIT e Wait 10011011 6 6 i f TEST e 0 LOCK e Bus lock prefix 11110000 2 3 ESC e Processor Extension Escape 11011TTT m o dL L L r / m 6 6 (TTT LLL are opcode to processor extension) NOP e No Operation 10010000 3 3 Shaded areas indicate instructions not available in 8086, 8088 microsystems. NOTE: *Clock cycles shown for byte transfers, for word operations, add 4 clock cycles for each memory transfer. FOOTNOTES The Effective Address (EA) of the memory operand is computed according to the mod and r/m fields: if mod e 11 then r/m is treated as REG field if mod e 00 then DISP e 0*, disp-low and disp-high are absent if mod e 01 then DISP e disp-low sign-extended to 16-bits, disp-high is absent if mod e 10 then DISP e disp-high: disp-low if r/m e 000 then EA e (BX) a (SI) a DISP if r/m e 001 then EA e (BX) a (DI) a DISP if r/m e 010 then EA e (BP) a (SI) a DISP if r/m e 011 then EA e (BP) a (DI) a DISP if r/m e 100 then EA e (SI) a DISP if r/m e 101 then EA e (DI) a DISP if r/m e 110 then EA e (BP) a DISP* if r/m e 111 then EA e (BX) a DISP DISP follows 2nd byte of instruction (before data if required) *except if mod e 00 and r/m e 110 then EA e disp-high: disp-low. EA calculation time is 4 clock cycles for all modes, and is included in the execution times given whenev- er appropriate. Segment Override Prefix 0 0 1 reg 1 1 0 reg is assigned according to the following: reg Segment Register 00 ES 01 CS 10 SS 11 DS REG is assigned according to the following table: 16-Bit (w e 1) 8-Bit (w e 0)

000 AX 000 AL

001 CX 001 CL

010 DX 010 DL

011 BX 011 BL

100 SP 100 AH

101 BP 101 CH

110 SI 110 DH

111 DI 111 BH

The physical addresses of all operands addressed by the BP register are computed using the SS seg- ment register. The physical addresses of the desti- nation operands of the string primitive operations (those addressed by the DI register) are computed using the ES segment, which may not be overridden.

REVISION HISTORY

This data sheet replaces the following data sheets: 210706-011 80188 210451-011 80186