6300ESB INTEL | Alldatasheet
Document overview
- Manufacturer or author: pROVIDED bY alldatasheet.com(free datasheet download site)
- PDF pages: 848
Technical content
Datasheet sections
- 8 Order Number: 300641-004US
- 1.1 About This Document
- 2 I n t e l ® 6300ESB ICH and System Clock Domains
- 3 Signal Description
- 3.1 Hub Interface to Host Controller
- 3.2 Firmware Hub Interface
- 3.3 PCI Interface
- 3.4 PCI-X Interface
- 3.5 SATA Interface
- 3.6 IDE Interface
- 3.7 LPC I/F
- 3.8 Interrupt Interface
- 3.9 USB Interface
- 3.10 Power Management Interface
- 3.11 CPU Interface
- 3.12 SMBus Interface
- 3.13 System Management Interface
- 3.14 Real Time Clock Interface
- 3.15 Other Clocks
- 3.16 Miscellaneous Signals
- 3.17 AC’97 Link
- 3.18 Universal Asynchronous Receive and Transmit (UART0,1)
- 3.19 General Purpose I/O
- 3.20 Power and Ground
- 3.21 Pin Straps
- 3.21.1 Functional Straps
- 3.22 Revision and Device ID Table
- 4.1 Power Planes
- 4.2 Integrated Pull-Ups and Pull-Downs
- 4.3 IDE Integrated Series Termination Resistors
- 4.4 Output and I/O Signals Planes and States
- 4.5 Power Planes for Input Signals
- 5 Functional Description
- 5.1 Hub Interface to PCI Bridge (D30:F0)
- 5.1.1 PCI Bus Interface
- 5.1.2 PCI-to-PCI Bridge Model
- 5.1.3 IDSEL to Device Number Mapping
- 5.1.4 SERR# Functionality
- 5.1.5 Parity Error Detection
- 5.1.6 Standard PCI Bus Configuration Mechanism
- 5.1.6.1 Type 0 to Type 0 Forwarding
- 5.1.6.2 Type 1 to Type 0 Conversion
- 5.1.7 PCI Dual Address Cycle (DAC) Support
- 5.2 LPC Bridge (with System and Management Functions) (D31:F0)
- 5.2.1 LPC Cycle Types
- 5.2.1.1 Start Field Definition
- 5.2.1.2 Cycle Type/Direction (CYCTYPE + DIR)
- 5.2.1.3 SIZE
- 5.2.1.4 SYNC
Order Number: 300641-004US Notice: The Intel® 6300ESB I/O Controller Hub may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Intel® 6300ESB I/O Controller Hub Datasheet November 2007
Intel® 6300ESB I/O Controller Hub DS November 2007
2 Order Number: 300641-004US
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT . Intel products are not intended for use in medical, life saving, life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. The Intel ® 6300ESB I/O Controller Hub may contain design defects or errors known as errata which may cause the product to deviate from published specifications.which may cause the product to deviate from published specifications. which may cause the product to deviate from published specifications. Current characterized errata are available on request. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel® 6300ESB I/O Controller Hub may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. AnyPoint, AppChoice, BoardWatch, BunnyPeople, CablePort, Celeron, Chips, CT Media, Dialogic, DM3, EtherExpress, ETOX, FlashFile, i386, i486, i960, iCOMP , InstantIP , Intel, Intel Centrino, Intel logo, Intel386, Intel486, Intel740, IntelDX2, IntelDX4, IntelSX2, Intel Create & Share, Intel GigaBlade, Intel InBusiness, Intel Inside, Intel Inside logo, Intel NetBurst, Intel NetMerge, Intel NetStructure, Intel Play, Intel Play logo, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel TeamStation, Intel Xeon, Intel XScale, IPLink, Itanium, MCS, MMX, MMX logo, Optimizer logo, OverDrive, Paragon, PC Dads, PC Parents, PDCharm, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, RemoteExpress, SmartDie, Solutions960, Sound Mark, StorageExpress, The Computer Inside., The Journey Inside, TokenExpress, VoiceBrick, VTune, and Xircom are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2007, Intel Corporation. All rights reserved.
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 3 —Intel ® 6300ESB ICH Intel® 6300ESB I/O Controller Hub Product Features
- 8-Bit Hub Interface — 266 Mbyte/s maximum throughput — Parallel Termination scheme for longer trace lengths — Supports Lower Voltages as per Hub Interface 1.5 spec
- PCI-X Bus I/F — Supports PCI-X Rev 1.0 Specification at
66 MHz
— Supports PCI Rev 2.2 Specification at 33 MHz — Support external master devices on PCI — 4 @ PCI 33 MHz — 2 @ PCI 64/66 MHz — 4 @ PCI-X 64/66 MHz (two slots and two soldered down devices) — Support for 64-bit addressing on PCI-X using DAC protocol
- PCI Bus I/F — Supports PCI 32b/33 MHz — 120 Mbyte/s throughput — Supports PCI Rev 2.2 Specification at 33 MHz — Supports 4 external master devices @
33 MHz
— Support for 44-bit addressing on PCI using DAC protocol. — 4 slots supported
- Integrated IDE Controller — Supports “Native Mode” Register and Interrupts — Supports faster PIO timings for non- data cycles — Independent timing of up to four drives, with separate Primary and Secondary IDE cable connections — Supports Ultra 100 DMA Mode Transfers up to 100 Mbytes/s for reads from disk;
88.88 Mbytes/s for writes to disk, as
well as Ultra66 and Ultra33 DMA modes. — PIO Mode four transfers up to 14 Mbytes/s
- Integrated Serial ATA Host Controllers — Independent DMA operation on two ports — Data transfer rates up to 150 Mbyte/s — Alternate Device ID and RAID Class Code option for support of Soft RAID
- Power Management Logic — ACPI 1.0 compliant — ACPI-defined power states S1 (Stop Grant), S3 (STR), S4 (STD), S5 (SOFF) — ACPI Power Management Timer —S M I # G e n e r a t i o n —P C I P M E # — Supports THRMTRIP# input, SYS_RESER# input and SLP_S4# output — Support for APM-based legacy power management for non-ACPI implementations
- External Glue Integration — Integrated Pull-up, Pull-down and Series Termination resistors on IDE, CPU I/F — Integrated Pull-down and Series resistors on USB
- Enhanced Hub I/F buffers improve routing flexibility (Not available with all Memory Controller Hubs)
- Firmware Hub (FWH) I/F supports BIOS Memory size up to 8 Mbytes
- Low Pin Count (LPC) I/F — New: No ISA/X-Bus support — Allows connections of devices such as Super I/O, microcontrollers, customers ASICs — Supports two Master/DMA devices — Memory size up to 8 Mbytes
- Enhanced DMA Controller — Two cascaded 8237 DMA controllers —S u p p o r t s L P C D M A — Supports DMA Collection Buffer to provide Type-F DMA performance for all DMA channels
- Real-Time Clock — 256-byte battery-backed CMOS RAM
- System TCO Reduction Circuits — Timers to generate SMI# and Reset upon detection of system hang — Interrupt capability to OS-specific manageability extension and OS capability to call TCO BIOS Timers to detect improper CPU reset — Alert On Lan (AOL) to enable heartbeats and system event reporting via LAN controller —S u p p o r t s C P U B I S T — Supports ability to disable external devices
Intel® 6300ESB ICH— Intel® 6300ESB I/O Controller Hub DS November 2007
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- USB — Includes one EHCI USB2 host controllers, a total of four ports (shared with the UHCI ports) — Two UHCI Host Controllers for a total of four ports (shared with EHCI ports) — New: supports a USB 2.0 High-speed Debug Port — Supports wake-up from sleeping states S1-S4 — Supports legacy Keyboard/Mouse software with USB-based keyboard and mouse
- SMBus — Flexible SMBus/SMLink architecture to optimize for ASF and eliminate board requirements of SMBus 2.0 compliance — Supports SMBus 2.0 Specification — Host interface allows CPU to communicate via SMBus — Slave interface allows an external Microcontroller to access system resources — Compatible with most 2-wire components that are also I compatible
- AC'97 Link for Audio and Telephony CODECs — New: Third AC_SDATA_IN Line for three codec support — AC’97 2.2 compliant — New: Independent bus master logic for 8 channels (PCM In/Out, Mic 1 Input, Mic 2 Input, Modem In/Out, S/PDIF Out) — Separate independent PCI functions for Audio and Modem — Support for up four to six channels of PCM audio output (full AC3 decode) — Support for 20-bit sample — Support for ACPI device states - D0 and
- Interrupt Controller — Supports up to 12 PCI interrupt pins; four are not shared — Two cascaded 82C59 with 15 interrupts — Supports PCI scheme for delivering interrupts as write cycles (MSI) — Integrated I/O APIC capability with 24 interrupts — Supports Serial Interrupt Protocol — Supports Front-Side Message Interrupt Delivery
- New: Multimedia Timers based on 82C54 — Includes three timer comparators — System timer, Refresh request, Speaker tone output — One-shot and periodic interrupts supported
- New: Watchdog Timer — Two-Stage Watchdog with independent count values for each stage — First stage generates an INT or SMI — Second stage drives external pin active until cleared by a system reset or power cycle — Configuration option for write-once enabling (count values can still change) — Configurable granularity from 1µs to 10 min
- New: Integrated 16550 compatible UARTs — Enable/disable per UARTs — Serial interrupts — Can disable when external SIO used
- New: Port 60/64 Emulation — Programmable interrupt generation on writes — Positive decode to Port 60/64 emulation registers
- GPIO — Four GPOs capable of directly driving LEDs — Two GPOs maintain state during and after reset
- 1.5 V operation with 3.3 V I/O. 5 V tolerance on many buffers, including IDE.
- Package 37.5 x 37.5 mm 689 BGA
- Process P859.6
Figure 1. Workstation/PC Model
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Figure 2. Low to Mid-Range Communication Appliance Model (Diskless)
Figure 3. Value Server, Ultra-Dense Server and Low-End Server Blade
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 9 Contents—Intel ® 6300ESB ICH
5.2.1.11 Configuration and Intel
5.3.4.1 Address Shifting When Programmed for 16-Bit I/O Count by Words105
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5.7.7.4 Registers Associated with Processor System Bus Interrupt Delivery 134
5.11.2 Intel
5.11.4 Intel
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 11 Contents—Intel ® 6300ESB ICH
5.11.8.4 Processor Initiated Passive Cooling (Via Programmed
5.11.11.4Controlling Leakage and Power Consumption during Low-Power States 167
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5.17.3.3 Command Register, Status Register, and TD Status Bit Interaction 204
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7.1.4 Offset 06 - 07h: PD_STS—Primary Device Status Register (HUB-PCI—D30:F0) .. 290
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7.1.5 Offset 08h: RID—Revision Identification Register
7.1.7 Offset 0Bh: BCC—Base-Class Code Register
7.1.8 Offset 0Dh: PMLT—Primary Master Latency Timer Register (HUB-PCI—D30:F0) .. 292
7.1.9 Offset 0Eh: HEADTYP—Header Type Register
7.1.10 Offset 18h: PBUS_NUM—Primary Bus Number Register (HUB-PCI—D30:F0) . 292 293
7.1.12 Offset 1A: SUB_BUS_NUM—Subordinate Bus Number Register (HUB-PCI—
D30:F0)293
7.1.13 Offset 1Bh: SMLT—Secondary Master Latency Timer Register (HUB-PCI—D30:F0)
7.1.17 Offset 20 - 21h: MEMBASE—Memory Base Register
7.1.18 Offset 22 - 23h: MEMLIM—Memory Limit Register
7.1.19 Offset 24h - 25h: PREF_MEM_BASE—Prefetchable Memory
7.1.20 Offset 26h-27h: PREF_MEM_MLT—Prefetchable Memory
7.1.21 Offset 30 - 31h: IOBASE_HI—I/O Base Upper 16 Bits Register (HUB-PCI—
D30:F0)299
7.1.22 Offset 32 - 33h: IOLIM_HI—I/O Limit Upper 16 Bits Register
7.1.23 Offset 3Ch: INT_LINE—Interrupt Line Register
7.1.24 Offset 3E - 3Fh: BRIDGE_CNT—Bridge Control Register (HUB-PCI—D30:F0). 301
7.1.25 Offset 40 - 43h: HI_CMD—Hub Interface Command Control
7.1.26 Offset 44 - 45h: DEVICE_HIDE—Secondary PCI Device
7.1.27 Offset 50 - 51h: CNF—Intel
® 6300ESB ICH Configuration Register (HUB-PCI— D30:F0)306
7.1.28 Offset 58 - 5Bh: D30_PNE — PERR#_NMI_ENABLE Register (HUB-PCI—D30:F0)
7.1.29 Offset 70h: MTT—Multi-Transaction Timer Register
7.1.30 Offset 82h: PCI_MAST_STS—PCI Master Status Register (HUB-PCI—D30:F0)309
7.1.31 Offset 90h: ERR_CMD—Error Command Register
7.1.32 Offset 92h: ERR_STS—Error Status Register
8.1.3 Offset 04 - 05h: PCICMD—PCI COMMAND Register
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8.1.4 Offset 06 - 07h: PCISTA—PCI Device Status
8.1.7 Offset 0Ah: SCC—Sub-Class Code Register
8.1.8 Offset 0Bh: BCC—Base-Class Code Register
8.1.9 Offset 0Eh: HEADTYP—Header Type Register
8.1.10 Offset 40 - 43h: PMBASE—ACPI Base Address
8.1.14 Offset 58h - 5Bh: GPIO_BASE—GPIO Base Address
8.1.16 Offset PIRQA - 60h: PIRQ[n]_ROUT—PIRQ[A,B,C,D]
8.1.17 Offset 64h: SERIRQ_CNTL—Serial IRQ Control
8.1.18 Offset PIRQE - 68h: PIRQ[n]_ROUT—PIRQ[E,F,G,H] Routing
8.1.19 Offset 88h: D31_ERR_CFG—Device 31 Error Config Register (LPC I/F—D31:F0) . 325 8.1.20 Offset 8Ah: D31_ERR_STS—Device 31 Error Status Register (LPC I/F—D31:F0). 325
8.1.21 Offset 90h - 91h: PCI_DMA_CFG—PCI DMA Configuration (LPC I/F—D31:F0) 326
8.1.22 Offset D0h - D3h: GEN_CNTL—General Control Register
8.1.24 Offset D5h: BACK_CNTL—Backed Up Control
8.1.25 Offset D8h: RTC_CONF—RTC Configuration Register
8.1.26 Offset E0h: COM_DEC—LPC I/F Communication Port
8.1.27 Offset E1h: FDD/LPT_DEC—LPC I/F FDD and LPT Decode Ranges (LPC I/F—
D31:F0)333 8.1.29 Offset E3h: FWH_DEC_EN1—FWH Decode Enable 1 Register (LPC I/F—D31:F0). 335
8.1.30 Offset E4h - E5h: GEN1_DEC—LPC I/F Generic Decode Range 1 (LPC I/F—D31:F0)
8.1.31 Offset E6h - E7h: LPC_EN—LPC I/F Enables
8.1.32 Offset E8h: FWH_SEL1—FWH Select 1 Register
8.1.33 Offset ECh - EDh: GEN2_DEC—LPC I/F Generic Decode
8.1.34 Offset EEh - EFh: FWH_SEL2—FWH Select 2 Register
8.1.35 Offset F0h: FWH_DEC_EN2—FWH Decode Enable 2 Register (LPC I/F—D31:F0) . 342
8.1.36 Offset F2h: FUNC_DIS—Function Disable Register
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8.1.37 Offset F4: ETR1—PCI-X Extended Features Register
8.5.10 Offset 10h - 11h (Vector 0) through 3E - 3Fh (Vector 23): Redirection Table 373
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8.8.1.1 Offset A0h: GEN_PMCON_1—General PM Configuration 1 Register
8.8.1.2 Offset A2h: GEN_PMCON_2—General PM Configuration 2 Register
8.8.1.3 Offset A4h: GEN_PMCON_3—General PM Configuration 3
8.8.1.5 Offset B8h - BBh: GPI_ROUT—GPI Routing Control Register
8.8.1.6 Offset C0h: MON_FWD_EN—IO Monitor Forward Enable Register
8.8.1.7 Offset C4h, C6h, C8h, CAh: MON[n]_TRP_RNG—I/O Monitor [4:7]
8.8.1.8 Offset CCh: MON_TRP_MSK—I/O Monitor Trap Range Mask Register
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 19 Contents—Intel ® 6300ESB ICH 8.10.4 Offset GPIOBASE + 0Ch: GP_LVL—GPIO Level for Input or Output Register.. 427
8.10.8 Offset GPIOBASE + 34h: GP_IO_SEL2—GPIO Input/Output Select 2 Register432
9.1.10 Offset 10h - 13h: PCMD_BAR—Primary Command Block
9.1.11 Offset 14h - 17h: PCNL_BAR—Primary Control Block Base
9.1.12 Offset 18h - 1Bh: SCMD_BAR—Secondary Command Block
9.1.13 Offset 1Ch - 1Fh: SCNL_BAR—Secondary Control Block
9.1.14 Offset 20h - 23h: BM_BASE—Bus Master Base Address Register (IDE—D31:F1).. 443
9.1.16 Offset 2Ch - 2Dh: IDE_SVID—Subsystem Vendor ID
9.1.18 Offset 3Ch: INTR_LN—Interrupt Line Register
9.1.22 Offset 48h: SDMA_CNT—Synchronous DMA Control Register (IDE—D31:F1). 452 9.1.23 Offset 4A - 4Bh: SDMA_TIM—Synchronous DMA Timing Register (IDE—D31:F1). 453
9.1.24 IDE_CONFIG—IDE I/O Configuration Register
10.1.1 Offset 00 - 01h: VID—Vendor Identification Register
10.1.2 Offset 02 - 03h: DID—Device Identification Register
10.1.3 Offset 04 - 05h: CMD—Command Register
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10.1.4 Offset 06 - 07h: STA—Device Status Register
10.1.5 Offset 08h: RID—Revision Identification Register
10.1.7 Offset 0Ah: SCC—Sub Class Code Register
10.1.8 Offset 0Bh: BCC—Base Class Code Register
10.1.10Offset 0Eh: HTYPE—Header Type Register 10.1.11Offset 20 - 23h: BASE—Base Address Register 10.1.12Offset 2Ch - 2Dh: SVID—Subsystem Vendor ID 10.1.14Offset 3Ch: INTR_LN—Interrupt Line Register 10.1.15Offset 3Dh: INTR_PN—Interrupt Pin Register 10.1.16Offset 60h: USB_RELNUM—USB Release Number Register 10.1.17Offset C0 - C1h: USB_LEGKEY—USB Legacy Keyboard/
11 USB EHCI Controller Registers
(D29:F7)485
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 21 Contents—Intel ® 6300ESB ICH
11.2.1.2 Offset 02 - 03h: HCIVERSION—Host Controller Interface Version
11.2.2.1 Offset CAPLENGTH + 00 - 03h: USB EHCI CMD—USB
11.2.2.2 Offset CAPLENGTH + 04 - 07h: USB EHCI STS—USB EHCI Status . 512
11.2.2.3 Offset CAPLENGTH + 08 - 0Bh: USB EHCI INTR—USB
11.2.2.5 Offset CAPLENGTH + 10 - 13h: CTRLDSSEGMENT—Control Data
11.2.2.6 Offset CAPLENGTH + 14 - 17h: PERIODICLISTBASE—Periodic Frame
11.2.2.7 Offset CAPLENGTH + 18 - 1Bh: ASYNCLISTADDR—Current
11.2.2.8 Offset CAPLENGTH + 40 - 43h: CONFIGFLAG—Configure Flag Register. 517
12 SMBUS Controller Registers
(D31:F3)527
12.1.3 Offset 04 - 05h: CMD—Command Register
12.1.4 Offset 06 - 07h: STA—Device Status Register
12.1.7 Offset 0Ah: SCC—Sub Class Code Register
12.1.8 Offset 0Bh: BCC—Base Class Code Register
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12.1.9 Offset 20 - 23h: SMB_BASE—SMBUS Base Address
12.1.10Offset 2Ch - 2Dh: SVID—Subsystem Vendor ID 12.1.12Offset 3Ch: INTR_LN—Interrupt Line Register 12.1.13Offset 3Dh: INTR_PN—Interrupt Pin Register 12.1.14Offset 40h: HOSTC—Host Configuration Register
13.1.3 Offset 04 - 05h: PCICMD—PCI Command Register
13.1.5 Offset 08h: RID—Revision Identification Register
13.1.6 Offset 09h: PI—Programming Interface Register
13.1.7 Offset 0Ah: SCC—Sub Class Code Register
13.1.8 Offset 0Bh: BCC—Base Class Code Register
13.1.10Offset 10 - 13h: NAMBAR—Native Audio 13.1.11Offset 14 - 17h: NABMBAR—Native Audio Bus Mastering 558
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 23 Contents—Intel ® 6300ESB ICH 13.1.15Offset 2E - 2Fh: SID—Subsystem ID Register 13.1.16Offset 34h: CAP_PTR—Capabilities Pointer 13.1.17Offset 3Ch: INTR_LN—Interrupt Line Register 13.1.18Offset 3Dh: INTR_PN—Interrupt Pin Register 13.1.19Offset 40h: PCID—Programmable Codec ID Register 13.1.21Offset 50h: PID—PCI Power Management Capability ID Register (Audio—D31:F5) 562 13.1.22Offset 52h: PC—Power Management Capabilities Register (Audio—D31:F5) .. 563 13.1.23Offset 54h: PCS—Power Management Control and Status Register (Audio— D31:F5)563
14.1.4 Offset 06 - 07h: PCISTA—Device Status Register
14.1.5 Offset 08h: RID—Revision Identification Register
14.1.6 Offset 09h: PI—Programming Interface Register
14.1.7 Offset 0Ah: SCC—Sub Class Code Register
14.1.8 Offset 0Bh: BCC—Base Class Code Register
14.1.10Offset 10 - 13h: MMBAR—Modem Mixer Base Address Register (Modem—D31:F6) 586 14.1.12Offset 2C - 2Dh: SVID—Subsystem Vendor ID 14.1.14Offset 34h: CAP_PTR—Capabilities Pointer 14.1.15Offset 3Ch: INTR_LN—Interrupt Line Register
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14.1.17Offset 50h: PID—PCI Power Management Capability ID Register (Modem— D31:F6)590 14.1.18Offset 52h: PC—Power Management Capabilities Register (Modem—D31:F6) 591 14.1.19Offset 54h: PCS—Power Management Control and Status Register (Modem— D31:F6)591
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17 APIC1 Configuration Registers
(D29:F5)631
17.1.1 Offset 00 - 03h: VID_DID—Vendor/ID Register
17.1.3 Offset 06 - 07h: APIC1STA—APIC1 Device Status
17.1.6 Offset 0C - 0Fh: HEADTYP—Header Type Register
17.1.7 Offset 2C - 2Fh: SS—APIC1 Subsystem Identifiers
17.1.8 Offset 34h: CAP_PTR—APIC1 Capabilities Pointer
17.1.11Offset 40 - 41h: ABAR—APIC1 Alternate Base Address Register (APIC1—D29:F5) 637 17.1.13Offset 50 - 51h: XID—PCI-X Identifiers Register 18.2.2 Prefetchable Memory Base and Limit Address Registers, Upper 32-Bit Registers.. 648
18.4.1 Type 0 Accesses to the Intel
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18.6.1.22Offset 40: CNF—Intel ® 6300ESB I/O Controller Hub Configuration.671 18.6.1.30Offset 5C: PX_DSTC - PCI-X Downstream Split Transaction Control 678 18.6.1.31Offset E0: ACNF – Additional Intel ® 6300ESB ICH Configuration....680
18.7.7.3 Target Termination Received by the Intel
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18.9.1 Behavior of Hub Interface Initiated Cycles to PCI/PCI-X
18.9.2 Behavior of Hub Interface Initiated Cycles to PCI-X Receiving Split Terminations. 696
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20 Serial ATA Controller Registers
(D31:F2)737
20.1.4 Offset 06 - 07h: STS—Device Status Register
20.1.9 Offset 10h - 13h: PCMD_BAR—Primary Command Block
20.1.10Offset 14h - 17h: PCNL_BAR—Primary Control Block Base 20.1.11Offset 18h - 1Bh: SCMD_BAR—Secondary Command Block 20.1.12Offset 14h - 17h: SCNL_BAR—Secondary Control Block 20.1.13Offset 20h - 23h: BAR—Legacy Bus Master Base Address 20.1.14Offset 2Ch - 2Dh: SVID—Subsystem Vendor ID 20.1.16Offset 34h: CAP—Capabilities Pointer Register 20.1.17Offset 3Ch: INTR_LN—Interrupt Line Register 20.1.18Offset 3Dh: INTR_PN—Interrupt Pin Register
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11 Intel
22 Intel
28 Intel
30 Intel
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25 Intel
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62 General Power States for Systems Using Intel
77 Intel
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137 Features Supported by Intel
143 Fixed I/O Ranges Decoded by Intel
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165 Offset 24h - 25h: PREF_MEM_BASE—Prefetchable Memory Base Register (HUB-PCI—D30:F0)
166 Offset 26h-27h: PREF_MEM_MLT—Prefetchable Memory Limit Register (HUB-PCI—D30:F0) ... 299 171 Offset 40 - 43h: HI_CMD—Hub Interface Command Control Register (HUB-PCI—D30:F0) .304 172 Offset 44 - 45h: DEVICE_HIDE—Secondary PCI Device Hiding Register (HUB-PCI—D30:F0) .. 305 173 Offset 50 - 51h: CNF—Intel® 6300ESB ICH Configuration Register (HUB-PCI—D30:F0) ...306 196 Offset PIRQA - 60h: PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control (LPC I/F—D31:F0) ..322 198 Offset PIRQE - 68h: PIRQ[n]_ROUT—PIRQ[E,F,G,H] Routing Control (LPC I/F—D31:F0)...324 206 Offset E0h: COM_DEC—LPC I/F Communication Port Decode Ranges (LPC I/F—D31:F0) ..332
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278 Offset C4h, C6h, C8h, CAh: MON[n]_TRP_RNG—I/O Monitor [4:7] Trap Range
279 Offset CCh: MON_TRP_MSK—I/O Monitor Trap Range Mask Register for Devices 4-7 (PM—
D31:F0)391
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332 Offset 10h - 13h: PCMD_BAR—Primary Command Block Base Address Register (IDE—D31:F1)
333 Offset 14h - 17h: PCNL_BAR—Primary Control Block Base Address Register (IDE—D31:F1) ... 442
334 Offset 18h - 1Bh: SCMD_BAR—Secondary Command Block Base Address Register (IDE
D31:F1)442 335 Offset 1Ch - 1Fh: SCNL_BAR—Secondary Control Block Base Address Register (IDE D31:F1) . 443
368 Offset C0 - C1h: USB_LEGKEY—USB Legacy Keyboard/ Mouse Control Register (USB—D29:F0/
F1)470
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416 Offset CAPLENGTH + 10 - 13h: CTRLDSSEGMENT—Control Data Structure Segment Register
417 Offset CAPLENGTH + 14 - 17h: PERIODICLISTBASE—Periodic Frame List Base Address ...516 418 Offset CAPLENGTH + 18 - 1Bh: ASYNCLISTADDR—Current Asynchronous List Address ....517
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 41 Contents—Intel ® 6300ESB ICH 469 Offset 10 - 13h: NAMBAR—Native Audio Mixer Base Address Register (Audio—D31:F5) ... 556
470 Offset 14 - 17h: NABMBAR—Native Audio Bus Mastering Base Address Register (Audio—
D31:F5)557
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619 Intel
623 Intel
628 Hub Interface Response to PCI-X Split Completion Terminations of Completion Required Cycles
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669 Offset 10h - 13h: PCMD_BAR—Primary Command Block Base Address Register (SATA–D31:F2)
670 Offset 14h - 17h: PCNL_BAR—Primary Control Block Base Address Register (SATA–D31:F2) .. 744
671 Offset 18h - 1Bh: SCMD_BAR—Secondary Command Block Base Address Register (IDE
D31:F1)745 672 Offset 14h - 17h: SCNL_BAR—Secondary Control Block Base Address Register (IDE D31:F1) . 745
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733 XOR Chain #1 (RTCRST# asserted for 4 PCI clocks
734 XOR Chain #2 (RTCRST# asserted for 5 PCI clocks
735 XOR Chain #3 (RTCRST# asserted for 6 PCI clocks
736 XOR Chain #4 (RTCRST# asserted for 7 PCI clocks
737 XOR Chain #5 (RTCRST# asserted for 59 PCI clocks
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Revision History
- Included Specification Changes from specification update, version 011 — Figure 61: Updated to replace V_CPU_IO with VccHI
- Included Specifications Clarifications from specification update, version 011 — Table 727 and Table 728: Updated t175, t176 & t184 timing definitions to clarify which Vcc supplies apply to each — Section 5.11.1 and 5.11.6: Clarified wording regarding support of C2 state for dual processors, dual core and processors with HyperThreading Technology. — Table 191: Remove incorrect references to TCO in Note — Section 5.7.1: Removed references to three wire APIC bus. 6300ESB does not support this feature. — Table 31: Moved Note 1 refernces from I/O to Memory cycles — Table 727: Changed Note 2 to require that 3.3V and 1.5V rails must power up or down together — Removed all references to Processor Speed Strapping. Processors used in conjunction with 6300ESB do not use this feature. — Table 319: Modified register defintions to reflect that signals are configured as native functions after a full reset. — Section 19.1: Add Note to indicate that SIUs are not completely 16550 compatible. — Table 635: Added % error rates. — Section 5.10.2.2: Changed to clarify where multiple processor or multiple core configurations can generate Stop Grant cycles in the MCH supports it.
- Included Documentation Changes 2 to 13 from specification update, version 011 — Table 568: Revised to allow bit column to align correctly. — Section 22.2: Added Case temperature under Bias value — Changed all references to PCIRST# to PXPCIRST# — Table 317: Changed register deult value to 00000000h — Figure 5: Correct typo in diagram — Table 28: Change GPIO[21] After Reset value to logic ‘1’ — Corrected Product Features section to show that PCI-X Rev 1.0 is supported — Table 22: Correct V5REF definition — Table 573: Correct indexes for Reserved Registers — Table 581: Revised naming and definitions for bits 10:8 and 7:0. Added Note at bottom of table. — Table 728: Revised ‘SLP_S5# inactive to SLP_S4#’ parameter timing values
- Table 313: Removed GPO_TTL register listing. This register was not relevant to 6300ESB
- Table 29, Figure 61 and Figure 62: Removed references to LAN_RST and RSM_PWROK signals which do not exist in 6300ESB
- Table 731, Figure 66: Updated to correct timing requirements for entering test mode.
- Section 5.7 and Section 8.5: Removed PCI register references for APIC0. APIC0 registers are purely memory mapped.
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A change bar to left of text, a table row or a figure heading indicates this item is either new or modified from the previous version of the document. December 2004 003
- Included changes from previous spec updates
- Updated Section 22.1
- Updated Section 22.2
- Updated DC Characteristics Section 22.3
- -Updated AC Characteristics Section 22.4 June 2004 002 • Clarified WDT Reload register bit details; listed USB HS reference voltage register bits. February 2004 001 • Initial release of this document. Date Revision Description
1.1 About This Document
Table 1. Industry Specifications
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This document contains these chapters: Chapter 1, “Introduction” introduces the Intel® 6300ESB ICH and provides information on manual organization. Chapter 3, “Signal Description” provides a detailed description of each Intel® 6300ESB ICH signal. Signals are arranged according to interface. Details are provided about the drive characteristics (Input/Output, Open Drain, etc.) of all signals. Chapter 2, “Intel® 6300ESB ICH and System Clock Domains” provides a list of each clock domain associated with the Intel ® 6300ESB ICH in an Intel® 6300ESB ICH-based system. Chapter 4, “Intel® 6300ESB ICH Power Planes and Pin States” provides a complete list of signals, their associated power well, their logic level in each suspend state, and their logic level before and after reset. Chapter 5, “Functional Description” provides a detailed description of the functions in the Intel ® 6300ESB ICH. All PCI buses, devices, and functions in this manual are abbreviated using the following nomenclature; Bus:Device:Function. This manual abbreviates buses as B0 and B1, devices as D8, D29, D30 and D31 and functions as F0, F1, F2, F3, F4, F5, F6 and F7. For example Device 31 Function 5 is abbreviated as D31:F5, Bus 1 Device 8 Function 0 is abbreviated as B1:D8:F0. Generally, the bus number will not be used, and may be considered to be Bus 0. Note that the Intel 6300ESB ICH’s external PCI bus is typically Bus 1, but may be assigned a different number depending upon system configuration. Chapter 6, “Register and Memory Mapping” provides an overview of the registers, fixed I/O ranges, variable I/O ranges, and memory ranges decoded by the Intel ® 6300ESB ICH. Chapter 7, “Hub Interface to PCI Bridge Registers (D30:F0)” provides a detailed description of all registers that reside in the Hub Interface to PCI bridge. This bridge resides at Device 30, Function 0 (D30:F0). Chapter 8, “LPC I/F Bridge Registers (D31:F0)” provides a detailed description of all registers that reside in the LPC bridge. This bridge resides at Device 31, Function 0 (D31:F0). This function contains registers for many different units within the Intel 6300ESB ICH including DMA, Timers, Interrupts, CPU Interface, GPIO, Power Management, System Management and RTC. Chapter 9, “IDE Controller Registers (D31:F1)” provides a detailed description of all registers that reside in the IDE controller. This controller resides at Device 31, Function 1 (D31:F1). Chapter 10, “USB UHCI Controllers Registers” provides a detailed description of all registers that reside in the three UHCI host controllers. These controllers reside at Device 29, Functions 0, 1 and 2 (D29:F0/F1/F2). Chapter 11, “USB EHCI Controller Registers (D29:F7)” provides a detailed description of all registers that reside in the EHCI host controller. This controller resides at Device 29, Function 7 (D29:F7). Chapter 12, “SMBUS Controller Registers (D31:F3)” provides a detailed description of all registers that reside in the SMBus controller. This controller resides at Device 31, Function 3 (D31:F3).
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 51 1—Intel ® 6300ESB ICH Chapter 13, “AC’97 Audio Controller Registers (D31:F5)” provides a detailed description of all registers that reside in the audio controller. This controller resides at Device 31, Function 5 (D31:F5). Note that this section of the EDS does not include the native audio mixer registers. Accesses to the mixer registers are forwarded over the AC-link to the codec where the registers reside. Chapter 14, “AC’97 Modem Controller Registers (D31:F6)” provides a detailed description of all registers that reside in the modem controller. This controller resides at Device 31, Function 6 (D31:F6). Note that this section of the EDS does not include the modem mixer registers. Accesses to the mixer registers are forwarded over the AC-link to the codec where the registers reside. Chapter 15, “Multimedia Timer Registers” provides a detailed description of all registers that reside in the multimedia event timer memory mapped register space. Chapter 16, “Watchdog Timer (WDT) (D29:F4)” provides a detailed description of the configuration registers in the WDT controller. These registers reside at Device 29, Function 4 (D29:F4). Chapter 17, “APIC1 Configuration Registers (D29:F5)” provides a detailed description of the configuration registers in the APIC1 controller. These registers reside at Device 29, Function 5 (D29:F5). Chapter 18, “PCI-X Overview (D28:F0)” provides a detailed description of the configuration registers of the PCI-X controller. These registers reside at Device 28, Function 0 (D28:F0). Chapter 19, “Serial I/O Unit” describes the SIU, its features, LPC interface, serial ports and Port 60/64 Emulation along with a description of the registers in the SIU. These registers reside at Device 31, Function 0 (D31:F0). Chapter 20, “Serial ATA Controller Registers (D31:F2)” provides a detailed description of the registers that reside in the SATA controller which encompasses a PCI device. This controller resides at Device 31, Function 2 (D31:F2). Chapter 21, “Package Information” provides ballout information, signal lists and mechanical drawings. Chapter 22, “Electrical Characteristics” provides AC and DC characteristics and AC timings. Chapter 23, “Testability” provides information on test modes and scan chains.
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clock generator component specification. Table 2. Intel ® 6300ESB ICH Clock Domains may be shut off using the CLKRUN# protocols. External Super I/O. Shut off in S3 or below.
48 MHz clock input is shut off (S1 for low power,
Always running, even in G3 state.
48 MHz
1.5 GHz clock generated internal to the Intel ®
6300ESB ICH for use by SATA phy.
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Figure 4. Conceptual System Clock Diagram
12.288 MHz
14.31818 MHz
functional groups according to their associated interface. signal is asserted when at the high voltage level.
3.1 Hub Interface to Host Controller
Table 3. Hub Interface Signals signals used to transmit and receive data through the Hub Interface. used to transmit and receive data through the Hub Interface.
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3.2 Firmware Hub Interface
voltage swing and impedance strength of Hub Interface pins.
- Refer to the platform design guide for expected voltages.
- Refer to the platform design guide for resistor values and routing
guidelines for each Hub Interface mode.
- The Hub Interface signals are all in a separate power plane, called the Hub Interface plane.
- During the S3, S4, and S5 states, power to the Hub Interface is assumed to be off. During S0
and S1 states, power to the Hub Interface must be on. Table 4. Firmware Hub Interface Signals Indicates the start of an LPC cycle, or an abort. NOTE: All LPC/FWH signals are in the core well.
3.3 PCI Interface
Table 5. PCI Interface Signals (Sheet 1 of 3) clock of a transaction, AD[31:0] contain the physical address (32 bits). After the first clock, AD[31:0] contain data. are used as Byte Enables. All command encoding not shown are reserved. the Intel® 6300ESB ICH’s role in the PCI cycle (target or initiator). by the Intel® 6300ESB ICH until driven as a target. read, it indicates the Intel® 6300ESB ICH is prepared to latch data.
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the Intel® 6300ESB ICH, as a Target, has placed valid data on AD[31:0]. ICH until driven as a target. STOP# causes the Intel® 6300ESB ICH to stop the current transaction. by the Intel® 6300ESB ICH as a slave. transaction, and when it is the Target of a read transaction. via PERR# signal) when serving as an initiator. REQ[0:3]# I PCI Requests: Supports up to 4 external masters on the PCI bus. GNT[0:3]# O PCI Grants: Supports up to 4 external masters on the PCI bus. Table 5. PCI Interface Signals (Sheet 2 of 3)
when PCI masters are granted the bus. Intel® 6300ESB ICH can be programmed to generate an NMI or SMI#. drive these signals due to internal sources. high (but it may be pulled up using the internal pull-up resistor). NOTE: PME# is also used in the PCI-X segment. Table 5. PCI Interface Signals (Sheet 3 of 3)
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3.4 PCI-X Interface
Table 6. PCI-X Interface Signals (Sheet 1 of 4) PXAD[31:0] during the address phase of all PCI-X Special Cycles. data bus. This bus provides an additional 32 bits to the PCI-X bus. 64-bit read data, when PXREQ64# and PXACK64# are both asserted. level through external resistors. phase of a transaction, PXC/BE#[3:0] define the bus command. During the data phase PXC/BE[3:0]# define the Byte Enables. ICH until driven by a Target device.
until driven by an Initiator. Intel® 6300ESB ICH until driven by an Initiator. completed when both PXTRDY# and PXIRDY# are sampled asserted. tri-stated by the Intel® 6300ESB ICH until driven by a target. Target and an input when the Intel® 6300ESB ICH is an Initiator. PXSTOP# is tri-stated from the leading edge of PXPCIRST#. PXSTOP# remains tri-stated until driven by the Intel ® 6300ESB ICH. that the Intel® 6300ESB ICH delays PAR by exactly one PXPCI clock. status bits, and has the option to generate an NMI# or SMI#. Table 6. PCI-X Interface Signals (Sheet 2 of 4)
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arbiter is an internal signal. should be used,PXREQ0, PXREQ1. PCI-X Grants: Supports up to 4 masters on the PCI-X bus. should be used: PXGNT0, PXGNT1. for the internal PCI-X logic. PXPCICLK I PCI-X Clock: PXPCICLK is the clock for the internal PCI-X circuitry. ® 6300ESB ICH and the PCI-X slots. is an active low signal that is a logical OR of all the RAS error events. minimum of 1 ms when initiated through the RC (CF9h) register. PXPLOCK# when it performs exclusive transactions on the PCI-X bus. PLOCK# is ignored when PCI-X masters are granted the bus. Table 6. PCI-X Interface Signals (Sheet 3 of 4)
that detects a system error condition except Intel ® 6300ESB ICH. will be pulled up to VccSus3_3 by an internal pull-up resistor. generate appropriate clock (33 or 66MHz) on the PCI-X Bus. asserted or when SBR bit is set. Table 6. PCI-X Interface Signals (Sheet 4 of 4)
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3.5 SATA Interface
3.6 IDE Interface
Table 7. SATA Interface Signals differential signals to Port 0. differential signals from Port 0. differential signals to Port 1. differential signals from Port 1. Table 8. IDE Interface Signals (Sheet 1 of 2) the corresponding signal on the primary or secondary IDE connector. corresponding signal on the primary or secondary IDE connector. either the ATA command block or control block is being addressed. function and are not associated with any AT compatible DMA channel. There is a weak internal pull-down resistor on these signals.
- The IDE signals are 5V tolerant.
- The IDE signals have integrated series terminating resistors.
- All signals may be tri-stated or driven low for mobile swap bays.
are not associated with any AT-compatible DMA channel. DMA acknowledge (PDDAK# or SDDAK#). SRDMARDY# to pause burst data transfers. acknowledge (PDDAK# or SDDAK#). 6300ESB ICH asserts this signal to terminate a burst. latches data on rising and falling edges of this signal from the disk. Table 8. IDE Interface Signals (Sheet 2 of 2)
- The IDE signals are 5V tolerant.
- The IDE signals have integrated series terminating resistors.
- All signals may be tri-stated or driven low for mobile swap bays.
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3.7 LPC I/F
3.8 Interrupt Interface
Table 9. LPC Interface Signals I/O LPC Frame: Indicates the start of an LPC cycle, or an abort. Super I/O chips, to request DMA or bus master access. Table 10. Interrupt Signals (Sheet 1 of 2) separate Route Control Register. This frees the legacy interrupts. These signals are 5V tolerant.
3.9 USB Interface
separate Route Control Register. These signals are 5 V tolerant. Secondary controller. These signals are 5 V tolerant. Table 11. USB Interface Signals USBRBIAS# as close to the resistor as possible. to USBRBIAS as close to the resistor as possible.
- The USB signals are all in the RESUME well.
- Since OC[3:0]# are in the 5 V tolerant resume well, the external biasing resistors are not
- All 4 ports support both USB1.0 and USB2.0 signaling.
Table 10. Interrupt Signals (Sheet 2 of 2)
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3.10 Power Management Interface
Table 12. Power Management Interface Signals (Sheet 1 of 2) buffer has the same characteristics as the FERR# input buffer. critical systems when in the S3 (Suspend To RAM) state. systems when in the S4 (Suspend to Disk) or S5 (Soft Off) state. S5 Sleep Control: Power plane control. low, the Intel® 6300ESB ICH asserts PXPCIRST#. power well and properly generate the PXPCIRST# output. event, and this is preserved across power failures. power is valid prior to RSMRST# going high. PWROK and RSMRST# which are in the RTC well.
3.11 CPU Interface
to indicate that the system will be entering a low power state soon. Suspend Clock: Output of the RTC generator circuit (32.768 KHz). 6300ESB ICH. Pull this input high to Vcc. Table 13. CPU Interface Signals (Sheet 1 of 2) active for all other sleep states. when the coprocessor error function is disabled. processor of pending interrupt events.
- The CPU I/F signals (except RCIN#, A20GATE, and FERR#) are on a separate power well. This
saves the external pull-up resistors that were needed on previous chipsets.
- RCIN# and A20GATE, and FERR# are on in the Core power well.
Table 12. Power Management Interface Signals (Sheet 2 of 2) PWROK and RSMRST# which are in the RTC well.
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Error Register is written, the IGNNE# signal is not asserted. serviced. It is an asynchronous output and normally driven low. response to one of many enabled hardware or software events. samples STPCLK# asserted, it responds by stopping its internal clock. since the processor has no corresponding input signal. transitions to the S1, S3, S4 and S5 states. needed with various other chipsets. Table 13. CPU Interface Signals (Sheet 2 of 2)
- The CPU I/F signals (except RCIN#, A20GATE, and FERR#) are on a separate power well. This
saves the external pull-up resistors that were needed on previous chipsets.
- RCIN# and A20GATE, and FERR# are on in the Core power well.
3.12 SMBus Interface
3.13 System Management Interface
3.14 Real Time Clock Interface
Table 14. SM Bus Interface Signals SMBDATA I/OD SMBus Data: External pull-up is required. SMBCLK I/OD SMBus Clock: External pull-up is required. #/ GPIO[11] I SMBus Alert: This signal is used to wake the system or generate SMI#. When not used for SMBALERT#, it may be used as a GPIO (GPIO[11]). NOTE: The SMBus I/F signals are all in the RESUME well. Table 15. System Management Interface Signals set to disable the system when box is detected open. Intruder switch is not needed. management ASIC or LAN Controller. External pull-ups are required. SMLINK[1] corresponds to a SMBus Data signal. NOTE: INTRUDER# is in the RTC well. The SMLINK signal is in the RESUME well. Table 16. Real Time Clock Interface external crystal is used, then RTCX2 should be left floating. Vbias I Bias Voltage for Oscillator: Sets the proper biasing for the oscillator.
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3.15 Other Clocks
3.16 Miscellaneous Signals
Table 17. Other Clocks configurations or S1 (or lower) states in mobile configurations. configurations or S1 (or lower) states in mobile configurations. configurations or S1 (or lower) states in mobile configurations. Table 18. Miscellaneous Signals system speaker. Upon PXPCIRST#, its output state is 0. strap. See Section 3.21.1, “Functional Straps” for more details. There is a weak integrated pull-down resistor on SPKR pin. well and sets the RTC_PWR_STS bit (bit 2 in GEN_PMCON3 register).
- Clearing CMOS in an Intel® 6300ESB ICH-based platform may be
- Unless entering the XOR Chain Test Mode, the RTCRST# input must
active low and remain in this state until a system reset or power cycle. This signal is muxed with GPIO[32].
3.17 AC’97 Link
3.18 Universal Asynchronous Receive and
Table 19. AC’97 Link Signals AC_RST# O AC’97 Reset: Master H/W reset to external Codec(s). AC_SYNC O AC’97 Sync: 48 KHz fixed rate sample sync to the Codec(s). external Codec(s). This signal has an integrated pull-down resistor3. AC_SDOUT O AC’97 Serial Data Out: Serial TDM data output to the Codec(s). Codec(s). Integrated pull-down resistors, which are always enabled.
- These signals are in the RESUME well, except AC_SYNC, AC_BIT_CLK, and AC_SDATA_OUT,
- See Section 4.2, “Integrated Pull-Ups and Pull-Downs” for details about when the integrated
pull-down resistors are enabled on AC_SYNC, AC_BIT_CLK, and AC_SDATA_OUT.
- An integrated pull-down resistor on AC_BIT_CLK is enabled when either:
Table 20. Universal Asynchronous Receive and Transmit (UART0, 1) (Sheet 1 of generation logic of each UART in the SIU. device pin to the receive port. pins will be set to MARKING condition (logic ‘1’ state). exchanged between the Intel® 6300ESB ICH and external interface. These pins have no effect on the transmitter. is generated when the Modem Status Interrupt is enabled.
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3.19 General Purpose I/O
based on GPIO configurations. ICH UARTS. These pins have no effect on the transmitter. Status Interrupt is enabled. that data carrier has been detected by the external agent. input has changed state since the previous reading of the MSR. generated when the Modem Status Interrupt is enabled. telephone ringing signal has been received by the external agent. the Modem Status Interrupt is enabled. holds this signal in its inactive state. signal in its inactive state. Table 20. Universal Asynchronous Receive and Transmit (UART0, 1) (Sheet 2 of
Table 21. General Purpose I/O Signals (Sheet 1 of 2) polarity in the General Purpose Event 0 Status Register. GPIO[9:10] I Reserved. These GPIO are not implemented. GPIO[12:13] I Fixed as Input only. Resume power well. GPIO[14:15] I Reserved. These GPIO are not implemented. GPIO[18] O Fixed as Output only. Main power well. GPIO[19] O Fixed as Output only. Main power well. GPIO[20] O Fixed as Output only. Main power well. GPIO[21] O Fixed as Output only. Main power well. GPIO[23] O Fixed as Output only. Main power well. GPIO[24] I/O May be input or output. Resume power well. Unmuxed. GPIO[25] I/O May be input or output. Resume power well. Unmuxed. GPIO[26] I/O Reserved. This GPIO is not implemented. GPIO[27:28] I/O May be input or output. Resume power well. Unmuxed. GPIO[29:31] O Reserved. These GPIO are not implemented. GPIO[37:39] I/O May be input or output. Core power well. GPIO[37,39] are unmuxed.
- GPIO[0:7], GPIO[16:21, 23], and GPIO[32:55] are in the core well.
- GPIO[8:15] and GPIO[24:31] are in the suspend well.
- Core-well GPIO are 5 V tolerant, except for GPIO[7:6] and [32:43].
- Resume-well GPIO are not 5 V tolerant.
- GPIO[56:57] pads are in the suspend well, the register bits are in the RTC well.
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3.20 Power and Ground
May be input or output. Core power well. GPIO[44:55] I/O Reserved. These GPIO are not implemented. GPIO[56:57] OD Output only. Resume and RTC power wells. Unmuxed. GPIO[58:63] I/O Reserved. These GPIO are not implemented. Table 22. Power and Ground Signals (Sheet 1 of 2) VCCHI 1.5 V supply for Hub Interface 1.5 logic. This power may be shut off in S3, S4, and S5 states. VCCA 1.5V supply for Hub Interface PLL. This power may be shut off in S3, S4, and S5 states. (Enhanced Hub Interface) Parallel Termination. This power is shut off in S3, S4, S5 and G3 states. shut off unless the system is unplugged in desktop configurations. unless the system is unplugged in desktop configurations. GPI, or using SAFEMODE strap. Table 21. General Purpose I/O Signals (Sheet 2 of 2)
- GPIO[0:7], GPIO[16:21, 23], and GPIO[32:55] are in the core well.
- GPIO[8:15] and GPIO[24:31] are in the suspend well.
- Core-well GPIO are 5 V tolerant, except for GPIO[7:6] and [32:43].
- Resume-well GPIO are not 5 V tolerant.
- GPIO[56:57] pads are in the suspend well, the register bits are in the RTC well.
3.21 Pin Straps
3.21.1 Functional Straps
an audible click due to the pull-up on the SPKR output. 0.8 to 1.75 V. The power will be shut in S3, S4, and S5 states. Table 22. Power and Ground Signals (Sheet 2 of 2) Table 23. Functional Strap Definitions D31: F0, Offset D5h, bit 5).
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3.22 Revision and Device ID Table
Table 24. Revision and Device ID Table of the Revision Identification Registers.
4.1 Power Planes
USAGE MODEL ASSUMPTION: The power planes and control are shown in Figure 5. Table 25. Intel ® 6300ESB I/O Controller Hub Power Planes S4, S5, or G3 state, this plane is assumed to be shut off. S4, S5, or G3 state, this plane is assumed to be shut off. by the trickle power supply when the system is in the S3, S4, S5, state. by the trickle power supply when the system is in the S3, S4, S5, state. plane is assumed to be shut off. diode coupling will provide power to reduce the drain on the RTC battery. Assumed to operate from 3.3 V down to 2.0 V.
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4.2 Integrated Pull-Ups and Pull-Downs
Figure 5. Power Plane Usage Model Table 26. Integrated Pull-Up and Pull-Down Resistors
- Simulation data shows that these resistor values may range from 10 K Ω to 40 KΩ.
- Simulation data shows that these resistor values may range from 9 K Ω to 50 KΩ.
- Simulation data shows that these resistor values may range from 15 K Ω to 35 KΩ
- Simulation data shows that these resistor values may range from 7.5 K Ω to 16 KΩ.
- Simulation data shows that these resistor values may range from 45 K Ω to 170 KΩ
- Simulation data shows that these resistor values may range from 5.7 K Ω to 28.3 KΩ.
- Simulation data shows that these resistor values may range from 14.25 K Ω to 24.8 KΩ
- The pull-up or pull-down on this signal is only enabled at boot/reset for strapping
4.3 IDE Integrated Series Termination
4.4 Output and I/O Signals Planes and States
“High” The Intel ® 6300ESB ICH is driving the signal to a logic ‘1’. “Low” The Intel ® 6300ESB ICH is driving the signal to a logic ‘0’.
- Simulation data shows that these resistor values may range from 10 K Ω to 40 KΩ.
- Simulation data shows that these resistor values may range from 9 K Ω to 50 KΩ.
- Simulation data shows that these resistor values may range from 15 K Ω to 35 KΩ
- Simulation data shows that these resistor values may range from 7.5 K Ω to 16 KΩ.
- Simulation data shows that these resistor values may range from 45 K Ω to 170 KΩ
- Simulation data shows that these resistor values may range from 5.7 K Ω to 28.3 KΩ.
- Simulation data shows that these resistor values may range from 14.25 K Ω to 24.8 KΩ
- The pull-up or pull-down on this signal is only enabled at boot/reset for strapping
Table 27. IDE Series Termination Resistors 33 Ω but may range from 31 Ω to 43 Ω.
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“Off” The power plane is off, so the Intel ® 6300ESB ICH is not driving. Note: The signal levels are the same in S4 and S5.
4.5 Power Planes for Input Signals
Table 28. Power Plane and States for Output and I/O Signal for Desktop
- The Intel® 6300ESB ICH sets these signals at reset for CPU frequency strap.
- The states of main I/O signals are taken at the times during PXPCIRST# and immediately after PXPCIRST#.
- The states of resume I/O signals are taken at the times during RSMRST# and immediately after RSMRST#
- GPIO[0:7], GPIO[16:21, 23], and GPIO[32:55] are in the core well.
- GPIO[8:15] and GPIO[24:31] are in the suspend well.
- Core-well GPIO are 5 V tolerant, except for GPIO[7:6] and [32:43].
- Resume-well GPIO are not 5 V tolerant.
- GPIO[56:57] pads are in the suspend well, the register bits are in the RTC well.
- PXIRQ[3:0] are input only, GPIO[36:33] are I/O in GPIO mode
10.PIRQ[H:E] are I/OD, GPIO[5:2] are input only.
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- The Intel® 6300ESB ICH sets these signals at reset for CPU frequency strap.
- The states of main I/O signals are taken at the times during PXPCIRST# and immediately after PXPCIRST#.
- The states of resume I/O signals are taken at the times during RSMRST# and immediately after RSMRST#
- GPIO[0:7], GPIO[16:21, 23], and GPIO[32:55] are in the core well.
- GPIO[8:15] and GPIO[24:31] are in the suspend well.
- Core-well GPIO are 5 V tolerant, except for GPIO[7:6] and [32:43].
- Resume-well GPIO are not 5 V tolerant.
- GPIO[56:57] pads are in the suspend well, the register bits are in the RTC well.
- PXIRQ[3:0] are input only, GPIO[36:33] are I/O in GPIO mode
10.PIRQ[H:E] are I/OD, GPIO[5:2] are input only.
- The Intel® 6300ESB ICH sets these signals at reset for CPU frequency strap.
- The states of main I/O signals are taken at the times during PXPCIRST# and immediately after PXPCIRST#.
- The states of resume I/O signals are taken at the times during RSMRST# and immediately after RSMRST#
- GPIO[0:7], GPIO[16:21, 23], and GPIO[32:55] are in the core well.
- GPIO[8:15] and GPIO[24:31] are in the suspend well.
- Core-well GPIO are 5 V tolerant, except for GPIO[7:6] and [32:43].
- Resume-well GPIO are not 5 V tolerant.
- GPIO[56:57] pads are in the suspend well, the register bits are in the RTC well.
- PXIRQ[3:0] are input only, GPIO[36:33] are I/O in GPIO mode
10.PIRQ[H:E] are I/OD, GPIO[5:2] are input only.
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- The Intel® 6300ESB ICH sets these signals at reset for CPU frequency strap.
- The states of main I/O signals are taken at the times during PXPCIRST# and immediately after PXPCIRST#.
- The states of resume I/O signals are taken at the times during RSMRST# and immediately after RSMRST#
- GPIO[0:7], GPIO[16:21, 23], and GPIO[32:55] are in the core well.
- GPIO[8:15] and GPIO[24:31] are in the suspend well.
- Core-well GPIO are 5 V tolerant, except for GPIO[7:6] and [32:43].
- Resume-well GPIO are not 5 V tolerant.
- GPIO[56:57] pads are in the suspend well, the register bits are in the RTC well.
- PXIRQ[3:0] are input only, GPIO[36:33] are I/O in GPIO mode
10.PIRQ[H:E] are I/OD, GPIO[5:2] are input only.
- The Intel® 6300ESB ICH sets these signals at reset for CPU frequency strap.
- The states of main I/O signals are taken at the times during PXPCIRST# and immediately after PXPCIRST#.
- The states of resume I/O signals are taken at the times during RSMRST# and immediately after RSMRST#
- GPIO[0:7], GPIO[16:21, 23], and GPIO[32:55] are in the core well.
- GPIO[8:15] and GPIO[24:31] are in the suspend well.
- Core-well GPIO are 5 V tolerant, except for GPIO[7:6] and [32:43].
- Resume-well GPIO are not 5 V tolerant.
- GPIO[56:57] pads are in the suspend well, the register bits are in the RTC well.
- PXIRQ[3:0] are input only, GPIO[36:33] are I/O in GPIO mode
10.PIRQ[H:E] are I/OD, GPIO[5:2] are input only.
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- The Intel® 6300ESB ICH sets these signals at reset for CPU frequency strap.
- The states of main I/O signals are taken at the times during PXPCIRST# and immediately after PXPCIRST#.
- The states of resume I/O signals are taken at the times during RSMRST# and immediately after RSMRST#
- GPIO[0:7], GPIO[16:21, 23], and GPIO[32:55] are in the core well.
- GPIO[8:15] and GPIO[24:31] are in the suspend well.
- Core-well GPIO are 5 V tolerant, except for GPIO[7:6] and [32:43].
- Resume-well GPIO are not 5 V tolerant.
- GPIO[56:57] pads are in the suspend well, the register bits are in the RTC well.
- PXIRQ[3:0] are input only, GPIO[36:33] are I/O in GPIO mode
10.PIRQ[H:E] are I/OD, GPIO[5:2] are input only.
- High
- Low
- Static: Will be high or low, but will not change
- Driven: Will be high or low, and is allowed to change
- Running: For input clocks GPIO[43:37] I/O Core None 0 0 until driven GPIO[57:56] OD RTC/ Suspend External pull up Driven (0 or 1) Driven (0 or 1) SIU Interface UART_CLK I Core None Input Only Input Only SIU0_RXD I Core None Input Only Input Only SIU1_RXD I/O Core Internal Pull-Up (15K - 35K) H H SIU0_TXD I/O Core None 1 1 SIU1_TXD I/O Core Internal Pull-Up (15K - 35K) H 1 SIU0_CTS# I Core None Input Only Input Only SIU1_CTS# I/O Core Internal Pull-Up (15K - 35K) H H SIU0_DSR# I Core None Input Only Input Only SIU1_DSR# I/O Core Internal Pull-Up (15K - 35K) H H SIU0_DCD# I Core None Input Only Input Only SIU1_DCD# I/O Core Internal Pull-Up (15K - 35K) H H SIU0_RI# I Core None Input Only Input Only SIU1_RI# I/O Core Internal Pull-Up (15K - 35K) H H SIU0_DTR# O Core Internal Pull-Up (15K - 35K) 1 1 SIU1_DTR# I/O Core Internal Pull-Up (15K - 35K) H 1 SIU0_RTS# O Core None 1 1 SIU1_RTS# I/O Core Internal Pull-Up (15K - 35K) H 1
- The Intel® 6300ESB ICH sets these signals at reset for CPU frequency strap.
- The states of main I/O signals are taken at the times during PXPCIRST# and immediately after PXPCIRST#.
- The states of resume I/O signals are taken at the times during RSMRST# and immediately after RSMRST#
- GPIO[0:7], GPIO[16:21, 23], and GPIO[32:55] are in the core well.
- GPIO[8:15] and GPIO[24:31] are in the suspend well.
- Core-well GPIO are 5 V tolerant, except for GPIO[7:6] and [32:43].
- Resume-well GPIO are not 5 V tolerant.
- GPIO[56:57] pads are in the suspend well, the register bits are in the RTC well.
- PXIRQ[3:0] are input only, GPIO[36:33] are I/O in GPIO mode
10.PIRQ[H:E] are I/OD, GPIO[5:2] are input only.
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Table 29. Power Plane for Input Signals for Desktop Configurations
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5.1 Hub Interface to PCI Bridge (D30:F0)
The Hub Interface to PCI Bridge resides in PCI Device 30, Function 0 on bus #0. This portion of the Intel® 6300ESB ICH implements the buffering and control logic between PCI and the Hub Interface. The arbitration for the PCI bus is handled by this PCI device. The PCI decoder in this device must decode the ranges for the Hub Interface. All register contents will be lost when core well power is removed.
5.1.1 PCI Bus Interface
The Intel® 6300ESB ICH PCI interface provides a 33 MHz, PCI Local Bus Specification, Rev. 2.2-compliant implementation. All PCI signals are 5 V tolerant. The Intel ® 6300ESB ICH integrates a PCI arbiter that supports up to four external PCI bus masters in addition to the internal Intel ® 6300ESB ICH requests. Most transactions targeted to the Intel ® 6300ESB ICH will first appear on the external PCI bus before being claimed back by the Intel ® 6300ESB ICH. The exceptions are I/O cycles involving USB, IDE, and AC’97. These transactions will complete over the Hub Interface without appearing on the external PCI bus. Configuration cycles targeting USB, IDE or AC’97 will appear on the PCI bus. When the Intel ® 6300ESB ICH is programmed for positive decode, the Intel ® 6300ESB ICH will claim the cycles appearing on the external PCI bus in medium decode time. When the Intel ® 6300ESB ICH is programmed for subtractive decode, the Intel ® 6300ESB ICH will claim these cycles in subtractive time. When the Intel ® 6300ESB ICH is programmed for subtractive decode, these cycles may be claimed by another positive decode agent out on PCI. This architecture enables the ability to boot off of a PCI card that positively decodes the boot cycles. In order to boot off a PCI card it is necessary to keep the Intel ® 6300ESB ICH in subtractive decode mode. When booting off a PCI card, the BOOT_STS bit (bit 2, TCO2 Status Register) will be set. When the processor issues a locked cycle to a resource that is too slow (e.g., PCI), the Intel® 6300ESB ICH will not allow upstream requests to be performed until the cycle completion. This may be critical for isochronous buses which assume certain timing for their data flow, such as AC’97 or USB. Devices on these buses may suffer from underrun when the asynchronous traffic is too heavy. Underrun means that the same data is sent over the bus while the Intel ® 6300ESB ICH is not able to issue a request for the next data. Snoop cycles are not permitted while the processor side bus is locked. Locked cycles are assumed to be rare. Locks by PCI targets are assumed to exist for a short duration (a few microseconds at most). When a system has a very large number of locked cycles and some that are very long, then the system will definitely experience underruns and overruns. The units most likely to have problems are the AC’97 controller and the USB controllers. Other units could get underruns/overruns, but are much less likely. The IDE controller (due to its stalling capability on the cable) should not get any underruns or overruns. Note: The Intel ® 6300ESB ICH’s AC’97, IDE and USB Controllers cannot perform peer-to-peer traffic. Note: Poor performing PCI devices that cause long latencies (numerous retries) to Processor- to-PCI Locked cycles may starve isochronous transfers between USB or AC’97 devices
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and memory. This will result in overrun or underrun, causing reduced quality of the isochronous data, such as audio. Note: PCI configuration write cycles, initiated by the processor, with the following characteristics will be converted to a Special Cycle with the Shutdown message type.
- Device Number (AD[15:11]) = ‘11111
- Function Number (AD[10:8]) = ‘111’
- Register Number (AD[7:2]) = ‘000000’
- Data = 00h
- Bus number matches secondary bus number
5.1.2 PCI-to-PCI Bridge Model
From a software perspective, the Intel ® 6300ESB ICH contains a PCI-to-PCI bridge. This bridge connects the Hub Interface to the PCI bus. By using the PCI-to-PCI bridge software model, the Intel® 6300ESB ICH may have its decode ranges programmed by existing plug-and-play software such that PCI ranges do not conflict with AGP and graphics aperture ranges in the Host controller.
5.1.3 IDSEL to Device Number Mapping
When addressing devices on the external PCI bus (with the PCI slots) the Intel ® 6300ESB ICH will assert one address signal as an IDSEL. When accessing device 0, the Intel® 6300ESB ICH will assert AD16. When accessing Device 1, the Intel ® 6300ESB ICH will assert AD17. This mapping continues all the way up to device 15 where the Intel® 6300ESB ICH asserts AD31. Note that the Intel ® 6300ESB ICH’s internal functions (AC’97, IDE, USB, and PCI Bridge) are enumerated like they are on a separate PCI bus (the Hub Interface) from the external PCI bus.
5.1.4 SERR# Functionality
There are several internal and external sources that may cause SERR#. The Intel ® 6300ESB ICH may be programmed to cause an NMI based on detecting that an SERR# condition has occurred. The NMI may also be routed to instead cause an SMI#. Note: Note that the Intel® 6300ESB ICH does not drive the external PCI bus SERR# signal active onto the PCI bus. The external SERR# signal is an input into the Intel® 6300ESB ICH driven only by external PCI devices. The conceptual logic diagrams in Figure 6 and Figure 7 illustrate all sources of SERR#, along with their respective enable and status bits. Figure 8 shows how the Intel® 6300ESB ICH error reporting logic is configured for NMI# generation.
Figure 6. Primary Device Status Register Error Reporting Logic
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Figure 7. Secondary Status Register Error Reporting Logic
5.1.5 Parity Error Detection
The Intel® 6300ESB ICH may detect and report different parity errors in the system. with their respective enable bits, status bits, and the results. device (PERR#) across the P2P bridge. NMI, since it considers the detection of a PCI error to be a catastrophic event. Figure 8. NMI# Generation Logic
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5.1.6 Standard PCI Bus Configuration Mechanism
ICH only supports Mechanism #1 as defined in the PCI specification. greater than 0 will be sent towards the Intel ® 6300ESB ICH from the host controller. configuration cycle is meant for Primary PCI or a downstream PCI bus.
5.1.6.1 Type 0 to Type 0 Forwarding
communicate the Intel® 6300ESB ICH device numbers in Type 0 configuration cycles.
5.1.6.2 Type 1 to Type 0 Conversion
- For device numbers 0 through 15, only one bit of the PCI address [31:16] will be
- The Intel ® 6300ESB ICH will always drive 0s on bits AD[15:11] when converting
Type 1 configurations cycles to Type 0 configuration cycles on PCI.
- Address bits [10:1] will also be passed unchanged to PCI.
- Address bit [0] will be changed to ‘0’.
Table 30. Type 0 Configuration Cycle Device Number Translation
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5.1.7 PCI Dual Address Cycle (DAC) Support
The Intel® 6300ESB ICH supports DAC format on PCI for cycles from PCI initiators to main memory. This allows PCI masters to generate an address up to 44 bits. The size of the actual supported memory space will be determined by the Memory Controller and the processor . The DAC mode is only supported for PCI adapters and USB EHCI, and is not supported for any of the internal PCI masters (IDE, USB UHCI, AC’97, 8237 DMA, etc.). When a PCI master wants to initiate a cycle with an address above 4G, it follows the following behavioral rules (See PCI Local Bus Specification, Revision 2.2, section 3.9 for more details): 1. On the first clock of the cycle (when FRAME# is first active), the peripheral uses the DAC encoding on the C/BE# signals. This unique encoding is: 1101. 2. Also during the first clock, the peripheral drives the AD[31:0] signals with the low address. 3. On the second clock, the peripheral drives AD[31:0] with the high address. The address is right justified: A[43:32] appear on AD[12:0]. The value of AD[31:13] is expected to be 0, however the Intel ® 6300ESB ICH will ignore these bits. C/BE# indicate the bus command type (Memory Read, Memory Write, etc.) 4. The rest of the cycle proceeds normally.
5.2 LPC Bridge (with System and Management
Functions) (D31:F0) The LPC Bridge function of the Intel ® 6300ESB ICH resides in PCI Device 31:Function 0. In addition to the LPC bridge function, D31:F0 contains other functional units including DMA, Interrupt Controllers, Timers, Power Management, System Management, GPIO, and RTC.
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5.2.1 LPC Cycle Types
5.2.1.1 Start Field Definition
Table 31. LPC Cycle Types Supported cycles into multiple 8-bit transfers. cycles into multiple 8-bit transfers.
- For memory cycles below 16M which do not target enabled FWH ranges, the Intel® 6300ESB
resistors would keep the bus high when no device responds.
- Bus Master Read or Write cycles must be naturally aligned. For example, a 1-byte transfer
Table 32. Start Field Bit Definitions 0000 Start of cycle for a generic target. 0010 Grant for bus master 0. 0011 Grant for bus master 1.
1101 Start of cycle for firmware memory read cycle
1110 Start of cycle for firmware memory write cycle
1111 Stop/Abort: End of a cycle for a target. NOTE: All other encodings are Reserved.
5.2.1.2 Cycle Type/Direction (CYCTYPE + DIR)
5.2.1.3 SIZE
Bits[3:2] are reserved. The Intel ® 6300ESB ICH will always drive them to 00.
5.2.1.4 SYNC
Table 33. Cycle Type Bit Definitions this value, the Intel® 6300ESB ICH will abort the cycle. Table 34. Transfer Size Bit Definition 6300ESB ICH may abort the transfer. Table 35. SYNC Bit Definition (Sheet 1 of 2) request deassertion and no more transfers desired for that channel. encoding (see next encoding below). NOTE: All other combinations are Reserved.
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5.2.1.5 SYNC Time-Out
5.2.1.6 SYNC Error Indication
communicating errors to aid higher layers with more robust error recovery. data had already been transferred. three bytes will not be transferred. transfers desired for that channel. Table 35. SYNC Bit Definition (Sheet 2 of 2) NOTE: All other combinations are Reserved. Table 36. Response to Sync Failures when the peripheral is not operating properly.
this the same as IOCHK# going active on the ISA bus.
5.2.1.7 LFRAME# Usage
ICH will drive LAD[3:0] with the proper START field. consecutive clocks. On the fourth clock, it will drive LAD[3:0] to ‘1111b’.
- Intel® 6300ESB ICH starts a Memory, I/O, or DMA cycle, but no device drives a valid SYNC after four consecutive clocks.
- Intel® 6300ESB ICH starts a Memory, I/O, or DMA cycle, and the peripheral drives an invalid SYNC pattern.
- A peripheral drives an illegal address when performing bus master cycles.
- A peripheral drives an invalid value.
Figure 9. Typical Timing for LFRAME# Figure 10. Abort Mechanism
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5.2.1.8 I/O Cycles
For I/O cycles targeting registers specified in the Intel® 6300ESB ICH’s decode ranges, the Intel® 6300ESB ICH performs I/O cycles as defined in the LPC spec. These will be 8-bit transfers. When the processor attempts a 16-bit or 32-bit transfer, the Intel ® 6300ESB ICH will break the cycle up into multiple 8-bit transfers to consecutive I/O addresses. Note: When the cycle is not claimed by any peripheral (and subsequently aborted), the Intel 6300ESB ICH will return a value of all ones (FFh) to the processor . This is to maintain compatibility with ISA I/O cycles where pull-up resistors would keep the bus high when no device responds.
5.2.1.9 Bus Master Cycles
The Intel® 6300ESB ICH supports Bus Master cycles and requests (using LDRQ#) as defined in the LPC specification. The Intel ® 6300ESB ICH has two LDRQ# inputs, and thus supports two separate bus master devices. It uses the associated START fields for Bus Master 0 (‘0010b’) or Bus Master 1 (‘0011b’). Note: The Intel ® 6300ESB ICH does not support LPC Bus Masters performing I/O cycles. LPC Bus Masters should only perform memory read or memory write cycles.
5.2.1.10 LPC Power Management
LPCPD# Protocol Same timings as for SUS_STAT#. Upon driving SUS_STAT# low, LPC peripherals will drive LDRQ# low or tri-state it. The Intel ® 6300ESB ICH will shut off the LDRQ# input buffers. After driving SUS_STAT# active, the Intel® 6300ESB ICH drives LFRAME# low, and tri-states (or drive low) LAD[3:0]. The Intel® 6300ESB ICH does not follow one part of the LPC spec that says “LRESET# is always asserted after LPCPD#”. The exception is the S1-M state. In that case, LPCPD# (SUSSTAT#) will go active, but LRESET# (PXPCIRST#) will not go active.
5.2.1.11 Configuration and Intel ® 6300ESB ICH Implications
In order to allow the I/O cycles and memory mapped cycles to go to the LPC I/F, the Intel® 6300ESB ICH includes several decoders. During configuration, the Intel ® 6300ESB ICH must be programmed with the same decode ranges as the peripheral. The decoders are programmed through the Device 31:Function 0 configuration space. Note: The Intel® 6300ESB ICH cannot accept PCI write cycles from PCI-to-PCI bridges or devices with similar characteristics (specifically those with a “Retry Read” feature which is enabled) to an LPC device when there is an outstanding LPC read cycle towards the same PCI device or bridge. These cycles are not part of normal system operation, but may be encountered as part of platform validation testing using custom test fixtures.
fields for a particular bus master. assign a particular BIOS range to a particular IDSEL field.
5.3 DMA Operation (D31:F0)
5.3.1 DMA Overview
The Intel® 6300ESB ICH supports LPC DMA through LPC, similar to ISA DMA. allow configuration of individual channels for use by LPC DMA. DMA service request by setting any bit in the DMA Channel Request Register to 1. hardwired to 16-bit, count-by-words (address shifted) transfers. following a DMA termination. Figure 11. Intel ® 6300ESB ICH DMA Controller
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5.3.2 Channel Priority
information in the DMA I/O Register ( Section 8.2, “DMA I/O Registers”).
5.3.2.1 Fixed Priority
The initial fixed priority structure is as described in Table 37.
5.3.2.2 Rotating Priority
last channel serviced is assigned the lowest priority in the channel group (0–3, 5–7). channel 7 in the priority list.
5.3.3 Address Compatibility Mode
address is 020000h and decrements, the next address will be 02FFFFh, not 01FFFFh. Table 37. Fixed Priority
5.3.4 Summary of DMA Transfer Sizes
5.3.4.1 Address Shifting When Programmed for 16-Bit I/O Count
address shifting is described in Table 39.
5.3.5 Autoinitialize
Table 38. DMA Transfer Size Table 39. Address Shifting in 16-bit I/O DMA Transfers NOTE: The least significant bit of the Page Register is dropped in 16-bit shifted mode.
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5.3.6 Software Commands
There are three additional special software commands that the DMA controller may execute. The three software commands are: 1. Clear Byte Pointer Flip-Flop 2. Master Clear 3. Clear Mask Register They do not depend on any specific bit pattern on the data bus.
5.3.6.1 Clear Byte Pointer Flip-Flop
This command is executed prior to writing or reading new address or word count information to/from the DMA controller. This initializes the flip-flop to a known state so that subsequent accesses to register contents by the microprocessor will address upper and lower bytes in the correct sequence. When the Host processor is reading or writing DMA registers, two Byte Pointer flip-flops are used; one for channels 0–3 and one for channels 4–7. Both of these act independently. There are separate software commands for clearing each of them (0Ch for channels 0–3, 0D8h for channels 4–7).
5.3.6.2 DMA Master Clear
This software instruction has the same effect as the hardware reset. The Command, Status, Request, and Internal First/Last Flip-Flop Registers are cleared and the Mask Register is set. The DMA controller will enter the idle cycle. There are two independent master clear commands; 0Dh which acts on channels 0–3, and 0DAh which acts on channels 4–7.
5.3.6.3 Clear Mask Register
This command clears the mask bits of all four channels, enabling them to accept DMA requests. I/O port 00Eh is used for channels 0–3 and I/O port 0DCh is used for channels 4–7.
5.4 LPC DMA
DMA on LPC is handled through the use of the LDRQ# lines from peripherals and special encodings on LAD[3:0] from the host. Single, Demand, Verify, and Increment modes are supported on the LPC interface. Channels 0 – 3 are 8 bit channels. Channels 5 – 7 are 16-bit channels. Channel 4 is reserved as a generic bus master request.
5.4.1 Asserting DMA Requests
Peripherals that need DMA service encode their requested channel number on the LDRQ# signal. To simplify the protocol, each peripheral on the LPC I/F has its own dedicated LDRQ# signal (they may not be shared between two separate peripherals). The Intel ® 6300ESB ICH has two LDRQ# inputs, allowing at least two devices to support DMA or bus mastering.
- Peripheral starts the sequence by asserting LDRQ# low (start bit). LDRQ# is high during idle conditions.
- The next 3 bits contain the encoded DMA channel number (MSB first).
- The next bit (ACT) indicates whether the request for the indicated DMA channel is active or inactive. The ACT bit will be a 1 (high) to indicate when it is active and 0 (low) when it is inactive. The case where ACT is low will be rare, and is only used to indicate that a previous request for that channel is being abandoned.
- After the active/inactive indication, the LDRQ# signal must go high for at least 1 clock. After that one clock, LDRQ# signal may be brought low to the next encoding sequence. When another DMA channel also needs to request a transfer, another sequence may be sent on LDRQ#. For example, if an encoded request is sent for channel 2, and then channel 3 needs a transfer before the cycle for channel 2 is run on the interface, the peripheral may send the encoded request for channel 3. This allows multiple DMA agents behind an I/O device to request use of the LPC interface, and the I/O device does not need to self-arbitrate before sending the message.
5.4.2 Abandoning DMA Requests
needs to be removed prior to a data transfer. has overrun or underrun its FIFO, or software stopping a device prematurely. ® 6300ESB ICH and the peripheral. Figure 12. DMA Request Assertion Through LDRQ#
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5.4.3 General Flow of DMA Transfers
Arbitration for DMA channels is performed through the 8237 within the host. Once the host has won arbitration on behalf of a DMA channel assigned to LPC, it asserts LFRAME# on the LPC I/F and begins the DMA transfer. The general flow for a basic DMA transfer is as follows: 1. The Intel ® 6300ESB ICH starts transfer by asserting ‘0000b’ on LAD[3:0] with LFRAME# asserted. 2. The Intel ® 6300ESB ICH asserts ‘cycle type’ of DMA, direction based on DMA transfer direction. 3. The Intel ® 6300ESB ICH asserts channel number and, when applicable, terminal count. 4. The Intel ® 6300ESB ICH indicates the size of the transfer: 8 or 16 bits. 5. When a DMA read… —T h e I n t e l® 6300ESB ICH drives the first 8 bits of data and turns the bus around. — The peripheral acknowledges the data with a valid SYNC. — When a 16 bit transfer, the process is repeated for the next 8 bits. 6. When a DMA write… —T h e I n t e l® 6300ESB ICH turns the bus around and waits for data. — The peripheral indicates data ready through SYNC and transfers the first byte. — When a 16 bit transfer, the peripheral indicates data ready and transfers the next byte. 7. The peripheral turns around the bus.
5.4.4 Terminal Count (TC)
Terminal count is communicated through LAD[3] on the same clock that DMA channel is communicated on LAD[2:0]. This field is the CHANNEL field. Terminal count indicates the last byte of transfer, based upon the size of the transfer. For example, on an eight bit transfer size (SIZE field is ‘00b’), when the TC bit is set, this is the last byte. On a 16 bit transfer (SIZE field is ‘01b’), when the TC bit is set, the second byte is the last byte. The peripheral, therefore, must internalize the TC bit when the CHANNEL field is communicated, and only signal TC when the last byte of that transfer size has been transferred.
5.4.5 Verify Mode
Verify mode is supported on the LPC interface. A verify transfer to the peripheral is similar to a DMA write, where the peripheral is transferring data to main memory. The indication from the host is the same as a DMA write, so the peripheral will be driving data onto the LPC interface. However, the host will not transfer this data into main memory.
5.4.6 DMA Request Deassertion
An end of transfer is communicated to the Intel® 6300ESB ICH through a special SYNC field transmitted by the peripheral. An LPC device must not attempt to signal the end of a transfer by deasserting LDREQ#. When a DMA transfer is several bytes, such as a transfer from a demand mode device, the Intel ® 6300ESB ICH needs to know when to deassert the DMA request based on the data currently being transferred.
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 109 5—Intel ® 6300ESB ICH The DMA agent uses a SYNC encoding on each byte of data being transferred, which indicates to the Intel® 6300ESB ICH whether this is the last byte of transfer or when more bytes are requested. To indicate the last byte of transfer, the peripheral uses a SYNC value of ‘0000b’ (ready with no error), or ‘1010b’ (ready with error). These encodings tell the Intel® 6300ESB ICH that this is the last piece of data transferred on a DMA read (Intel® 6300ESB ICH to peripheral), or the byte which follows is the last piece of data transferred on a DMA write (peripheral to the Intel ® 6300ESB ICH). When the Intel® 6300ESB ICH sees one of these two encodings, it ends the DMA transfer after this byte and deasserts the DMA request to the 8237. Therefore, when the Intel ® 6300ESB ICH indicated a 16 bit transfer, the peripheral may end the transfer after one byte by indicating a SYNC value of ‘0000b’ or ‘1010b’. The Intel® 6300ESB ICH will not attempt to transfer the second byte, and will deassert the DMA request internally. This also holds true for any byte in a 32 bit transfer. This allows the peripheral, therefore, to terminate a DMA burst. When the peripheral indicates a ‘0000b’ or ‘1010b’ SYNC pattern on the last byte of the indicated size, then the Intel ® 6300ESB ICH will only deassert the DMA request to the 8237 since it does not need to end the transfer. When the peripheral wishes to keep the DMA request active, it uses a SYNC value of ‘1001b’ (ready plus more data). This tells the 8237 that more data bytes are requested after the current byte has been transferred, so the Intel ® 6300ESB ICH will keep the DMA request active to the 8237. Therefore, on an 8-bit transfer size, when the peripheral indicates a SYNC value of ‘1001b’ to the Intel ® 6300ESB ICH, the data will be transferred and the DMA request will remain active to the 8237. At a later time, the Intel® 6300ESB ICH will then come back with another START–CYCTYPE–CHANNEL–SIZE etc. combination to initiate another transfer to the peripheral. The peripheral must not assume that the next START indication from the Intel ® 6300ESB ICH is another grant to the peripheral when it had indicated a SYNC value of ‘1001b’. On a single mode DMA device, the 8237 will rearbitrate after every transfer . Only demand mode DMA devices may be ensured that they will receive the next START indication from the Intel ® 6300ESB ICH. Note: Indicating a ‘0000b’ or ‘1010b’ encoding on the SYNC field of an odd byte of a 16 bit channel (first byte of a 16 bit transfer) is an error condition. Note: The host will stop the transfer on the LPC bus as indicated, fill the upper byte with random data on DMA writes (peripheral to memory), and indicate to the 8237 that the DMA transfer occurred, incrementing the 8237’s address and decrementing its byte count.
5.4.7 SYNC Field/LDRQ# Rules
Since DMA transfers on LPC are requested through an LDRQ# assertion message, and are ended through a SYNC field during the DMA transfer, the peripheral must obey the following rule when initiating back-to-back transfers from a DMA channel. The peripheral must not assert another message for eight LCLKs after a deassertion is indicated through the SYNC field. This is needed to allow the 8237, which typically runs off a much slower internal clock, to see a message deasserted before it is re-asserted so that it may arbitrate to the next agent. Under default operation, the host will only perform 8-bit transfers on 8-bit channels and 16-bit transfers on 16 bit channels. The method by which this communication between host and peripheral through system BIOS is performed is beyond the scope of this specification. Since the LPC host and LPC peripheral are motherboard devices, no “plug-n-play” registry is required.
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The peripheral must not assume that the host will be able to perform transfer sizes that are larger than the size allowed for the DMA channel, and be willing to accept a SIZE field that is smaller than what it may currently have buffered. To that end, it is recommended that future devices which may appear on the LPC bus, which require higher bandwidth than 8-bit or 16-bit DMA allow, do so with a bus mastering interface and not rely on the 8237. 5.5 8254 Timers (D31:F0) The Intel® 6300ESB ICH contains three counters which have fixed uses. All registers and functions associated with the 8254 timers are in the core well. The 8254 unit is clocked by a 14.31818 MHz clock. The 14.31818 MHz clock will stop during the S3-S5 and G3 states.
5.5.1 Counter 0, System Timer
This counter functions as the system timer by controlling the state of IRQ0 and is typically programmed for Mode 3 operation. The counter produces a square wave with a period equal to the product of the counter period (838 ns) and the initial count value. The counter loads the initial count value one counter period after software writes the count value to the counter I/O address. The counter initially asserts IRQ0 and decrements the count value by two each counter period. The counter negates IRQ0 when the count value reaches zero. It then reloads the initial count value and again decrements the initial count value by two each counter period. The counter then asserts IRQ0 when the count value reaches zero, reloads the initial count value, and repeats the cycle, alternately asserting and negating IRQ0.
5.5.2 Counter 1, Refresh Request Signal
Prior to ICH1, typically in ISA platforms, this counter provided the refresh request signal. Today, it is still typically programmed for Mode 2 operation and only impacts the period of the REF_TOGGLE bit in Port 61. The initial count value is loaded one counter period after being written to the counter I/O address. The REF_TOGGLE bit will have a square wave behavior (alternate between 0 and 1) and will toggle at a rate based on the value in the counter. Programming the counter to anything other than Mode 2 will result in undefined behavior for the REF_TOGGLE bit. See Section 8.7.1, “NMI_SC—NMI Status and Control Register” (D31:F0:61h:bit 4) for REF_TOGGLE bit details.
5.5.3 Counter 2, Speaker Tone
This counter provides the speaker tone and is typically programmed for Mode 3 operation. The counter provides a speaker frequency equal to the counter clock frequency (1.193 MHz) divided by the initial count value. The speaker must be enabled by a write to port 061h (see Section 8.7.1, “NMI_SC—NMI Status and Control Register” for more information).
5.5.4 Timer Programming
The counter/timers are programmed in the following fashion:
- Write a control word to select a counter .
- Write an initial count for that counter.
- Load the least and/or most significant bytes (as required by Control Word bits 5, 4)
of the 16-bit counter. See Section 8.3, “Timer I/O Registers” for more information.
- Repeat with other counters.
each counter, the control word must be written before the initial count is written. definitions. The new count must follow the programmed count format. be loaded with an incorrect count. The Control Word Register at port 43h controls the operation of all three counters.
- Control Word Command. Specifies which counter to read or write, the operating mode, and the count format (binary or BCD).
- Counter Latch Command. Latches the current count so that it may be read by the system. The countdown process continues.
- Read Back Command. Reads the count value, programmed mode, the current state of the OUT pins, and the state of the Null Count Flag of the selected counter. Table 40 lists the six operating modes for the interval counters.
5.5.5 Reading from the Interval Timer
counter Latch command, and the Read-Back command. Each is explained below. Table 40. Counter Operating Modes
0 Out signal on end of count (=0)
to ‘1’ for one clock period.
2 Rate generator (divide by n
time, then back to ‘1’ and counter is reloaded. expires for one clock period. expires for one clock period.
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With the simple read and counter latch command methods, the count must be read according to the programmed format; specifically, when the counter is programmed for two byte counts, two bytes must be read. The two bytes do not have to be read one right after the other. Read, write, or programming operations for other counters may be inserted between them.
5.5.5.1 Simple Read
The first method is to perform a simple read operation. The counter is selected through port 40h (counter 0), 41h (counter 1), or 42h (counter 2). Note: Performing a direct read from the counter will not return a determinate value, because the counting process is asynchronous to read operations. However, in the case of counter 2, the count may be stopped by writing to the GATE bit in port 61h.
5.5.5.2 Counter Latch Command
The Counter Latch Command, written to port 43h, latches the count of a specific counter at the time the command is received. This command is used to ensure that the count read from the counter is accurate, particularly when reading a two-byte count. The count value is then read from each counter's Count Register as was programmed by the Control Register. The count is held in the latch until it is read or the counter is reprogrammed. The count is then unlatched. This allows reading the contents of the counters on the fly without affecting counting in progress. Multiple Counter Latch Commands may be used to latch more than one counter. Counter Latch commands do not affect the programmed mode of the counter in any way. When a Counter is latched and then, some time later , latched again before the count is read, the second Counter Latch command is ignored. The count read will be the count at the time the first Counter Latch command was issued.
5.5.5.3 Read Back Command
The Read Back command may be used to latch multiple counter outputs at one time. counter without reading the count, all but the first are ignored. reading the status, all but the first are ignored. functionally the same as issuing two consecutive, separate Read Back commands. counters without any intervening reads, all but the first are ignored. type counts, return the latched count. Subsequent reads return unlatched count. how the cores are connected. Table 41. Interrupt Controller Core Connections (Sheet 1 of 2)
0 Internal Internal Timer / Counter 0 output / MMT #0
1 Keyboard IRQ1 via SERIRQ
2 Internal Slave Controller INTR output
3 Serial Port A IRQ3 via SERIRQ, PIRQx
4 Serial Port B IRQ4 via SERIRQ, PIRQx
5 Parallel Port / Generic IRQ5 via SERIRQ, PIRQx
6 Floppy Disk IRQ6 via SERIRQ PIRQx,
7 Parallel Port / Generic IRQ7 via SERIRQ PIRQx,
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IRQ12 or IRQ1 (see bit 11 and bit 12 in General Control Register , D31:F0, offset D0h).
5.6.1 Interrupt Handling
5.6.1.1 Generating Interrupts
status of any other pending interrupts. Table 42 defines the IRR, ISR and IMR.
0 Internal Real Time
1 Generic IRQ9 via SERIRQ, SCI or TCO, PIRQx, Boot
2 Generic IRQ10 via SERIRQ, SCI, or TCO, PIRQx
3 Generic IRQ11 via SERIRQ, SCI, or TCO, PIRQx,
4 PS/2 Mouse IRQ12 via SERIR, SCI, or TCO, PIRQx
5 Internal
Not Supported via SERIRQ” for more information.
7 Secondary IDE Cable IRQ15 from input signal (secondary IDE in legacy
Table 41. Interrupt Controller Core Connections (Sheet 2 of 2) Table 42. Interrupt Status Registers not the interrupt is masked. However, a masked interrupt will not generate INTR. IMR Interrupt Mask Register. This bit determines whether an interrupt is masked. Masked interrupts will not generate INTR.
5.6.1.2 Acknowledging Interrupts
translates this command into two internal INTA# pulses expected by the 8259 cores. representing the interrupt within that controller.
5.6.1.3 Hardware/Software Interrupt Sequence
- One or more of the Interrupt Request lines (IRQ) are raised high in edge mode, or
seen high in level mode, setting the corresponding IRR bit.
- The PIC sends INTR active to the processor when an asserted interrupt is not
- The processor acknowledges the INTR and responds with an interrupt acknowledge
bridge. This command is broadcast over PCI by the Intel ® 6300ESB ICH.
- Upon observing its own interrupt acknowledge cycle on PCI, the Intel ® 6300ESB
cascaded interrupt controllers.
- Upon receiving the first internally generated INTA# pulse, the highest priority ISR
- Upon receiving the second internally generated INTA# pulse, the PIC returns the
short in duration, the PIC will return vector 7 from the master controller .
- This completes the interrupt cycle. In AEOI mode the ISR bit is reset at the end of
EOI command is issued at the end of the interrupt subroutine.
5.6.2 Initialization Command Words (ICWx)
their acronyms: ICW1, ICW2, ICW3, and ICW4. Table 43. Content of Interrupt Vector Byte
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The base address for each 8259 initialization command word is a fixed location in the I/ O memory space: 20h for the master controller, and A0h for the slave controller.
5.6.2.1 ICW1
An I/O write to the master or slave controller base address with data bit 4 equal to 1 is interpreted as a write to ICW1. Upon sensing this write, the Intel ® 6300ESB ICH PIC expects three more byte writes to 21h for the master controller, or A1h for the slave controller, to complete the ICW sequence. A write to ICW1 starts the initialization sequence during which the following automatically occur: 1. Following initialization, an interrupt request (IRQ) input must make a low-to-high transition to generate an interrupt. 2. The Interrupt Mask Register is cleared. 3. IRQ7 input is assigned priority 7. 4. The slave mode address is set to 7. 5. Special mask mode is cleared and Status Read is set to IRR.
5.6.2.2 ICW2
The second write in the sequence, ICW2, is programmed to provide bits [7:3] of the interrupt vector that will be released during an interrupt acknowledge. A different base is selected for each interrupt controller.
5.6.2.3 ICW3
The third write in the sequence, ICW3, has a different meaning for each controller.
- For the master controller, ICW3 is used to indicate which IRQ input line is used to cascade the slave controller . Within the Intel® 6300ESB ICH, IRQ2 is used. Therefore, bit 2 of ICW3 on the master controller is set to a 1, and the other bits are set to 0s.
- For the slave controller, ICW3 is the slave identification code used during an interrupt acknowledge cycle. On interrupt acknowledge cycles, the master controller broadcasts a code to the slave controller when the cascaded interrupt won arbitration on the master controller. The slave controller compares this identification code to the value stored in its ICW3, and when it matches, the slave controller assumes responsibility for broadcasting the interrupt vector.
5.6.2.4 ICW4
The final write in the sequence, ICW4, must be programmed both controllers. At the very least, bit 0 must be set to one to indicate that the controllers are operating in an Intel® Architecture-based system.
5.6.3 Operation Command Words (OCW)
These command words reprogram the Interrupt Controller to operate in various interrupt modes.
- OCW1 masks and unmasks interrupt lines.
- OCW2 controls the rotation of interrupt priorities when in rotating priority mode, and controls the EOI function.
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- OCW3 is sets up ISR/IRR reads, enables/disables the special mask mode (SMM), and enables/disables polled interrupt mode.
5.6.4 Modes of Operation
5.6.4.1 Fully Nested Mode
In this mode, interrupt requests are ordered in priority from zero through seven, with zero being the highest. When an interrupt is acknowledged, the highest priority request is determined and its vector placed on the bus. Additionally, the ISR for the interrupt is set. This ISR bit remains set until: the processor issues an EOI command immediately before returning from the service routine; or when in AEOI mode, on the trailing edge of the second INTA#. While the ISR bit is set, all further interrupts of the same or lower priority are inhibited, while higher levels will generate another interrupt. Interrupt priorities may be changed in the rotating priority mode.
5.6.4.2 Special Fully-Nested Mode
This mode will be used in the case of a system where cascading is used, and the priority has to be conserved within each slave. In this case, the special fully-nested mode will be programmed to the master controller. This mode is similar to the fully- nested mode with the following exceptions:
- When an interrupt request from a certain slave is in service, this slave is not locked out from the master's priority logic and further interrupt requests from higher priority interrupts within the slave will be recognized by the master and will initiate interrupts to the processor . In the normal-nested mode, a slave is masked out when its request is in service.
- When exiting the Interrupt Service routine, software has to check whether the interrupt serviced was the only one from that slave. This is done by sending a Non- Specific EOI command to the slave and then reading its ISR. When it is zero, a non- specific EOI may also be sent to the master.
5.6.4.3 Automatic Rotation Mode (Equal Priority Devices)
In some applications, there are a number of interrupting devices of equal priority. Automatic rotation mode provides for a sequential 8-way rotation. In this mode, a device receives the lowest priority after being serviced. In the worst case, a device requesting an interrupt will have to wait until each of seven other devices are serviced at most once. There are two ways to accomplish automatic rotation using OCW2; the Rotation on Non-Specific EOI Command (R=1, SL=0, EOI=1) and the rotate in automatic EOI mode which is set by (R=1, SL=0, EOI=0).
5.6.4.4 Specific Rotation Mode (Specific Priority)
Software may change interrupt priorities by programming the bottom priority. For example, when IRQ5 is programmed as the bottom priority device, IRQ6 will be the highest priority device. The Set Priority Command is issued in OCW2 to accomplish this, where: R=1, SL=1, and LO-L2 is the binary priority level code of the bottom priority device.
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In this mode, internal status is updated by software control during OCW2. However, it is independent of the EOI command. Priority changes may be executed during an EOI command by using the Rotate on Specific EOI Command in OCW2 (R=1, SL=1, EOI=1 and LO-L2=IRQ level to receive bottom priority.
5.6.4.5 Poll Mode
Poll mode may be used to conserve space in the interrupt vector table. Multiple interrupts that may be serviced by one interrupt service routine do not need separate vectors when the service routine uses the poll command. Poll mode may also be used to expand the number of interrupts. The polling interrupt service routine may call the appropriate service routine, instead of providing the interrupt vectors in the vector table. In this mode, the INTR output is not used and the microprocessor internal Interrupt Enable flip-flop is reset, disabling its interrupt input. Service to devices is achieved by software using a Poll command. The Poll command is issued by setting P=1 in OCW3. The PIC treats its next I/O read as an interrupt acknowledge, sets the appropriate ISR bit when there is a request, and reads the priority level. Interrupts are frozen from the OCW3 write to the I/O read. The byte returned during the I/O read will contain a ‘1’ in bit 7 when there is an interrupt, and the binary code of the highest priority level in bits 2:0.
5.6.4.6 Cascade Mode
The PIC in the Intel® 6300ESB ICH has one master 8259 and one slave 8259 cascaded onto the master through IRQ2. This configuration may handle up to 15 separate priority levels. The master controls the slaves through a three bit internal bus. In the Intel ® 6300ESB ICH, when the master drives 010b on this bus, the slave controller takes responsibility for returning the interrupt vector. An EOI command must be issued twice: once for the master and once for the slave.
5.6.4.7 Edge and Level Triggered Mode
In ISA systems this mode is programmed using bit 3 in ICW1, which sets level or edge for the entire controller. In the Intel ® 6300ESB ICH, this bit is disabled and a new register for edge and level triggered mode selection, per interrupt input, is included. This is the Edge/Level control Registers ELCR1 and ELCR2. When an ELCR bit is ‘0’, an interrupt request will be recognized by a low to high transition on the corresponding IRQ input. The IRQ input may remain high without generating another interrupt. When an ELCR bit is ‘1’, an interrupt request will be recognized by a high level on the corresponding IRQ input and there is no need for an edge detection. The interrupt request must be removed before the EOI command is issued to prevent a second interrupt from occurring. In both the edge and level triggered modes, the IRQ inputs must remain active until after the falling edge of the first internal INTA#. When the IRQ input goes inactive before this time, a default IRQ7 vector will be returned.
5.6.4.8 End of Interrupt Operations
An EOI may occur in one of two fashions: by a command word write issued to the PIC before returning from a service routine, the EOI command; or automatically when AEOI bit in ICW4 is set to one.
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5.6.4.9 Normal End of Interrupt
In Normal EOI, software writes an EOI command before leaving the interrupt service routine to mark the interrupt as completed. There are two forms of EOI commands: Specific and Non-Specific. When a Non-Specific EOI command is issued, the PIC will clear the highest ISR bit of those that are set to one. Non-Specific EOI is the normal mode of operation of the PIC within the Intel ® 6300ESB ICH, as the interrupt being serviced currently is the interrupt entered with the interrupt acknowledge. When the PIC is operated in modes which preserve the fully nested structure, software may determine which ISR bit to clear by issuing a Specific EOI. An ISR bit that is masked will not be cleared by a Non-Specific EOI when the PIC is in the special mask mode. An EOI command must be issued for both the master and slave controller.
5.6.4.10 Automatic End of Interrupt Mode
In this mode, the PIC will automatically perform a Non-Specific EOI operation at the trailing edge of the last interrupt acknowledge pulse. From a system standpoint, this mode should be used only when a nested multi-level interrupt structure is not required within a single PIC. The AEOI mode may only be used in the master controller and not the slave controller.
5.6.5 Masking Interrupts
5.6.5.1 Masking on an Individual Interrupt Request
Each interrupt request may be masked individually by the Interrupt Mask Register (IMR). This register is programmed through OCW1. Each bit in the IMR masks one interrupt channel. Masking IRQ2 on the master controller will mask all requests for service from the slave controller.
5.6.5.2 Special Mask Mode
Some applications may require an interrupt service routine to dynamically alter the system priority structure during its execution under software control. For example, the routine may wish to inhibit lower priority requests for a portion of its execution but enable some of them for another portion. The special mask mode enables all interrupts not masked by a bit set in the Mask Register. Normally, when an interrupt service routine acknowledges an interrupt without issuing an EOI to clear the ISR bit, the interrupt controller inhibits all lower priority requests. In the special mask mode, any interrupts may be selectively enabled by loading the Mask Register with the appropriate pattern. The special mask mode is set by OCW3 where: SSMM=1, SMM=1, and cleared where SSMM=1, SMM=0.
5.6.6 Steering PCI Interrupts
The Intel® 6300ESB ICH may be programmed to allow PIRQA#-PIRQH# to be internally routed to interrupts 3-7, 9-12, 14 or 15. The assignment is programmable through the PIRQx Route Control registers, located at 60-63h and 68-6Bh in function 0. One or more PIRQx# lines may be routed to the same IRQx input. When interrupt steering is not required, the Route Registers may be programmed to disable steering. The PIRQx# lines are defined as active low, level sensitive to allow multiple interrupts on a PCI Board to share a single line across the connector. When a PIRQx# is routed to specified IRQ line, software must change the IRQ's corresponding ELCR bit to level
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active low non-ISA interrupts may share their interrupt with PCI interrupts. other external sources, and routes it accordingly.
5.6.7 Special Handling of IRQ1 and IRQ12
keyboard controller that the interrupt has been serviced. 6300ESB ICH is not necessarily responding to the cycle. Figure 13. Port 60 Read Clearing IRQ1 AND IRQ12 Latch
60 Data
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5.7 Advanced Interrupt Controller (APIC)
(D29:F5) There are two APICs in the Intel® 6300ESB ICH: APIC0 and APIC1 (device 29, function 5). APIC0’s direct registers are assigned with base address FEC0xxxxH; however, only primary (legacy) PCI devices can write to these registers. APIC1’s direct register are assigned with base address FEC1xxxxH. To support legacy devices/drivers on the PCI-X segment used with the Intel ICHx, APIC1 has an alternate base address FEC0xxxxH. This means devices on the PCI-X segment can only write to the IRQ Pin Assertion Register (either FEC0_0020H or FEC1_0020H) to generate an interrupt from APIC1. APIC1 writes to addresses FEC1_0020 to FEC1_0027 are claimed by APIC1 from PCI-X. Devices on the primary PCI Bus can write to IRQ Pin Assertion Register FEC0_0020H to generate an APIC0 interrupt. Devices/drivers on the PCI-X segment have write access only to the APIC1 IRQ Pin Assertion Register. Devices/drivers on the PCI segment can access only APIC0 registers. Since the Intel ® 6300ESB ICH does not implement Hub Interface EOI special cycles, the MCH will translate EOI special cycle to a memory write cycle to EOI register at address FEC0_0040H and passes it to the Intel® 6300ESB ICH. This memory write cycle will be passed to both APIC0 and APIC1 internally. From the CPU/MCH point of view, it should always use address FEC0xxxxH to access APIC0 registers and address FEC1xxxxH to access APIC1 registers. APIC1 will not respond to CPU/MCU’s access to address FEC0xxxxH, other than the EOI cycle stated above.
5.7.1 Interrupt Handling
The I/O APIC handles interrupts very differently than the 8259. Briefly, these differences are:
- Method of Interrupt Transmission. Interrupts are handled without the need for the processor to run an interrupt acknowledge cycle. The Intel® 6300ESB ICH only supports FSB delivery of interrupts.
- Interrupt Priority. The priority of interrupts in the I/O APIC is independent of the interrupt number. For example, interrupt 10 may be given a higher priority than interrupt 3.
- More Interrupts. The I/O APIC in the Intel® 6300ESB ICH supports a total of 24 interrupts.
- Multiple Interrupt Controllers. The I/O APIC interrupt transmission protocol has an arbitration phase, which allows for multiple I/O APICs in the system with their own interrupt vectors. The Intel ® 6300ESB ICH I/O APIC must arbitrate for the APIC bus before transmitting its interrupt message.
5.7.2 SMI/NMI/INIT/ExtINT Delivery Modes
These delivery modes are not supported by the Intel® 6300ESB ICH for the following reasons: NMI/INIT: This signal has issues with delivery under power management. It cannot be delivered while the processor is in the Stop Grant state. In addition, this is a break event for power management. Breaking on the APIC bus message is more difficult than breaking on the pin. SMI: On the 82093, the I/O APIC could deliver the SMI through the pin SMIOUT# or as an APIC bus message. When the message was masked by the OS, then the SMIOUT# will be used. In other words, there is no way to block the delivery of the SMI#, except through BIOS. Adding this interrupt to the I/O APIC only increases validation time.
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5.7.3 Boot Interrupt
The Intel® 6300ESB ICH’s APIC1 contains a capability to logically OR several of its interrupt inputs together to generate a single interrupt through PIC. This is necessary for systems that do not support the APIC, and for boot. The generated interrupt is routed to IRQ 9. This interrupt is generated when the following conditions met:
- Boot interrupt is enabled in configuration register.
- Any of PXIRQ[3:0] or internal interrupt source is asserted.
- Boot interrupts are not MASKed in redirection table. (Refer to Bit 16 in the Redirection Table)
- IRQ9 of PIC is enabled with bit 6 set to 0 of the ETR1- Extended Features Register, D:31:F0:offset F4h,bit 6 or PIRQG# is assigned to an enabled IRQx of the PIC with ETR1 bit 6 set to 1. See Section 8.1.37, “Offset F4: ETR1—PCI-X Extended Features Register (LPC I/F—D31:F0)” for more information. To support this function, all internal interrupt sources to APIC1 are level trigger, active low signals immediately after reset.
5.7.4 Interrupt Mapping
from external device. Each interrupt has its own unique vector assigned by software. The interrupt vectors are mapped as follows. Table 44. Interrupt Mapping in Non-APIC
0 No No 8254 Counter 0, MMT#0
2 No No 8259 #2 cascade only
8 No No RTC, MMT#1
9 Yes No Option for PIRQx, SCI, TCO, boot interrupt
10 Yes No Option for PIRQx, SCI, TCO
11 Yes No Option for PIRQx, SCI, TCO, MMT #2
12 Yes No Option for PIRQx
13 No No FERR# Logic
14 Yes Yes 3 PIRQx, Storage (IDE/SATA) Primary (legacy mode)
15 Yes Yes 3 PIRQx, Storage (IDE/SATA) Secondary (legacy
- If an interrupt is used for Boot interrupt, PCI IRQ[A:H], SCI, or TCO, it should not be used for
ISA-style interrupts (via SERIRQ or IRQ14/15 pins). IRQ9 will be default to boot interrupt.
- In non-APIC mode, the PCI interrupts are mapped to IRQ3, 4, 5, 6, 7, 9, 10, 11, 12, 14, or
- IRQ 14 and 15 can only be driven directly from the pins when in Legacy IDE mode.
- If IRQ11 is used for MMT #2, software should ensure IRQ 11 is not shared with any other
- SW: Boot interrupt may optionally be routed to PIRQG# output for programmable PIRQx#
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5.7.5 APIC Bus Functional Description
Table 45. APIC Interrupt Mapping, APIC0 Agent
0 No No No Cascade from 8259 #1
1 Yes No No 2
2 No No No 8254 Counter 0, MMT #0 (legacy mode)
3 Yes No No
4 Yes No No 2
5 Yes No No 2
6 Yes No No 2
7 Yes No No 2
9 Yes No No
2 Option for SCI, TCO
10 Yes No No 2 Option for SCI, TCO
11 Yes No No 2 Option for SCI, TCO, MMT #2
12 Yes No No 2
13 No No No FERR# logic
14 Yes Yes
1 No2 Storage (IDE/SATA) Primary (legacy mode)
15 Yes Yes 1 No2 Storage (IDE/SATA) Secondary (legacy mode)
16 PIRQ[A]# PIRQ[A]# No USB1 UHCI Controller #1
17 PIRQ[B]# PIRQ[B]# No AC’97 Audio, Modem, option for SMbus
18 PIRQ[C]# PIRQ[C]# No Storage (IDE/SATA) native mode
20 N/A PIRQ[E]# No 2 Option for SCI, TCO, MMT #0,1,2
21 N/A PIRQ[F]# No 2 Option for SCI, TCO, MMT #0,1,2
22 N/A PIRQ[G]# No 2 Option for SCI, TCO, MMT #0,1,2
- IRQ 14 and 15 may only be driven directly from the pins when in Legacy IDE mode.
- NO from external devices, YES of access from processor
- In APIC mode, the PCI interrupts A:H are mapped to IRQ[16:23].
- When an interrupt is used for PCI IRQ[A:H], SCI, or TCO, it should not be used for ISA-style
- When programming the polarity of internal interrupt sources on the APIC, interrupts 0
- When IRQ11 is used for MMT #2, software should ensure IRQ 11 is not shared with any other
- PCI Message interrupts are not prevented by hardware in these cases. However, the system
5.7.5.1 APIC Bus Arbitration
acceptance error was reported for that message. agents requesting the bus with normal priorities will back off. Table 46. APIC Interrupt Mapping, APIC1 Agent
10 No No Yes WDT
11 No No Yes
12 No No Yes
13 No No Yes
14 No No Yes
15 No No Yes
16 No No Yes
17 No No Yes
18 No No Yes
19 No No Yes
20 No No Yes
21 No No Yes
22 No No Yes
23 No No Yes
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arbitration and will stop driving the APIC bus. will stop driving the APIC bus. Table 47 describes the arbitration cycles.
5.7.5.2 Bus Message Formats
message. APIC messages come in four formats, determined by the Delivery Mode bits. Table 47. Arbitration Cycles
1 EOI 0 Bit 1 = 1: Normal, Bit 1 = 0: EOI
a different value than it sent, it lost arbitration. Table 48. APIC Message Formats
Table 49. EOI Message
10 NOT(C1) NOT(C0) Check Sum from Cycles 6 - 9
12 NOT(A) NOT(A) Status Cycle 0
13 NOT(A1) NOT(A1) Status Cycle 1
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message. All short messages take 21 cycles including the idle cycle. Table 50. Short Message
6 NOT(DM) NOT(M2) DM1 = Destination Mode from bit 11 of the redirection
8 NOT(L) NOT(TM) L = Level, TM = Trigger Mode
10 NOT(V5) NOT(V4)
11 NOT(V3) NOT(V2)
12 NOT(V1) NOT(V0)
13 NOT(D7) NOT(D6)
14 NOT(D5) NOT(D4)
15 NOT(D3) NOT(D2)
16 NOT(D1) NOT(D0)
17 NOT(C1) NOT(C0) Checksum for Cycles 6 - 16 2
19 NOT(A) NOT(A) Status Cycle 0. See Table 51. 20 NOT(A1) NOT(A1) Status Cycle 1. See Table 51.
- When DM is 0 (physical mode), cycles 15 and 16 are the APIC ID and cycles 13 and 14 are
sent as ‘1’. When DM is 1 (logical mode), cycles 13 through 16 are the 8-bit Destination field. use physical destination mode and a destination field containing APIC ID value of all ones.
- The checksum field is the cumulative add (mod 4) of all data bits (DM, M0-3, L, TM, V0-7,D0-
bits of an adder at the end of the message.
- This cycle allows all APICs to perform various internal computations based on the information
Table 51. APIC Bus Status Cycle Definition
11 Checksum OK 1x Error
01 Accepted
00 Retry
10 Error xx
01 Error xx
00 Checksum Error xx
00 Error
11 Checksum OK: No Focus
01 End and Retry
00 Go for Low Priority Arbitration
01 Checksum OK: Focus
11 Checksum OK xx
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Table 52. Lowest Priority Message (Without Focus Processor)
17 NOT(C1) NOT(C0) Checksum for Cycles 6 - 16
19 NOT(A) NOT(A) Status Cycle 0. 20 NOT(A1) NOT(A1) Status Cycle 1.
21 P7 1
22 P6 1
23 P5 1
24 P4 1
25 P3 1
26 P2 1
27 P1 1
28 P0 1
29 ArbID3 1
30 ArbID2 1
31 ArbID1 1
32 ArbID0 1
33 S S Status
- Cycle 21 through 28 are used to arbitrate for the lowest priority processor. The processor that
have “free interrupt slots” will participate in the lowest priority arbitration.
- Cycles 29 through 32 are used to break tie in case two more processors have lowest priority.
The bus arbitration ID's are used to break the tie.
this cycle. The message format is same as short message for the first 21 cycles. Table 53. Remote Read Message (Sheet 1 of 2)
6 NOT(DM) NOT(M2) DM = Destination Mode from bit 11 of the redirection table
19 NOT(A) NOT(A) Status Cycle 0. 20 NOT(A1) NOT(A1) Status Cycle 1.
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5.7.6 PCI Message-Based Interrupts
5.7.6.1 Theory of Operation
devices are given a write path directly to a register that will cause the desired interrupt. send the interrupt message to the processor using the I/O APIC’s serial bus.
- During PCI PnP, the PCI peripheral is first programmed with an address
- To cause the interrupt, the PCI peripheral requests the PCI bus and when granted,
- The MESSAGE_DATA will be a 32-bit value, although only the lower 5 bits
- When the PRQ bit in the APIC Version Register is set, the Intel ® 6300ESB ICH
positively decodes the cycles (as a slave) in Medium time.
- The Intel ® 6300ESB ICH decodes the binary value written to MESSAGE_ADDRESS
- After sending the interrupt message to the processor, the Intel ® 6300ESB ICH will
automatically clear the interrupt.
37 S S Data Status: 00 = valid, 11 = invalid
38 C C Check Sum for data d31-d00
respond should not cause the debugger to hang. Table 53. Remote Read Message (Sheet 2 of 2)
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 133 5—Intel ® 6300ESB ICH Since they are edge triggered, the interrupts that are allocated to the PCI bus for this scheme may not be shared with any other interrupt (such as the standard PCI PIRQ[A:D], those received via SERIRQ#, or the internal level-triggered interrupts such as SCI or TCO). The Intel ® 6300ESB ICH will ignore interrupt messages sent by PCI masters that attempt to use IRQ0, 2, 8, or 13.
5.7.6.2 Registers and Bits Associated with PCI Interrupt Delivery
The capability to support PCI interrupt delivery will be indicated through ACPI configuration techniques. This involves the BIOS creating a data structure that gets reported to the ACPI configuration software. The OS reads the PRQ bit in the APIC Version Register to see when the Intel ® 6300ESB ICH is capable of supporting PCI- based interrupt messages. Interrupt Message Register The PCI devices will all write their message into the IRQ Pin Assertion Register, which is a memory-Mapped register located at the APIC base memory location + 20h.
5.7.7 Processor System Bus Interrupt Delivery
5.7.7.1 Theory of Operation
For processors that support Processor System Bus interrupt delivery, the Intel ® 6300ESB ICH has an option to let the integrated I/O APIC behave as an I/O (x) APIC. In this case, it will deliver interrupt messages to the processor in a parallel manner, rather than using the I/O APIC serial scheme. The Intel ® 6300ESB ICH is intended to be compatible with the I/O (x) APIC specification, Rev 1.1 This is done by the Intel® 6300ESB ICH writing (through the Hub Interface) to a memory location that is snooped by the processor(s). The processor(s) snoop the cycle to know which interrupt goes active. The processor enables the mode by setting the I/O APIC Enable (APIC_EN) bit and by setting the DT bit in the I/O APIC ID register . The following sequence is used: 1. When the Intel ® 6300ESB ICH detects an interrupt event (active edge for edge- triggered mode or a change for level-triggered mode), it sets or resets the internal IRR bit associated with that interrupt. 2. Internally, the Intel ® 6300ESB ICH requests to use the bus in a way that automatically flushes upstream buffers. This may be internally implemented similar to a DMA device request. 3. The Intel ® 6300ESB ICH then delivers the message by performing a write cycle to the appropriate address with the appropriate data. The address and data formats are described below in Section 5.7.7.5, “Interrupt Message Format”. Note: PSB Interrupt Delivery compatibility with processor clock control depends on the processor, not the Intel® 6300ESB ICH.
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5.7.7.2 Edge-Triggered Operation
5.7.7.3 Level-Triggered Operation
is sent to indicate that the interrupt is still active.
5.7.7.4 Registers Associated with Processor System Bus Interrupt
that gets reported to the ACPI configuration software. ignored when the APIC mode is not enabled.
5.7.7.5 Interrupt Message Format
Table 54. Interrupt Message Address Format (Sheet 1 of 2) for the interrupt associated with this message. Table entry for the interrupt associated with this message.
5.8 Serial Interrupt (D31:F0)
- S - Sample Phase. Signal driven low
- R - Recovery Phase. Signal driven high Redirection Hint: This bit is used by the processor host bridge to allow the interrupt message to be redirected. 0 = The message will be delivered to the agent (processor) listed in bits 19:12. 1 = The message will be delivered to an agent with a lower interrupt priority. This may be derived from bits 10:8 in the Data Field (see below). The Redirection Hint bit will be a 1 when bits 10:8 in the delivery mode field associated with corresponding interrupt are encoded as 001 (Lowest Priority). Otherwise, the Redirection Hint bit will be 0. Destination Mode: This bit is used only the Redirection Hint bit is set to 1. When the Redirection Hint bit and the Destination Mode bit are both set to 1, then the logical destination mode is used, and the redirection is limited only to those processors that are part of the logical group as based on the logical ID. 1:0 Will always be 00.
Table 55. Interrupt Message Data Format Redirection Table for that interrupt. Delivery Status: 1 = Assert, 0 = Deassert. When using level-triggered interrupts, this bi t indicates the state of the interrupt input. O Redirection Table for that interrupt. Table 54. Interrupt Message Address Format (Sheet 2 of 2)
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- T - Turn-around Phase. Signal released The Intel® 6300ESB ICH supports a message for 21 serial interrupts. These represent the 15 ISA interrupts (IRQ0-1, 2-15), the four PCI interrupts, and the control signals SMI# and IOCHK#. The serial IRQ protocol does not support the additional APIC interrupts (20-23). Serial interrupt information is transferred using three types of frames:
- Start Frame: SERIRQ line driven low by the Intel ® 6300ESB ICH to indicate the start of IRQ transmission
- Data Frames: IRQ information transmitted by peripherals. The Intel ® 6300ESB ICH will support 21 data frames.
- Stop Frame: SERIRQ line driven low by the Intel® 6300ESB ICH to indicate end of transmission and next mode of operation. Note: When the IDE primary and secondary controllers are configured for native IDE mode, the only way to use the internal IRQ14 and IRQ15 connections to the Interrupt Controllers is through the Serial Interrupt pin.
5.8.1 Start Frame
The serial IRQ protocol has two modes of operation which affect the start frame. These two modes are: Continuous, where the Intel ® 6300ESB ICH is solely responsible for generating the start frame; and Quiet, where a serial IRQ peripheral is responsible for beginning the start frame. The mode that must first be entered when enabling the serial IRQ protocol is continuous mode. In this mode, the Intel ® 6300ESB ICH will assert the start frame. This start frame is 4, 6, or 8 PCI clocks wide based upon the Serial IRQ Control Register, bits 1:0 at 64h in Device 31:Function 0 configuration space. This is a polling mode. When the serial IRQ stream enters quiet mode (signaled in the Stop Frame), the SERIRQ line remains inactive and pulled up between the Stop and Start Frame until a peripheral drives the SERIRQ signal low. The Intel ® 6300ESB ICH senses the line low and continues to drive it low for the remainder of the Start Frame. Since the first PCI clock of the start frame was driven by the peripheral in this mode, the Intel ® 6300ESB ICH will drive the SERIRQ line low for 1 PCI clock less than in continuous mode. This mode of operation allows for a quiet, and therefore lower power, operation.
5.8.2 Data Frames
Once the Start frame has been initiated, all of the SERIRQ peripherals must start counting frames based on the rising edge of SERIRQ. Each of the IRQ/DATA frames has exactly 3 phases of 1 clock each:
- Sample Phase. During this phase, the SERIRQ device drives SERIRQ low when the corresponding interrupt signal is low. When the corresponding interrupt is high, the SERIRQ devices will tri-state the SERIRQ signal. The SERIRQ line will remain high due to pull-up resistors (there is no internal pull-up resistor on this signal, an external pull-up resistor is required). A low level during the IRQ0-1 and IRQ2-15 frames indicates that an active-high ISA interrupt is not being requested, but a low level during the PCI INT[A:D], SMI#, and IOCHK# frame indicates that an active- low interrupt is being requested.
- Recovery Phase. During this phase, the device will drive the SERIRQ line high when in the Sample Phase it was driven low. When it was not driven in the sample phase, it will be tri-stated in this phase.
- Turn-around Phase. The device will tri-state the SERIRQ line.
5.8.3 Stop Frame
5.8.4 Specific Interrupts Not Supported via SERIRQ
- IRQ0. Heartbeat interrupt generated off of the internal 8254 counter 0.
- IRQ8#. RTC interrupt may only be generated internally.
- IRQ13. Floating point error interrupt generated off of the processor assertion of FERR#. The Intel® 6300ESB ICH will ignore the state of these interrupts in the serial stream, and will not adjust their level based on the level seen in the serial stream. In addition, the interrupts IRQ14 and IRQ15 from the serial stream are treated differently than their ISA counterparts. These two frames are not passed to the Bus Master IDE logic. The Bus Master IDE logic expects IDE to be behind the Intel ® 6300ESB ICH.
5.8.5 Data Frame Format
SERIRQ signal (they are shared). Table 56. Stop Frame Explanation Table 57. Data Frame Format (Sheet 1 of 2)
2 IRQ1 5 Before Port 60h latch
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5.9 Real Time Clock (D31:F0)
5.9.1 RTC Overview
Table 290 for more information. locations. Any RAM writes under the same conditions will be ignored.
10 IRQ9 29
11 IRQ10 32
12 IRQ11 35
13 IRQ12 38 Before Port 60h latch
14 IRQ13 41 Ignored. IRQ13 may only be generated from FERR#. 15 IRQ14 44 Do not include in BM IDE interrupt logic. 16 IRQ15 47 Do not include in BM IDE interrupt logic. 17 IOCHCK# 50 Same as ISA IOCHCK# going active.
18 PCI INTA# 53 Drive PIRQA#
19 PCI INTB# 56 Drive PIRQB#
20 PCI INTC# 59 Drive PIRQC#
21 PCI INTD# 62 Drive PIRQD#
NOTE: SIU_SERIRQ Period 13 is used to transfer IRQ12. Table 57. Data Frame Format (Sheet 2 of 2)
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 139 5—Intel ® 6300ESB ICH Note: The Intel® 6300ESB ICH supports the ab ility to generate an SMI# based on a century rollover. See Section 5.9.1.4, “Century Rollover” for more information on the century rollover. Note: The Intel® 6300ESB ICH does not implement month/year alarms.
5.9.1.1 Update Cycles
An update cycle occurs once a second, when the SET bit of register B is not asserted and the divide chain is properly configured. During this procedure, the stored time and date will be incremented, overflow will be checked, a matching alarm condition will be checked, and the time and date will be rewritten to the RAM locations. The update cycle will start at least 488 µs after the UIP bit of register A is asserted, and the entire cycle will not take more than 1984 µs to complete. The time and date RAM locations (0-9) will be disconnected from the external bus during this time. To avoid update and data corruption conditions, external RAM access to these locations may safely occur at two times. When an updated-ended interrupt is detected, almost 999 ms is available to read and write the valid time and date. When the UIP bit of Register A is detected to be low, there is at least 488 µs before the update cycle begins. Warning:The overflow conditions for leap years and daylight savings adjustments are based on more than one date or time item. To ensure proper operation when adjusting the time, the new time and data values should be set at least two seconds before one of these conditions (leap year, daylight savings time adjustments) occurs.
5.9.1.2 Interrupts
The real-time clock interrupt is internally routed within the Intel® 6300ESB ICH both to the I/O APIC and the 8259. It is mapped to interrupt vector 8. This interrupt does not leave the Intel® 6300ESB ICH, nor is it shared with any other interrupt. IRQ8# from the SERIRQ stream is ignored.
5.9.1.3 Lockable RAM Ranges
The RTC’s battery-backed RAM supports two 8-byte ranges that may be locked through the configuration space. When the locking bits are set, the corresponding range in the RAM will not be readable or writable. A write cycle to those locations will have no effect. A read cycle to those locations will return an undefined value. Once a range is locked, the range may be unlocked only by a hard reset, which will invoke the BIOS and allow it to relock the RAM range.
5.9.1.4 Century Rollover
The Intel® 6300ESB ICH will detect a rollover when the Year byte (RTC I/O space, index offset 09h) transitions form 99 to 00. Upon detecting the rollover , the Intel® 6300ESB ICH will set the NEWCENTURY_STS bit (TCOBASE + 04h, bit 7). When the system is in an S0 state, this will cause an SMI#. The SMI# handler may update registers in the RTC RAM that are associated with century value. When the system is in a sleep state (S1-S5) when the century rollover occurs, the Intel ® 6300ESB ICH will also set the NEWCENTURY_STS bit, but no SMI# is generated. When the system resumes from the sleep state, BIOS should check the NEWCENTURY_STS bit and update the century value in the RTC RAM.
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5.9.1.5 Clearing Battery-Backed RTC RAM
attempt to clear CMOS by using a jumper to pull VccRTC low. and those configuration bits in the RTC power well will be set to their default state. state when RTCRST# is asserted. setting of this GPI on system boot-up, and manually clear the CMOS array. A jumper on AC_SDOUT (SAFEMODE strap) may also be used to clear CMOS values. on system boot-up, and manually clear the CMOS array. may be detected in the set state. Table 58. Configuration Bits Reset By RTCRST# Assertion
5.10 Processor Interface (D31:F0)
- Standard Outputs to the processor: A20M#, SMI#, NMI, INIT#, INTR, STPCLK#, IGNNE#, CPUSLP#
- The FERR# input to the Intel ® 6300ESB ICH has special buffer requirements. The Vil threshold is compatible with processors that drive FERR# no higher than 1.3V +/- 5%. Most Intel® 6300ESB ICH outputs to the processor use standard buffers. The Intel ® 6300ESB ICH has a separate V CC signal which is pulled up at the system level to the processor voltage, and thus determines VOH for the outputs to the processor. Note that this is different than previous generations of chips, that have used open-drain outputs. This new method saves up to 12 external pull-up resistors. The Intel® 6300ESB ICH does not support the processor’s FRC mode.
5.10.1 Processor Interface Signals
5.10.1.1 A20M#
- The ALT_A20_GATE bit (Bit 1 of PORT92 register) is a ‘0’
- The A20GATE input signal is a ‘0’ The A20GATE input signal is expected to be generated by the external microcontroller (KBC).
5.10.1.2 INIT#
Table 59. When any of these events occur, INIT# will be driven low for 16 PCI clocks, not go active until after STPCLK# goes inactive. Table 59. INIT# Going Active (Sheet 1 of 2) Shutdown special cycle from processor.
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5.10.1.3 FERR#/IGNNE# (Coprocessor Error)
until FERR# is driven inactive. IGNNE# is never driven active unless FERR# is active. internal IRQ13, nor will the write to F0h generate IGNNE#. SYS_RST(bit 1) transitions from 0 to 1. be driven by the external microcontroller (KBC). INIT# to be generated again. processor reset using the CF9 register. Table 59. INIT# Going Active (Sheet 2 of 2) Figure 14. Coprocessor Error Timing Diagram
5.10.1.4 NMI
5.10.1.5 STPCLK# and CPUSLP# Signals
The Intel® 6300ESB ICH power management logic controls these active-low signals. functionality of these signals.
5.10.2 Dual Processor Issues
5.10.2.1 Signal Differences
5.10.2.2 Dual Processor Power Management
sync with the processor on multiple STPCLK# assertions. Table 60. NMI Sources Table 61. DP Signal Differences A20M# / A20GATE Generally not used, but still supported by the Intel ® 6300ESB ICH. Used for S1 State as well as preparation for entry to S3-S5. methods). Should be connected to both processors. FERR# / IGNNE# Generally not used, but still supported by the Intel ® 6300ESB ICH.
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Because the S1 state will have the STPCLK# signal active, the STPCLK# signal can be connected to both processors. However, for ACPI implementations, the BIOS must indicate that the 6300ESB only supports the C1 state for dual-processor designs. In going to the S1 state, multiple Stop-Grant cycles will be generated by the CPUs. The Intel 6300ESB also has the option to assert the CPU’s SLP# signal (CPUSLP#). It is assumed that prior to setting the SLP_EN bit (which causes the transition to the S1 state), the CPUs will not be executing code that is likely to delay the Stop-Grant cycles. In going to the S3, S4, or S5 states, the system will appear to pass through the S1 state; thus, STPCLK# and SLP# are also used. During the S3, S4, and S5 states, both processors will lose power. Upon exit from those states, the processors will have their power restored.
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 145 5—Intel ® 6300ESB ICH
5.11 Power Management (D31:F0)
5.11.1 Features
- ACPI Power and Thermal Management Support — Processor THRMTRIP# emergency shutdown — ACPI 24-Bit Timer — Software initiated throttling of processor performance for Thermal and Power Reduction — Hardware Override to throttle processor performance when system too hot —S C I a n d S M I # G e n e r a t i o n
- PME# Signal for Wake Up from Low-Power states (PME signal shared between both PCI and PCI-X interfaces)
- SYS_Reset# input to eliminate external glue logic
- System Clock Control — ACPI C2 state: Stop-Grant (in desktop) or Quickstart (in mobile) state (using STPCLK# signal) halts processor’s instruction stream
- System Sleeping State Control — ACPI S1 state: Like C2 state (only STPCLK# active, and SLP# optional) — ACPI S3 state - Suspend to RAM (STR) — ACPI S4 state - Suspend-to-Disk(STD) — ACPI G2/S5 state - Soft Off(SOFF) — Power Failure Detection and Recovery — Supports new output signal - SLP_S4#
- Streamlined Legacy Power Management Support for APM-Based Systems
- Support for Prescott Processor
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5.11.2 Intel ® 6300ESB ICH Power States and Transition
state names generally match the corresponding ACPI states. Table 62. General Power States for Systems Using Intel ® 6300ESB ICH Full On: Processor operating. Individual devices may be shut down to save power. Table 63. Within the C0 state, the Intel® 6300ESB ICH may throttle the STPCLK# code. The processor snoops the bus and maintains cache coherency. processor snoops the bus and maintains cache coherency. continue. All clocks stop except RTC clock. power is then shut off to the system except for the logic required to resume. for the logic required to restart. A full boot is required when waking. GEN_PMCON3 register (D31:F0, offset A4). Refer to Table 71 for more details.
C2 states. These intermediate transitions and states are not listed in the table. Table 63. State Transition Rules for Intel ® 6300ESB I/O Controller Hub
- Processor halt instruction
- L e v e l 2 R e a d
- S L P _ E N b i t s e t
- Power Button Override
- Mechanical Off/Power Failure
- G 0 / S 0 / C 1
- G 0 / S 0 / C 2
- G1/Sx or G2/S5state
- G 2 / S 5
- G 3 G0/S0/C1
- Any Enabled break event
- S T P C L K # g o e s a c t i v e
- Power Button Override
- Power Failure
- G 0 / S 0 / C 0
- G 0 / S 0 / C 2
- G 2 / S 5
- G 3 G0/S0/C2
- Any Enabled break event
- STPCLK# goes inactive and previously in C1
- Power Button Override
- Power Failure
- G 0 / S 0 / C 0
- G 0 / S 0 / C 1
- G 2 / S 5
- G 3 G1/S1, G1/S3, or G1/S4
- Any Enabled Wake Event
- Power Button Override
- Power Failure
- G 0 / S 0 / C 0
- G 2 / S 5
- G 3 G2/S5 • Any Enabled Wake Event
- Power Failure
- G0/S0/C0
- G 3 G3 • Power Returns
- Optional to go to S0/C0 (reboot) or G2/S5 (stay off until power button pressed or other wake event). NOTE: Some wake events may be preserved through power failure.
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5.11.3 System Power Planes
5.11.4 Intel ® 6300ESB ICH Power Planes
- IDE: Output signals may be tri-stated or driven low and all input buffers may be shut off
- USB: Output signals may be tri-stated and all input buffers may by shut off when USB wakeup is not desired.
- AC’97: Output signals may be driven low and input buffers may be shut off.
Table 64. System Power Plane be retained to the main memory. power to the memory may also be shut down. power to the memory may also be shut down. drives, audio amplifiers, or the display screen.
5.11.5 SMI#/SCI Generation
which will cause it to enter SMM space. SMI# remains active until the EOS bit is set. When the EOS bit (bit 1) is set, SMI# will go inactive for a minimum of four PCI clocks. to level mode for that interrupt. Causes of TCO SCI are discussed in Section 5.12.3, “TCO Theory of Operation”. Table 65. Causes of SCI
- SCI_EN must be 1 to enable SCI.
- SCI may be routed to cause Interrupt 9:11 or 20:23 (20:23 only available in APIC mode).
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Table 66. Causes of SMI# (Sheet 1 of 2)
1 PME_B0_STS
1 TMROF_STS
- GBL_SMI_EN must be 1 to enable SMI.
- EOS must be written to 1 to re-enable SMI for the next one.
- Some SMI#s are considered “synchronous”, in that the processor should recognize the SMI#
possible in IA64 platforms, since they do not support the SMI# signal.
- NMI2SMI_STS is not gated by TCO_EN.
Table 67. Causes of TCO SMI# NOTE: NMI2SMI_STS is not gated by TCO_EN. See table above. Table 66. Causes of SMI# (Sheet 2 of 2)
- GBL_SMI_EN must be 1 to enable SMI.
- EOS must be written to 1 to re-enable SMI for the next one.
- Some SMI#s are considered “synchronous”, in that the processor should recognize the SMI#
possible in IA64 platforms, since they do not support the SMI# signal.
- NMI2SMI_STS is not gated by TCO_EN.
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5.11.6 Dynamic Processor Clock Control
section. The various Sleep states may also perform types of non-dynamic clock control.
- STPCLK#: Used to halt processor instruction stream. Note: The Intel® 6300ESB ICH does support THRM# based throttling. The C1 state (processor auto halt) may be used with either one or two processors, however. Processors are free to perform their own dynamic clock control; however, this is done without any coordination by the Intel® 6300ESB ICH. The C1 state is entered based on the processor performing an auto halt instruction. The C2 state is entered based on the processor reading the Level 2 register in the Intel® 6300ESB ICH. A C1 or C2 state ends due to a break event. Based on the break event, the Intel ® 6300ESB ICH returns the system to C0 state. Table 68 lists the possible break events from C2 states. The break events from C1 are indicated in the processor’s datasheet. The Intel® 6300ESB ICH supports the Pending Break Event (PBE) indication from the processor us- ing the FERR# signal. The following rules apply: 1. When STPCLK# is detected active by the processor, the FERR# signal from the processor will be redefined to indicate whether an interrupt is pending. The signal is active low (i.e., FERR# will be low to indicate a pending interrupt). 2. When the Intel ® 6300ESB ICH asserts STPCLK#, it will latch the current state of the FERR# signal and continue to present this state to the FERR# state machine (independent of what the FERR# pin does after the latching). 3. When the Intel ® 6300ESB ICH detects the Stop-Grant cycle, it will start looking at the FERR# signal as a break event indication. When FERR# is sampled low, a break event is indicated. This will force a transition to the C0 state. 4. When the processor detects the deassertion of STPCLK#, the processor will start driving the FERR# signal with the natural value (i.e.the value it would do when the pin was not muxed). The time from STPCLK# inactive to the FERR# signal transition back to the native function must be less than 120 ns.
Table 68. Break Events interrupt, any SCI will also be a break event. cause an NMI or SMI# C2 Many possible sources. through the RCIN input signal. General Control Register (LPC I/F—D31:F0)” ).
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 153 5—Intel ® 6300ESB ICH 5. The Intel ® 6300ESB ICH waits at least 180 ns to 8 PCI clocks (240 ns) after deasserting STPCLK# and then starts using the FERR# signal for an indication of a floating point error. The maximum time that the Intel ® 6300ESB ICH may wait is bounded such that it must have a chance to look at the FERR# signal before reasserting STPCLK#. Based on current implementation, that maximum time would be 240 ns (8 PCI clocks). Since the processor has 120-210 ns to revert to the proper FERR# function, there are 60-30 ns of margin inherent in the timings. The break event associated with this new mechanism does not need to set any particular status bit, since the pending interrupt will be serviced by the processor after returning to the C0 state.
5.11.6.1 Throttling Using STPCLK#
Throttling is used to lower power consumption or reduce heat. The Intel® 6300ESB ICH asserts STPCLK# to throttle the processor clock and the processor appears to temporarily enter a C2 state. After a programmable time, the Intel ® 6300ESB ICH deasserts STPCLK# and the processor appears to return to the C0 state. This allows the processor to operate at reduced average power, with a corresponding decrease in performance. Two methods are included to start throttling: 1. Software enables a timer with a programmable duty cycle. The duty cycle is set by the THTL_DTY field and the throttling is enabled using the THTL_EN field. This is known as Manual Throttling. The period is fixed to be in the non-audible range, due to the nature of switching power supplies. 2. A Thermal Override condition (THRM# signal active for >2 seconds) occurs that unconditionally forces throttling, independent of the THTL_EN bit. The throttling due to Thermal Override has a separate duty cycle (THRM_DTY) which may vary by field and system. The Thermal Override condition will end when THRM# goes inactive. Throttling due to the THRM# signal has higher priority than the software initiated throttling. Throttling does not occur when the system is in a C2 state, even when Thermal override occurs.
5.11.6.2 Transition Rules among S0/Cx and Throttling States
The following priority rules and assumptions apply among the various S0/Cx and throttling states:
- Entry to any S0/Cx state is mutually exclusive with entry to any S1–S5 state. This is because the processor may only perform one register access at a time and Sleep states have higher priority than thermal throttling.
- When the SLP_EN bit is set (system going to a sleep state (S1–S5), the THTL_EN bit may be internally treated as being disabled (no throttling while going to sleep state). Note that thermal throttling (based on THRM# signal) cannot be disabled in an S0 state. However , once the SLP_EN bit is set, the thermal throttling is shut off (since STPCLK# will be active in S1–S5 states).
- When the THTL_EN bit is set, and a Level 2 read then occurs, the system should immediately go and stay in a C2 state until a break event occurs. A Level 2 read has higher priority than the software initiated throttling or thermal throttling.
- When Thermal Override is causing throttling, and a Level 2 read then occurs, the system will stay in a C2 state until a break event occurs. A Level 2 read has higher priority than the Thermal Override.
- After an exit from a C2 state (due to a break event), and when the THTL_EN bit is still set, or when a Thermal Override is still occurring, the system will continue to throttle STPCLK#. Depending on the time of break event, the first transition on STPCLK# active may be delayed by up to one THRM period (1024 PCI clocks=30.72 microseconds).
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- The Host controller must post Stop-Grant cycles in such a way that the processor gets an indication of the end of the special cycle prior to the Intel ® 6300ESB ICH observing the Stop-Grant cycle. This ensures that the STPCLK# signals stays active for a sufficient period after the processor observes the response phase.
- When in the C1 state and the STPCLK# signal goes active, the processor will generate a Stop-Grant cycle, and the system should go to the C2 state. When STPCLK# goes inactive, it should return to the C1 state.
5.11.6.3 STPCLK# Implementation Notes
when it is reset, or upon sampling STPCLK# inactive.
- INTR
- INIT#
- SMI#
- NMI These signals should be run through a transparent latch internal to the Intel® 6300ESB ICH. While STPCLK# is inactive (HIGH) these signals propagate to the Intel ® 6300ESB ICH's pins and onto the processor as normal. However when STPCLK# is asserted then these signals are latched so that they may not change until STPCLK# is deasserted. This ensures that an edge on these signals is seen while the processor has a valid clock. These signals need to be latched at least 1 HCLK clock before STPCLK# assertion, and held 16 HCLK clocks after STPCLK# deassertion.
Figure 15. Latching Processor I/F Signals with STOPCLK#
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 155 5—Intel ® 6300ESB ICH Other Implementation Notes:
- When STPCLK# goes active due to a Level read, it must go active prior to the completion of the associated I/O read. This is to ensure that the STPCLK# is recognized by the processor prior to it recognizing the end of the I/O cycle. That will prevent the next instruction from being executed.
- The state machine must insure that the STPCLK# signal stays high for a minimum period of time. When STPCLK# is to go low due to throttling (regular or due to the THRM# signal), this could be very soon after it was driven high. The MCH should ensure that the Stop-Grant cycle coming down the Hub Interface occurs after the BRDY# is seen by the processor. Exception: For SMI#s that are caused by a processor I/O cycle, when STPCLK# is active, the Intel® 6300ESB ICH will still drive SMI# active. This is because the STPCLK# was obviously too late to be recognized at the instruction boundary. The I/O cycles that may cause SMI# include: writes to the APM register (B2h), accesses to 60/ 64h when “Legacy USB KBC scheme” is used, traps for Monitors 4, 5, 6, and 7, the SMI# on SLP_EN bit, accesses to 62/66h when the MCSMI_EN bit is set, access to registers with their associated enable set in the DEVTRAP_EN register, and the BIOS_STS bit (which is set by the processor writing a 1 to the GLB_RLS bit when the BIOS_EN bit is also set).
5.11.7 Sleep States
5.11.7.1 Sleep State Overview
The Intel® 6300ESB ICH directly supports different sleep states (S1–S5), which are entered by setting the SLP_EN bit, or due to a Power Button press. The entry to the Sleep states are based on several assumptions:
- Entry to a Cx state is mutually exclusive with entry to a Sleep state. This is because the processor may only perform one register access at a time. A request to Sleep always has higher priority than throttling.
- Prior to setting the SLP_EN bit, the software will turn off processor-controlled throttling. Note that thermal throttling cannot be disabled, but setting the SLP_EN bit will disable thermal throttling (since S1–S5 sleep state has higher priority).
- The G3 state cannot be entered through any software mechanism. The G3 state indicates a complete loss of power.
5.11.7.2 Initiating Sleep State
Sleep states (S1–S5) are initiated by:
- Masking interrupts, turning off all bus master enable bits, setting the desired type in the SLP_TYP field and then setting the SLP_EN bit. The hardware will then attempt to gracefully put the system into the corresponding Sleep state by first going to a C2 state. See Section 5.11.6, “Dynamic Processor Clock Control” for details on going to the C2 state.
- Pressing the PWRBTN# Signal for more than four seconds to cause a Power Button Override event. In this case the transition to the S5 state will be less graceful, since there will be no dependencies on observing Stop-Grant cycles from the processor or on clocks other than the RTC clock.
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- Entry to a Cx state is mutually exclusive with entry to a Sleep state. This is because the processor may only perform one register access at a time. A request to Sleep always has higher priority than throttling.
- Prior to setting the SLP_EN bit, the software will turn off processor-controlled throttling. Note that thermal throttling cannot be disabled, but setting the SLP_EN bit will disable throttling (since S1-S5 sleep state has higher priority).
- The G3 state cannot be entered through any software mechanism. The G3 state indicates a complete loss of power . Before entering sleep state, an ACPI OS will mask all interrupts and will turn off all bus master enable bits. For non-ACPI systems, the BIOS will mask interrupts and turn off all bus master enable bits. Note: Interrupts might not be masked at the I/O subsystem. Some Operating Systems have been observed to only mask interrupts inside the processor.
5.11.7.3 Exiting Sleep States
The possible causes of Wake Events (and their restrictions) are shown in Table 70. Table 69. Sleep Types snooping is possible in this state. wake from this sleeping state, as well as to the memory. this state should be powered. Table 70. Causes of Wake Events (Sheet 1 of 2) through software setting the SLP_EN and SLP_TYP bits, or if there is a power failure.
5.11.7.4 Sx-G3-Sx, Handling Power Failures
designed, different transitions could occur due to a power failure. possible events that will wake the system after a power failure.
- PWRBTN#: PWRBTN# is always enabled as a wake event. When RSMRST# is low
- RI#: RI# does not have an internal pull-up. Therefore, when this signal is enabled
be set and the system will interpret that as a wake event.
- RTC Alarm: The RTC_EN bit is in the RTC well and is preserved after a power loss.
Like PWRBTN_STS the RTC_STS bit is cleared when RSMRST# goes low. where the core well is not powered. Secondary PME# S1 –S5 Set PME_EN bit in GPE0_EN Register. USB EHCI controller) S1–S5 Set PME_B0_EN bit in GPE0_EN Register. Table 70. Causes of Wake Events (Sheet 2 of 2) through software setting the SLP_EN and SLP_TYP bits, or if there is a power failure.
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5.11.8 Thermal Management
5.11.8.1 THRM# Signal
be generated (depending on the SCI_EN bit being set). turn off the cooling methods. the signal will not be reported in the heartbeat message.
5.11.8.2 THRM# Initiated Passive Cooling
will reduce the overall power consumption by the system, and should cool the system. The intended result of the cooling is that the THRM# signal should go back inactive. cycle before starting the count of the time the STPCLK# signal is active. When THRM# goes inactive, the throttling will stop. Table 71. Transitions Due to Power Failure
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 159 5—Intel ® 6300ESB ICH Note: There is a small window where the Intel ® 6300ESB ICH may assert STPCLK# for one more throttling period after THRM# goes inactive. This is due to a sampling delay on THRM# (the signal is still active internally, but has just gone inactive externally). In case that the Intel® 6300ESB ICH is already attempting throttling because the THTL_EN bit is set, the duty cycle associated with the THRM# signal will have higher priority. When the Intel ® 6300ESB ICH is in the C2, or S1–S5 states, then no throttling will be caused by the THRM# signal being active.
5.11.8.3 THRM# Override Software Bit
The FORCE_THTL bit allows the BIOS to force passive cooling, just as though the THRM# signal had been active for two seconds. When this bit is set, the Intel ® 6300ESB ICH will start throttling using the ratio in the THRM_DTY field. When this bit is cleared the Intel® 6300ESB ICH will stop throttling, unless the THRM# signal has been active for two seconds or when the THTL_EN bit is set (indicating that ACPI software is attempting throttling). Duty Cycle on STPCLK#) Using the THTL_EN and THTL_DTY bits, the Intel ® 6300ESB ICH may force a programmed duty cycle on the STPCLK# signal. This will reduce the effective instruction rate of the processor and cut its power consumption and heat generation. See Section 8.8.3.5, “PROC_CNT—Processor Control Register” for more details on the programming of these bits.
5.11.8.5 Active Cooling
Active cooling involves fans. The GPIO signals from the Intel ® 6300ESB ICH may be used to turn on/off a fan.
5.11.9 Event Input Signal Usage
The Intel® 6300ESB ICH has various input signals that trigger specific events. This section describes those signals and how they should be used.
5.11.9.1 PWRBTN# - Power Button
The Intel® 6300ESB ICH PWRBTN# signal operates as a “Fixed Power Button” as described in the ACPI specification. PWRBTN# signal has a 16 ms debounce on the input. The state transition descriptions are included in the following table. Note: Transitions start as soon as the PWRBTN# is pressed (but after the debounce logic) and do not depend on when the Power Button is released.
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dependency from any other subsystem. resumed to the S0 state, the four second timer will start. the Power Button may wake the system, but the Sleep Button cannot. Button. See the ACPI specification for implementation details.
5.11.9.2 RI# - Ring Indicate
The Ring Indicator may cause a wake event (when enabled) from the S1–S5 states. RI# active, and the interrupt will be set up as a break event. Table 72. Transitions Due to Power Button G3 PWRBTN# pressed None No effect since no power.
5.11.9.3 PME# - PCI Power Management Event
between both the PCI and the PCI-X interfaces. external PME# signal and may cause the same effect.
5.11.9.4 SYS_RESET# Signal
to our chip and externally to the system as when PWROK had gone low. activity is still occurring. state as indicated by all of the PWROK inputs being active.
5.11.9.5 THRMTRIP# Signal
with a stop grant special cycle. Therefore, the Intel® 6300ESB ICH will not wait for one. transition to the S5 state, drive SLP_S3#, SLP_S4#, SLP_S5# low, and set the CTS bit. The transition will look like a power button override. after sampling THRMTRIP# active. Table 73. Transitions Due to RI# Signal
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When the processor is running extremely hot and is heating up, it is possible (although very unlikely) that components around it, such as the Intel ® 6300ESB ICH, are no longer executing cycles properly. Therefore, when THRMTRIP# fires and the Intel ® 6300ESB ICH is relying on state machine logic to perform the power down, the state machine may not be working and the system will not power down. The Intel® 6300ESB ICH will follow this flow for THRMTRIP#. 1. At boot (PXPCIRST# low), THRMTRIP# ignored. 2. After power-up (PXPCIRST# high), when THRMTRIP# sampled active, SLP_S3#, SLP_S4#, and SLP_S5# fire, and normal sequence of sleep machine starts. 3. Until sleep machine enters the S5 state, SLP_S3#, SLP_S4#, and SLP_S5# stay active, even when THRMTRIP# is now inactive. This is the equivalent of “latching” the thermal trip event. 4. When S5 state reached, go to step #1, otherwise stay here. When the Intel ® 6300ESB ICH never reaches S5, the Intel® 6300ESB ICH will not reboot until power is cycled. A Processor Thermal trip event will:
- Set the AFTERG3_EN bit
- Clear the PWRBTN_STS bit
- Clear all the GPE0_EN and GPE1_EN register bits
- Clear the SMB_WAK_STS bit only when SMB_WAK_STS was set due to SMBus slave receiving message and not set due to SMBAlert. Note: The THRMTRIP# pin must be glitch free.
5.11.10 ALT Access Mode
Before entering a low power state, several registers from powered down parts may need to be saved. In the majority of cases, this is not an issue, as registers have read and write paths. However, several of the ISA compatible registers are either read only or write only. To get data out of write-only registers, and to restore data into read-only registers, the Intel ® 6300ESB ICH implements an ALT access mode. When the ALT access mode is entered and exited after reading the registers of the Intel® 6300ESB ICH timer (8254), the timer starts counting faster (13.5 ms). The following steps listed below may cause problems: 1. BIOS enters ALT access mode for reading the Intel ® 6300ESB ICH timer related registers. 2. BIOS exits ALT access mode. 3. BIOS continues through the execution of other needed steps and passes control to the OS. After getting control in step #3, when the OS does not reprogram the system timer again the timer ticks may be happening faster than expected. For example DOS and its associated software assume that the system timer is running at 54.6 ms and as a result the timeouts in the software may be happening faster than expected. For some other OSs, such as DOS, the BIOS should restore the timer back to 54.6 ms before passing control to the OS. When the BIOS is entering ALT access mode before entering the suspend state it is not necessary to restore the timer contents after the exit from ALT access mode.
Table 74. Write Only Registers with Read Paths in ALT Access Mode (Sheet 1 of
1 DMA Chan 0 base address low
1 Timer Counter 0 status, bits [5:0]
2 DMA Chan 0 base address high
1 DMA Chan 0 base count low
2 DMA Chan 0 base count high
1 DMA Chan 1 base address low
2 DMA Chan 1 base address high
1 DMA Chan 1 base count low
2 DMA Chan 1 base count high
1 DMA Chan 2 base address low
2 DMA Chan 2 base address high
1 DMA Chan 2 base count low
1 DMA Chan 5 base address low
2 DMA Chan 2 base count high
1 DMA Chan 3 base address low
1 DMA Chan 5 base count low byte
2 DMA Chan 3 base address high
1 DMA Chan 3 base count low
1 DMA Chan 6 base address low
2 DMA Chan 3 base count high
- The OCW1 register must be read before entering ALT access mode.
- Bits 5, 3, 1, and 0 return zero.
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return the values listed in the following table.
1 DMA Chan 0-3 Command 2
1 DMA Chan 6 base count low byte
2 DMA Chan 0-3 Request 2 DMA Chan 6 base count high byte
3 DMA Chan 0 Mode: Bits(1:0) =
1 DMA Chan 7 base address low
4 DMA Chan 1 Mode: Bits(1:0) =
5 DMA Chan 2 Mode: Bits(1:0) =
1 DMA Chan 7 base count low byte
6 DMA Chan 3 Mode: Bits(1:0) =
1 PIC ICW2 of Master controller
1 DMA Chan 4-7 Command 2
2 PIC ICW3 of Master controller 2 DMA Chan 4-7 Request
3 PIC ICW4 of Master controller 3 DMA Chan 4 Mode: Bits(1:0) =
4 PIC OCW1 of Master controller 1 4 DMA Chan 5 Mode: Bits(1:0) =
5 PIC OCW2 of Master controller 5 DMA Chan 6 Mode: Bits(1:0) =
6 PIC OCW3 of Master controller 6 DMA Chan 7 Mode: Bits(1:0) =
7 PIC ICW2 of Slave controller
8 PIC ICW3 of Slave controller
9 PIC ICW4 of Slave controller
10 PIC OCW1 of Slave controller 1
11 PIC OCW2 of Slave controller
12 PIC OCW3 of Slave controller
Table 74. Write Only Registers with Read Paths in ALT Access Mode (Sheet 2 of
- The OCW1 register must be read before entering ALT access mode.
- Bits 5, 3, 1, and 0 return zero.
The registers described in Table 76 have write paths to them in ALT access mode. base address/count register also writes to the current address/count register. access mode and the current address/count register is written.
5.11.11 System Power Supplies, Planes, and Signals
circuits that need to generate Wake signals from the STR state. the power supply, or by external FETs to the motherboard. The PWROK input should go active based on the core supply voltages becoming valid. PWROK should go active at least 16 ms after the power is ensured valid. Table 75. PIC Reserved Bits Return Values Table 76. Register Write Accesses in ALT Access Mode 08h DMA Status Register for channels 0-3. D0h DMA Status Register for channels 4-7.
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- Traditional designs have a reset button logically ANDs with the PWROK signal from the power supply and the processor’s voltage regulator module. When this is done with the Intel® 6300ESB ICH, the PWROK_FLR bit will be set. The Intel ® 6300ESB ICH treats this internally as though the RSMRST# signal had gone active. However, it is not treated as a full power failure. When PWROK goes inactive and then active (but RSMRST# stays high), then the Intel® 6300ESB ICH will reboot (regardless of the state of the AFTERG3 bit). When the RSMRST# signal also goes low before PWROK goes high, then this is a full power failure and the reboot policy is controlled by the AFTERG3 bit. 2. PWROK and RSMRST# are sampled using the RTC clock. Therefore, low times that are less than one RTC clock period may not be detected by the Intel ® 6300ESB ICH. 5.11.11.3VRMPWRGD Signal The VRMPWRGD signal is not implemented in the Intel ® 6300ESB ICH. VRMPWRGD need to be pulled up to Vcc in order to disable internal legacy logic. If not pulled up, this logic may come up in an unknown state.
- All signals going to powered down planes (either internally or externally) must be either tri-stated or driven low.
- Signals with pull-up resistors should not be low during low-power states. This is to avoid the power consumed in the pull-up resistor.
- Buses should be halted (and held) in a known state to avoid a floating input (perhaps to some other device). Floating inputs may cause extra power consumption. Based on the above principles, the following measures are taken:
- During S3 (STR), all signals attached to powered down planes will be tri-stated or driven low.
5.11.12 Clock Generators
The clock generator is expected to provide the frequencies shown in Table 77. Table 77. Intel ® 6300ESB ICH Clock Inputs assertion. This signal is not 5V tolerant. This clock may be stopped in S3, S3 or S5 states. This signal is not 5V tolerant. This clock may be stopped in S3, S3 or S5 states. This signal is not 5V tolerant.
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5.11.13 Legacy Power Management Theory of Operation
5.11.13.1Overview Instead of relying on ACPI software, legacy power management uses BIOS and various hardware mechanisms. The Intel® 6300ESB ICH has a greatly simplified method for legacy power management compared with previous component generations. The scheme relies on the concept of detecting when individual subsystems are idle, detecting when the whole system is idle, and detecting when accesses are attempted to idle subsystems. However , the OS is assumed to be at least APM enabled. Without APM calls, there is no quick way to know when the system is idle between keystrokes. The Intel ® 6300ESB ICH does not support the burst modes found in previous components. 5.11.13.2APM Feature Notes The Intel® 6300ESB ICH has a timer that, when enabled by the 1MIN_EN bit in the SMI Control and Enable register, will generate an SMI# once per minute. The SMI handler may check for system activity by reading the DEVACT_STS register. When none of the system bits are set, the SMI handler may increment a software counter. When the counter reaches a sufficient number of consecutive minutes with no activity, the SMI handler may then put the system into a lower power state. When there is activity, various bits in the DEVACT_STS register will be set. Software clears the bits by writing a one to the bit position. The DEVACT_STS register allows for monitoring various internal devices, or Super I/O devices (SP, PP, FDC) on LPC or PCI, keyboard controller accesses, or audio functions on LPC or PCI. Other PCI activity may be monitored by checking the PCI interrupts.
5.12 System Management (D31:F0)
5.12.1 Overview of System Management Functions
The Intel® 6300ESB ICH provides various functions to make a system easier to manage and to lower the Total Cost of Ownership (TCO) of the system. It builds on functions that have been found in prior generations of serial interface ACPI-compatible processor system monitor components products, such as the LM78 and LM80. Features and functions may be augmented through external A/D converters and GPIO, as well as an external microcontroller. The Intel® 6300ESB ICH supports the following features and functions:
- First Hard Coded Timer to Generate SMI# after Programmable Time.
- First timeout causes SMI#. Allows for SMM-Based Recovery from OS lockup.
- OS-based software agent accesses the Intel ® 6300ESB ICH to periodically reload timer.
- Ability for SMM Handler to generate “TCO” interrupt to OS.
- Allows for OS-based code augmentation.
- Ability for OS to generate SMI#.
- Call-back from OS to TCO code in SMM handler.
- Second hard coded timer to generate reboot after programmable time.
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- Used only after first timeout occurs.
- Second timeout allows for system “reset and reboot” when a hardware error is detected. Various system states are preserved through this special reset to allow for possible error detection and correction.
- Reset associated with “reboot” may attempt to preserve some registers for diagnostic purposes.
- SMI# handler must periodically reload second timer to prevent “reboot” (timeout during SMI is assumed as broken processor or stuck hardware).
- Option to generate limited reset when second timeout occurs.
- Ability to detect a “Broken” processor.
- Detects when the processor fails to restart after it has been reset.
- When processor failure detected, option to pulse a GPIO or send SMBus message. The SMBus message may be used to indicate to an external LAN controller to send a distress message. The GPIO may control an LED with optional blink.
- Ability to Handle Various Errors (such as ECC Errors) Indicated by MCH.
- Can generate SMI# or TCO interrupt.
- Intruder Detect input when the system cover is removed.
- May generate TCO interrupt or SMI#.
- Ability for TCO messages to coexist with standard SMBus devices.
- Detection of bad FWH programming. Done by checking that data on the first read is not FFh.
5.12.2 TCO Signal Usage
5.12.2.1 Intruder# Signal
This signal may be used to detect the chassis being opened. The activation of this signal may be used to cause an SMI#, and is reported through the Heartbeat/Event mechanism. When SMI# is desired, the signal’s level may be read, so this may be used as a type of General Purpose Input.
5.12.2.2 Pin Straps
Some the TCO functions are decided at powerup (rising edge of PWROK). See Section 3.21, “Pin Straps” for specific assignments of the pin straps.
5.12.2.3 SMLINK Signals
The Intel® 6300ESB ICH supports TCO compatible mode connectivity. The Intel ® 6300ESB ICH supports LAN controllers. A LAN controller can be used to receive or retrieve TCO message or information on Host SMBus if needed. In Legacy TCO mode messages will be driven via SMLink. For the Intel ® 6300ESB ICH, messages on this link will use SMBus protocol at the rates described in Section 5.12, “System Management (D31:F0)” for TCO compatible mode. Note: All mention of “LAN” refers to an external LAN controller.
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5.12.3 TCO Theory of Operation
5.12.3.1 Overview
The System Management functions are designed to allow the system to diagnose failing subsystems. The intent of this logic is that some of the system management functionality be provided without the aid of an external microcontroller.
5.12.3.2 Detecting a System Lockup
When the processor is reset, it is expected to fetch its first instruction. When the processor fails to fetch the first instruction after reset, the TCO timer will timeout twice and the Intel ® 6300ESB ICH will assert PXPCIRST#. When TCO Reboots are not enabled, then the Intel ® 6300ESB ICH will either:
- The SMLink will still send out the first 8 bits of the message. After the eighth bit, the logic will stall because there is no integrated LAN controller to send the ACK. The logic will abort the transfer . External logic may monitor the toggling and use that to drive LED.
- If an LAN controller is connected: send the appropriate message to the LAN controller. When TCO Reboots are enabled, then the Intel ® 6300ESB ICH will attempt to reboot the system. Note: When the NO-REBOOT bit (D31:F0:Offset D4:bit 1) is set (no reboots are intended), and the SECOND_TO_STS bit (TCO I/O Offset 06h, bit 1) is set, and the DOACPU_STS bit (TCO I/O Offset 06h, bit 2), the Intel ® 6300ESB ICH will indicate this in the TCO message by setting the CPU Missing bit in the message. When the NO-REBOOT bit is not set (reboots intended), and the SECOND_TO_STS bit is set, the Intel® 6300ESB ICH will attempt to reboot. After the reboot, the SECOND_TO_STS bit will still be set. When the processor fails to fetch the first instruction, the DOA_CPU_STS bit is set, and when the TCO timer times out (actually for the third time, the first 2 times caused the SECOND_TO_STS bit to be set), the Intel ® 6300ESB ICH will set the CPU MISSING EVENT bit for the TCO message.
5.12.3.3 Handling an OS Lockup
Under some conditions, the OS may lock up. To handle this, the TCO Timer is used with the following algorithm: 1. BIOS programs the TCO Timer , through the TCO_TMR register, with an initial value. Generally, this will probably be set to four seconds, but could be greater. 2. An OS-based software agent periodically writes to the TCO_RLD register to reload the timer and keep it from generating the SMI#. The software agent may read the TCO_RLD register to see when it is close to timing out, and possibly determine if the time-out should be increased. 3. When the timer reaches 0, an SMI# may be generated. This should only occur when the OS was not able to reload the timer . It is assumed that the OS will not be able to reload the timer if it has locked up. 4. Upon generating the SMI#, the TCO Timer automatically reloads with the value in the TCO_TMR register and start counting down. 5. The SMI handler may then: a. Read the TIMEOUT bit in the TCO_STS register to check that the SMI# was caused by the TCO timer.
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 171 5—Intel ® 6300ESB ICH b. Write to the TCO_RLD register to reload the timer to make sure the TCO timer does not reach 0 again. c. Attempt to recover. May need to periodically reload the TCO timer. The exact recovery algorithm will be system-specific. When after the TIMEOUT SMI is generated, and the TCO timer again reaches 0, and reboots are enabled, the System Management logic will reset (and reboot) the system. This would be in the case where the processor or system is locked up. During every boot, BIOS should read the SECOND_TO_STS bit in the TCO_STS register to see if this is normal boot or a reboot due to the timeout.
5.12.3.4 Handling an Intruder
The Intel® 6300ESB ICH has an input signal, INTRUDER#, that may be attached to a switch that is activated by the system’s case being open. This input has a two RTC clock debounce. When INTRUDER# goes active (after the debouncer), this will set the INTRD_DET bit in the TCO_STS register. The INTRD_SEL bits in the TCO_CNT register may enable the Intel ® 6300ESB ICH to cause an SMI# or interrupt. The BIOS or interrupt handler may then cause a transition to the S5 state by writing to the SLP_EN bit. The software may also directly read the status of the INTRUDER# signal (high or low) by clearing and then reading the INTRD_DET bit. This allows the signal to be used as a GPI when the intruder function is not required. When the INTRUDER# signal goes inactive some point after the INTRD_DET bit is written as a 1, the INTRD_DET signal will go to a 0 when INTRUDER# input signal goes inactive. Note that this is slightly different than a classic sticky bit, since most sticky bits would remain active indefinitely when the signal goes active and would immediately go inactive when a 1 is written to the bit. Note: The INTRD_DET bit resides in the Intel ® 6300ESB ICH’s RTC well, and is set and cleared synchronously with the RTC clock. Thus, when software attempts to clear INTRD_DET (by writing a ‘1’ to the bit location) there may be as much as two RTC clocks (about 65 µs) delay before the bit is actually cleared. Also, the INTRUDER# signal should be asserted for a minimum of 1 ms in order to ensure that the INTRD_DET bit will be set. Note: When the INTRUDER# signal is still active when software attempts to clear the INTRD_DET bit, the bit will remain set and the SMI will be generated again immediately. The SMI handler may clear the INTRD_SEL bits to avoid further SMIs. However, when the INTRUDER# signal goes inactive and then active again, there will not be further SMIs, since the INTRD_SEL bits would select that no SMI# be generated.
5.12.3.5 Detecting Improper FWH Programming
The Intel® 6300ESB ICH may detect the case where the FWH is not programmed. This will result in the first instruction fetched to have a value of FFh. When this occurs, the Intel® 6300ESB ICH will set the BAD_BIOS bit, which may then be reported through the Heartbeat and Event reporting via an LAN Controller .
5.12.3.6 Handling an ECC Error or Other Memory Error
The Host Controller provides a message to indicate that it would like to cause an SMI#, SCI, SERR#, or NMI. The software must check the Host Controller as to the exact cause of the error.
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5.12.4 Heartbeat and Event Reporting through SMLink/
5.12.4.1 Overview
5.12.4.1.1 TCO Compatible Mode
messages to a network management console without the aid of the system processor . and is beyond the Intel® 6300ESB ICH’s recovery mechanisms. stored in a non-volatile memory connected directly to the LAN. Heartbeat). The Event and Heartbeat messages will have exactly the same form. Table 78. Event Transitions that Cause Messages GPIO11_ALERT_DISABLE bit) regardless of whether it is configured as a GPI or not.
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 173 5—Intel ® 6300ESB ICH When a triggering event occurs while a message is already being generated and sent, the new event may not appear in the current message. If not, then a second message will be generated, with the SEQ[3:0] field incremented, to report the new event. The following rules/steps apply when the system is in a G0 state and the policy is for the Intel ® 6300ESB ICH to reboot the system after a hardware lockup: 1. Upon detecting the lockup the SECOND_TO_STS bit will be set. The Intel ® 6300ESB ICH may send up to 1 Event message to the LAN. The Intel ® 6300ESB ICH will then attempt to reboot the processor . 2. When the reboot at step 1 is successful then the BIOS should clear the SECOND_TO_STS bit. This will prevent any further Heartbeats from being sent. The BIOS may then perform addition recovery/boot steps. Warning:It is important that the BIOS clears the SECOND_TO_STS bit, as the messages (alerts) will interfere with the LAN device driver from working properly. The alerts reset part of the LAN and would prevent an OS’s device driver from sending or receiving some messages. 3. When the reboot attempt in step 1 is not successful, then the timer will timeout a third time. At this point the system has locked up and was unsuccessful in rebooting. The Intel® 6300ESB ICH will not attempt to automatically reboot again. The Intel® 6300ESB ICH will start sending a message every heartbeat period (30- 32 seconds). The heartbeats will continue until some external intervention occurs (reset, power failure, etc.). 4. After step 3 (unsuccessful reboot after third timeout), when the user does a Power Button Override, the system will go to an S5 state. The Intel ® 6300ESB ICH will continue sending the messages every heartbeat period. 5. After step 4 (power button override after unsuccessful reboot) when the user presses the Power Button again, the system should wake to an S0 state and the processor should start executing the BIOS. 6. When step 5 (power button press) is successful in waking the system, the Intel ® 6300ESB ICH will continue sending messages every heartbeat period until the BIOS clears the SECOND_TO_STS bit. 7. When step 5 (power button press) is unsuccessful in waking the system, the Intel ® 6300ESB ICH will continue sending a message every heartbeat period. The Intel ® 6300ESB ICH will not attempt to automatically reboot again. The Intel ® 6300ESB ICH will start sending a message every heartbeat period (30-32 seconds). The heartbeats will continue until some external intervention occurs (reset, power failure, etc.). 8. After step 3 (unsuccessful reboot after third timeout), when a reset is attempted (using a button that pulses PWROK low or through the message on the SMBus slave I/F), the Intel® 6300ESB ICH will attempt to reset the system. 9. After step 8 (reset attempt), when the reset is successful, then the BIOS will be run. The Intel® 6300ESB ICH will continue sending a message every heartbeat period until the BIOS clears the SECOND_TO_STS bit. 10. After step 8 (reset attempt), when the reset is unsuccessful, then the Intel ® 6300ESB ICH will continue sending a message every heartbeat period. The Intel ® 6300ESB ICH will not attempt to reboot the system again without external intervention.
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The following rules/steps apply when the system is in a G0 state and the policy is for the Intel® 6300ESB ICH to not reboot the system after a hardware lockup: 1. Upon detecting the lockup the SECOND_TO_STS bit will be set. The Intel ® 6300ESB ICH will send a message with the Watchdog (WD) Event status bit set (and any other bits that must also be set). This message will be sent as soon as the lockup is detected, and will be sent with the next (incremented) sequence number. 2. After step 1, the Intel ® 6300ESB ICH will send a message every heartbeat period until some external intervention occurs. 3. Rules/steps 4-10 apply when no user intervention (resets, power button presses, SMBus reset messages) occur after a third timeout of the watchdog timer. When the intervention occurs before the third timeout, then jump to rule/step11. 4. After step 3 (third timeout), when the user does a Power Button Override, the system will go to an S5 state. The Intel ® 6300ESB ICH will continue sending heartbeats at this point. 5. After step 4 (power button override), when the user presses the power button again, the system should wake to an S0 state and the processor should start executing the BIOS. 6. When step 5 (power button press) is successful in waking the system, the Intel ® 6300ESB ICH will continue sending heartbeats until the BIOS clears the SECOND_TO_STS bit. 7. When step 5 (power button press) is unsuccessful in waking the system, the Intel ® 6300ESB ICH will continue sending heartbeats. The Intel ® 6300ESB ICH will not attempt to reboot the system again until some external intervention occurs (reset, power failure, etc.). 8. After step 3 (third timeout), when a reset is attempted (using a button that pulses PWROK low or through the message on the SMBus slave I/F), the Intel ® 6300ESB ICH will attempt to reset the system. 9. When step 8 (reset attempt) is successful, then the BIOS will be run. The Intel ® 6300ESB ICH will continue sending heartbeats until the BIOS clears the SECOND_TO_STS bit. 10.When step 8 (reset attempt), is unsuccessful, then the Intel ® 6300ESB ICH will continue sending heartbeats. The Intel ® 6300ESB ICH will not attempt to reboot the system again without external intervention. 11.This and the following rules/steps apply when the user intervention (power button press, reset, SMBus message, etc.) occur prior to the third timeout of the watchdog timer. 12. After step 1 (second timeout), when the user does a Power Button Override, the system will go to an S5 state. The Intel ® 6300ESB ICH will continue sending heartbeats at this point. 13.After step 12 (power button override), when the user presses the power button again, the system should wake to an S0 state and the processor should start executing the BIOS. 14. When step 13 (power button press) is successful in waking the system, the Intel ® 6300ESB ICH will continue sending heartbeats until the BIOS clears the SECOND_TO_STS bit. 15.When step 13 (power button press) is unsuccessful in waking the system, the Intel® 6300ESB ICH will continue sending heartbeats. The Intel® 6300ESB ICH will not attempt to reboot the system again until some external intervention occurs (reset, power failure, etc.). 16.After step 1 (second timeout), when a reset is attempted (using a button that pulses PWROK low or through the message on the SMBus slave I/F), the Intel ® 6300ESB ICH will attempt to reset the system. 17.When step 16 (reset attempt) is successful, then the BIOS will be run. The Intel ® 6300ESB ICH will continue sending heartbeats until the BIOS clears the SECOND_TO_STS bit. 18.When step 16 (reset attempt), is unsuccessful, then the Intel ® 6300ESB ICH will continue sending heartbeats. The Intel ® 6300ESB ICH will not attempt to reboot the system again without external intervention.
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 175 5—Intel ® 6300ESB ICH The following rules will apply when the system is in a G1 (S1-S4) state: 1. The Intel ® 6300ESB ICH will send a Heartbeat message every Heartbeat Period (30-32 seconds). 2. When an event occurs prior to the system being shut down, the Intel ® 6300ESB ICH will immediately send another Event message with the next (incremented) sequence number. 3. After the event, it will resume sending Heartbeat messages. Note: There is a boundary condition when a hardware event (event or heartbeat) happens right as the system is transitioning into a G0 state. In this condition, the hardware will send messages even though the system will be in a G0 state (and the status bits could potentially indicate that). Normally the Intel ® 6300ESB ICH will not send heartbeats in the G0 state (except in the case of a lockup). Note: A spurious alert could occur in the following sequence: a. The processor has initiated an alert using the SEND_NOW bit b. During the alert, the THRM#, INTRUDER# or GPI[11] changes state c. The system then goes to a non-S0 state. Once the system transitions to the non-S0 state, it may send a single alert with an incremented SEQUENCE number. Note: An inaccurate alert message may be generated in the following scenario: a. The system successfully boots after a second watchdog Timeout occurs. b. PWROK goes low (typically due to a reset button press) or a power button override occurs (before the SECOND_TO_STS bit is cleared). c. An alert message indicating that the processor is missing or locked up is generated with a new sequence number.
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5.13 General Purpose I/O
5.13.1 GPIO Mapping
Table 79. GPIO Implementation (Sheet 1 of 2) GPIO_USE_SEL bit 0 enables REQ/GNT[A]# pair. GPIO_USE_SEL bit 1 enables REQ/GNT[B]# pair. GPIO_USE_SEL bits [2:5] enable PIRQ[E:H]#.
- GPIO[0:7], GPIO[16:21, 23], and GPIO[32:43] are in the core well.
- GPIO[8:13] and GPIO[24:28] are in the suspend well.
- Core-well GPIO are 5V tolerant, except for GPIO[7:6] and [32:43].
- Resume-well GPIO are not 5V tolerant.
- GPIO[56:57] pads are in the suspend well, the register bits are in the RTC well.
Output controlled through GP_LVL register bit 16. t Only PXGNT[3]# Core 5.0 V Output controlled through GP_LVL register bit 17. t Only Unmuxed Core 5.0 V Output controlled through GP_LVL register bit 20. t Only Unmuxed Core 5.0 V Output controlled through GP_LVL register bit 21. t Only Unmuxed Core 5.0 V Output controlled through GP_LVL register bit [23]. Input active status read from GP_LVL register bit 24. Output controlled through GP_LVL register bit 24. Blink enabled through GPO_BLINK register bit 25. Output controlled through GP_LVL register bit 25. Table 79. GPIO Implementation (Sheet 2 of 2)
- GPIO[0:7], GPIO[16:21, 23], and GPIO[32:43] are in the core well.
- GPIO[8:13] and GPIO[24:28] are in the suspend well.
- Core-well GPIO are 5V tolerant, except for GPIO[7:6] and [32:43].
- Resume-well GPIO are not 5V tolerant.
- GPIO[56:57] pads are in the suspend well, the register bits are in the RTC well.
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5.13.2 Power Wells
Some GPIOs exist in the resume power plane. Care must be taken to make sure GPIO signals are not driven high into powered-down planes. Some Intel® 6300ESB ICH GPIOs may be connected to pins on devices that exist in the core well. When these GPIOs are outputs, there is a danger that a loss of core power (PWROK low) or a Power Button Override event will result in the Intel ® 6300ESB ICH driving a pin to a logic ‘1’ to another device that is powered down.
5.13.3 SMI# and SCI Routing
The routing bits for GPIO[0:15] allow an input to be routed to SMI# or SCI, or neither. See Section 8.8.3.3 for the routing register Note: A bit may be routed to either an SMI# or an SCI, but not both.
5.13.4 Triggering
GPIO[0:15] have “sticky” bits on the input. See Section 8.8.3.7 for the GPE0_STS register. As long as the signal goes active for at least 2 clocks, the Intel® 6300ESB ICH will keep the sticky status bit active. The active level (high or low) can be selected via the GP_INV register. If the system is in an S0 or S1-D state, the GPI are sampled at 33 MHz, so the signal only needs to be active for about 60 ns to be latched. In the S3-S5 states, the GPI are sampled at 32.768 KHz, and thus must be active for at least 61 microseconds to be latched. Note: GPIs that are in the core well are not capable of waking the system from sleep states where the core well is not powered. If the input signal is still active when the latch is cleared, it will again be set (another edge is not required). This makes these signals ìlevelî triggered inputs.
5.14 IDE Controller (D31:F1)
5.14.1 Overview
The Intel® 6300ESB ICH IDE controller features two sets of interface signals (Primary and Secondary) that may be independently enabled, tri-stated or driven low. The Intel® 6300ESB ICH IDE controller supports both legacy mode and native mode IDE interface. In native mode, the IDE controller is a fully PCI compliant software interface and does not use any legacy I/O or interrupt resources. The IDE interfaces of the Intel ® 6300ESB ICH may support several types of data transfers: Programmed I/O (PIO): Processor is in control of the data transfer. 8237 style DMA: DMA protocol that resembles the DMA on the ISA bus, although it does not use the 8237 in the Intel® 6300ESB ICH. This protocol off loads the processor from moving data. This allows higher transfer rate of up to 16 Mbytes/s.
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 179 5—Intel ® 6300ESB ICH Ultra ATA/33: DMA protocol that redefines signals on the IDE cable to allow both host and target throttling of data and transfer rates of up to 33 Mbytes/s. Ultra ATA/66: DMA protocol that redefines signals on the IDE cable to allow both host and target throttling of data and transfer rates of up to 66 Mbytes/s. Ultra ATA/100: DMA protocol that redefines signals on the IDE cable to allow both host and target throttling of data and transfer rates of up to 100 Mbytes/s.
5.14.2 PIO Transfers
5.14.2.1 Overview
The Intel® 6300ESB ICH IDE controller includes both compatible and fast timing modes. The fast timing modes may be enabled only for the IDE data ports. All other transactions to the IDE registers are run in single transaction mode with compatible timings. Up to two IDE devices may be attached per IDE connector (drive 0 and drive 1). The IDETIM and SIDETIM Registers permit different timing modes to be programmed for drive 0 and drive 1 of the same connector. The Ultra ATA/33/66/100 synchronous DMA timing modes may also be applied to each drive by programming the IDE I/O Configuration register and the Synchronous DMA Control and Timing registers. When a drive is enabled for synchronous DMA mode operation, the DMA transfers are executed with the synchronous DMA timings. The PIO transfers are executed using compatible timings or fast timings when also enabled.
5.14.2.2 IDE Port Decode
The Command and Control Block registers are accessed differently depending on the decode mode, which is selected by the Programming Interface configuration register (Offset 09h). Note: The primary and secondary channels are controlled by separate bits, allowing one to be in native mode and the other in legacy mode simultaneously.
5.14.2.3 IDE Legacy Mode and Native Mode
The Intel® 6300ESB ICH IDE controller supports both legacy mode and PCI native mode. In legacy mode, the Command and Control Block registers are accessible at fixed I/O addresses, may not be accessed through the I/O BARs. These blocks are decoded when I/O space is enabled through the P-ATA function’s configuration space and ATA decode is enabled through the PTIM/STIM registers, bit 15. An access to these addresses results in the assertion of the appropriate chip select (CS1#/CS3#) and the command strobes (DIOR#, DIOW#). There are two I/O ranges for each IDE cable: the Command Block, which corresponds to the CS1P#/CS1S# chip select, and the Control Block, which corresponds to the CS3P#/CS3S# chip select. The Command Block is an 8 byte range, while the control block is a 4 byte range.
- Command Block Offset: 01F0h for Primary, 0170h for Secondary
- Control Block Offset: 03F4h for Primary, 0374h for Secondary Table 80 and Table 81 specify the registers and transaction timings as they affect the Intel® 6300ESB ICH hardware definition.
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instructions. All other registers should be accessed using 8-bit I/O instructions. registers cause corresponding accesses on the IDE interface. BARs, rather than fixed I/O locations. received by the P-ATA host controller.
5.14.2.4 PIO IDE Timing Modes
Cycle latency consists of the I/O command strobe assertion length and recovery time. to 1, 2, 3, or 4 PCI clocks. of IORDY must be synchronized, at least two additional PCI clocks are added. Table 80. IDE Legacy I/O Ports: Command Block Registers (CS1x# Chip Select) it is received by the Intel® 6300ESB ICH.
DIOW#). Shutdown latency is two PCI clocks in duration. The IDE timings for various transaction types are shown in Table 81.
5.14.2.5 IORDY Masking
Point (ISP) on a drive by drive basis through the IDETIM Register.
5.14.2.6 PIO 32-Bit IDE Data Port Accesses
two PCI clocks between the two cycles.
5.14.2.7 PIO IDE Data Port Prefetching and Posting
data to be posted to and prefetched from the IDE data ports. the write buffer is transferred to the drive. Table 81. IDE Transaction Timings (PCI Clocks)
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5.14.3 Bus Master Function
The Intel® 6300ESB ICH may act as a PCI Bus master on behalf of an IDE slave device.
5.14.3.1 Physical Region Descriptor Format
Descriptor (PRD). The PRDs are stored sequentially in a Descriptor Table in memory. support memory regions or descriptor tables located on ISA. bytes in length. The first 4 bytes specify the byte address of a physical memory region. This memory region must be DWORD aligned and must not cross a 64-Kbyte boundary. last descriptor has been retired. line, the byte enables will be deasserted for invalid data. Figure 16. Physical Region Descriptor Table Entry
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5.14.3.2 Line Buffer
A single line buffer exists for the Intel ® 6300ESB ICH Bus master IDE interface. This buffer is not shared with any other function. The buffer is maintained in either the read state or the write state. Memory writes are typically 4-DWORD bursts and invalid DWORDs have C/BE[3:0]#=0Fh. The line buffer allows burst data transfers to proceed at peak transfer rates. The Bus Master IDE Active bit in Bus Master IDE Status register is reset automatically when the controller has transferred all data associated with a Descriptor Table (as determined by EOT bit in last PRD). The IDE Interrupt Status bit is set when the IDE device generates an interrupt. These events may occur prior to line buffer emptying for memory writes. When either of these conditions exist, all PCI Master non-Memory read accesses to the Intel ® 6300ESB ICH are retried until all data in the line buffers has been transferred to memory.
5.14.3.3 Bus Master IDE Timings
The timing modes used for Bus Master IDE transfers are identical to those for PIO transfers. The DMA Timing Enable Only bits in IDE Timing register may be used to program fast timing mode for DMA transactions only. This is useful for IDE devices whose DMA transfer timings are faster that its PIO transfer timings. The IDE device DMA request signal is sampled on the same PCI clock that DIOR# or DIOW# is deasserted. When inactive, the DMA Acknowledge signal is deasserted on the next PCI clock and no more transfers take place until DMA request is asserted again.
5.14.3.4 Interrupts
Legacy Mode: The Intel® 6300ESB ICH is connected to IRQ14 for the primary interrupt and IRQ15 for the secondary interrupt. This connection is done from the ISA pin, before any mask registers. This implies the following:
- Bus Master IDE is operating under an interrupt based driver. Therefore, it will not operate under environments where the IDE device drives an interrupt but the interrupt is masked in the system.
- Bus Master IDE devices are connected directly off of the Intel ® 6300ESB ICH. IDE interrupts cannot be communicated through PCI devices or the serial stream. Caution:In this mode, the Intel ® 6300ESB ICH will not drive the PCI Interrupt associated with this function. That is only used in native mode. Native Mode: In this case both the Primary and Secondary channels share an interrupt. It will be internally connected to PIRQ[C]# (IRQ18 in APIC mode). The interrupt will be active- low and shared. Behavioral notes in native mode
- The IRQ14 and IRQ15 pins do not affect the internal IRQ14 and IRQ15 inputs to the interrupt controllers. The IDE logic forces these signals inactive in such a way that the Serial IRQ source may be used.
- The IRQ14 and IRQ15 inputs (not external IRQ[14:15] pins) to the interrupt controller may come from other sources (Serial IRQ, PIRQx).
- The IRQ14 and IRQ15 pins are inverted from active-high to the active-low PIRQ.
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- When switching the IDE controller to native mode, the IDE Interrupt Pin Register will be masked (see Section 9.1.19, “Offset 3Dh: INTR_PN—Interrupt Pin Register (IDE—D31:F1)” ). When an interrupt occurs while the masking is in place and the interrupt is still active when the masking ends, the interrupt will be allowed to be asserted.
- The active-low PIRQ must be masked by hardware when the IOSE bit is cleared in order to allow other interrupts that are shared with this pin to be delivered and serviced. When the IOSE bit is 0, software may not clear the IDE interrupt status bits. When in Native Mode, a ‘1’ in the Bus Master Interrupt status bit (bit 2 of BMISP/BMISS) forces the interrupt asserted. This bit must be cleared in order to deassert the interrupt. This implementation is different from the Legacy Mode.
5.14.3.5 Bus Master IDE Operation
To initiate a bus master transfer between memory and an IDE device, the following steps are required: 1. Software prepares a PRD Table in system memory. The PRD Table must be DWORD aligned and must not cross a 64-Kbyte boundary. 2. Software provides the starting address of the PRD Table by loading the PRD Table Pointer Register. The direction of the data transfer is specified by setting the Read/ Write Control bit. The interrupt bit and Error bit in the Status register are cleared. 3. Software issues the appropriate DMA transfer command to the disk device. 4. The bus master function is engaged by software writing a '1' to the Start bit in the Command Register . The first entry in the PRD table is fetched and loaded into two registers which are not visible by software, the Current Base and Current Count registers. These registers hold the current value of the address and byte count loaded from the PRD table. The value in these registers is only valid when there is an active command to an IDE device. 5. Once the PRD is loaded internally, the IDE device will receive a DMA acknowledge. 6. The controller transfers data to/from memory responding to DMA requests from the IDE device. The IDE device and the host controller may or may not throttle the transfer several times. When the last data transfer for a region has been completed on the IDE interface, the next descriptor is fetched from the table. The descriptor contents are loaded into the Current Base and Current Count registers. 7. At the end of the transfer the IDE device signals an interrupt. 8. In response to the interrupt, software resets the Start/Stop bit in the command register. It then reads the controller status followed by the drive status to determine when the transfer completed successfully. The last PRD in a table has the End of List (EOL) bit set. The PCI bus master data transfers will terminate when the physical region described by the last PRD in the table has been completely transferred. The active bit in the Status Register will be reset and the DDRQ signal will be masked. The buffer is flushed (when in the write state) or invalidated (when in the read state) when a terminal count condition exists; that is, the current region descriptor has the EOL bit set and that region has been exhausted. The buffer is also flushed (write state) or invalidated (read state) when the Interrupt bit in the Bus Master IDE Status register is set. Software that reads the status register and finds the Error bit reset, and either the Active bit reset or the Interrupt bit set, may be assured that all data destined for system memory has been transferred and that data is valid in system memory. Table 82 describes how to interpret the Interrupt and Active bits in the Status Register after a DMA transfer has started. During concurrent DMA or Ultra ATA transfers, the Intel ® 6300ESB ICH IDE interface will arbitrate between the primary and secondary IDE cables when a PRD expires.
5.14.3.6 Error Conditions
registers help isolate the cause of the problem. was completed and to construct a new PRD table to complete the requested operation. In most cases the existing PRD table may be used to complete the operation. ® 6300ESB ICH does not use the 8237 for this mode. Table 82. Interrupt/Active Bit Interaction Definition specified a smaller size than the IDE transfer size.
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5.14.4 Ultra ATA/33 Protocol
- A source synchronous protocol to allow higher data transfer rates of up to 33 Mbytes/s. The device that drives the data lines also drives the data strobe signal.
- Both the source and destination may pause the transfer. The source pauses the burst by not toggling its strobe signal, while the destination pauses the burst by deasserting a redefined signal, DMARDY#.
- 16 bit wide CRC error checking, sent from the Intel ® 6300ESB ICH to the IDE device on DDACK# deassertion. Ultra ATA/33 is a physical protocol used to transfer data between a Ultra ATA/33 capable IDE controller such as the Intel ® 6300ESB ICH and one or more Ultra ATA/33 capable IDE devices. It utilizes the standard Bus Master IDE functionality and interface to initiate and control the transfer. Ultra ATA/33 utilizes a “source synchronous” signaling protocol to transfer data at rates up to 33 Mbytes/s. The Ultra ATA/33 definition also incorporates a Cyclic Redundancy Checking (CRC-16) error checking protocol.
5.14.4.1 Signal Descriptions
redefine a number of the standard IDE control signals when in Ultra ATA/33 mode. defined as transferring data from the Intel ® 6300ESB ICH to IDE device. as an acknowledgment to stop a request from the IDE device. ICH on which data is transferred during each rising and falling edge transition. data and to add wait-states to the current transaction. Table 83. UltraATA/33 Control Signal Redefinitions
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5.14.4.2 Operation
Initial setup programming consists of enabling and performing the proper configuration of the Intel ® 6300ESB ICH and the IDE device for Ultra ATA/33 operation. For the Intel® 6300ESB ICH, this consists of enabling synchronous DMA mode and setting up appropriate Synchronous DMA timings. When ready to transfer data to or from an IDE device, the Bus Master IDE programming model is followed. Once programmed, the drive and Intel® 6300ESB ICH control the transfer of data through the Ultra ATA/33 protocol. The actual data transfer consists of three phases, a start-up phase, a data transfer phase, and a burst termination phase. The IDE device begins the start-up phase by asserting DMARQ signal. When ready to begin the transfer, the Intel ® 6300ESB ICH will assert DMACK# signal. When DMACK# signal is asserted, the host controller will drive CS0# and CS1# inactive, DA0–DA2 low. For write cycles, the Intel® 6300ESB ICH will deassert STOP, wait for the IDE device to assert DMARDY#, and then drive the first data word and STROBE signal. For read cycles, the Intel® 6300ESB ICH will tri-state the DD lines, deassert STOP, and assert DMARDY#. The IDE device will then send the first data word and STROBE. The data transfer phase continues the burst transfers with the data transmitter (Intel ® 6300ESB ICH - writes, IDE device - reads) providing data and toggling STROBE. Data is transferred (latched by receiver) on each rising and falling edge of STROBE. The transmitter may pause the burst by holding STROBE high or low, resuming the burst by again toggling STROBE. The receiver may pause the burst by deasserting DMARDY# and resumes the transfers by asserting DMARDY#. The Intel ® 6300ESB ICH will pause a burst transaction in order to prevent an internal line buffer over or under flow condition, resuming once the condition has cleared. It may also pause a transaction when the current PRD byte count has expired, resuming once it has fetched the next PRD. Warning:The current burst may be terminated by either the transmitter or receiver. A burst termination consists of a Stop Request, Stop Acknowledge and transfer of CRC data. The Intel ® 6300ESB ICH may stop a burst by asserting STOP, with the IDE device acknowledging by deasserting DMARQ. The IDE device stops a burst by deasserting DMARQ and the Intel ® 6300ESB ICH acknowledges by asserting STOP. The transmitter then drives the STROBE signal to a high level. The Intel ® 6300ESB ICH will then drive the CRC value onto the DD lines and deassert DMACK#. The IDE device will latch the CRC value on rising edge of DMACK#. The Intel ® 6300ESB ICH will terminate a burst transfer when it needs to service the opposite IDE channel, when a Programmed I/O (PIO) cycle is executed to the IDE channel currently running the burst, or upon transferring the last data from the final PRD.
5.14.4.3 CRC Calculation
Cyclic Redundancy Checking (CRC-16) is used for error checking on Ultra ATA/33 transfers. The CRC value is calculated for all data by both the Intel ® 6300ESB ICH and the IDE device over the duration of the Ultra ATA/33 burst transfer segment. This segment is defined as all data transferred with a valid STROBE edge from DDACK# assertion to DDACK# deassertion. At the end of the transfer burst segment, the Intel ®
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6300ESB ICH will drive the CRC value onto the DD[15:0] signals. It is then latched by the IDE device on deassertion of DDACK#. The IDE device compares the Intel ® 6300ESB ICH CRC value to its own and reports an error if there is a mismatch.
5.14.5 Ultra ATA/66 Protocol
In addition to Ultra ATA/33, the Intel® 6300ESB ICH supports the Ultra ATA/66 protocol. The Ultra ATA/66 protocol is enabled through config bits 3:0 at offset 54h. The two protocols are similar, and are intended to be device driver compatible. The Ultra ATA/66 logic may achieve transfer rates of up to 66Mbytes/s. In order to achieve the higher data rate, the timings are shortened and the quality of the cable is improved to reduce reflections, noise, and inductive coupling. Note that the improved cable is required and will still plug into the standard IDE connector. The Ultra ATA/66 protocol also supports a 44 Mbytes/s mode.
5.14.6 Ultra ATA/100 Protocol
When the ATA_FAST bit is set for any of the four IDE devices, then the timings for the transfers to and from the corresponding device run at a higher rate. The Intel ® 6300ESB ICH Ultra ATA/100 logic may achieve read transfer rates up to 100 Mbytes/s, and write transfer rates up to 88.9 Mbytes/s. The cable improvements required for Ultra ATA/66 are sufficient for Ultra ATA/100, so no further cable improvements are required when implementing Ultra ATA/100.
5.14.7 Ultra ATA/33/66/100 Timing
The timings for Ultra ATA/33/66/100 modes are programmed through the Synchronous DMA Timing Register and the IDE Configuration Register. Different timings may be programmed for each drive in the system. The Base Clock frequency for each drive is selected in the IDE Configuration Register. The Cycle Time (CT) and Ready to Pause (RP) time (defined as multiples of the Base Clock) are programmed in the Synchronous DMA Timing Register . The Cycle Time represents the minimum pulse width of the data strobe (STROBE) signal. The Ready to Pause time represents the number of Base Clock periods that the Intel ® 6300ESB ICH will wait from deassertion of DMARDY# to the assertion of STOP when it desires to stop a burst read transaction. Note: The internal Base Clock for Ultra ATA/100 (Mode 5) runs at 133 MHz, and the Cycle Time (CT) must be set for three Base Clocks. The Intel ® 6300ESB ICH will thus toggle the write strobe signal every 22.5 ns, transferring two bytes of data on each strobe edge. This means that the Intel® 6300ESB ICH will perform Mode 5 write transfers at a maximum rate of 88.9 Mbytes/s. For read transfers, the read strobe will be driven by the ATA/100 device, and the Intel® 6300ESB ICH supports reads at the maximum rate of 100 Mbytes/s.
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5.15 SATA Host Controller (D31:F2)
5.15.1 Overview
The Intel® 6300ESB ICH SATA controller features two sets of interface signals that may be independently enabled, tri-stated or driven low. Each interface is supported by an independent DMA controller. The Intel ® 6300ESB ICH SATA controller interacts with an attached mass storage device through a register interface that is equivalent to that presented by a traditional IDE host adapter. The host software follows existing standards and conventions when accessing the register interface and follows standard command protocol conventions.
5.15.2 Theory of Operation
5.15.2.1 Standard ATA Emulation
The Intel® 6300ESB ICH contains a set of registers that shadow the contents of the legacy IDE registers. The behavior of the Command and Control Block registers, PIO and DMA data transfers, resets, and interrupts are all emulated. 5.15.2.2 48-bit LBA Operation (Logical Block Addressing) The SATA host controller supports 48-bit LBA through the host-to-device register FIS, Frame Information Structure, when accesses are performed through writes to the task file. The SATA host controller will ensure that the correct data is put into the correct byte of the host-to-device FIS. There are special considerations when reading from the task file to support 48-bit LBA operation. Software may need to read all 16 bits. Since the registers are only 8 bits wide and act as a FIFO, a bit must be set in the device/control register , which is at offset 3F6h for primary and 376h for secondary (or their native counterparts). When software clears bit 7 of the control register before performing a read, the last item written will be returned from the FIFO. When software sets bit 7 of the control register before performing a read, the first item written will be returned from the FIFO.
5.15.3 Hot Plug Operation
Dynamic hot plug (such as surprise removal) is not supported by the SATA Host controller. However , using the SPC register configuration bits, and power management flows, a device may be powered down by software, and the port may then be powered off, allowing removal and insertion of a new device.
5.15.4 Power Management Operation
Power management of the Intel ® 6300ESB ICH SATA Controller and ports will cover operations of the host controller and the SATA wire.
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5.15.4.1 Power State Mappings
D0 – Device is working and instantly available. called which will reset the device and then cut its power. Each of these device states are subsets of the host controller’s D0 state. SATA Controller defines these states as sub-states of the device D0 state. Figure 17. SATA Power States
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5.15.4.2 Power State Transitions
5.15.4.2.1 Partial and Slumber State Entry/Exit
The partial and slumber states save interface power when the interface is idle. It would be most analogous to PCI CLKRUN# (in power savings, not in mechanism), where the interface may have power saved while no commands are pending. The SATA Controller defines PHY layer power management (as performed through primitives) as a driver operation from the host side, and a device proprietary mechanism on the device side. The SATA Controller will accept device transition types, but will not issue any transitions as a host. All received requests from a SATA device will be ACKed. When an operation is performed to the SATA Controller such that it needs to use the SATA cable, the controller must check whether the link is in the Partial or Slumber states, and if so, must issue a COM_WAKE to bring the link back online. Similarly, the SATA device must perform the same action.
5.15.4.2.2 Device D1, D3 States
These states are entered after some period of time when software has determined that no commands will be sent to this device for some time. The mechanism for putting a device in these states does not involve any work on the host controller, other then sending commands over the interface to the device. The command most likely to be used in ATA/ATAPI is the “STANDBY IMMEDIATE” command.
5.15.4.2.3 Host Controller D3 state
After the interface and device have been put into a low power state, the host controller may be put into a low power state. This is performed through the PCI power management registers in configuration space. There are two very important aspects to note when using PCI power management. 1. When the power state is D3, only accesses to configuration space are allowed. Any attempt to access the memory or I/O spaces must result in master abort. 2. When the power state is D3, no interrupts may be generated, even when they are enabled. When an interrupt status bit is pending when the controller transitions to D0, an interrupt may be generated. When the controller is put into D3, it is assumed that software has properly shut down the device and disabled the ports. Therefore, there is no need to sustain any values on the port wires. The interface will be treated as though no device is present on the cable, and power will be minimized.
5.15.4.3 SMI Trapping (APM)
Offset 48h, bits 3:0 in the power management I/O space contain control for generating SMI# on accesses to the IDE I/O spaces. These bits map to the legacy ranges only (1f0-1f7h, 3f6h, 170-177h, and 376h). When the SATA controller is in legacy mode and is using these addresses, accesses to one of these ranges with the appropriate bit set will cause the cycle to not be forwarded to the SATA controller, and an SMI# is generated. To block accesses to the native IDE ranges, software must use the generic Power Management control registers described in Section 8.8.1.7, “Offset C4h, C6h, C8h, CAh: MON[n]_TRP_RNG—I/O Monitor [4:7] Trap Range Register for Devices 4-7 (PM— D31:F0)”.
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5.15.5 SATA Interrupts
for I/O space register details.
5.15.6 SATALED#
asserted, the LED is active.
5.16 Multimedia Event Timers
5.16.1 Overview
include only a subset of these timers. may be enabled to generate a periodic interrupt. OS will move the location of these timers once it is set by the BIOS. Table 84. SATA MSI vs. PCI IRQ Actions
5.16.2 Timer Accuracy
- The timers are accurate over any 1 ms period to within 0.005% of the time
specified in the timer resolution fields.
- Within any 100 ms period, the timer will report a time that is up to two ticks too
- The timer is monotonic. It will not return the same value on two consecutive reads
(unless the counter has rolled over and reached the same value).
5.16.3 Interrupt Mapping
Section 15.1.3, “Offset 010-017h: General Config Register” for LEG_RT_CNF details. 64-bit mode, whereas Timers 1 and 2 only support 32-bit mode. by the hardware. Software may change the value. Table 85. Legacy Routing
0 IRQ0 IRQ2 In this case, the 8254 timer will not cause any
1 IRQ8 IRQ8 In this case, the RTC will not cause any interrupts.
2 As per IRQ
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may pass the value before it reaches the register and the interrupt will be missed. All three timers support non-periodic mode. Periodic Mode Timer 0 is the only timer that supports periodic mode. When Timer 0 is set up for periodic mode, the software writes a value into the timer’s comparator value register . When the main counter value matches the value in the timer’s comparator value register, an interrupt may be generated. The hardware will then automatically increase the value in the comparator value register by the last value written to that register. To make the periodic mode work properly, the main counter is typically written with a value of zero so that the first interrupt occurs at the right point for the comparator. When the main counter is not set to zero, interrupts may not occur as expected. During run-time, the value in the timer’s comparator value register may be read by software to find out when the next periodic interrupt will be generated (not the rate at which it generates interrupts). Software is expected to remember the last value written to the comparator’s value register (the rate at which interrupts are generated). When software wants to change the periodic rate, it should write a new value to the comparator value register. At the point when the timer’s comparator indicates a match, this new value will be added to derive the next matching point. When the software resets the main counter, the value in the comparator’s value register needs to be reset as well. This may be done by setting the TIMER0_VAL_SET_CNF bit. Again, to avoid race conditions, this should be done with the main counter halted. See Section 15, “Multimedia Timer Registers” for register and bits details. The following usage model is expected: 1. Software clears the ENABLE_CNF bit to prevent any interrupts 2. Software Clears the main counter by writing a value of 00h to it. 3. Software sets the TIMER0_VAL_SET_CNF bit. 4. Software writes the new value in the TIMER0_COMPARATOR_VAL register 5. Software sets the ENABLE_CNF bit to enable interrupts. Warning:As the timer period approaches zero, the interrupts associated with the periodic timer may not get completely serviced before the next timer match occurs. Interrupts may get lost and/or system performance may be degraded in this case. The Timer 0 Comparator Value register cannot be programmed reliably by a single 64- bit write in a 32-bit environment except when only the periodic rate is being changed during run-time. When the actual Timer 0 Comparator Value needs to be reinitialized, the following software solution will always work regardless of the environment: 1. Set TIMER0_VAL_SET_CNF bit 2. Set the lower 32 bits of the Timer0 Comparator Value register 3. Set TIMER0_VAL_SET_CNF bit 4. Set the upper 32 bits of the Timer0 Comparator Value register
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5.16.5 Enabling the Timers
The BIOS or OS PnP code should route the interrupts. This includes the Legacy Rout bit, Interrupt Rout bit (for each timer), interrupt type (to select the edge or level type for each timer) The Device Driver code should do the following for an available timer: 1. Set the Overall Enable bit (Offset 04h, bit 0). 2. Set the timer type field (selects one-shot or periodic). 3. Set the interrupt enable. 4. Set the comparator value.
5.16.6 Interrupt Levels
Interrupts directed to the internal 8259s are active high. See Section 5.7, “Advanced Interrupt Controller (APIC) (D29:F5)” for information regarding the polarity programming of the I/O APIC for detecting internal interrupts. When the interrupts are mapped to the I/O APIC and set for level-triggered mode, they may be shared with PCI interrupts, although it is unlikely for the OS to attempt this. When more than one timer is configured to share the same IRQ using the TIMERn_INT_ROUT_CNF fields, the software must configure the timers to level-triggered mode. Edge-triggered interrupts cannot be shared.
5.16.7 Handling Interrupts
When each timer has a unique interrupt and the timer has been configured for edge- triggered mode, no specific steps are required. No read is required to process the interrupt. When a timer has been configured to level-triggered mode, its interrupt must be cleared by the software. This is done by reading the interrupt status register and writing a 1 back to the bit position for the interrupt to be cleared. Independent of the mode, software may read the value in the main counter to see how much time has passed between when the interrupt was generated and when it was first serviced. When Timer 0 is set up to generate a periodic interrupt, the software may check to see how much time remains until the next interrupt by checking the timer value register.
5.16.8 Issues Related to 64-bit Timers with 32-bit
A 32-bit timer may be read directly using processors that are capable of 32-bit or 64- bit instructions. However , a 32-bit processor may not be able to directly read 64-bit timer . A race condition comes up when a 32-bit processor reads the 64-bit register using two separate 32-bit reads. The danger is that just after reading one half, the other half rolls over and changes the first half. When a 32-bit processor needs to access a 64-bit timer, it must first halt the timer before reading both the upper and lower 32-bits of the timer.
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behave as a 32-bit timer. The upper 32 bits will always be 0.
5.17 USB UHCI Controllers (D29:F0 and F1)
5.17.1 Overview
Interface (UHCI) Specification, Rev 1.1. 5V-tolerant and may be used as GPIs when not needed. standard PCI devices to improve arbitration latency. support for USB High-speed signaling rates instead of USB I/O buffers.
5.17.2 Data Structures in Main Memory
Descriptors and Queue Heads are aligned on 16-byte boundaries.
5.17.2.1 Frame List Pointer
the frame, as well as the control bits defined in Table 86. Table 86. Frame List Pointer Bit Description processed in the frame and corresponds to memory address signals [31:4], respectively. 3:2 Reserved. These bits must be written as zero. this frame has valid entries in it. 1 = Empty Frame (pointer is invalid). 0 = Pointer is valid (points to a QH or TD).
5.17.2.2 Transfer Descriptors (TD)
during operation. All Transfer Descriptors have the same basic, 32-byte structure. within the Intel® 6300ESB ICH. Figure 18. Transfer Descriptor Table 87. TD Link Pointer respectively. This field points to another TD or QH. 3 Reserved. Must be 0 when writing this field. queue rather than starting a new queue. ICH to perform the proper type of processing on the item after it is fetched. indicates to the Intel® 6300ESB ICH that there are no more valid entries in the queue. 6300ESB ICH that this is the last TD in the frame. 0 = Link Pointer field is valid. 1 = Link Pointer field not valid.
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Table 88. TD Control and Status (Sheet 1 of 3) when the interrupt is enabled, the interrupt will be sent at the end of the frame. for this TD and there will be no limit on the retries of this TD.
00 No Error Limit
sink) is a low speed device, running at 1.5 Mb/s, instead of at full speed (12 Mb/s). root hub port is connected to a low speed device.
“Data Transfers to/from Main Memory”, Data Transfers to/from Main Memory. stall handshake is received from the endpoint. error will also be reported.
21 Data Buffer Error (DBE):
(overrun) or is unable to supply data fast enough during transmission (underrun). When this occurs, the actual length and Max Length field of the TD will not match. will force a timeout condition on the USB, invalidating the transaction at the source.
20 Babble Detected (BABD):
executed. Execution resumes with the next frame list index.
19 Negative Acknowledgment (NAK) Received (NAKR):
out error will also be reported. endpoint within the time specified by the protocol chapter of the USB specification. the transaction associated with this transfer descriptor. 6300ESB ICH detecting a timeout from the target device/endpoint. NAK or STALL handshake being received in response to a SETUP transaction.
17 Bit stuff Error (BSE):
that the receive data stream contained a sequence of more than 6 ones in a row. Table 88. TD Control and Status (Sheet 2 of 3)
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Table 89. TD Token Note that values from 500h to 7FEh are illegal and cause a consistency check failure. which more than one sub-channel is required. halt of the Intel® 6300ESB ICH. Bits [3:0] are complements of bits [7:4]. Table 88. TD Control and Status (Sheet 3 of 3)
5.17.2.3 Queue Head (QH)
Table 90. TD Buffer Pointer field described int the TD token. The data buffer may be byte-aligned. Table 91. Queue Head Block Table 92. Queue Head Link Pointer 3:2 Reserved. These bits must be written as zeros.
1 QH/TD Select (Q): This bit indicates to the hardware whether the item referenced by
the link pointer is another TD or a QH. 0 = Pointer is valid (points to a QH or TD). 1 = Last QH (pointer is invalid). Table 93. Queue Element Link Pointer (Sheet 1 of 2)
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5.17.3 Data Transfers to/from Main Memory
discussion on Transfer Queuing.
5.17.3.1 Executing the Schedule
fetched until the current element in the frame list is retired. field is the pointer itself.
- When isochronous traffic is to be moved in a given frame, the Frame List entry
transfers are initiated in that frame.
- When the Frame List entry indicates that it points to a Transfer Descriptor, the
entry, as well as indicating whether it is a TD or a QH.
- When the Frame List entry contains a pointer to a QH, the Intel ® 6300ESB ICH
object that it should process.
- The TD/QH process continues until the millisecond allotted to the current frame
1 = Terminate (No valid queue entries). Table 93. Queue Element Link Pointer (Sheet 2 of 2)
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5.17.3.2 Processing Transfer Descriptors
The Intel® 6300ESB ICH executes a TD using the following generalized algorithm. These basic steps are common across all modes of TDs. Subsequent sections present processing steps unique to each TD mode. 1. The Intel ® 6300ESB ICH fetches TD or QH from the current Link Pointer. 2. When a QH, go to 1 to fetch from the Queue Element Link Pointer . When inactive, go to 12. 3. Build token, actual bits are in TD token. 4. When (Host-to-Function) then [PCI Access] issue request for data, (referenced through TD.BufferPointer) wait for first chunk data arrival end if 5. [Begin USB Transaction] Issue token (from token built in 2, above) and begin data transfer. if (Host-to-Function) then Go to 6 else Go to 7 end if 6. Fetch data from memory (through TD BufferPointer) and transfer over USB until TD Max-Length bytes have been read and transferred. [ Concurrent system memory and USB Accesses]. Go to 8. 7. Wait for data to arrive (from USB). Write incoming bytes into memory beginning at TD BufferPointer. Internal HC buffer should signal end of data packet. Number of bytes received must be TD Max-Length; The length of the memory area referenced by TD BufferPointer. 8. Issue handshake based on status of data received (Ack or Time-out). Go to 10. 9. Wait for handshake, when required [ End of USB Transaction]. 10. Update Status [PCI Access] (TD.Status and TD.ActualLength). When the TD was an isochronous TD, mark the TD inactive. Go to 12. When not an isochronous TD, and TD completed successfully, mark the TD inactive. Go to 11. When not successful, and the error count has not been reached, leave the TD active. When the error count has been reached, mark the TD inactive. Go to 12. 11. Write the link pointer from the current TD into the element pointer field of the QH structure. When the Vf bit is set in the TD link pointer, go to 2. 12. Proceed to next entry.
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5.17.3.3 Command Register, Status Register, and TD Status Bit
0 and Stalled bit to 1 as normal.
5.17.3.4 Transfer Queuing
linked list. The linked list of TDs and QHs has an indeterminate length (0 to n). Table 94. Command Register, Status Register and TD Status Bit Interaction
- Only when error counter counted down from 1 to 0.
- Suspend mode may be entered only when Run/Stop bit is 0.
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- QH (Queue Element Link Pointer)
- Write-Back to QH (Queue Element Link Pointer)
- QH (Queue Head Link pointer).
® 6300ESB ICH traverses the QH’s Queue Head Link Pointer. 6300ESB ICH follows the TD’s link pointer to the next schedule work item. successful TD’s link pointer is written back to the QH’s Queue Element link pointer. status of the TD at the “Top” of a currently “active” queue. Table 95. Queue Advance Criteria
Table 96. USB Schedule List Traversal Decision Table 0 ----x0 0 Not in Queue - execute TD. Use TD.LP to get next (QH+QE). In Queue. Use QE.LP to get TD. Execute TD. Update QE.LP with TD.LP. In Queue. Use QE.LP to get TD. Execute TD. Update QE.LP with TD.LP. In Queue. Use QE.LP to get TD. Execute TD. Update QE.LP with TD.LP. Use TD.LP to get next (QH+QE). 10 0 x 1 x x x In Queue. Empty queue. In Queue. Use QE.LP to get TD. Execute TD. Update QE.LP with TD.LP. In Queue. Use QE.LP to get TD. Execute TD. Update QE.LP with TD.LP. Use QH.LP to get next (QH+QE). 11 0 x 1 x x x In Queue. Empty queue.
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5.17.4 Data Encoding and Bit Stuffing
5.17.5 Bus Protocol
5.17.5.1 Bit Ordering
through to the most significant bit (MSb) last.
5.17.5.2 SYNC Field
5.17.5.3 Packet Field Formats
clarity. All packets have distinct start and end of packet delimiters. Figure 20. USB Data Encoding
Table 97. PID Format
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Table 97. The PID indicates the type of packet and, by inference, the format of the complement of the packet type field. and is ignored by the receiver. PID types, codes, and descriptions are listed in Table 98.
5.17.5.4 Address Fields
Table 98. PID Types Table 99. Address Field
ADDR field is specified for IN, SETUP, and OUT tokens.
5.17.5.5 Frame Number Field
is sent only for SOF tokens at the start of each frame.
5.17.5.6 Data Field
bytes. Data bits within each byte are shifted out LSB first.
5.17.5.7 Cyclic Redundancy Check (CRC)
ignore those fields, and, in most cases, the entire packet.
5.17.6 Packet Formats
5.17.6.1 Token Packets
Table 100. Endpoint Field
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after three bytes, it must be considered invalid and ignored by the receiver.
5.17.6.2 Start of Frame Packets
packet type followed by an 11-bit frame number field. needs to track frame number , it must comprehend both the PID and the time stamp.
5.17.6.3 Data Packets
packet PIDs are defined to support data toggle synchronization. Table 101. Token Format Table 102. SOF Packet Table 103. Data Packet Format
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5.17.6.4 Handshake Packets
Handshake packets consist of only a PID. Handshake packets are used to report the status of a data transaction and may return values indicating successful reception of data, flow control, and stall conditions. Only transaction types that support flow control may return handshakes. Handshakes are always returned in the handshake phase of a transaction and may be returned, instead of data, in the data phase. Handshake packets are delimited by an EOP after one byte of packet field. When a packet is decoded as an otherwise valid handshake but does not terminate with an EOP after one byte, it must be considered invalid and ignored by the receiver. There are three types of handshake packets:
- ACK indicates that the data packet was received without bit stuff or CRC errors over the data field and that the data PID was received correctly. An ACK handshake is applicable only in transactions in which data has been transmitted and where a handshake is expected. ACK may be returned by the host for IN transactions and by a function for OUT transactions.
- NAK indicates that a function was unable to accept data from the host (OUT) or that a function has no data to transmit to the host (IN). NAK may only be returned by functions in the data phase of IN transactions or the handshake phase of OUT transactions. The host may not issue a NAK. NAK is used for flow control purposes to indicate that a function is temporarily unable to transmit or receive data, but will eventually be able to do so without need of host intervention. NAK is also used by interrupt endpoints to indicate that no interrupt is pending.
- STALL is returned by a function in response to an IN token or after the data phase of an OUT . STALL indicates that a function is unable to transmit or receive data, and that the condition requires host intervention to remove the stall. Once a function’s endpoint is stalled, the function must continue returning STALL until the condition causing the stall has been cleared through host intervention. The host is not permitted to return a STALL under any condition.
5.17.6.5 Handshake Responses
A function may respond to an IN transaction with a STALL or NAK. When the token received was corrupted, the function will issue no response. When the function may transmit data, it will issue the data packet. The Intel ® 6300ESB ICH, as the USB host, may return only one type of handshake on an IN transaction, an ACK. When it receives a corrupted data, or cannot accept data due to a condition such as an internal buffer overrun, it discards the data and issues no response. OUT Transaction A function may respond to an OUT transaction with a STALL, ACK, or NAK. When the transaction contained corrupted data, it will issue no response. SETUP Transaction Setup defines a special type of host to function data transaction which permits the host to initialize an endpoint’s synchronization bits to those of the host. Upon receiving a Setup transaction, a function must accept the data. Setup transactions cannot be STALLed or NAKed and the receiving function must accept the Setup transfer’s data. When a non-control endpoint receives a SETUP PID, it must ignore the transaction and return no response.
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5.17.7 USB Interrupts
5.17.7.1 Overview
There are two general groups of USB interrupt sources, those resulting from execution of transactions in the schedule, and those resulting from an Intel ® 6300ESB ICH operation error. All transaction-based sources may be masked by software through the Intel® 6300ESB ICH’s Interrupt Enable register. Additionally, individual transfer descriptors may be marked to generate an interrupt on completion. When the Intel® 6300ESB ICH drives an interrupt for USB, it internally drives the PIRQ[A]# pin for USB function #0, PIRQ[D]# pin for USB function #1 until all sources of the interrupt are cleared. In order to accommodate some operating systems, the Interrupt Pin register must contain a different value for each function of this new multi- function device.
5.17.7.2 Transaction Based Interrupts
These interrupts are not signaled until after the status for the last complete transaction in the frame has been written back to host memory. This ensures that software may safely process through (Frame List Current Index -1) when it is servicing an interrupt. CRC Error/Time-Out A CRC/Time-Out error occurs when a packet transmitted from the Intel ® 6300ESB ICH to a USB device or a packet transmitted from a USB device to the Intel ® 6300ESB ICH generates a CRC error. The Intel® 6300ESB ICH is informed of this event by a time-out from the USB device or by the Intel ® 6300ESB ICH’s CRC checker generating an error on reception of the packet. Additionally, a USB bus time-out occurs when USB devices do not respond to a transaction phase within 19-bit times of an EOP. Either of these conditions will cause the C_ERR field of the TD to decrement. When the C_ERR field decrements to zero, the following occurs:
- The Active bit in the TD is cleared
- The Stalled bit in the TD is set
- The CRC/Time-out bit in the TD is set.
- At the end of the frame, the USB Error Interrupt bit is set in the HC status register. When the CRC/Time out interrupt is enabled in the Interrupt Enable register, a hardware interrupt will be signaled to the system. Interrupt on Completion Transfer Descriptors contain a bit that may be set to cause an interrupt on their completion. The completion of the transaction associated with that block causes the USB Interrupt bit in the HC Status Register to be set at the end of the frame in which the transfer completed. When a TD is encountered with the IOC bit set to 1, the IOC bit in the HC Status register is set to 1 at the end of the frame when the active bit in the TD is set to 0 (even when it was set to zero when initially read). When the IOC Enable bit of Interrupt Enable register (bit 2 of I/O offset 04h) is set, a hardware interrupt is signaled to the system. The USB Interrupt bit in the HC status register is set either when the TD completes successfully or because of errors. When the completion is because of errors, the USB Error bit in the HC status register is also set. Short Packet Detect
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 215 5—Intel ® 6300ESB ICH A transfer set is a collection of data which requires more than one USB transaction to completely move the data across the USB interface. An example might be a large print file which requires numerous TDs in multiple frames to completely transfer the data. Reception of a data packet that is less than the endpoint’s Max Packet size during Control, Bulk or Interrupt transfers signals the completion of the transfer set, even when there are active TDs remaining for this transfer set. Setting the SPD bit in a TD indicates to the HC to set the USB Interrupt bit in the HC status register at the end of the frame in which this event occurs. This feature streamlines the processing of input on these transfer types. When the Short Packet Interrupt Enable bit in the Interrupt Enable register is set, a hardware interrupt is signaled to the system at the end of the frame where the event occurred. Serial Bus Babble When a device transmits on the USB for a time greater than its assigned Max Length, it is said to be babbling. Since isochrony may be destroyed by a babbling device, this error results in the Active bit in the TD being cleared to 0 and the Stalled and Babble bits being set to one. The C_ERR field is not decremented for a babble. The USB Error Interrupt bit in the HC Status register is set to 1 at the end of the frame. A hardware interrupt is signaled to the system. When an EOF babble was caused by the Intel ® 6300ESB ICH (due to incorrect schedule for instance), the Intel® 6300ESB ICH will force a bit stuff error followed by an EOP and the start of the next frame. Stalled This event indicates that a device/endpoint returned a STALL handshake during a transaction or that the transaction ended in an error condition. The TDs Stalled bit is set and the Active bit is cleared. Reception of a STALL does not decrement the error counter. A hardware interrupt is signaled to the system. Data Buffer Error This event indicates that an overrun of incoming data or a under-run of outgoing data has occurred for this transaction. This would generally be caused by the Intel 6300ESB ICH not being able to access required data buffers in memory within necessary latency requirements. Either of these conditions will cause the C_ERR field of the TD to be decremented. When C_ERR decrements to zero, the Active bit in the TD is cleared, the Stalled bit is set, the USB Error Interrupt bit in the HC Status register is set to 1 at the end of the frame and a hardware interrupt is signaled to the system. Bit Stuff Error A bit stuff error results from the detection of a sequence of more that 6 ones in a row within the incoming data stream. This will cause the C_ERR field of the TD to be decremented. When the C_ERR field decrements to 0, the Active bit in the TD is cleared to 0, the Stalled bit is set to one, the USB Error Interrupt bit in the HC Status register is set to 1 at the end of the frame and a hardware interrupt is signaled to the system.
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5.17.7.3 Non-Transaction Based Interrupts
6300ESB ICH halts and immediately issues a hardware interrupt to the system. the USB to be brought out of the suspend state and returned to normal operation. This interrupt cannot be disabled through the Interrupt Enable register. Stop bit in the Command register to prevent further execution of the scheduled TDs. This interrupt cannot be disabled through the Interrupt Enable register.
5.17.8 USB Power Management
The Host Controller may be put into a suspended state and its power may be removed. event, the system will wake up and an SCI will be generated. Table 104. Bits Maintained in Low Power States
2 Port Enabled/Disabled
8 Low Speed Device Attached
12 Suspend
5.17.9 USB Legacy Keyboard Operation
the USB keyboard into ports 60/64. Keyboard/Mouse Control Registers. Table 105. USB Legacy Keyboard/Mouse Control Register Bit Implementation be implemented separately for each controller or shared and aliased.
13 PCI Interrupt
enable Each bit provides individual host control.
12 SMI Caused by
status Individual status bits for each controller.
11 SMI Caused by
be implemented separately for each controller or shared and aliased.
10 SMI Caused by
be implemented separately for each controller or shared and aliased.
9 SMI Caused by
be implemented separately for each controller or shared and aliased.
8 SMI Caused by
be implemented separately for each controller or shared and aliased. together and used to enable the SMI based on bit 15.
6 Pass Through
A20Gate Pass-Through Enable (bit 5) in all of the host controllers.
5 A20Gate Pass-
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equivalent) is on the LPC bus. This legacy operation is performed through SMM space. responsibility to logically AND the value with the appropriate enable bits. observed. This method is used on MPIIX and has been validated. for the “Pass-through” case. The state table for the diagram is shown in Table 106. Enable Each bit provides individual host control.
3 SMI on Port 64
together and used to enable the SMI based on bit 11.
2 SMI on Port 64
used to enable the SMI based on bit 10.
1 SMI on Port 60
enable the SMI based on bit 9.
0 SMI on Port 60
enable the SMI based on bit 8.
Figure 21. USB Legacy Keyboard Flow Diagram
60 READ
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Table 106. USB Legacy Keyboard State Transitions Standard D1 command. Cycle passed through to 8042. through to 8042 and if SMI# generated. through to 8042 and if SMI# generated. through to 8042 and if SMI# generated. through to 8042 and if SMI# generated. the 8042 may chose to ignore it. through Bit 3 in Config Register. No SMI# generated. part of the double-trigger sequence. Config Register is set, then SMI# should be generated. enabled in Bit 2 of Config Register. PSTATE remains 1.
- PSTATE goes to 0. Bit 7 in Config Space
determines if SMI# should be generated. Config Register is set, then SMI# should be generated. enabled in Bit 2 of Config Register. PSTATE remains 1.
5.18 USB EHCI Controller (D29:F7)
5.18.1 Overview
5.18.2 EHC Initialization
complete power cycle in which the suspend well and core well have been off. Config Register is set, then SMI# should be generated. Config Register is set, then SMI# should be generated.
- If bit 7 of the Extended Test Mode Register 1 (D31:F0, offset F4h ETR1, section 9.1.36) is set. Port 60/64h
- System Software should ensure that the host controller and an external PCI agent are not simultaneously
supported and the results may be indeterminate. Table 107. UHCI vs. EHCI
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5.18.2.1 Power On
The suspend well is a “deeper” power plane than the core well, which means that the suspend well is always functional when the core well is functional but the core well may not be functional when the suspend well is. Therefore, the suspend well reset pin (RSMRST#) deasserts before the core well reset pin (PWROK) rises. 1. The suspend well reset deasserts, leaving all registers and logic in the suspend well in the default state. However , it is not possible to read any registers until after the core well reset deasserts. Note that normally the suspend well reset will only occur when a desktop system is unplugged or the battery is removed from a mobile system. In other words, suspend well resets are not easily achieved by software or the end-user. This step will typically not occur immediately before the remaining steps. 2. The core well reset deasserts, leaving all registers and logic in the core well in the default state. The EHC configuration space is accessible at this point. Note that the core well reset may (and typically does) occur without the suspend well reset asserting. This means that all of the Configure Flag and Port Status and Control bits (and any other suspend-well logic) may be in any valid state at this time.
5.18.2.2 BIOS Initialization
BIOS performs a number of platform customization steps after the core well has powered up as described in the Intel ® 6300ESB ICH BIOS Specification.
5.18.2.3 Driver Initialization
See Chapter 4 of the Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 0.96.
5.18.2.4 EHC Resets
In addition to the standard Intel ® 6300ESB ICH hardware resets, portions of the EHC are reset by the HCRESET bit and the transition from the D3hot device power management state to the D0 state. The effects of each of these resets are:
5.18.3 Data Structures in Main Memory
for Universal Serial Bus, Revision 0.96. Table 108. EHC Resets
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performs any pending asynchronous traffic until the end of the microframe (EOF1). ports are idle during this time.
5.18.4.1 Periodic List Execution
the two buffered control structures.
5.18.4.1.1 Read Policies for Periodic DMA
The Periodic DMA engine performs reads for the following structures. Table 109. Read Policies for Periodic DMA frame list is not internally cached across microframes. iTD 23 Only the 64-bit addressing format is supported. siTD 9 Only the 64-bit addressing format is supported. qTD 13 Only the 64-bit addressing format is supported. Queue Head 17 Only the 64-bit addressing format is supported. setting of the Read Request Max Length field.
unless all three of the following conditions are met.
- The HCHalted bit is 0 (memory space, offset 04h, bit 12). Software clears this bit indirectly by setting the RUN/STOP bit to 1. See Section 11.2.2.2, “Offset CAPLENGTH + 04 - 07h: USB EHCI STS—USB EHCI Status” for more information.
- The Periodic Schedule Status bit is 1 (memory space, offset 04h, bit 14). Software sets this bit indirectly by setting the Periodic Schedule Enable Bit to 1. See Section 11.2.2.2, “Offset CAPLENGTH + 04 - 07h: USB EHCI STS—USB EHCI Status” for more information.
- The Bus Master Enable bit is 1 (configuration space, offset 04h, bit 2). See Section 11.1.1, “Offset 04 - 05h: Command Register” for more information. Note: Prefetching is limited to the current and next microframes only. Note: Once the PDE checks the length of a periodic packet against the remaining time in the microframe (late-start check) and decides that there is not enough time to run it on the wire, then the EHC switches over to run asynchronous traffic.
5.18.4.1.2 Write Policies for Periodic DMA
The Periodic DMA engine performs writes for the following reasons. Table 110. Write Policies for Periodic DMA fields are re-written with the original value. Overlay 14 Only the 64-bit addressing format is supported. Status Write 5 DWORDs 14:27h are written.
- The Periodic DMA Engine (PDE) will only generate writes after a transaction is executed on
- Status writes are always performed after In Data writes for the same transaction.
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5.18.4.2 Asynchronous List Execution
5.18.4.2.1 Read Policies for Asynchronous DMA
The Asynchronous DMA engine performs reads for the following structures.
- The HCHalted bit is 0 (memory space, offset 04h, bit 12). Software clears this bit indirectly by setting the RUN/STOP bit to 1.
- The Asynchronous Schedule Status bit is 1 (memory space, offset 04h, bit 15). Software sets this bit indirectly by setting the Asynchronous Schedule Enable Bit to 1. See Section 11.2.2.2, “Offset CAPLENGTH + 04 - 07h: USB EHCI STS—USB EHCI Status” for more information.
- The Bus Master Enable bit is 1 (configuration space, offset 04h, bit 2). See Section 11.1.1, “Offset 04 - 05h: Command Register” for more information.
- The ADE is not sleeping due to the detection of an empty schedule. There is not one single bit that indicates this state. However, the sleeping state is entered when the Queue Head with the H bit set is encountered when the Reclamation bit in the USB EHCI Status register is 0. See Section 11.2.2.2, “Offset CAPLENGTH + 04 - 07h: USB EHCI STS—USB EHCI Status” for information regarding offset 04h, bit 13. Note: The ADE does not fetch data when a QH is encountered in the Ping state. An Ack handshake in response to the Ping results in the ADE writing the QH to the Out state, which results in the fetching and delivery of the Out Data on the next iteration through the asynchronous list. Note: Once the ADE checks the length of an asynchronous packet against the remaining time in the microframe (late-start check) and decides that there is not enough time to run it on the wire, then the EHC stops all activity on the USB ports for the remainder of that microframe. Note: Once the ADE detects an “empty” asynchronous schedule as described in Section 4 of the EHCI specification, it implements a waking mechanism like the one in the example. The amount of time that the ADE “sleeps” is 10 µs ± 30 ns.
Table 111. Read Policies for Asynchronous DMA qTD 13 Only the 64-bit addressing format is supported. Queue Head 17 Only the 64-bit addressing format is supported. setting of the Read Request Max Length field.
5.18.4.2.2 Write Policies for Asynchronous DMA
The Asynchronous DMA engine performs writes for the following reasons.
5.18.5 Data Encoding and Bit Stuffing
See Chapter 8 of the Universal Serial Bus Revision 2.0 Specification .
5.18.6 Packet Formats
See Chapter 8 of the Universal Serial Bus Revision 2.0 Specification .
5.18.7 USB EHCI Interrupts and Error Conditions
interrupt and error-reporting functionality.
- Based on the EHC’s Buffer sizes and buffer management policies, the Data Buffer Error may not occur on the Intel ® 6300ESB ICH.
- Master Abort and Target Abort responses from Hub Interface on EHC-initiated read packets will be treated as Fatal Host Errors. The EHC halts when these conditions are encountered.
- The Intel® 6300ESB ICH may assert the interrupts which are based on the interrupt threshold as soon as the status for the last complete transaction in the interrupt interval has been posted in the internal write buffers. The requirement in the EHCI Specification (that the status is written to memory) is met internally, even though the write may not be seen on the Hub Interface before the interrupt is asserted.
- Since the Intel® 6300ESB ICH supports the 1024-element Frame List size, the Frame List Rollover interrupt occurs every 1024 milliseconds.
Table 112. Write Policies for Asynchronous DMA 34 DWORDs 14:1Fh are written.
- The Asynchronous DMA Engine (ADE) will only generate writes after a transaction is executed
- Status writes are always performed after In Data writes for the same transaction.
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- The Intel® 6300ESB ICH delivers interrupts using PIRQ#[H].
- The Intel® 6300ESB ICH does not modify the CERR count on an Interrupt IN when the “Do Complete-Split” execution criteria are not met.
- For complete-split transactions in the Periodic list, the “Missed Microframe” bit does not get set on a control-structure-fetch that fails the late-start test. When subsequent accesses to that control structure do not fail the late-start test, then the “Missed Microframe” bit will get set and written back.
5.18.7.1 Aborts on USB EHCI-Initiated Memory Reads
When a read initiated by the EHC is aborted, the EHC treats it as a fatal host error. The following actions are taken when this occurs:
- The Host System Error status bit is set. See Section 11.2.2.2, “Offset CAPLENGTH + 04 - 07h: USB EHCI STS—USB EHCI Status” for information regarding offset 04h, bit 4.
- The DMA engines are halted after completing up to one more transaction on the USB interface.
- When enabled (by the Host System Error Enable), an interrupt is generated. See Section 11.2.2.3, “Offset CAPLENGTH + 08 - 0Bh: USB EHCI INTR—USB EHCI Interrupt Enable” for information regarding offset 08h, bit 4.
- When the status is Master Abort, the Received Master Abort bit in configuration space is set. Section 11.1.2, “Offset 06 - 07h: Device Status” for information regarding offset 06h, bit 13.
- When the status is Target Abort, the Received Target Abort bit in configuration space is set. Section 11.1.2, “Offset 06 - 07h: Device Status” for information regarding offset 06h, bit 12.
- When enabled (by the SERR Enable bit in the function’s configuration space, see Section 11.1.1, “Offset 04 - 05h: Command Register”, offset 04h, bit 8), the Signaled System Error bit is set by the Intel ® 6300ESB ICH when it signals SERR# (internally). Section 11.1.2, “Offset 06 - 07h: Device Status” for information regarding offset 06h, bit 14.
5.18.8 USB EHCI Power Management
5.18.8.1 Pause Feature
This feature allows platforms, especially mobile systems, to dynamically enter low- power states during brief periods when the system is idle, i.e., between keystrokes. This is useful for enabling power management features like C3, C4, and Intel ® SpeedStep® technology in the Intel® 6300ESB ICH. The policies for entering these states typically are based on the recent history of system bus activity to incrementally enter deeper power management states. Normally, when the EHC is enabled, it regularly accesses main memory while traversing the DMA schedules looking for work to do; this activity is viewed by the power management software as a non-idle system, thus preventing the power managed states to be entered. Suspending all of the enabled ports may prevent the memory accesses from occurring, but there is an inherent latency overhead with entering and exiting the suspended state on the USB ports that makes this unacceptable for the purpose of dynamic power management. As a result, the EHCI software drivers are allowed to pause the EHC’s DMA engines when it knows that the traffic patterns of the attached devices may afford the delay. The pause only prevents the EHC from generating memory accesses; the SOF packets continue to be generated on the USB ports (unlike the suspended state).
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5.18.8.2 Suspend Feature
The EHCI Specification describes the details of Port Suspend and Resume in detail in Section 4.3.
5.18.8.3 ACPI Device States
The USB EHCI function only supports the D0 and D3 PCI Power Management states. Notes regarding the Intel® 6300ESB ICH implementation of the Device States: 1. The EHC hardware does not inherently consume any more power when it is in the D0 state than it does in the D3 state. However, software is required to suspend or disable all ports prior to entering the D3 state such that the maximum power consumption is reduced. 2. In the D0 state, all implemented EHC features are enabled. 3. In the D3 state, accesses to the EHC memory-mapped I/O range will master abort. Note that, since the Debug Port uses the same memory range, the Debug Port is only operational when the EHC is in the D0 state. 4. In the D3 state, the EHC interrupt must never assert for any reason. The internal PME# signal is used to signal wake events, etc. 5. When the Device Power State field is written to D0 from D3, an internal reset is generated. See section EHC Resets for general rules on the effects of this reset. 6. Attempts to write any other value into the Device Power State field other than 00b (D0 state) and 11b (D3 state) will complete normally without changing the current value in this field. See Section 11.1.17, “Offset 54 - 55h: Power Management Control/Status” for information regarding offset 54h, bits [1:0].
5.18.8.4 ACPI System States
The EHC behavior as it relates to other power management states in the system is summarized in the following list:
- The System is always in the S0 state when the EHC is in the D0 state. However, when the EHC is in the D3 state, the system may be in any power management state (including S0).
- When in D0, the Pause feature (See Section 5.18.8.1, “Pause Feature”) enables dynamic processor low-power states to be entered.
- All core well logic is reset in the S3/S4/S5 states (core power turns off).
5.18.8.5 Low-power system Considerations
The Intel® 6300ESB ICH USB EHCI implementation does not behave differently in low power configurations. However, some features may be especially useful for the low power configurations.
- Low-power systems are not likely to use all four of the USB ports that are provided on the Intel® 6300ESB ICH. With this in mind, the Intel ® 6300ESB ICH provides mechanisms for changing the structural parameters of the EHC and hiding unused USB UHCI controllers. See Intel ® 6300ESB ICH BIOS Specification on how BIOS should configure the Intel® 6300ESB ICH.
- Low-power systems may want to minimize the conditions that will wake the system. The Intel® 6300ESB ICH implements the “Wake Enable” bits in the Port Status and Control registers, as specified in the EHCI spec, for this purpose.
- Low-power systems may want to cut suspend well power to some or all USB ports when in a low-power state. The Intel ® 6300ESB ICH implements the optional Port Wake Capability Register in the EHC Configuration Space for this platform-specific information to be communicated to software.
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5.18.9 Interaction with Classic Host Controllers
and the USB UHCI Controller at D29:F1 shares ports 2 and 3 with the EHCI Controller. other than the muxing control which is provided as part of the EHCI Controller. indicates all of the logic that is part of the Enhanced Host Controller cluster.
5.18.9.1 Port-Routing Logic
information that is generated by the port-routing logic. event is recorded in both controllers’ status registers. exiting a system sleep state in which the core power is turned off. Figure 22. Intel ® 6300ESB ICH-USB Port Connections
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 231 5—Intel ® 6300ESB ICH The Intel® 6300ESB ICH also allows the USB Debug Port traffic to be routed in and out of Port #0. When in this mode, the Enhanced Host Controller is the owner of Port #0.
5.18.9.2 Device Connects
Section 4.2 of the EHCI Specification describes the details of handling Device Connects. There are four general scenarios that are summarized below. See Section 11.2.2.8, “Offset CAPLENGTH + 40 - 43h: CONFIGFLAG—Configure Flag Register” . 1. Configure Flag = 0 and a USB Full-speed/Low-speed -only Device is connected In this case, the USB UHCI Controller is the owner of the port both before and after the connect occurs. The EHC (except for the port-routing logic) never sees the connect occur. The UHCI driver handles the connection and initialization process. 2. Configure Flag = 0 and an USB High-speed-capable Device is connected In this case, the USB UHCI Controller is the owner of the port both before and after the connect occurs. The EHC (except for the port-routing logic) never sees the connect occur. The UHCI driver handles the connection and initialization process. Since the USB UHCI Controller does not perform the high-speed chirp handshake, the device operates in compatible mode. 3. Configure Flag = 1 and a USB Full-speed/Low-speed-only Device is connected In this case, the USB EHCI Controller is the owner of the port before the connect occurs. The EHCI driver handles the connection and performs the port reset. After the reset process completes, the EHC hardware has cleared (not set) the Port Enable bit in the EHC’s PORTSC register. The EHCI driver then writes a 1 to the Port Owner bit in the same register, causing the USB UHCI Controller to see a connect event and the EHC to see an “electrical” disconnect event. The UHCI driver and hardware handle the connection and initialization process from that point on. The EHCI driver and hardware handle the perceived disconnect. 4. Configure Flag = 1 and an USB High-speed-capable Device is connected In this case, the USB EHCI Controller is the owner of the port before, and remains the owner after, the connect occurs. The EHCI driver handles the connection and performs the port reset. After the reset process completes, the EHC hardware has set the Port Enable bit in the EHC’s PORTSC register. The port is functional at this point. The USB UHCI Controller continues to see an unconnected port.
5.18.9.3 Device Disconnects
Section 4.2 of the EHCI Specification describes the details of handling Device Connects. There are three general scenarios that are summarized below. See Section 11.2.2.8, “Offset CAPLENGTH + 40 - 43h: CONFIGFLAG—Configure Flag Register” . 1. Configure Flag = 0 and the device is disconnected. In this case, the USB UHCI Controller is the owner of the port both before and after the disconnect occurs. The EHC (except for the port-routing logic) never sees a device attached. The UHCI driver handles disconnection process. 2. Configure Flag = 1 and a USB Full-speed/Low-speed-capable Device is disconnected. In this case, the USB UHCI Controller is the owner of the port before the disconnect occurs. The disconnect is reported by the USB UHCI Controller
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- Configure Flag = 1 and a USB High-speed-capable Device is disconnected.
5.18.9.4 Effect of Resets on Port-Routing Logic
entering and exiting a system sleep state in which the core power is turned off. is unchanged from USB UHCI (See Section 5.17.9, “USB Legacy Keyboard Operation”). more sophisticated control of the generation of SMIs. the ability for new debugger software to interact with devices on a USB EHCI port.
- Must be operational before USB EHCI drivers are loaded.
- Must work even when the port is disabled.
- Must work even though non-configured port is default-routed to the classic controller. Note that the Debug Port cannot be used to debug an issue that requires a classic USB device on Port #0 using the UHCI drivers.
- Must allow normal system USB EHCI traffic in a system that may only have one USB port.
- Debug Port device (DPD) must be High-Speed capable and connect to a High-Speed port on Intel ® 6300ESB ICH systems.
- Debug Port FIFO must always make forward progress (a bad status on USB is simply presented back to software)
- The Debug Port FIFO is only given one USB access per microframe
Table 113. Effect of Resets on Port-Routing Logic
USB EHCI software is broken, or where the USB EHCI software is being debugged.
- Only works with an external USB 2.0 debug device (console)
- Implemented for a specific port on the host controller
- Operational anytime the port is not suspended AND the host controller is in D0 power state.
- Capability is interrupted when port is driving USB RESET 5.18.11.2Theory of Operation There are two operational modes for the USB debug port: 1. Mode 1 is when the USB port is in a disabled state from the viewpoint of a standard host controller driver. In Mode 1, the Debug Port controller is required to generate a “keepalive” packets less than 2 ms apart to keep the attached debug device from suspending. The keepalive packet should be a standalone 32-bit SYNC field. 2. Mode 2 is when the host controller is running (i.e., Host controller’s Run/Stop# bit is 1). In Mode 2, the normal transmission of SOF packets will keep the debug device from suspending. Detail for the registers mentioned in the next sections can be found in Section 11.2.3, “USB 2.0-Based Debug Port Register” and in Section 11.2, “Memory-Mapped I/O Registers”. Behavioral Rules: 1. In both modes 1 and 2, the Debug Port controller must check for software requested debug transactions at least every 125 microseconds. 2. When the debug port is enabled by the debug driver, and the standard host controller driver resets the USB port, USB debug transactions are held off for the duration of the reset and until after the first SOF is sent. 3. When the standard host controller driver suspends the USB port, then USB debug transactions are held off for the duration of the suspend/resume sequence and until after the first SOF is sent. 4. The ENABLED_CNT bit in the debug register space is independent of the similar port control bit in the associated Port Status and Control register. Table 114 describes the debug port behavior related to the state of bits in the debug registers as well as bits in the associated Port Status and Control register .
Table 114. USB Debug Port Behavior (Sheet 1 of 2) 0X X X X Debug port is not being used. 10 X X X Debug port is not being used.
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- The debug port is enabled.
- The debug software sets the GO_CNT bit.
- The WRITE_READ#_CNT bit is set.
The sequence of the transaction is listed below.
- Software sets the appropriate values in these bits:
Table 114. USB Debug Port Behavior (Sheet 2 of 2)
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 235 5—Intel ® 6300ESB ICH 2. The debug port controller sends a token packet consisting of: a. SYNC b. TOKEN_PID_CNT field c. USB_ADDRESS_CNT field d. USB_ENDPOINT_CNT field e. 5-bit CRC field 3. After sending the token packet, the debug port controller sends a data packet consisting of a. SYNC b. SEND_PID_CNT field c. The number of data bytes indicated in DATA_LEN_CNT from the DATA_BUFFER d. 16-bit CRC Note: A DATA_LEN_CNT value of zero is valid in which case no data bytes would be included in the packet. 4. After sending the data packet, the controller waits for a handshake response from the debug device.
- When a handshake is received, the debug port controller: a. Places the received PID in the RECEIVED_PID_STS field b. Resets the ERROR_GOOD#_STS bit c. Sets the DONE_STS bit
- When no handshake PID is received, the debug port controller: a. Sets the EXCEPTION_STS field to 001b b. Sets the ERROR_GOOD#_STS bit c. Sets the DONE_STS bit 5.18.11.2.2IN Transactions An IN transaction receives data from the debug device. It may occur only when the following are true: 1. The debug port is enabled 2. The debug software sets the GO_CNT bit 3. The WRITE_READ#_CNT bit is reset The sequence of the transaction is: 1. Software sets the appropriate values in the following bits: — USB_ADDRESS_CNF —U S B _ E N D P O I N T _ C N F — TOKEN_PID_CNT[7:0] —D A T A _ L E N _ C N T — WRITE_READ#_CNT ( Note: This will always be 0 for IN transactions.) —G O _ C N T (Note: This will always be 1 to initiate the transaction.) 2. The debug port controller sends a token packet consisting of: a. SYNC b. TOKEN_PID_CNT field
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c. USB_ADDRESS_CNT field d. USB_ENDPOINT_CNT field e. 5-bit CRC field. 3. After sending the token packet, the debug port controller waits for a response from the debug device. When a response is received: a. The received PID is placed into the RECEIVED_PID_STS field b. Any subsequent bytes are placed into the DATA_BUFFER c. The DATA_LEN_CNT field is updated to show the number of bytes that were received after the PID. 4. When valid packet was received from the device that was one byte in length (indicating it was a handshake packet), then the debug port controller: a. Resets the ERROR_GOOD#_STS bit b. Sets the DONE_STS bit 5. When valid packet was received from the device that was more than one byte in length (indicating it was a data packet), then the debug port controller: a. Transmits an ACK handshake packet b. Resets the ERROR_GOOD#_STS bit c. Sets the DONE_STS bit 6. When no valid packet is received, then the debug port controller: a. Sets the EXCEPTION_STS field to 001b b. Sets the ERROR_GOOD#_STS bit c. Sets the DONE_STS bit.
5.18.11.2.3 Debug Software
There are two mutually exclusive conditions that debug software must address as part of its startup processing: 1. The EHCI has been initialized by system software 2. The EHCI has not been initialized by system software Debug software may determine the current ‘initialized’ state of the EHCI by examining “Offset CAPLENGTH + 40 - 43h: CONFIGFLAG—Configure Flag Register” for information regarding offset 40h, bit 0. When this flag is set, then system software has initialized the EHCI. Otherwise, the EHCI should not be considered initialized. Debug software will initialize the debug port registers depending on the state the EHCI. However, before this may be accomplished, debug software must determine which root USB port is designated as the debug port. Determining the Debug Port Debug software may determine which USB root port has been designated as the debug port by examining bits 20:23 of the EHCI Host Controller Structural Parameters register. See Section 11.2.1.3, “Offset 04 - 07h: HCSPARAMS—Host Controller Structural Parameters” for information regarding offset 04h. This 4-bit field represents the numeric value assigned to the debug port (i.e., 0000=port 0). Debug Software Startup with Non-Initialized EHCI
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 237 5—Intel ® 6300ESB ICH Debug software may attempt to use the debug port after setting the OWNER_CNT bit in the Control/Status Register, Section 11.2.3.1, “Offset 00h: Control/Status Register”, offset 00h, bit 30, and the Current Connect Status bit in the appropriate (See Determining the Debug Port) PORTSC register is set. See Section 11.2.2.9, “PORTSC- Port N Status and Control” for information regarding bit 0. When the Current Connect Status bit is not set, then debug software may choose to terminate or it may choose to wait until a device is connected. When a device is connected to the port, then debug software must reset/enable the port. Debug software does this by setting and then clearing the Port Reset bit the PORTSC register. To ensure a successful reset, debug software should wait at least 50 ms before clearing the Port Reset bit. Due to possible delays, this bit may not change to zero immediately; reset is complete when this bit reads as zero. Software must not continue until this bit reads zero. When a high-speed device is attached, the EHCI will automatically set the Port Enabled/Disabled bit in the PORTSC register and the debug software may proceed. Debug software should set the ENABLED_CNT bit in the Debug Port Control/Status register, and then reset (clear) the Port Enabled/Disabled bit in the PORTSC register (so that the system host controller driver doesn't see an enabled port when it is first loaded). Debug Software Startup with Initialized EHCI Debug software may attempt to use the debug port when the Current Connect Status bit in the appropriate (See Determining the Debug Port) PORTSC register is set. When the Current Connect Status bit is not set, then debug software may choose to terminate or it may choose to wait until a device is connected. When a device is connected, then debug software must set the OWNER_CNT bit and then the ENABLED_CNT bit in the Debug Port Control/Status register . See Section 11.2.3.1, “Offset 00h: Control/Status Register” for information regarding offset 00h, bits 30 and 28. Determining Debug Peripheral Presence After enabling the debug port functionality, debug software may determine when a debug peripheral is attached by attempting to send data to the debug peripheral. When all attempts result in an error (Exception bits in the Debug Port Control/Status register indicates a Transaction Error), the attached device is not a debug peripheral. See Section 11.2.3.1, “Offset 00h: Control/Status Register” for information regarding offset 00h, bits [9:7]. When the debug port peripheral is not present, then debug software may choose to terminate or it may choose to wait until a debug peripheral is connected.
5.19 SMBus Controller Functional Description
(D31:F3)
5.19.1 Overview
The Intel® 6300ESB ICH provides an SMBus 2.0 compliant Host Controller as well as an SMBus slave interface. The host controller provides a mechanism for the processor to initiate communications with SMBus peripherals (slaves). The Intel ® 6300ESB ICH is also capable of operating in a mode in which it may communicate with I 2C compatible devices.
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The Intel® 6300ESB ICH may perform SMBus messages with either packet error checking (PEC) enabled or disabled. The actual PEC calculation and checking is performed in software.The SMBus Host Controller logic may automatically append the CRC byte when configured to do so. The Slave Interface allows an external master to read from or write to the Intel 6300ESB ICH. Write cycles may be used to cause certain events or pass messages, and the read cycles may be used to determine the state of various status bits. The Intel 6300ESB ICH’s internal Host Controller cannot access the Intel® 6300ESB ICH’s internal Slave Interface. The Intel® 6300ESB ICH SMBus logic exists in Device 31:Function 3 configuration space, and consists of a transmit data path, and host controller. The transmit data path provides the data flow logic needed to implement the seven different SMBus command protocols and is controlled by the host controller. The Intel ® 6300ESB ICH SMBus controller logic is clocked by RTC clock. The SMBus Address Resolution Protocol (ARP) is supported by using the existing host controller commands through software, except for the new Host Notify command (which is actually a received message). The programming model of the host controller is combined into two portions: a PCI configuration portion, and a system I/O mapped portion. All static configuration, such as the I/O base address, is done through the PCI configuration space. Real-time programming of the Host interface is done in system I/O space.
5.19.2 Host Controller
The SMBus Host Controller is used to send commands to other SMBus slave devices. Software sets up the host controller with an address, command, and, for writes, data and optional PEC; and then tells the controller to start. When the controller has finished transmitting data on writes, or receiving data on reads, it will generate an SMI# or interrupt, when enabled. The host controller supports seven command protocols of the SMBus interface (see the SMBus Specification): Quick Command, Send Byte, Receive Byte, Write Byte/Word, Read Byte/Word, ProcessCall, Block Read, Block Write and Block Write-Block Read process call. The SMBus Host Controller requires that the various data and command fields be setup for the type of command to be sent. When software sets the START bit, the SMBus Host Controller will perform the requested transaction, and interrupt the processor (or generate an SMI#) when the transaction is completed. Once a START command has been issued, the values of the “active registers” (Host Control, Host Command, Transmit Slave Address, Data 0, Data 1) should not be changed or read until the interrupt status bit (INTR) has been set (indicating the completion of the command). Any register values needed for computation purposes should be saved prior to issuing of a new command, as the SMBus Host Controller will update all registers while completing the new command. Using the SMBus Host Controller to send commands to the Intel ® 6300ESB ICH's SMBus slave port is supported. The Intel® 6300ESB ICH supports slave functionality, including the Host Notify protocol, on the SMLink pins when in TCO compatible mode. Therefore, in order to be fully compliant with the SMBus 2.0 specification (which requires the Host Notify cycle), the SMLink and SMBus signals must be tied together externally. However, this requirement to tie both SMLink and SMBus signals externally is not needed in advanced TCO mode as the slave functionality is available on the SMBus pins.
5.19.2.1 Command Protocols
the timeout period, assert a STOP condition and then releases SMBCLK and SMBDATA. ® 6300ESB ICH to force a timeout when it is not performing a transaction. When programmed for a Quick Command, the Transmit Slave Address Register is sent. transfer. The format of the protocol is shown in Table 116 and Table 117. Table 115. Quick Protocol
1 Start Condition
9 Read / Write Direction
10 Acknowledge from
11 Stop
Table 116. Send/Receive Byte Protocol without PEC
1 Start 1 Start
10 Acknowledge from slave 10 Acknowledge from slave
19 Acknowledge from slave 19 NOT Acknowledge
20 Stop 20 Stop
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Table 117. Send/Receive Byte Protocol with PEC
19 Acknowledge from slave 19 Acknowledge
28 Acknowledge from slave 28 Not Acknowledge
29 Stop 29 Stop
Table 118. Write Byte/Word Protocol without PEC
9 Write 9 Write
19 Acknowledge from slave 19 Acknowledge from slave
28 Acknowledge from Slave 28 Acknowledge from Slave
29 Stop 29–36 Data Byte High - 8 bits
37 Acknowledge from slave
38 Stop
Table 119. Write Byte/Word Protocol with PEC
shown in Table 120 and Table 121.
37 Acknowledge from Slave 37 Acknowledge from slave
38 Stop 38–45 PEC
46 Acknowledge from slave
47 Stop
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Table 120. Read Byte/Word Protocol without PEC
20 Repeated Start 20 Repeated Start
28 Read 28 Read
29 Acknowledge from slave 29 Acknowledge from slave
38 NOT acknowledge 38 Acknowledge
39 Stop 39–46 Data Byte High from slave - 8 bits
47 NOT acknowledge
48 Stop
Table 121. Read Byte/Word Protocol with PEC
38 Acknowledge 38 Acknowledge
47 NOT Acknowledge 47 Acknowledge
48 Stop 48–55 PEC from slave
56 NOT acknowledge
57 Stop
a Read Word, but without a second command or stop condition. command with I2C_EN set and the PEC_EN bit set produces undefined results. format of the protocol is shown in Table 122 and Table 123. Register (SMBus I/O register, offset 04h) needs to be 0. Table 122. Process Call Protocol without PEC
10 Acknowledge from Slave
19 Acknowledge from slave
28 Acknowledge from slave
38 Repeated Start
46 Read
47 Acknowledge from slave
56 Acknowledge
65 NOT acknowledge
66 Stop
Table 123. Process Call Protocol with PEC (Sheet 1 of 2)
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the entire byte count has been transmitted/received. after all bytes it cares about have been sent or received. AAC bits to 0 when running this command. not be 0. A Block Read or Write is allowed to transfer a maximum of 32 data bytes. remaining bytes are stored in the Block Data Byte register. The format of the Block Read/Write protocol is shown in Table 124 and Table 125.
65 Acknowledge
74 NOT acknowledge
75 Stop
Table 123. Process Call Protocol with PEC (Sheet 2 of 2)
will not send the contents of the DATA0 register as part of the message. Table 124. Block Read/Write Protocol without PEC
20 Repeated Start
37 Acknowledge from Slave 29 Acknowledge from slave
46 Acknowledge from slave 38 Acknowledge
Table 125. Block Read/Write Protocol with PEC (Sheet 1 of 2)
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an offset (address) within the serial memory chips. both the PEC_EN and AAC bit to 0 when running this command. Register (SMBus I/O register, offset 04h) needs to be 0. with the format: shown in Table 126. Table 125. Block Read/Write Protocol with PEC (Sheet 2 of 2) Table 126. I 2C Block Read Protocol (Sheet 1 of 2)
The Intel® 6300ESB ICH will continue reading data from the peripheral until the NAK is received.
- M ≥ 1 byte
- N ≥ 1 byte
- M + N ≤ 32 bytes The read byte count does not include the PEC byte. The PEC is computed on the total message beginning with the first slave address and using the normal PEC computational rules. It is highly recommended that a PEC byte be used with the Block Write-Block Read Process Call. Software must do a read to the command register (offset 2h) to reset the 32 byte buffer pointer prior to reading the block data register. Note: There is no STOP condition before the repeated START condition, and a NACK signifies the end of the read transfer. Note: E32B bit in the Auxiliary Control register must be set when using this protocol.
28 Read
29 Acknowledge from slave
39 Acknowledge
47 Acknowledge
Table 126. I 2C Block Read Protocol (Sheet 2 of 2)
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Table 127. Block Write-Block Read Process Call Protocol With/Without PEC
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5.19.2.2 I 2C Behavior
When the I2C_EN bit is set, the Intel® 6300ESB ICH SMBus logic will instead be set to communicate with I2C devices. This forces the following changes: 1. The Process Call command will skip the Command code (and its associated acknowledge). 2. The Block Write command will skip sending the Byte Count (DATA0). In addition, the Intel® 6300ESB ICH will support the new I 2C Read command. This is independent of the I2C_EN bit. Note: When operating in I2C mode the Intel® 6300ESB ICH will not use the 32-byte buffer for block commands.
5.19.2.3 Heartbeat for Use with the External LAN Controller
The Heartbeat method allows the Intel® 6300ESB ICH to send messages to an external LAN Controller when the processor is otherwise unable to do so. It uses the SMLINK I/F between the Intel® 6300ESB ICH and the external LAN Controller. The actual Heartbeat message is a Block Write. Only eight bytes are sent.
5.19.3 Bus Arbitration
Several masters may attempt to get on the bus at the same time by driving the SMBDATA line low to signal a start condition. The Intel ® 6300ESB ICH must continuously monitor the SMBDATA line. When the Intel ® 6300ESB ICH is attempting to drive the bus to a ‘1’ by letting go of the SMBDATA line, and it samples SMBDATA low, then some other master is driving the bus and the Intel ® 6300ESB ICH must stop transferring data. When the Intel® 6300ESB ICH sees that it has lost arbitration, the condition is called a collision. The Intel® 6300ESB ICH will set the BUS_ERR bit in the Host Status Register, and when enabled, generate an interrupt or SMI#. The processor is responsible for restarting the transaction. When the Intel® 6300ESB ICH is a SMBus master, it will drive the clock. When the Intel® 6300ESB ICH is sending address or command as an SMBus master , or data bytes as a master on writes, it will drive data relative to the clock it is also driving. It will not start toggling the clock until the start or stop condition meets proper setup and hold time. The Intel® 6300ESB ICH will also ensure minimum time between SMBus transactions as a master. Note: The Intel® 6300ESB ICH supports the same arbitration protocol for both the SMBus and the System Management (SMLINK) interfaces.
5.19.4 Bus Timing
5.19.4.1 Clock Stretching
Some devices may not be able to handle their clock toggling at the rate that the Intel® 6300ESB ICH as an SMBus master would like. They have the capability of stretching the low time of the clock. When the Intel ® 6300ESB ICH attempts to release the clock (allowing the clock to go high), the clock will remain low for an extended period of time.
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5.19.4.2 Bus Time Out (Intel ® 6300ESB ICH as SMBus Master)
® 6300ESB ICH will discard the cycle, and set the DEV_ERR bit. waiting for a response. The 25 ms will be a count of 800 RTC clocks.
5.19.5 Interrupts/SMI#
setting the SMBUS_SMI_EN bit. control the generation of the interrupt, Host and Slave SMI, and Wake internal signals. for a particular scenario then the results for all of the activated rows will occur. Table 128. Enable for SMBALERT# Table 129. Enables for SMBus Slave Write and SMBus Host Events
11 H o s t S M I # g e n e r a t e d
5.19.6 SMBALERT#
5.19.7 SMBus CRC Generation and Checking
bit is set, or unspecified behavior will result. Auxiliary Status register at offset 0Ch will be set.
5.19.8 SMBus Slave Interface
- Supports decode of three types of messages: Byte Write, Byte Read, and Host Notify
- Receive Slave Address register: This is the address that the Intel ® 6300ESB ICH decodes. A default value is provided so that the slave interface may be used without the processor having to program this register.
- Receive Slave Data register in the SMBus I/O space that includes the data written by the external microcontroller
- Registers that the external microcontroller may read to get the state of the Intel ® 6300ESB ICH. See Table 135.
- Status bits to indicate that the SMLink/SMBus slave logic caused an interrupt or SMI# due to the reception of a message that matched the slave address. — Bit 0 of the Slave Status Register for the Host Notify command.
Table 130. Enables for the Host Notify Command
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SMBus slave logic until 1 second after both: RTEST# is high and RSMRST# is high. performing management activities to the slave logic.
5.19.8.1 Format of Slave Write Cycle
Slave I/F . The “Command” field (bits 11-18) indicate which register is being accessed. The Data field (bits 20-27) indicates the value that should be written to that register. Table 131. Slave Write Cycle Format
1 Start Condition External
10 ACK Intel® 6300ESB
19 ACK Intel® 6300ESB
28 ACK Intel® 6300ESB
29 Stop External
Table 132. Slave Write Registers 0 Command Register. See Table 133 for legal values written to this register.
4 Data Message Byte 0
5 Data Message Byte 1
contents of the data byte registers until they have been read by the system processor. it is being read. Intel® 6300ESB ICH will not attempt to cover this race condition (i.e. unpredictable results in this case). Table 133. Command Types (Sheet 1 of 2) awake, then an SMI# will be generated. system is already awake. The SMI handler should then clear this bit.
2 Unconditional Powerdown: This command sets the PWRBTNOR_STS bit, and
has the same effect as the Powerbutton Override occurring. register with bits 2:1 set to 1, but bit 3 set to 0. only be re enabled by assertion and deassertion of the RSMRST# signal. 6 WD Reload: Reload watchdog timer.
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5.19.8.2 Format of Read Command
Slave I/F. The “Command” field (bits 11-18) indicate which register is being accessed. The Data field (bits 30-37) contains the value that should be read from that register.
7 Reserved
Table 133. Command Types (Sheet 2 of 2) Table 134. Read Cycle Format (Sheet 1 of 2) Microcontroller Always zero.
20 Repeated Start External
28 Read External
29 ACK Intel® 6300ESB
38 NOT ACK External
39 Stop External
Table 135. Data Values for Slave Read Registers (Sheet 1 of 2) cover has probably been opened.
43 This bit will be set after the TCO timer times out a second time (Both TIMEOUT
and SECOND_TO_STS bits set). equal the level of the GPI[11]/SMBALERT# pin (high = 1, low = 0). returned FFh, which indicates that the FWH is probably blank. 51 Battery Low Status. ‘1’ when the BATLOW# pin is a ‘0’.
52 CPU Power Failure Status: ‘1’ when the CPUPWR_FLR bit in the
GEN_PMCON_2 register is set. Table 134. Read Cycle Format (Sheet 2 of 2)
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5.19.8.2.1 Behavioral Notes
protocol is followed, ignore bit 28, and proceed with the Slave Read cycle.
5.19.8.3 Format of Host Notify Command
completely services the interrupt. necessary reads of the address and data registers. Table 136 shows the Host Notify format. OEh: TCO_WDSTATUS—TCO2 Control Register” . Table 135. Data Values for Slave Read Registers (Sheet 2 of 2)
5.20 AC’97 Controller Functional Description
5.20.1 Overview
protocol, please see the AC ’97 specification.
- Independent (FDX) channels for mono Line in and out.
- Supports 16 bit samples.
- Multiple sample rates up to 48 KHz
- Supports dual codec implementations for audio in dock
- Supports read/write access to all Primary and Secondary AC'97 registers
- Supports low latency access to 16 GPIO and wake up event status bits. Note: The AC’97 Rev 2.0 spec. defines the following features which are NOT supported by the Intel® 6300ESB ICH:
- Support for optional double rate sampling (n+1 sample for PCM L, R and C)
- Support for 18 and 20 bit sample lengths
- Handset channels (In and Out)
- Dual Audio Codec support
Table 136. Host Notify Format
1 Start External Master
9 Write External Master Always zero.
10 ACK (or NACK) Intel® 6300ESB ICH Intel® 6300ESB ICH NACKs when
18 Unused - Always 0 External Master 7-bit-only address; this bit is
19 ACK Intel® 6300ESB ICH
28 ACK Intel® 6300ESB ICH
37 ACK Intel® 6300ESB ICH
38 Stop External Master
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Table 137. Features Supported by Intel ® 6300ESB ICH (Sheet 1 of 2)
- Isochronous low latency bus master memory interface
- Scatter/gather support for word-aligned buffers in memory (all mono or stereo 20-bit and 16-bit data types are supported, no 8-bit data types are supported)
- Data buffer size in system memory from 3 to 65535 samples per input
- Data buffer size in system memory from 0 to 65535 samples per output
- Independent PCI audio and modem functions with configuration and IO spaces
- AC’97 codec registers are shadowed in system memory through driver.
- AC’97 codec register accesses are serialized through semaphore bit in PCI IO space (new accesses are not allowed while a prior access is still in progress). Power Management • Power management through PCI Power Management PCI Audio Function
- Read/write access to audio codec registers 00h-3Ah and vendor registers 5Ah-7Eh
- 20-bit stereo PCM output, up to 48 KHz (L,R, Center, Sub-woofer, L-rear and R-rear channels on slots 3,4,6,7,8,9,10,11)
- 16-bit stereo PCM input, up to 48 KHz (L,R channels on slots 3,4)
- 16-bit mono mic in w/ or w/o mono mix, up to 48 KHz (L,R channel, slots 3,4) (mono mix supports mono hardware AEC reference for speakerphone)
- 16-bit mono PCM input, up to 48 KHz from dedicated mic ADC (slot 6) (supports speech recognition or stereo hardware AEC ref for speakerphone)
- During cold reset AC_RST# is held low until after POST and software deassertion of AC_RST# (supports passive PC_BEEP to speaker connection during POST).
exists in PCI Device 31, Function 6. excess verbiage this EDS refers to it as the third or tertiary codec.
- Read/write access to modem codec registers 3Ch-58h and vendor registers 5Ah-7Eh
- 16-bit mono modem line1 output and input, up to 48 KHz (slot 5)
- Low latency GPIO[15:0] via hardwired update between slot 12 and PCI IO register.
- Programmable PCI interrupt on modem GPIO input changes via slot 12 GPIO_INT
- SCI event generation on AC_SDIN[2:0] wake-up signals AC-link
- AC’97 2.0 compliant AC-link interface
- Variable sample rate output support through AC’97 SLOTREQ protocol
- Variable sample rate input support through monitoring of slot valid tag bits (slots 3,4,5,6)
- 3.3 V digital operation meets AC’97 2.2 DC switching levels
- AC-link IO driver capability meets AC’97 2.2 triple codec specifications
- Codec register status reads must be returned with data in the next AC-link frame, per AC’97 2.2 spec. Multiple Codec
- Triple codec addressing: All AC’97 Audio codec register accesses are addressable to codec ID 00 (primary), codec ID 01 (secondary), or codec ID 10 (tertiary).
- Modem codec addressing: All AC’97 Modem codec register accesses are addressable to codec ID 00 (primary) or codec ID 01 (secondary).
- Triple codec receive capability through AC_SDIN[2:0] pins (AC_SDIN[2:0] frames are internally validated, synch’d, and OR’d depending on the Steer Enable bit status in the SDM register)
- AC_SDIN mapping to DMA engine mapping capability allows for simultaneous input from three different audio codecs. NOTES: 1. Audio Codec IDs are remappable and not limited to 00,01,10 2. Modem Codec IDs are remappable and limited to 00,01 3. When using multiple codecs, the Modem Codec must be ID 01.
Table 137. Features Supported by Intel ® 6300ESB ICH (Sheet 2 of 2)
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5.20.1.1 PCI Power Management
sections below describe these events and the AC’97 controller power states.
- The AC’97 controller hardware does not inherently consume any more power when
- In the D0 state, all implemented AC’97 controller features are enabled.
- In D3 state, accesses to the AC’97 controller memory-mapped or I/O range will
- In D3 state, the AC’97 controller interrupt must never assert for any reason. The
internal PME# signal is used to signal wake events, etc.
- When the Device Power State field is written from D3
- AC’97 STS bit will be set only when the audio or modem resume events were
detected and their respective PME enable bits were set.
- GPIO Status change interrupt no longer has a direct path to AC’97 STS bit. This will
cause a wake up event only when the modem controller was in D3.
- Resume events on AC_SDIN[2:0] will cause resume interrupt status bits to be set
only if their respective controllers are not in D3.
- Edge detect logic will prevent the interrupts from being asserted in case AC’97
controller is switched from D3 to D0 after a wake event.
- Once the interrupt status bits are set, they will cause PIRQB# if their respective
5.20.2 AC-Link Overview
Figure 23. Intel ® 6300ESB ICH Based AC’97 Controller Connection to Companion
modem streams and command/status information is communicated over the AC-link. codec topology of the AC-link for the Intel ® 6300ESB ICH. The AC-link consists of a five signal interface between the controller and codec. Figure 24. AC’97 2.2 Controller-Codec Connection
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serial bit on the falling edge of BIT_CLK. set will return data of FFh to prevent system hangs. as the data phase. Each data bit is sampled on the falling edge of BIT_CLK. Table 138. AC’97 Signals NOTE: Power well voltage levels are 3.3 V. Figure 25. AC-Link Protocol
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 263 5—Intel ® 6300ESB ICH not distinguish between codecs on its AC_SDIN[2:0] pins, however the registers do distinguish between AC_SDIN[0], AC_SDIN[1], and AC_SDIN[2] for wake events, etc. When using a Modem Codec it is recommended to connect it to AC_SDIN[1]. See your Platform Design Guide for a matrix of valid codec configurations. The Intel ® 6300ESB ICH does not support optional test modes as outlined in the AC’97 specification.
5.20.2.1 AC-link Output Frame (SDOUT)
A new output frame begins with a low to high transition of AC_SYNC. AC_SYNC is synchronous to the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, the codec samples the assertion of AC_SYNC. This falling edge marks the time when both sides of AC-link are aware of the start of a new frame. On the next rising edge of BIT_CLK, the Intel ® 6300ESB ICH transitions SDOUT into the first bit position of slot 0, or the valid frame bit. Each new bit position is presented to the AC- link on a rising edge of BIT_CLK, and subsequently sampled by the codec on the following falling edge of BIT_CLK. This sequence ensures that data transitions and subsequent sample points for both incoming and outgoing data streams are time aligned. The output frame data phase corresponds to the multiplexed bundles of all digital output data targeting codec DAC inputs and control registers. Each output frame supports up to twelve outgoing data time slots. The Intel ® 6300ESB ICH generates 16 or 20 bits and stuffs remaining bits with zeros. The output data stream is sent with the most significant bit first, and all invalid slots are stuffed with zeros. When mono audio sample streams are output from the Intel ® 6300ESB ICH, software must ensure both left and right sample stream time slots are filled with the same data.
5.20.2.2 Output Slot 0: Tag Phase
Slot 0 is considered the tag phase. The tag phase is a special 16 bit time slot wherein each bit conveys a valid tag for its corresponding time slot within the current frame. A one in a given bit position of slot 0 indicates that the corresponding time slot within the current frame has been assigned to a data stream and contains valid data. When a slot is tagged invalid with a zero in the corresponding bit position of slot 0, the Intel 6300ESB ICH stuffs the corresponding slot with zeros during that slot’s active time. Within slot 0, the first bit is a valid frame bit (slot 0, bit 15) which flags the validity of the entire frame. When the valid frame bit is set to one, this indicates that the current frame contains at least one slot with valid data. When there is no transaction in progress, the Intel ® 6300ESB ICH will deassert the frame valid bit. Note that after a write to slot 12, that slot will always stay valid, and therefore the frame valid bit will remain set. The next 12 bit positions of slot 0 (bits [14:3]) indicate which of the corresponding twelve time slots contain valid data. Bits [1:0] of slot 0 are used as codec ID bits to distinguish between separate codecs on the link. Using the valid bits in the tag phase allows data streams of differing sample rates to be transmitted across the link at its fixed 48 KHz frame rate. The codec may control the output sample rate of the Intel ® 6300ESB ICH using the SLOTREQ bits as described in the AC’97 specification.
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5.20.2.3 Output Slot 1: Command Address Port
The command port is used to control features and monitor status of AC‘97 functions including, but not limited to, mixer settings and power management. The control interface architecture supports up to 64 16-bit read/write registers, addressable on even byte boundaries. Only the even registers (00h, 02h, etc.) are valid. Output frame slot 1 communicates control register address, and write/read command information. In the case of the multiple codec implementation, accesses to the codecs are differentiated by the driver using address offsets 00h –7Fh for the primary codec, address offsets 80h–FEh for the secondary codec, and address offsets 100h –17Fh for the tertiary codec. The differentiation on the link, however, is done through the codec ID bits.
5.20.2.4 Output Slot 2: Command Data Port
The command data port is used to deliver 16-bit control register write data in the event that the current command port operation is a write cycle as indicated in slot 1, bit 19. When the current command port operation is a read, the entire slot time stuffed with zeros by the Intel ® 6300ESB ICH. Bits [19:4] contain the write data. Bits [3:0] are reserved and are stuffed with zeros.
5.20.2.5 Output Slot 3: PCM Playback Left Channel
Output frame slot 3 is the composite digital audio left playback stream. Typically this slot is composed of standard PCM (.wav) output samples digitally mixed by the host processor. The Intel® 6300ESB ICH transmits sample streams of 16 bits or 20 bits and stuffs remaining bits with zeros. Data in output slots 3 and 4 from the Intel ® 6300ESB ICH should be duplicated by software when there is only a single channel out.
5.20.2.6 Output Slot 4: PCM Playback Right Channel
Output frame slot 4 is the composite digital audio right playback stream. Typically this slot is composed of standard PCM (.wav) output samples digitally mixed by the host processor. The Intel® 6300ESB ICH transmits sample streams of 16 or 20 bits and stuffs remaining bits with zeros. Data in output slots 3 and 4 from the Intel ® 6300ESB ICH should be duplicated by software when there is only a single channel out.
5.20.2.7 Output Slot 5: Modem Codec
Output frame slot 5 contains modem DAC data. The modem DAC output supports 16-bit resolution. At boot time, when the modem codec is supported, the AC’97 controller driver determines the DAC resolution. During normal runtime operation the Intel ® 6300ESB ICH stuffs trailing bit positions within this time slot with zeros.
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5.20.2.8 Output Slot 6: PCM Playback Center Front Channel
When set up for 6-channel mode, this slot is used for the front center channel. The format is the same as Slots 3 and 4. When not set up for 6-channel mode, this channel will always be stuffed with zeros by Intel ® 6300ESB ICH.
5.20.2.9 Output Slots 7-8: PCM Playback Left and Right Rear
When set up for 4 or 6 channel modes, slots 7 and 8 are used for the rear Left and Right channels. The format for these two channels are the same as Slots 3 and 4. 5.20.2.10Output Slot 9: Playback Sub Woofer Channel When set for 6-channel mode, this slot is used for the Sub Woofer. The format is the same as Slot three. When not set up for 6-channel mode, this channel will always be stuffed with zeros by Intel ® 6300ESB ICH. 5.20.2.11Output Slots 10-11: Reserved Output frame slots 10-11 are reserved and are always stuffed with 0s by the Intel ® 6300ESB ICH AC’97 controller. 5.20.2.12Output Slot 12: I/O Control Sixteen bits of DAA and GPIO control (output) and status (input) have been directly assigned to bits on slot 12 in order to minimize latency of access to changing conditions. The value of the bits in this slot are the values written to the GPIO control register at offset 54h and D4h (in the case of a secondary codec) in the modem codec I/O space. The following rules govern the usage of slot 12. 1. Slot 12 is marked invalid by default on coming out of AC-link reset, and will remain invalid until a register write to 54h/D4h. 2. A write to offset 54h/D4h in codec I/O space will cause the write data to be transmitted on slot 12 in the next frame, with slot 12 marked valid, and the address/data information to also be transmitted on slots 1 and 2. 3. After the first write to offset 54h/D4h, slot 12 remains valid for all following frames. The data transmitted on slot 12 is the data last written to offset 54h/D4h. Any subsequent write to the register will cause the new data to be sent out on the next frame. 4. Slot 12 will get invalidated after the following events: — PCI reset, AC'97 cold reset, warm reset, and hence a wake from S3, S4, or S5. — Slot 12 will remain invalid until the next write to offset 54h/D4h. 5.20.2.13AC-Link Input Frame (SDIN) There are three AC_SDIN lines on the Intel ® 6300ESB ICH for use with up to three codecs. Each AC_SDIN pin may have a codec attached. The input frame data streams correspond to the multiplexed bundles of all digital input data targeting the AC’97 controller. As in the case for the output frame, each AC-link input frame consists of twelve time slots.
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A new audio input frame begins with a low to high transition of AC_SYNC. AC_SYNC is synchronous to the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, the receiver samples the assertion of AC_SYNC. This falling edge marks the time when both sides of AC-link are aware of the start of a new audio frame. On the next rising edge of BIT_CLK, the codec transitions AC_SDIN into the first bit position of slot 0 (codec ready bit). Each new bit position is presented to AC-link on a rising edge of BIT_CLK, and subsequently sampled by the Intel ® 6300ESB ICH on the following falling edge of BIT_CLK. This sequence ensures that data transitions and subsequent sample points for both incoming and outgoing data streams are time aligned. SDIN data stream must follow the AC’97 specification and be MSB justified with all non- valid bit positions (for assigned and/or unassigned time slots) stuffed with zeros. AC_SDIN data is sampled by the Intel ® 6300ESB ICH on the falling edge of BIT_CLK.
subsequent slot in the frame (bits [14:3]). register in the codec to determine exactly which subsections, when any, are ready. to, mixer settings and power management. SLOTREQ bits are always set active (low) and a sample is transferred each frame. Table 139. Input Slot 1 Bit Definitions
19 Reserved (Set to zero)
2 Control Register Index (Stuffed with zeros when tagged as invalid)
11 Slot 3 Request: PCM Left Channel (1)
10 Slot 4 Request: PCM Right Channel (1)
9 Slot 5 Request: Modem Line 1
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As shown in Table 139, slot 1 delivers codec control register read address and multiple sample rate slot request flags for all output slots of the controller. When a slot request bit is set by the codec, the controller will return data in that slot in the next output frame. Slot request bits for slots 3 and 4 are always set or cleared in tandem, i.e. both are set or cleared. When set, the input slot 1 tag bit only pertains to Status Address Port data from a previous read. SLOTREQ bits are always valid independent of the slot 1 tag bit. 5.20.2.16Input Slot 2: Status Data Port The status data port receives 16-bit control register read data. Bit [19:4]: Control Register Read Data Bit [3:0]: Reserved. 5.20.2.17Input Slot 3: PCM Record Left Channel Input slot 3 is the left channel input of the codec. The Intel ® 6300ESB ICH supports 16-bit sample resolution. Samples transmitted to the Intel ® 6300ESB ICH must be in left/right channel order. 5.20.2.18Input Slot 4: PCM Record Right Channel Input slot 4 is the right channel input of the codec. The Intel ® 6300ESB ICH supports 16-bit sample resolution. Samples transmitted to the Intel ® 6300ESB ICH must be in left/right channel order. 5.20.2.19Input Slot 5: Modem Line Input slot 5 contains MSB justified modem data. The Intel ® 6300ESB ICH supports 16- bit sample resolution. 5.20.2.20Input Slot 6: Optional Dedicated Microphone Record Data Input slot 6 is a third PCM system input channel available for dedicated use by a microphone. This input channel supplements a true stereo output which enables more precise echo cancellation algorithm for speakerphone applications. The Intel® 6300ESB ICH supports 16-bit resolution for slot 6 input. 5.20.2.21Input Slots 7-11: Reserved Input frame slots 7-11 are reserved for future use and should be stuffed with zeros by the codec, per the AC’97 specification. 5.20.2.22Input Slot 12: I/O Status The status of the GPIOs configured as inputs are to be returned on this slot in every frame. The data returned on the latest frame is accessible to software by reading the register at offset 54h/D4h in the codec I/O space. Only the 16 MSBs are used to return GPI status. In order for GPI events to cause an interrupt, both the 'sticky' and 'interrupt' bits must be set for that particular GPIO pin in regs 50h and 52h. Therefore, the interrupt will be signalled until it has been cleared by the controller, which may be much longer than one frame.
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 269 5—Intel ® 6300ESB ICH Reads from 54h/D4h will not be transmitted across the link in slot 1 and 2. The data from the most recent slot 12 is returned on reads from offset 54h/D4h. 5.20.2.23Register Access In the Intel® 6300ESB ICH implementation of the AC-link, up to three codecs may be connected to the SDOUT pin. The following mechanism is used to address the primary, secondary, and tertiary codecs individually. The primary device uses bit 19 of slot 1 as the direction bit to specify read or write. Bits [18:12] of slot 1 are used for the register index. For I/O writes to the primary codec, the valid bits [14:13] for slots 1 and 2 must be set in slot 0, as shown in Table 140. Slot 1 is used to transmit the register address, and slot 2 is used to transmit data. For I/O reads to the primary codec, only slot 1 should be valid since only an address is transmitted. For I/O reads only slot 1 valid bit is set, while for I/O writes both slots 1 and 2 valid bits are set. The secondary and tertiary codec registers are accessed using slots 1 and 2 as described above, however the slot valid bits for slots 1 and 2 are marked invalid in slot 0 and the codec ID bits [1:0] (bit 0 and bit 1 of slot 0) is set to a non zero value. This allows the secondary or tertiary codec to monitor the slot valid bits of slots 1 and 2, and bits [1:0] of slot 0 to determine when the access is directed to the secondary or tertiary codec. When the register access is targeted to the secondary or tertiary codec, slot 1 and 2 will contain the address and data for the register access. Since slots 1 and 2 are marked invalid, the primary codec will ignore these accesses. When accessing the codec registers, only one I/O cycle may be pending across the AC- link at any time. The Intel ® 6300ESB ICH implements write posting on I/O writes across the AC-link (i.e., writes across the link are indicated as complete before they are actually sent across the link). In order to prevent a second I/O write from occurring before the first one is complete, software must monitor the CAS bit in the Codec Access Semaphore register which indicates that a codec access is pending. Once the CAS bit is cleared, then another codec access (read or write) may go through. The exception to this being reads to offset 54h/D4h/154h (slot 12) which are returned immediately with the most recently received slot 12 data. Writes to offset 54h, D4h, and 154h (primary, secondary and tertiary codecs), get transmitted across the AC-link in slots 1 and 2 as a normal register access. Slot 12 is also updated immediately to reflect the data being written. The controller will not issue back to back reads. It must get a response to the first read before issuing a second. In addition, codec reads and writes are only executed once across the link, and are not repeated. Table 140. Output Tag Slot 0
Description
14 1 0 Slot 1 Valid, Command Address bit (Primary codec only) 13 1 0 Slot 2 Valid, Command Data bit (Primary codec only) 12:
3 X X Slot 3-12 Valid
1:0 00 01 Codec ID (00 reserved for primary; 01 indicate secondary; 10 indicate tertiary).
5.20.3 AC-Link Low Power Mode
will be brought to, and held at a logic low voltage level. this low power, halted mode. event, cold reset and warm reset. does not drive the output pins of the link.
5.20.3.1 External Wake Event
Figure 26. AC-Link Powerdown Timing
during all power down modes.
5.20.4 AC‘97 Cold Reset
default power on reset values. AC_RST# is an asynchronous AC‘97 input to the codec.
5.20.5 AC‘97 Warm Reset
used in the generation of a warm reset. sampled low again by the codec. This will prevent the false detection of a new frame. Figure 27. SDIN Wake Signaling
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Note: On receipt of wake up signalling from the codec, the digital controller will issue an interrupt when enabled. Software will then have to issue a warm or cold reset to the codec by setting the appropriate bit in the Global Control Register.
5.20.6 System Reset
The transition of AC_RST# to the deasserted state will only occur under driver control.
- RSMRST# (system reset, including the reset of the resume well and PXPCIRST#)
- Mechanical power up (causes PXPCIRST#)
- Write to CF9h hard reset (causes PXPCIRST#)
- Transition to S3/S4/S5 sleep states (causes PXPCIRST#)
- Write to AC’97 Cold Reset# bit in the Global Control Register. Hardware will never deassert AC_RST# (i.e., never deasserts the Cold Reset# bit) automatically. Only software may deassert the Cold Reset# bit, and hence the AC_RST# signal. This bit, while it resides in the core well, will remain cleared upon return from S3/S4/S5 sleep states. The AC_RST# pin will remain actively driven from the resume well as indicated.
5.20.7 Hardware Assist to Determine AC_SDIN Used Per
Table 141. AC-link State during PXPCIRST#
- Intel® 6300ESB ICH core well outputs are used as strapping options for the Intel ® 6300ESB ICH, sampled
entering test mode. Straps are tied to the core well to prevent leakage during a suspend state.
- The pull-down resistors on these signals are only enabled when the AC-Link Shut Off bit in the AC’97 Global
Control Register is set to 1. All other times, the pull-down resistor is disabled.
- AC_RST# will be held low during S3-S5. It cannot be programmed high during a suspend state.
- BIT_CLK and AC_SDIN[2:0] are driven low by the codecs during normal states. When the codec is powered
in suspend, external pull-down resistors are required.
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The codec will do this by indicating that status data is valid in its TAG, then echo the read address in slot 1 followed by the read data in slot 2. The new function of the Intel® 6300ESB ICH hardware is to notice which AC_SDIN line contains the read return data, and to set new bits in the new register indicating which AC_SDIN line the register read data returned on. When it returned on AC_SDIN0, bits [1:0] contain the value ‘00’. When it returned on AC_SDIN1, the bits contain the value ‘01’, etc. Intel ® 6300ESB ICH hardware may set these bits every time register read data is returned from a function 5 read. No special command is necessary to cause the bits to be set. The new driver/BIOS software will read the bits from this register when it cares to, and may ignore it otherwise. When software is attempting to establish the codec-to- AC_SDIN mapping, it will single feed the read request and not pipeline to ensure it gets the right mapping, hardware cannot ensure the serialization of the access.
5.20.8 Software Mapping of AC_SDIN to DMA Engine
Once software has performed the register read to determine codec-to-AC_SDIN mapping, it will then either set bits [5:4] or [7:6] in the SDATA_IN MAP register to map this codec to the DMA engine. After it maps the audio codecs, it will set the “SE” (steer enable) bit, which now lets the hardware know to no longer OR the AC_SDIN lines, and to use the mappings in the register to steer the appropriate AC_SDIN line to the correct DMA engines.
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 275 6—Intel ® 6300ESB ICH Register and Memory Mapping 6 The Intel® 6300ESB ICH contains registers that are located in the processor’s I/O space, memory space and sets of PCI configuration registers that are located in PCI configuration space. This chapter details the Intel ® 6300ESB ICH I/O and memory maps. Register access is also described. Register-level address maps and Individual register bit descriptions are provided in the following chapters. The following notations are used in the chapters that follow. RO Read Only: Writes to this register location generally have no effect. However, in some cases, two separate registers are located at the same location where a read will access one register and a write will access the other register. See the I/O and memory map tables for details. WO Write Only: Reads to this register location generally have no effect. However , in some cases, two separate registers are located at the same location where a read will access one register and a write will access the other register. See the I/O and memory map tables for details. R/W Read/Write: A register with this attribute may be read and written. R/WC Read/Write Clear: A register bit with this attribute may be read and written. However, writing a 1 will clear (sets to zero) the corresponding bit, and writing a 0 will have no effect. Default When coming out of reset, the registers are set to predetermined default states. It is the responsibility of the system initialization software to determine configuration, operating parameters, and optional system features that are applicable, and to program the Intel 6300ESB ICH registers accordingly.
6.1 PCI Devices and Functions
The Intel® 6300ESB ICH incorporates multiple PCI functions as shown in Table 142. These functions are divided into four PCI devices. The first is the Hub Interface Link-To- PCI bridge, D: 30 F:0. The second device, D31:F1, contains most of the standard PCI functions present in most ICHs, as well as some new related Intel ® 6300ESB ICH features; SATA and SMBus Controller. The third device, D29 Fx, is the USB host controller device which includes new features specific to the Intel ® 6300ESB ICH; Watchdog Timer and an additional IOxAPIC. The fourth PCI device, D28:F0, is also a new Intel® 6300ESB ICH feature; a Hub Interface-to-PCI-X bridge. When a particular system does not want to support any one of Device 31’s, 29’s or 28’s functions, they may individually be disabled. When a function is disabled, it does not appear at all to the software. A disabled function will not respond to any register reads or writes.
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Table 142. PCI Devices and Functions Management, GPIO, CPU Interface, RTC, Interrupts, Timers, DMA.
6.2 PCI Configuration Map
Each PCI function on the Intel ® 6300ESB ICH has a set of PCI configuration registers. Specification, Revision 2.2. read, merge, write operation for the Configuration Address Register (0xCF8h). Figure 28. Intel ® 6300ESB ICH Device Diagram
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device-specific region (above address offset 3Fh).
6.3 I/O Map
6.3.1 Fixed I/O Address Ranges
6300ESB ICH in medium speed. Note: Unclaimed PCI cycles will be subtractively decoded and forwarded to the LPC. Intel® 6300ESB ICH (unless assigned to one of the variable ranges). Table 143. Fixed I/O Ranges Decoded by Intel ® 6300ESB I/O Controller Hub
- Only when the Port 61 Alias Enable bit (Device 31:Function 0, Offset D0, Bit 4) bit is set.
Otherwise, the target is PCI.
- Only when IDE Standard I/O space is enabled for Secondary Channel and the IDE Controller
is in legacy mode. Otherwise, the target is PCI.
- Only when IDE Standard I/O space is enabled for Primary Channel and the IDE Controller is
in legacy mode. Otherwise, the target is PCI.
- Should forward read cycles to this address to LPC Variable I/O Decode Ranges.
- Only when the Port 61 Alias Enable bit (Device 31:Function 0, Offset D0, Bit 4) bit is set.
Otherwise, the target is PCI.
- Only when IDE Standard I/O space is enabled for Secondary Channel and the IDE Controller
is in legacy mode. Otherwise, the target is PCI.
- Only when IDE Standard I/O space is enabled for Primary Channel and the IDE Controller is
in legacy mode. Otherwise, the target is PCI.
- Should forward read cycles to this address to LPC Variable I/O Decode Ranges.
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- Only when the Port 61 Alias Enable bit (Device 31:Function 0, Offset D0, Bit 4) bit is set.
Otherwise, the target is PCI.
- Only when IDE Standard I/O space is enabled for Secondary Channel and the IDE Controller
is in legacy mode. Otherwise, the target is PCI.
- Only when IDE Standard I/O space is enabled for Primary Channel and the IDE Controller is
in legacy mode. Otherwise, the target is PCI.
- Should forward read cycles to this address to LPC Variable I/O Decode Ranges.
6.3.2 Variable I/O Decode Ranges
Registers (BARs) or other configuration bits in the various PCI configuration spaces. 6300ESB ICH will forward the cycle to the LPC. Refer to Table 144 for a complete list of all variable I/O registers. Table 144. Variable I/O Decode Ranges
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6.4 Memory Map
subtractive decoded cycle may be forwarded to the LPC I/F or to the FWH. memory ranges for functions that decode directly from Hub Interface. Table 145. Memory Decode Ranges from CPU Perspective (Sheet 1 of 2) also decoded by D29:F5 APIC to support EOI. FFB0 0000 - FFB7 FFFF FWH Bit 6 in FWH Decode Enable Register is set.
- These ranges are decoded directly from Hub Interface. The memory cycles will not be seen on
- Software must not attempt locks to memory mapped I/O ranges for USB EHCI, High
which means potential deadlock conditions may occur.
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1 Kbyte anywhere
1 Kbyte anywhere in 4
column) is 0h, 1h, 2h, or 3h.
1 Mbyte to 4 Gbyte
as a standard LPC memory cycle. Table 145. Memory Decode Ranges from CPU Perspective (Sheet 2 of 2)
- These ranges are decoded directly from Hub Interface. The memory cycles will not be seen on
- Software must not attempt locks to memory mapped I/O ranges for USB EHCI, High
which means potential deadlock conditions may occur.
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6.4.1 Boot-Block Update Scheme
The Intel® 6300ESB ICH supports a “top-block swap” mode that has the Intel® 6300ESB ICH swap the top block in the FWH (the boot block) with another location. This allows for safe update of the Boot Block (even if a power failure occurs). When the “TOP_SWAP” Enable bit is set, the Intel ® 6300ESB ICH will invert A16 for cycles targeting FWH BIOS space. When this bit is zero, the Intel ® 6300ESB ICH will not invert A16. This bit is automatically set to zero by RTCRST#, but not by PXPCIRST#. The scheme is based on the concept that the top block is reserved as the “boot” block, and the block immediately below the top block is reserved for doing boot-block updates. The algorithm is: 1. Software copies the top block to the block immediately below the top. 2. Software checks that the copied block is correct. This could be done by performing a checksum calculation. 3. Software sets the TOP_SWAP bit. This will invert A16 for cycles going to the FWH. Processor access to FFFF_0000 through FFFF_FFFF will be directed to FFFE_0000 through FFFE_FFFF in the FWH, and processor accesses to FFFE_0000 through FFFE_FFFF will be directed to FFFF_0000 through FFFF_FFFF. 4. Software erases the top block. 5. Software writes the new top block. 6. Software checks the new top block. 7. Software clears the TOP_SWAP bit. If a power failure occurs at any point after step 3, the system will be able to boot from the copy of the boot block that is stored in the block below the top. This is because the TOP_SWAP bit is backed in the RTC well. Note: The top-block swap mode may be forced by an external strapping option (See Section 3.21.1, “Functional Straps”). When top-block swap mode is forced in this manner, the TOP_SWAP bit cannot be cleared by software. A re-boot with the strap removed will be required to exit a forced top-block swap mode. Note: Top-block swap mode only affects accesses to the FWH BIOS space, not feature space. Note: The top-block swap mode has no effect on accesses below FFFE_0000.
Intel® 6300ESB ICH—6 Intel® 6300ESB I/O Controller Hub DS November 2007
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PCI and the Hub Interface. The arbitration for the PCI bus is handled by this PCI device. register contents will be lost when core well power is removed.
7.1 PCI Configuration Registers (D30:F0)
Configuration Map” for details). Table 146. PCI Configuration Registers (D30:F0) (Sheet 1 of 2)
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7.1.1 Offset 00 - 01h: VID—Vendor ID Register (HUB-
7.1.2 Offset 02 - 03h: DID—Device ID Register (HUB-
Table 147. Offset 00 - 01h: VID—Vendor ID Register (HUB-PCI—D30:F0) Table 148. Offset 02 - 03h: DID—Device ID Register (HUB-PCI—D30:F0) Table 146. PCI Configuration Registers (D30:F0) (Sheet 2 of 2)
7.1.3 Offset 04 - 05h: CMD—Command Register (HUB-
Table 149. Offset 04 - 05h: CMD—Command Register (HUB-PCI—D30:F0)
9 Fast Back to Back Enable
8 SERR# Enable
(offset 06h, bit 14) is set.
7 Wait Cycle Control Hardwired to ‘0’ RO
6 Parity Error Response
detected on the Hub Interface.
4 Memory Write and
3 Special Cycle Enable
2 Bus Master Enable
from PCI to run on the Hub Interface.
1 Memory Space Enable
0 I/O Space Enable (IOE)
PCI that are not intended for USB, IDE, or AC’97.
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7.1.4 Offset 06 - 07h: PD_STS—Primary Device Status
Table 150. Offset 06 - 07h: PD_STS—Primary Device Status Register (HUB-PCI—
15 Detected Parity Error
0 = Software clears this bit by writing a ‘1’ to the bit location.
14 Signaled System Error
0 = Software clears this bit by writing a ‘1’ to the bit location.
13 Received Master Abort
0 = Software clears this bit by writing a ‘1’ to the bit location.
12 Received Target Abort
0 = Software clears this bit by writing a ‘1’ to the bit location. enabled to cause an internal SERR#.
11 Signaled Target Abort
0 = Software clears this bit by writing a ‘1’ to the bit location.
8 Master Data Parity Error
0 = Software clears this bit by writing a ‘1’ to the bit location. Command Register (offset 04h, bit 6) is set.
6 User Definable Features
7.1.6 Offset 0Ah: SCC—Sub-Class Code Register (HUB-
Table 151. Offset 08h: RID—Revision Identification Register (HUB-PCI—D30:F0) Table 152. Offset 0Ah: SCC—Sub-Class Code Register (HUB-PCI—D30:F0) indicating a PCI-to-PCI bridge. Table 153. Offset 0Bh: BCC—Base-Class Code Register (HUB-PCI—D30:F0)
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7.1.8 Offset 0Dh: PMLT—Primary Master Latency Timer
Note: This register does not apply to Hub Interface.
7.1.10 Offset 18h: PBUS_NUM—Primary Bus Number
Table 154. Offset 0Dh: PMLT—Primary Master Latency Timer Register (HUB-PCI— 7:3 Master Latency Count Not implemented. Table 155. Offset 0Eh: HEADTYP—Header Type Register (HUB-PCI—D30:F0) Table 156. Offset 18h: PBUS_NUM—Primary Bus Number Register (HUB-PCI—
7.1.11 Offset 19h: SBUS_NUM—Secondary Bus Number
7.1.12 Offset 1A: SUB_BUS_NUM—Subordinate Bus
7.1.13 Offset 1Bh: SMLT—Secondary Master Latency
removed, the expiration of the MLT counter will result in the deassertion of FRAME#. Table 157. Offset 19h: SBUS_NUM—Secondary Bus Number Register (HUB-PCI— This field indicates the bus number of PCI. configuration cycles on PCI. Table 158. Offset 1A: SUB_BUS_NUM—Subordinate Bus Number Register (HUB- ICH will indicate a master abort back to the Hub Interface.
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to end a burst prematurely due to a timeout.
7.1.14 Offset 1Ch: IOBASE—I/O Base Register (HUB-
Table 159. Offset 1Bh: SMLT—Secondary Master Latency Timer Register (HUB- Table 160. Offset 1Ch: IOBASE—I/O Base Register (HUB-PCI—D30:F0)
7.1.15 Offset 1Dh: IOLIM—I/O Limit Register (HUB-PCI—
7.1.16 Offset 1E - 1Fh: SECSTS—Secondary Status
Table 161. Offset 1Dh: IOLIM—I/O Limit Register (HUB-PCI—D30:F0) Table 162. Offset 1E - 1Fh: SECSTS—Secondary Status Register (HUB-PCI— 0 = This bit is cleared by software writing a 1.
14 Received System Error
0 = Software clears this bit by writing a’1’ to the bit position. 0 = Software clears this bit by writing a’1’ to the bit position. 0 = Software clears this bit by writing a’1’ to the bit position.
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to accept cycles as a target. the defined memory address range will be aligned to a 1 Mbyte boundary. 0 = Software clears this bit by writing a’1’ to the bit position.
7 Fast Back to Back Hardwired to ‘1’ to indicate that the PCI to Hub Interface
4 PERR# Assertion Detect
an internal SERR# and be a source for the NMI logic.
when not to accept cycles as a target. defined memory address range will be aligned to a 1 Mbyte boundary. Table 163. Offset 20 - 21h: MEMBASE—Memory Base Register (HUB-PCI—D30:F0) Table 164. Offset 22 - 23h: MEMLIM—Memory Limit Register (HUB-PCI—D30:F0)
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7.1.19 Offset 24h - 25h: PREF_MEM_BASE—Prefetchable
when not to accept cycles as a target. Note: When the Hub Interface is acting as the initiator , it will not respond as a target. memory address range will be aligned to a 1 Mbyte boundary. Table 165. Offset 24h - 25h: PREF_MEM_BASE—Prefetchable Memory Base
7.1.20 Offset 26h-27h: PREF_MEM_MLT—Prefetchable
when not to accept cycles as a target. Note: When the Hub Interface is acting as the initiator, it will not respond as a target. memory address range will be aligned to a 1 Mbyte boundary.
7.1.21 Offset 30 - 31h: IOBASE_HI—I/O Base Upper 16
Table 166. Offset 26h-27h: PREF_MEM_MLT—Prefetchable Memory Limit Register Table 167. Offset 30 - 31h: IOBASE_HI—I/O Base Upper 16 Bits Register (HUB-
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7.1.22 Offset 32 - 33h: IOLIM_HI—I/O Limit Upper 16
Table 168. Offset 32 - 33h: IOLIM_HI—I/O Limit Upper 16 Bits Register (HUB- Table 169. Offset 3Ch: INT_LINE—Interrupt Line Register (HUB-PCI—D30:F0)
7.1.24 Offset 3E - 3Fh: BRIDGE_CNT—Bridge Control
Table 170. Offset 3E - 3Fh: BRIDGE_CNT—Bridge Control Register (HUB-PCI—
12 PERR# to SERR# Enable
When this bit is set to ‘1’ PCI PERR NMI reporting is enabled. SERR# can be a s source on NMI.
11 Discard Timer SERR#
- When ‘0’: Do not generate SERR# on a secondary timer discard
- When ‘1’: Generate SERR# in response to a secondary timer discard. This bit replaces bit 1 of offset 90h, which held this function in ICH3. R/W
10 Discard Timer Status
expires (there is no discard timer for the primary interface).
9 Secondary Discard
- When ‘0’: The PCI master timeout value is between 215 and 216 PCI clocks
- When ‘1’: The PCI master timeout value is between 210 and 211 PCI clocks R/W
8 Primary Discard
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Controls PXPCIRST# assertion on PCI(X). the configuration registers are not affected. Hub Interface-PCI bridge in either direction. The default is 0.
- Hub Interface Completion-Required requests to PCI: When these master abort on PCI, the Intel® 6300ESB ICH returns a master abort status. For reads, FFFFh is returned for each DWORD.
- Hub Interface Posted Writes to PCI: When these master abort on PCI, the Intel® 6300ESB ICH discards the data.
- PCI Reads to Hub Interface: When these master abort on Hub Interface, the Intel® 6300ESB ICH returns the data provided with the Hub Interface master abort packet to the PCI requestor.
- PCI writes to Hub Interface: Intel ® 6300ESB ICH has no idea when these “master-abort.” When set to 1, the Intel® 6300ESB ICH treats the master abort as an error:
- Hub Interface Completion-Required requests to PCI: When these master abort on PCI, the Intel® 6300ESB ICH returns a target abort status. For reads, FFFFh is returned for each DWORD.
- Hub Interface Posted Writes to PCI: When these master abort on PCI, the Intel® 6300ESB ICH discards the data and sets the Primary Signaled SERR# bit (when the corresponding SERR_EN bit is set).
- PCI Reads to Hub Interface: When these master abort on Hub Interface, the Intel® 6300ESB ICH terminates the cycle with a target abort and flushes the remainder of the prefetched data.
- PCI writes to Hub Interface: The Intel ® 6300ESB ICH has no idea when these “master-abort.” R/W VGA 16-Bit Decode This bit does not have any functionality relative to address decodes because the Intel® 6300ESB ICH will forward the cycles to PCI, independent of the decode. Writes of one have no impact other than to force the bit to one. Writes of zero have no impact other than to force the bit to zero. Reads to this bit will return the previously written value (or zero when no writes since reset).
cycles in the VGA range before the legacy PCI Bridge. AC’97, or IDE ranges to PCI, this bit would have no effect.
1 SERR# Enable
0 Parity Error Response
detection and reporting on the PCI bus.
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7.1.25 Offset 40 - 43h: HI_CMD—Hub Interface
Table 171. Offset 40 - 43h: HI_CMD—Hub Interface Command Control Register
8 SATA Hub ID This field identifies the Hub Interface ID number for the Serial
4 Second Hub ID This field identifies the Hub Interface ID number for
1 First Hub ID This field identifies the Hub Interface ID number for
20 Hub Interface Parity
Error Response bit of D28.F0.04h bit 6 is set.
6 Hub Interface Timeslice
serviced after every message.
4 HI Width This field is hardwired to 00b, indicating that the Hub
0 HI Rate
field is fixed for 4x mode only. will always do 64 byte bursts.
7.1.26 Offset 44 - 45h: DEVICE_HIDE—Secondary PCI
configuration cycles are run. This ensures that the device is not in a semi-enable state. Table 172. Offset 44 - 45h: DEVICE_HIDE—Secondary PCI Device Hiding Register 3 HIDE_DEV3 Same as bit 0 of this register, except for device 3 (AD{19]). 2 HIDE_DEV2 Same as bit 0 of this register, except for device 2 (AD{18]).
1 HIDE_DEV1 Same as bit 0 of this register, except for device 1 (AD[17])
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7.1.27 Offset 50 - 51h: CNF—Intel ® 6300ESB ICH
recommended configuration of this register. Table 173. Offset 50 - 51h: CNF—Intel® 6300ESB ICH Configuration Register
13 Prefetch Flush Enable
occurred since the delayed transaction was initiated. NOTE: This bit must be set by system BIOS.
9 HP_PCI_EN
has a higher arbitration priority.
8 Hole Enable (15 MB-16
6 HI-PCI Write Combining
2 Delayed Transaction
7.1.28 Offset 58 - 5Bh: D30_PNE — PERR#_NMI_ENABLE
Table 174. Offset 58 - 5Bh: D30_PNE — PERR#_NMI_ENABLE Register (HUB- lock transaction targeting PCIX.
2 PCI-X PERR NMI
This bit enables PCI-X PERR NMI reporting. This bit enables PCI PERR NMI reporting. When this bit is set to ’1’ PCI PERR NMI reporting is enabled.
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7.1.29 Offset 70h: MTT—Multi-Transaction Timer
default value of MTT is 20h (32 PCI clocks). MTT timer will timeout before the Grant-to-FRAME# trigger causing a rearbitration. Table 175. Offset 70h: MTT—Multi-Transaction Timer Register (HUB-PCI—
7.1.30 Offset 82h: PCI_MAST_STS—PCI Master Status
SMI#) is enabled through the PCI Command register. Table 176. Offset 82h: PCI_MAST_STS—PCI Master Status Register (HUB-PCI— has requested use of the PCI bus. 0 = Software clears this bit by writing a’1‘to the bit position. has requested use of the PCI bus. requested use of the PCI bus. Table 177. Offset 90h: ERR_CMD—Error Command Register (HUB-PCI—D30:F0) will report SERR# when SERR_RTA is set. BRIDGE_CNT—Bridge Control Register (HUB-PCI—D30:F0)” .
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SERR# is enabled through the PCI Command register.
7.1.33 Offset F8h - FBh: MANID— Manufacturer’s ID
Table 178. Offset 92h: ERR_STS—Error Status Register (HUB-PCI—D30:F0) 0 = This bit is cleared by writing a 1. BRIDGE_CNT—Bridge Control Register (HUB-PCI—D30:F0)” . Table 179. Offset F8h - FBh: MANID— Manufacturer’s ID
- This function contains many other functional units, such as DMA and Interrupt
Controllers, Timers, Power Management, System Management, GPIO RTC and LPC. IDE, etc.) are described in their respective sections.
8.1 PCI Configuration Registers (D31:F0)
Configuration Map” for details). Table 180. PCI Configuration Registers (D31:F0) (Sheet 1 of 2)
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8.1.1 Offset 00 - 01h: VID—Vendor ID Register (LPC I/
Table 181. Offset 00 - 01h: VID—Vendor ID Register (LPC I/F—D31:F0) Table 180. PCI Configuration Registers (D31:F0) (Sheet 2 of 2)
8.1.2 Offset 02 - 03h: DID—Device ID Register (LPC I/
Table 182. Offset 02 - 03h: DID—Device ID Register (LPC I/F—D31:F0) Table 183. Offset 04 - 05h: PCICMD—PCI COMMAND Register (LPC I/F—D31:F0)
9 FBE: Fast Back to Back
8 SERR_EN: SERR#
1 = Enable. Allow SERR# to be generated.
6 PER: Parity Error
0 = No action is taken when detecting a parity error.
5 VPS: VGA Palette Snoop Hardwired to 0 RO
4 PMWE: Postable Memory
3 SCE: Special Cycle
2 BME: Bus Master Enable Hardwired to 1 to indicate that bus mastering cannot be
1 MSE: Memory Space
0 IOE: I/O Space Enable Hardwired to 1 to indicate that the I/O space cannot be
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Table 184. Offset 06 - 07h: PCISTA—PCI Device Status (LPC I/F—D31:F0)
15 DPE: Detected Parity
1 = PERR# signal goes active. Set even when the PER bit is 0.
14 SSE: Signaled System
routed to cause SMI#, NMI, or interrupt.
13 RMA: Received Master
PCI due to LPC I/F master or DMA cycles.
12 RTA: Received Target
LPC I/F master or DMA cycles to PCI.
11 STA: Signaled Target
8 DPED: Data Parity Error
6 UDF: User Definable
8.1.5 Offset 08h: RID—Revision ID Register (LPC I/F—
8.1.6 Offset 09h: PI—Programming Interface (LPC I/F—
Table 185. Offset 08h: RID—Revision ID Register (LPC I/F—D31:F0) Table 186. Offset 09h: PI—Programming Interface (LPC I/F—D31:F0) Table 187. Offset 0Ah: SCC—Sub-Class Code Register (LPC I/F—D31:F0)
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Table 188. Offset 0Bh: BCC—Base-Class Code Register (LPC I/F—D31:F0) Table 189. Offset 0Eh: HEADTYP—Header Type Register (LPC I/F—D31:F0)
Note: Usage: ACPI or Legacy. anywhere in the 64K I/O space on 128-byte boundaries.
8.1.11 Offset 44h: ACPI_CNTL—ACPI Control (LPC I/F—
Note: Usage: ACPI or Legacy. Table 190. Offset 40 - 43h: PMBASE—ACPI Base Address (LPC I/F—D31:F0) Table 191. Offset 44h: ACPI_CNTL—ACPI Control (LPC I/F—D31:F0) (Sheet 1 of
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4 ACPI_EN: ACPI Enable
are not affected by this bit. shared with other interrupts.
000 IRQ9
001 IRQ10
010 IRQ11
011 Reserved
100 IRQ20 (Only available when APIC enabled)
101 IRQ21 (Only available when APIC enabled)
110 IRQ22 (Only available when APIC enabled)
111 IRQ23 (Only available when APIC enabled)
programmed for active-low reception. Table 191. Offset 44h: ACPI_CNTL—ACPI Control (LPC I/F—D31:F0) (Sheet 2 of
8.1.12 Offset 4E - 4Fh: BIOS_CNTL (LPC I/F—D31:F0)
Table 192. Offset 4E - 4Fh: BIOS_CNTL (LPC I/F—D31:F0)
1 BLE: BIOS Lock Enable
bit may only be cleared by a PXPCIRST#. 1 = Enables setting the BIOSWE bit to cause SMIs.
0 BIOSWE: BIOS Write
0 = Only read cycles result in FWH I/F cycles. BIOS lock Enable (BLE) is also set, an SMI# is generated. This ensures that only SMI code may update BIOS.
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8.1.13 Offset 54h: TCO_CNTL—TCO Control (LPC I/F—
Table 193. Offset 54h: TCO_CNTL—TCO Control (LPC I/F—D31:F0)
3 TCO_INT_EN: TCO
This bit enables/disables the TCO interrupt. as the SCI, and the TCO_INT_SEL bits will have no meaning.
8.1.15 Offset 5Ch: GPIO_CNTL—GPIO Control (LPC I/F—
Table 194. Offset 58h - 5Bh: GPIO_BASE—GPIO Base Address (LPC I/F—D31:F0) Table 195. Offset 5Ch: GPIO_CNTL—GPIO Control (LPC I/F—D31:F0)
4 GPIO_EN: GPIO Enable
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8.1.16 Offset PIRQA - 60h: PIRQ[n]_ROUT—
Table 196. Offset PIRQA - 60h: PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control
7 IRQEN: Interrupt
compatible interrupts specified in bits[3:0]. 1 = The PIRQ is not routed to the 8259. up for I/O APIC interrupt delivery mode.
Table 197. Offset 64h: SERIRQ_CNTL—Serial IRQ Control (LPC I/F—D31:F0)
7 SIRQEN: Serial IRQ
0 = The buffer is input only and internally SERIRQ will be a 1.
6 SIRQMD: Serial IRQ
0 = The serial IRQ machine will be in quiet mode. 1 = The serial IRQ machine will be in continuous mode. default will be programmed to be in continuous mode. the smallest data frame size. driven low by the serial IRQ machine to signal a start frame.
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8.1.18 Offset PIRQE - 68h: PIRQ[n]_ROUT—
Table 198. Offset PIRQE - 68h: PIRQ[n]_ROUT—PIRQ[E,F,G,H] Routing Control compatible interrupts specified in bits[3:0]. 1 = The PIRQ is not routed to the 8259. up for I/O APIC interrupt delivery mode.
8.1.19 Offset 88h: D31_ERR_CFG—Device 31 Error Config
8.1.20 Offset 8Ah: D31_ERR_STS—Device 31 Error Status
Table 199. Offset 88h: D31_ERR_CFG—Device 31 Error Config Register (LPC I/F— 0 = Disable. No SERR# assertion on Received Target Abort. SERR_RTA is set and if SERR_EN is set. SERR_DTT bit is set and if SERR_EN is set.
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8.1.21 Offset 90h - 91h: PCI_DMA_CFG—PCI DMA
assigned to LPC should be assigned as Disabled. Table 200. Offset 8Ah: D31_ERR_STS—Device 31 Error Status Register (LPC I/F—
2 SERR_RTA: SERR# Due
0 = Software clears this bit by writing a 1 to the bit location. will also generate an SERR# when SERR_RTA is set. 0 = Software clears this bit by writing a 1 to the bit location. Table 201. Offset 90h - 91h: PCI_DMA_CFG—PCI DMA Configuration (LPC I/F—
4 Channel 7 Select
8.1.22 Offset D0h - D3h: GEN_CNTL—General Control
Table 202. Offset D0h - D3h: GEN_CNTL—General Control Register (LPC I/F—
24 HIDE_ISA: Hide ISA
asserting during config cycles to the PCI-to-ISA bridge. AD22 to connect to the PCI-to-ISA bridge’s IDSEL input. FERR# signal during C2, C3 or C4.
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8 SCRATCHPAD These bits are provided for possible future use.
17 MMT_ADDR_EN
Range selected by bits 16:15 below.
5 MMT_ADDR_SEL
00 FED0_0000h - FED0_03FFh
01 FED0_1000h - FED0_13FFh
10 FED0_2000h - FED0_23FFh
11 FED0_3000h - FED0_33FFh
0 = FERR# will not generate IRQ13 nor IGNNE#. F0h. It will also drive IGNNE# active.
12 IRQ1LEN: Keyboard
0 = IRQ1 will bypass the latch.
11 IRQ12LEN: Mouse
0 = IRQ12 will bypass the latch. 8 APIC_EN: APIC Enable 0 = Disables internal I/O (x) APIC.
6 ALTACC_EN: Alternate
otherwise unwritable registers.
8.1.23 Offset D4h: GEN_STA—General Status (LPC I/F—
2 DCB_EN: DMA Collection
1 DTE: Delayed
0 = Delayed transactions disabled. internal register, FWH and LPC I/F accesses.
0 POS_DEC_EN
PCI to ISA (subtractive docking bridge) is used. Table 203. Offset D4h: GEN_STA—General Status (LPC I/F—D31:F0)
1 NO_REBOOT
when the strap is set to No Reboot. or by software writing a 1 to the bit.
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Table 204. Offset D5h: BACK_CNTL—Backed Up Control (LPC I/F—D31:F0)
5 TOP_SWAP: Top-Block
jumper should be removed and the system rebooted.
4 CPU_BIST_EN: Enables
RSMRST#, but not by PXPCIRST# nor CF9h writes. external pin strap or through the RTCRST# input signal.
8.1.25 Offset D8h: RTC_CONF—RTC Configuration
Table 205. Offset D8h: RTC_CONF—RTC Configuration Register (LPC I/F—
4 U128LOCK: Upper 128-
that may only be reset by a hardware reset.
3 L128LOCK: Lower 128-
that may only be reset by a hardware reset.
2 U128E: Upper 128-byte
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8.1.26 Offset E0h: COM_DEC—LPC I/F Communication
Table 206. Offset E0h: COM_DEC—LPC I/F Communication Port Decode Ranges
8.1.27 Offset E1h: FDD/LPT_DEC—LPC I/F FDD and LPT
Table 207. Offset E1h: FDD/LPT_DEC—LPC I/F FDD and LPT Decode Ranges (LPC
4 FDD Decode Range
This field determines which range to decode for the LPTPort.
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8.1.28 Offset E2h: SND_DEC—LPC I/F Sound Decode
Note: This register is no longer supported and will not be validated. Table 208. Offset E2h: SND_DEC—LPC I/F Sound Decode Ranges (LPC I/F— This bit determines which range to decode for the Midi Port.
8.1.29 Offset E3h: FWH_DEC_EN1—FWH Decode Enable 1
unless POS_DEC_EN is set to 1. Table 209. Offset E3h: FWH_DEC_EN1—FWH Decode Enable 1 Register (LPC I/F—
7 FWH_F8_EN
6 FWH_F0_EN
Enables decoding two 512 Kbyte FWH memory ranges.
5 FWH_E8_EN
Enables decoding two 512 Kbyte FWH memory ranges.
4 FWH_E0_EN
Enables decoding two 512 Kbyte FWH memory ranges.
3 FWH_D8_EN
Enables decoding two 512 Kbyte FWH memory ranges.
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8.1.30 Offset E4h - E5h: GEN1_DEC—LPC I/F Generic
2 FWH_D0_EN
Enables decoding two 512 Kbyte FWH memory ranges.
1 FWH_C8_EN
Enables decoding two 512 Kbyte FWH memory ranges.
0 FWH_C0_EN
Enables decoding two 512 Kbyte FWH memory ranges. Table 210. Offset E4h - E5h: GEN1_DEC—LPC I/F Generic Decode Range 1 (LPC I/ have address lines 31:16 as 0. memory addresses. The size of this range is 128 bytes.
0 GEN1_EN: Generic
Table 211. Offset E6h - E7h: LPC_EN—LPC I/F Enables (LPC I/F—D31:F0) (Sheet
13 CNF2_LPC_EN
the LPC interface. This is used for the internal SIU.
12 CNF1_LPC_EN
11 MC_LPC_EN
the LPC interface. This range is used for a microcontroller.
10 KBC_LPC_EN
the LPC interface. This range is used for a microcontroller.
9 GAMEH_LPC_EN
the LPC interface. This range is used for a gameport.
8 GAMEL_LPC_EN
the LPC interface. This range is used for a gameport.
7 ADLIB_LPC_EN
6 MSS_LPC_EN
5 MIDI_LPC_EN
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4 SB16_LPC_EN
3 FDD_LPC_EN
2 LPT_LPC_EN
Table 212. Offset E8h: FWH_SEL1—FWH Select 1 Register (LPC I/F—D31:F0)
8 FWH_F8_IDSEL
4 FWH_F0_IDSEL
IDSEL for two 512 Kbyte FWH memory ranges.
0 FWH_E8_IDSEL
IDSEL for two 512 Kbyte FWH memory ranges.
6 FWH_E0_IDSEL
IDSEL for two 512 Kbyte FWH memory ranges.
2 FWH_D8_IDSEL
IDSEL for two 512 Kbyte FWH memory ranges. IDSEL for two 512 Kbyte FWH memory ranges. IDSEL for two 512 Kbyte FWH memory ranges. IDSEL for two 512 Kbyte FWH memory ranges.
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8.1.33 Offset ECh - EDh: GEN2_DEC—LPC I/F Generic
Table 213. Offset ECh - EDh: GEN2_DEC—LPC I/F Generic Decode Range 2 (LPC I/ memory addresses. The size of this range is 16 bytes. 3:1 Reserved Reserved. Read as 0.
0 GEN2_EN
8.1.34 Offset EEh - EFh: FWH_SEL2—FWH Select 2
Table 214. Offset EEh - EFh: FWH_SEL2—FWH Select 2 Register (LPC I/F—
2 FWH_70_IDSEL
IDSEL for two 1M FWH memory ranges. IDSEL for two 1M FWH memory ranges. IDSEL for two 1M FWH memory ranges. IDSEL for two 1M FWH memory ranges.
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8.1.35 Offset F0h: FWH_DEC_EN2—FWH Decode Enable 2
unless POS_DEC_EN is set to 1. Table 215. Offset F0h: FWH_DEC_EN2—FWH Decode Enable 2 Register (LPC I/F—
3 FWH_70_EN
Enables decoding two 1M FWH memory ranges.
2 FWH_60_EN
Enables decoding two 1M FWH memory ranges.
1 FWH_50_EN
Enables decoding two 1M FWH memory ranges.
0 FWH_40_EN
Enables decoding two 1M FWH memory ranges.
example, if only 2 USB host controllers are wanted, software must disable Function #2. USB functions are expected to only be disabled by BIOS during system initialization. Table 216. Offset F2h: FUNC_DIS—Function Disable Register (LPC I/F—D31:F0)
15 D29_F7_Disable
functions that are to be disabled.
9 D29_F1_Disable
functions that are to be disabled.
8 D29_F0_Disable
functions that are to be disabled.
7 Reserved Reserved
6 D31_F6_Disable
that function are not decoded by the Intel ® 6300ESB ICH.
5 D31_F5_Disable
functions that are to be disabled.
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3 D31_F3_Disable
functions that are to be disabled.
2 D31_F2_Disable
Software sets this bit to disable the SATA Controller function.
1 D31_F1_Disable
Software sets this bit to disable the IDE controller function. This bit is used in conjunction with bit 3 in this register.
8.1.37 Offset F4: ETR1—PCI-X Extended Features
8.1.38 Offset F8h: Manufacturer’s ID
Table 217. Offset F4: ETR1—PCI-X Extended Features Register (LPC I/F—D31:F0)
7 Trapping Disable
details on USB Legacy Keyboard Operation. when an external PCI Master is accessing these ports. 1 = Routes the APIC1 boot interrupt to the PIRQG# output. Table 218. Offset F8h: Manufacturer’s ID
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8.2 DMA I/O Registers
Table 219. DMABASE_CA—DMA Base and Current Address Registers (Sheet 1 of
Table 219. DMABASE_CA—DMA Base and Current Address Registers (Sheet 2 of
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8.2.1 DMABASE_CA—DMA Base and Current Address
Table 220. DMABASE_CA—DMA Base and Current Address Registers the value is returned from the Current Address register. Address register after a terminal count is generated.
8.2.2 DMABASE_CC—DMA Base and Current Count
Table 221. DMABASE_CC—DMA Base and Current Count Registers the value is returned from the Current Count register. register after a terminal count is generated. register indicates the number of words to be transferred. cleared to ensure that the low byte is accessed first.
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8.2.3 DMAMEM_LP—DMA Memory Low Page Registers
8.2.4 DMACMD—DMA Command Register
Table 222. DMABASE_CC—DMA Base and Current Count Registers the bit 15 shifted out from the current address register. Table 223. DMACMD—DMA Command Register 7:5 Reserved Reserved. Must be 0.
4 DMA Group Arbitration
initialized in fixed priority. 1 = Rotating priority to the group. 3 Reserved Reserved. Must be zero.
2 DMA Channel Group
Both channel groups are enabled following part reset. 0 = Enable the DMA channel group. channel group 0-3, which is cascaded through channel 4. 1:0 Reserved Reserved. Must be zero.
8.2.5 DMASTA—DMA Status Register
Table 224. DMASTA—DMA Status Register status for channels 0 through 3.
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8.2.6 DMA_WRSMSK—DMA Write Single Mask Register
8.2.7 DMACH_MODE—DMA Channel Mode Register
Table 225. DMA_WRSMSK—DMA Write Single Mask Register 7:3 Reserved Reserved. Must be zero.
2 Channel Mask Select
may be masked / unmasked at a time. 1 = Disable DREQ for the selected channel. These bits select the DMA Channel Mode Register to program. Table 226. DMACH_MODE—DMA Channel Mode Register (Sheet 1 of 2)
5 Address Increment/
8.2.8 DMA Clear Byte Pointer Register
4 Autoinitialize Enable
Clear disables autoinitialization. the current registers following a terminal count (TC). “11”) the transfer type is irrelevant. Table 227. DMA Clear Byte Pointer Register precedes the first access to a 16-bit DMA controller register. accesses the most significant byte. Table 226. DMACH_MODE—DMA Channel Mode Register (Sheet 2 of 2)
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8.2.9 DMA Master Clear Register
8.2.10 DMA_CLMSK—DMA Clear Mask Register
Table 228. DMA Master Clear Register cleared and the Mask Register is set. Table 229. DMA_CLMSK—DMA Clear Mask Register
8.2.11 DMA_WRMSK—DMA Write All Mask Register
8.3 Timer I/O Registers
Table 230. DMA_WRMSK—DMA Write All Mask Register 7:4 Reserved Reserved. Must be 0. channel is in auto-initialization mode). Setting the bit(s) to a 1 disables the corresponding DREQ(s). Setting the bit(s) to a 0 enables the corresponding DREQ(s). the cascade of channel’s 0 - 3 through channel 4. Table 231. Timer I/O Registers
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8.3.1 TCW —Timer Control Word Register
counter output is 0. Each timer must be programmed to bring it into a known state. formats are described below. Table 232. TCW —Timer Control Word Register selected when bits[7:6] are both 1. counter 0, 41h for counter 1, and 42h for counter 2).
0 Binary/BCD Countdown
8.3.1.1 RDBK_CMD—Read Back Command
8.3.1.2 LTCH_CMD—Counter Latch Command
before the count is read, the second Counter Latch Command is ignored. Table 233. RDBK_CMD—Read Back Command
5 Latch Count of Selected
4 Latch Status of Selected
1 Counter 0 Select. 1 = Counter 0 count and/or status will be latched. 0 Reserved Reserved. Must be 0.
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8.3.2 SBYTE_FMT—Interval Timer Status Byte Format
Table 234. LTCH_CMD—Counter Latch Command written, the write is interpreted as a read back command. 5:4 Counter Latch Command 00 = Selects the Counter Latch Command. 3:0 Reserved Reserved. Must be 0.
Table 235. SBYTE_FMT—Interval Timer Status Byte Format Register 7 Counter OUT Pin State 0 = OUT pin of the counter is also a 0. (CE), the count value will be incorrect. and is not yet available for reading. counter mode, as listed under the bit function above.
0 Countdown Type Status
This bit reflects the current countdown type. 1 = Binary Coded Decimal (BCD) countdown.
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8.3.3 Counter Access Ports Register
8.4.1 Interrupt Controller I/O MAP
below are descriptions of the different register possibilities for each address. Table 236. Counter Access Ports Register Table 237. PIC Registers
8.4.2 ICW1—Initialization Command Word 1 Register
- The Interrupt Mask register is cleared.
- IRQ7 input is assigned priority 7.
- The slave mode address is set to 7.
- Special mask mode is cleared and Status Read is set to IRR.
complete the initialization sequence. Table 238. ICW1—Initialization Command Word 1 Register 7:5 ICW/OCW select These bits are MCS-85 specific, and not needed.
4 ICW/OCW select 1 = This bit must be a 1 to select ICW1 and enable the ICW2,
3 Edge/Level Bank Select
1 Single or Cascade
0 ICW4 Write Required
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8.4.3 ICW2—Initialization Command Word 2 Register
for the master controller and 70h for the slave controller. Table 239. ICW2—Initialization Command Word 2 Register
000 IRQ0 IRQ8
001 IRQ1 IRQ9
010 IRQ2 IRQ10
011 IRQ3 IRQ11
100 IRQ4 IRQ12
101 IRQ5 IRQ13
110 IRQ6 IRQ14
111 IRQ7 IRQ15
8.4.4 ICW3—Master Controller Initialization Command
8.4.5 ICW3—Slave Controller Initialization Command
Table 240. ICW3—Master Controller Initialization Command Word 3 Register 7:3 0 = These bits must be programmed to zero. 1 = This bit must always be programmed to a 1. 1:0 0 = These bits must be programmed to zero. Table 241. ICW3—Slave Controller Initialization Command Word 3 Register 7:3 0 = These bits must be programmed to zero. to 02h to match the code broadcast by the master controller. for broadcasting the interrupt vector.
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8.4.6 ICW4—Initialization Command Word 4 Register
8.4.7 OCW1—Operational Control Word 1 (Interrupt
Table 242. ICW4—Initialization Command Word 4 Register 7:5 0 = These bits must be programmed to zero.
4 Special Fully Nested
0 = Should normally be disabled by writing a 0 to this bit. 3 Buffered Mode (BUF) 0 = Must be programmed to 0 for the Intel® 6300ESB ICH.
2 Master/Slave in Buffered
1 Automatic End of
1 = Automatic End of Interrupt (AEOI) mode is programmed.
0 Microprocessor Mode
is operating in an Intel® Architecture-based system. Table 243. OCW1—Operational Control Word 1 (Interrupt Mask) Register mask the interrupt requests from the slave controller.
8.4.8 OCW2—Operational Control Word 2 Register
specific EOI mode are disabled following initialization. Table 244. OCW2—Operational Control Word 2 Register modes and combinations of the two. programming L2, L1 and L0 to 0 is sufficient in this case.
000 IRQ0/8 100 IRQ4/12
001 IRQ1/9 101 IRQ5/13
010 IRQ2/10 110 IRQ6/14
011 IRQ3/11 111 IRQ7/15
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8.4.9 OCW3—Operational Control Word 3 Register
Table 245. OCW3—Operational Control Word 3 Register 7 Reserved Reserved. Must be 0.
6 Special Mask Mode
5 Enable Special Mask
0 = Disable. The SMM bit becomes a “don't care”. 0 = Disable. Poll Command is not issued. priority level requesting service. prior to attempting the read.
8.4.10 ELCR1—Master Controller Edge/Level Triggered
cannot be put into level mode.
8.4.11 ELCR2—Slave Controller Edge/Level Triggered
Table 246. ELCR1—Master Controller Edge/Level Triggered Register 2:0 Reserved Reserved. Must be 0. Table 247. ELCR2—Slave Controller Edge/Level Triggered Register (Sheet 1 of 2) 5 Reserved Reserved. Must be 0.
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8.5 Advanced Interrupt Controller (APIC0)
® ICHx, APIC1 has an alternate base address, FEC0xxxxH. FEC0_0020H or FEC1_0020H) to generate interrupts from APIC1. passed to both APIC0 and APIC1 internally. problem is found. For APIC1, this extension is always enabled.
8.5.1 APIC Register Map
into memory space and are shown in Table 248. 0 Reserved Reserved. Must be 0. Table 247. ELCR2—Slave Controller Edge/Level Triggered Register (Sheet 2 of 2) Table 248. APIC Direct Registers
Register. When accessing these registers, accesses must be done a DWORD at a time. programming model in this case.
8.5.2 IND—Index Register
will program this register to select the desired APIC internal register.
8.5.3 DAT—Data Register
to by the Index register. This register may only be accessed in DWORD quantities. Table 249. APIC Indirect Registers
00 ID 32 bits R/W
01 Version 32 bits RO
02 Arbitration ID 32 bits RO
03 Boot Configuration 32 bits R/W
Table 250. IND—Index Register
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8.5.4 Offset FEC0_0020h: IRQPA—IRQ Pin Assertion
8.5.5 Offset FEC0 - EOIR: EOI Register
semantics for level-triggered interrupts issued on the parallel bus. Table 251. DAT—Data Register Table 252. Offset FEC0_0020h: IRQPA—IRQ Pin Assertion Register should always write a value of 0 to Bits 31:5.
interrupt will be reissued and serviced at a later time.
8.5.6 Offset 00h: ID—Identification Register
APIC is derived from its I/O APIC ID. This register is reset to zero on power up reset. Table 253. Offset FEC0 - EOIR: EOI Register should always write a value of zero to Bits 31:8. Remote_IRR bit for that I/O Redirection Entry will be cleared. Table 254. Offset 00h: ID—Identification Register 15 Scratchpad Scratchpad bit.
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8.5.7 Offset 01h: VER—Version Register
8.5.8 Offset 02h: ARBID—Arbitration ID Register
the lowest priority agent and assumes an arbitration ID of zero. Table 255. Offset 01h: VER—Version Register hardwired to 17h to indicate 24 interrupts.
15 PRQ
to write to it to cause interrupts. ICH for the I/O (x) APIC is 20h. Table 256. Offset 02h: ARBID—Arbitration ID Register
8.5.9 Offset 03h: BOOT_CONFIG—Boot Configuration
8.5.10 Offset 10h - 11h (Vector 0) through 3E - 3Fh
the corresponding interrupt pin into an APIC message. from 0 to 1. (i.e., when the interrupt was not already pending at the destination). See Table 259 for Delivery Mode Encoding information. Table 257. Offset 02h: ARBID—Arbitration ID Register Table 258. Offset 10h - 11h (Vector 0) through 3E - 3Fh (Vector 23): Redirection
6 Destination
programmed by software to 0. the logical destination address of a set of processors. System Bus mode. They become bits [11:4] of the address. Default Value: Bit 16-1, Bits[15:12]=0.
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16 Mask
in the delivery of the interrupt to the destination. 1 = Masked: Interrupts are not delivered nor held pending. but before the interrupt is dispensed to the processor.
15 Trigger Mode
14 Remote IRR
SMI, NMI, INT or ExtINT delivery modes.
13 Interrupt Input Pin
connected to the interrupt pins.
12 Delivery Status
interrupt. Writes to this bit have no effect. 0 = Idle. No activity for this interrupt. receiving APIC unit to accept the interrupt at this time.
11 Destination Mode
0 = Physical. Destination APIC ID is identified by bits [59:56]. 7:0 Vector This field contains the interrupt vector for this interrupt. Default Value: Bit 16-1, Bits[15:12]=0.
8.6 Real Time Clock Registers
8.6.1 I/O Register Address Map
registers mapped to the standard I/O space. The register map appears in Table 260. Table 259. Delivery Mode Encoding
000 Fixed: Deliver the signal on the INTR signal of all processor cores listed in the
destination. Trigger Mode may be edge or level. destination. Trigger Mode may be edge or level. zeroes for future compatibility. -- not supported. be sent over the APIC bus again. -- not supported. vector. Requires the interrupt to be programmed as edge triggered.
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8.6.2 Indexed Registers
separate Index and Target registers (70/71h or 72/73h), as shown in Table 261. Table 260. RTC I/O Registers
- I/O locations 70h and 71h are the standard ISA location for the real-time clock. The map for
this bank is shown in Table 261. Locations 72h and 73h are for accessing the extended RAM. above 127h are not valid. When the extended RAM is not needed, it may be disabled.
- Software must preserve the value of bit 7 at I/O addresses 70h and 74h. When writing to
during the sequential address write. Table 261. RTC (Standard) RAM Bank
8.6.2.1 RTC_REGA—Register A
affected by RSMRST# or any other Intel ® 6300ESB ICH reset signal. Table 262. RTC_REGD—Register D (Flag Register)
7 UIP: Update In Progress
This bit may be monitored as a status flag. available when the UIP bit is 0. 1 = The update is soon to occur or is in progress. and are not affected by RSMRST# or any other reset signal. these bits should all be set to zero. RS3 corresponds to bit 3.
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8.6.2.2 RTC_REGB—Register B (General Configuration)
Table 263. RTC_REGB—Register B (General Configuration)
7 SET: Update Cycle
RSMRST# nor any other reset signal. 0 = Update cycle occurs normally once each second.
6 PIE: Periodic Interrupt
This bit is cleared by RSMRST#, but not on any other reset.
5 AIE: Alarm Interrupt
This bit is cleared by RSMRST#, but not on any other reset. once a second, one an hour, once a day, or one a month.
4 UIE: Update-Ended
This bit is cleared by RSMRST#, but not on any other reset. 1 = Allows an interrupt to occur when the update cycle ends.
3 SQWE: Square Wave
2 DM: Data Mode
not affected by RSMRST# nor any other reset signal.
1 HOURFORM: Hour
RSMRST# nor any other reset signal. represents AM as zero and PM as one.
0 DSE: Daylight Savings
is not affected by RSMRST# nor any other reset signal. 0 = Daylight Savings Time updates do not occur. increments from 1:59:59 AM to 3:00:00 AM. first reaches 1:59:59 AM, it is changed to 1:00:00 AM.
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8.6.2.3 RTC_REGC—Register C (Flag Register)
Note: Writes to Register C have no effect.
8.6.3 RTC_REGD—Register D (Flag Register)
Table 264. RTC_REGC—Register C (Flag Register)
7 IRQF: Interrupt Request
RSMRST# or a read of Register C.
6 PF: Periodic Interrupt
This bit is cleared upon RSMRST# or a read of Register C. Register A, this flag will not be set. specified by the RS bits of register A is 1.
5 AF: Alarm Flag
0 = This bit is cleared upon RTCRST# or a read of Register C. 0 = The bit is cleared upon RSMRST# or a read of Register C. 3:0 Reserved Reserved. Will always report 0. Table 265. RTC_REGD—Register D (Flag Register)
7 VRT: Valid RAM and
however it will return a 1 for read cycles. 1 = This bit is hard-wired to 1 in the RTC power well.
8.7 CPU Interface Registers
8.7.1 NMI_SC—NMI Status and Control Register
Table 266. NMI_SC—NMI Status and Control Register to 0. When writing to port 61h, this bit must be 0. to 1. When writing to port 61h, this bit must be a 0.
5 TMR2_OUT_STS: Timer
port 61h, this bit must be a 0.
4 REF_TOGGLE: Refresh
to port 61h, this bit must be a 0.
3 IOCHK_NMI_EN:
2 PCI_SERR_EN: PCI
1 SPKR_DAT_EN: Speaker
0 TIM_CNT2_EN: Timer
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8.7.2 NMI_EN—NMI Enable (and Real Time Clock Index)
8.7.3 PORT92—Fast A20 and Init Register
Table 267. NMI_EN—NMI Enable (and Real Time Clock Index) 7 NMI_EN: NMI Enable 0 = Enable NMI sources. Table 268. PORT92—Fast A20 and Init Register
1 ALT_A20_GATE:
0 = A20M# signal may potentially go active. 1 = This bit is set when INIT# goes active.
0 INIT_NOW When this bit transitions from a 0 to a 1, the Intel® 6300ESB
8.7.4 COPROC_ERR—Coprocessor Error Register
8.7.5 RST_CNT—Reset Control Register
Table 269. COPROC_ERR—Coprocessor Error Register (Device 31:Function 0, Offset D0, Bit 13) must be 1. Table 270. RST_CNT—Reset Control Register
3 FULL_RST: Full Reset
high), or after two TCO timeouts. and SLP_S5# low for 3 - 5 seconds. SLP_S4#, and SLP_S5# signals will not go active.
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8.8 Power Management Registers (D31:F0)
otherwise indicate, bits are in the main (core) power well. value read from a reserved bit, as it may not be consistently 1 or 0.
8.8.1 Power Management PCI Configuration Registers
Table 271 shows a small part of the configuration space for PCI Device 31: Function 0. registers are only used for Legacy Power management schemes. Table 271. Power Management PCI Configuration Registers (D31:F0)
8.8.1.1 Offset A0h: GEN_PMCON_1—General PM Configuration 1
Note: Usage: ACPI or Legacy. Table 272. Offset A0h: GEN_PMCON_1—General PM Configuration 1 Register
5 CPUSLP_EN: CPU SLP#
states. This reduces the processor power. even when this bit is not set. only be cleared by PXPCIRST#).
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8.8.1.2 Offset A2h: GEN_PMCON_2—General PM Configuration 2
Note: Usage: ACPI or Legacy. Table 273. Offset A2h: GEN_PMCON_2—General PM Configuration 2 Register
4 System Reset Status
3 CPU Thermal Trip Status
S1 state. This bit is also reset by RSMRST# and CF9h resets.
1 CPUPWR_FLR: CPU
0 = Software clears this bit by writing a 0 to the bit position. Software clears this bit by writing a 0 to this bit position.
0 PWROK_FLR: PWROK
or when the system goes into a G3 state. as though the RSMRST# signal had gone active. policy is controlled by the AFTERG3 bit.
Note: Usage: ACPI or Legacy. Table 274. Offset A4h: GEN_PMCON_3—General PM Configuration 3 Register This 2-bit value indicates when the SWSMI timer will time out.
2 RTC_PWR_STS: RTC
writing a 1 to the bit position. or trickle supply) was removed or failed.
0 AFTERG3_EN
may not be detected by the Intel® 6300ESB ICH.
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8.8.1.4 Offset ACh: RST_CNT2—Reset Control 2 Register (PM—
Table 275. Offset ACh: RST_CNT2—Reset Control 2 Register (PM—D31:F0)
23 Change Sub Class Code
not reset when returning from S3.
22 Change Device ID
SATA controller will report the value of “25A3h”(hard drive). Intel® 6300ESB ICH internal logic.
00 CPUTHRMTRIP# Event will cause asynchronous assertion of
01 CPUTHRMTRIP# Event will be double-synchronized to
10 CPUTHRMTRIP Event will cause asynchronous assertion of
8.8.1.5 Offset B8h - BBh: GPI_ROUT—GPI Routing Control
Table 276. Offset B8h - BBh: GPI_ROUT—GPI Routing Control Register (PM— 31:2 GPI[15] through GPI[1] See bits 1:0 for description.
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8.8.1.6 Offset C0h: MON_FWD_EN—IO Monitor Forward Enable
determined by the MON[n]_TRP_RNG and MON_TRP_MSK register settings.
8.8.1.7 Offset C4h, C6h, C8h, CAh: MON[ n]_TRP_RNG—I/O
corresponds to Monitor 4. Offset C6h corresponds to Monitor 5, etc. Table 277. Offset C0h: MON_FWD_EN—IO Monitor Forward Enable Register (PM—
7 MON7_FWD_EN
6 MON6_FWD_EN
5 MON5_FWD_EN
4 MON4_FWD_EN
through the TRP_FWD_EN register settings.
8.8.1.8 Offset CCh: MON_TRP_MSK—I/O Monitor Trap Range Mask
Table 278. Offset C4h, C6h, C8h, CAh: MON[n]_TRP_RNG—I/O Monitor [4:7] Trap Table 279. Offset CCh: MON_TRP_MSK—I/O Monitor Trap Range Mask Register
2 MON7_MASK Selects low 4-bit mask for the I/O locations that MON7 will
the base I/O selection will not be decoded.
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8.8.2 APM I/O Decode
8.8.2.1 APM_CNT—Advanced Power Management Control Port
8.8.2.2 APM_STS—Advanced Power Management Status Port
Table 280. APM Register Map Table 281. APM_CNT—Advanced Power Management Control Port Register Table 282. APM_STS—Advanced Power Management Status Port Register Used to pass data between the OS and the SMI handler. any other register or function (other than a PCI reset).
8.8.3 Power Management I/O Registers
Table 283. ACPI and Legacy I/O Register Map
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8.8.3.1 PM1_STS—Power Management 1 Status Register
Table 284. PM1_STS—Power Management 1 Status Register (Sheet 1 of 2)
15 WAK_STS: Wake Status
0 = Software clears this bit by writing a 1 to the bit position. ICH will transition the system to the ON state. returns, and the WAK_STS bit will not be set.
11 PRBTNOR_STS: Power
This bit is set any time a Power Button Override occurs (I.E. transition to the S5 state, as well as sets the AFTERG3 bit. The BIOS or SCI handler clears this bit by writing a 1 to it.
10 RTC_STS: RTC Status
0 = Software clears this bit by writing a 1 to the bit position.
8 PWRBTN__STS: Power
This bit is not affected by hard resets caused by a CF9 write. bit, BIOS_RLS, which will cause an SCI and set this bit.
0 TMROF_STS: Timer
generate an SCI or SMI# (depending on the SCI_EN). Table 284. PM1_STS—Power Management 1 Status Register (Sheet 2 of 2)
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8.8.3.2 PM1_EN—Power Management 1 Enable Register
Note: Usage: ACPI or Legacy. Table 285. PM1_EN—Power Management 1 Enable Register
10 RTC_EN: RTC Event
RTCRST# or a Power Button Override event. bit is set and the RTC_STS bit goes active.
10 S M I #
11 S C I
always enabled as a Wake event.
5 GBL_EN: Global Enable
Enable SCI on GBL_STS going active.
8.8.3.3 PM1_CNT—Power Management 1 Control
Note: Usage: ACPI or Legacy. Table 286. PM1_CNT—Power Management 1 Control
13 SLP_EN: Sleep Enable Setting this bit causes the system to sequence into the Sleep
0 SLP_TYP: Sleep Type
enter when the SLP_EN bit is set to 1. 000 = ON: Typically maps to S0 state. 001 = Asserts STPCLK#. Puts CPU in Stop-Grant state. SLP_S4#: Typically maps to S4 state. SLP_S5#: Typically maps to S5 state. NOTE: These bits are only reset by RTCRST#.
2 GBL_RLS: Global
0 = This bit always reads as 0. status bits to control its ability to receive ACPI events. 0 = These events will generate an SMI#. 1 = These events will generate an SCI.
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8.8.3.4 PM1_TMR—Power Management 1 Timer Register
8.8.3.5 PROC_CNT—Processor Control Register
Note: Usage: ACPI or Legacy. Table 287. PM1_TMR—Power Management 1 Timer Register as long as the system is in the S0 state. the TMROF_EN bit is set, an SCI interrupt is also generated. Table 288. PROC_CNT—Processor Control Register (Sheet 1 of 2)
17 THTL_STS: Throttle
8 FORCE_THTL: Force
throttling only occurs when the system is in the C0 state. When in the C2 state, no throttling occurs. selected in the THTL_DTY field. throttle period is 1024 PCICLKs. Table 288. PROC_CNT—Processor Control Register (Sheet 2 of 2)
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8.8.3.6 LV2—Level 2 Register
Note: Usage: ACPI or Legacy.
8.8.3.7 GPE0_STS—General Purpose Event 0 Status Register
reset by CF9h write. All are reset by RSMRST#. Table 289. LV2—Level 2 Register
Table 290. GPE0_STS—General Purpose Event 0 Status Register (Sheet 1 of 3)
6 GPIn_STS
- When the system is in an S1-S5 state, the event will also wake the system.
- When the system is in an S0 state (or upon waking back to an S0 state), a SCI will be caused depending on the GPI_ROUT bits for the corresponding GPI. NOTE: These bits are sticky and are cleared by writing a 1 back to this bit position. Corresponding bits and GPIOs Bit # GPI[n]Bit # GPI[n] 16 0 24 8 17 1 25 na 18 2 26 na 19 3 27 11 20 4 28 12 21 5 29 13 22 6 30 na 23 7 31 na R/WC 15:1 4 Reserved Reserved.
13 PME_B0_STS
the PME_B0_STS bit will not cause a wake event or SCI.
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11 PME_STS
0 = Software clears this bit by writing a 1 to the bit position. 1 = Set by hardware when the PME# signal goes active. generate an SCI or SMI# (when SCI_EN is not set). 8R I _ S T S 0 = Software clears this bit by writing a 1 to the bit position.
7 SMBus Wake Status
0 = Software clears this bit by writing a 1 to the bit position. command or just prior to entering the sleep state. when it is set due to SMBALERT# signal going active. 6 TCOSCI_STS 0 = Software clears this bit by writing a 1 to the bit position. Table 290. GPE0_STS—General Purpose Event 0 Status Register (Sheet 2 of 3)
5 AC97_STS
Status register at bit 8 of offset 54h in each AC’97 function. 0 = Software clears this bit by writing a 1 to the bit position.
- The PMEE bit for the function is set, and the AC-link bit
- For modem, when audio routing is disabled, the wake
Interrupt bit (NABMBAR + 30h, bit 0) is 1.
4 USB2_STS
0 = Software clears this bit by writing a 1 to the bit position. corresponding USB2_EN bit is set.
3 USB1_STS
0 = Software clears this bit by writing a 1 to the bit position. corresponding USB1_EN bit is set. 0 = Software clears this bit by writing a 1 to the bit position.
0 Thermal Interrupt
0 = Software clears this bit by writing a 1 to the bit position. Table 290. GPE0_STS—General Purpose Event 0 Status Register (Sheet 3 of 3)
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8.8.3.8 GPE0_EN—General Purpose Event 0 Enables Register
well bits are all cleared by RSMRST#. The RTC well bits are cleared by RTCRST#. Table 291. GPE0_EN—General Purpose Event 0 Enables Register (Sheet 1 of 2)
6 GPIn_EN
13 PME_B0_EN
11 PME_EN
RTCRST#. It is not cleared by CF9h writes. SLP_EN or power failure, but not power button override). and is not affected by a hard reset caused by a CF9h write.
8.8.3.9 SMI_EN—SMI Control and Enable Register
handled through the USB interrupt. handled through the USB interrupt. power management event (SCI or SMI). Table 292. SMI_EN—SMI Control and Enable Register (Sheet 1 of 3) 18 INTEL_USB2_EN Enables Intel-Specific USB EHCI SMI logic to cause SMI#. 17 LEGACY_USB2_EN Enables legacy USB EHCI logic to cause SMI#. Table 291. GPE0_EN—General Purpose Event 0 Enables Register (Sheet 2 of 2)
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14 PERIODIC_EN
13 TCO_EN
1 = Enables the TCO logic to generate SMI#.
11 MCSMI_EN: Microcon-
Intel® 6300ESB ICH on PCI, but not forwarded to LPC.
7 BIOS_RLS: BIOS
4 SLP_SMI_EN
3 LEGACY_USB_EN 0 = Disable. Table 292. SMI_EN—SMI Control and Enable Register (Sheet 2 of 3)
8.8.3.10 SMI_STS—SMI Status Register
OS from clearing the SMI GPE0_EN bits. Note: Usage: ACPI or Legacy. writes a 1 to the GBL_RLS bit. assert SMI# low to the processor. bit is automatically cleared. setting of a SMI status bit.
0 GBL_SMI_EN
0 = No SMI# will be generated by the Intel® 6300ESB ICH. This bit is reset by a PCI reset event. Table 292. SMI_EN—SMI Control and Enable Register (Sheet 3 of 3)
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Table 293. SMI_STS—SMI Status Register (Sheet 1 of 2) 23 WDT_SMI_STS 0 = SMI# not caused by WDT 1st timeout. 1 = Indicates the SMI# was caused by the WDT 1st timeout.
18 INTEL_USB2_STS
17 LEGACY_USB2_STS
16 SMBus SMI Status
is set from the 64 KHz clock domain used by the SMBus. assertion of this bit before clearing it.
- The SMBus Slave receiving a message, or
- The SMBALERT# signal goes active and the
- The SMBus Slave receiving a Host Notify message and
- The Intel® 6300ESB ICH detecting the
SMLINK_SLAVE_SMI command while in the S0 state.
15 SERIRQ_SMI_STS
14 PERIODIC_STS
0 = This bit is cleared by writing a 1 to its bit position. set, the Intel® 6300ESB ICH will generate an SMI#.
13 TCO_STS
0 = SMI# not caused by TCO logic. that this is not a wake event.
12 DEVMON_STS: Device
0 = SMI# not caused by Device Monitor. corresponding DEV[7:4]_TRAP_EN bits are also set. corresponding DEVTRAP_EN bits are also set.
11 MCSMI_STS: Microcon-
is cleared by software writing a 1 to the bit position. Intel® 6300ESB ICH will generate an SMI#.
10 GPE1_STS
to cause an SMI# will have no effect on this bit. 0 = SMI# was not generated by a GPI assertion. 1 = SMI# was generated by a GPI assertion.
9 GPE0_STS
0 = SMI# was not generated by a GPE0 event. 1 = SMI# was generated by a GPE0 event.
8 PM1_STS_REG
(offset PMBASE+00h) that may cause an SMI#. 0 = SMI# was not generated by a PM1_STS event. 1 = SMI# was generated by a PM1_STS event.
6 SWSMI_TMR_STS
0 = Software clears this bit by writing a 1 to the bit location. 0 = Software clears this bit by writing a 1 to the bit location. register with the APMC_EN bit set. 0 = Software clears this bit by writing a 1 to the bit location. bit when SLP_SMI_EN bit is also set.
3 LEGACY_USB_STS
the enable bits are not set. 0 = SMI# was not generated by USB Legacy event. 1 = SMI# was generated by USB Legacy event.
2 BIOS_STS
0 = This bit cleared by software writing a 1 to its bit position. Table 293. SMI_STS—SMI Status Register (Sheet 2 of 2)
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8.8.3.11 ALT_GP_SMI_EN—Alternate GPI SMI Enable Register
Note: Usage: ACPI or Legacy. Table 294. ALT_GP_SMI_EN—Alternate GPI SMI Enable Register
- The corresponding bit in the ALT_GP_SMI_EN register is set.
- The corresponding GPI must be routed in the GPI_ROUT register to cause an SMI.
- The corresponding GPIO must be implemented. Device: 31 Function: 0 I/O Address: PMBASE +38h Attribute: Read/Write Default Value: 0000h Size: 16-bit Lockable: No Power Well: Resume
8.8.3.12 ALT_GP_SMI_STS—Alternate GPI SMI Status Register
Note: Usage: ACPI or Legacy.
8.8.3.13 MON_SMI—Device Monitor SMI Status and Enable Register
Table 295. ALT_GP_SMI_STS—Alternate GPI SMI Status Register
- The corresponding bit in the ALT_GPI_SMI_EN register is set.
- The corresponding GPI must be routed in the GPI_ROUT register to cause an SMI.
- The corresponding GPIO must be implemented. All bits are in the resume well. Default for these bits is dependent on the state of the GPI pins.
Table 296. MON_SMI—Device Monitor SMI Status and Enable Register
2 DEV[7:4]_TRAP_STS
0 = SMI# was not caused by the associated device monitor.
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8.8.3.14 DEVACT_STS—Device Activity Status Register
activity for legacy power management. time to read the DEVTRAP_STS register. Table 297. DEVACT_STS—Device Activity Status Register (Sheet 1 of 2)
13 ADLIB_ACT_STS
by writing a 1 to the bit location.
12 KBC_ACT_STS
by writing a 1 to the bit location. PCI agent will not set this bit.
11 MIDI_ACT_STS
by writing a 1 to the bit location.
10 AUDIO_ACT_STS
Audio (Sound Blaster “OR’d” with MSS). by writing a 1 to the bit location. 0 = The corresponding PCI interrupts have not been active. active. Clear this bit by writing a 1 to the bit location.
8 PIRQCG_ACT_STS
0 = The corresponding PCI interrupts have not been active. active. Clear this bit by writing a 1 to the bit location. 0 = The corresponding PCI interrupts have not been active. active. Clear this bit by writing a 1 to the bit location. 0 = The corresponding PCI interrupts have not been active. active. Clear this bit by writing a 1 to the bit location. by writing a 1 to the bit location. by writing a 1 to the bit location. by writing a 1 to the bit location.
1 IDEP1_ACT_STS
by writing a 1 to the bit location.
0 IDEP0_ACT_STS
by writing a 1 to the bit location. Table 297. DEVACT_STS—Device Activity Status Register (Sheet 2 of 2)
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8.8.3.15 DEVTRAP_EN— Device Trap Enable Register
O cycles associated with that range will not be forwarded to LPC or IDE. Table 298. DEVTRAP_EN— Device Trap Enable Register
13 ADLIB_TRP_EN
12 KBC_TRP_EN
11 MIDI_TRP_EN
10 AUDIO_TRP_EN
Audio (Sound Blaster “ORed” with MSS).
5 LEG_IO_TRP_EN
8.8.3.16 BUS_ADDR_TRACK— Bus Address Tracker
Asynchronous SMIs are disabled.
8.8.3.17 BUS_CYC_TRACK— Bus Cycle Tracker
Asynchronous SMIs are disabled.
2 IDES0_TRP_EN
Table 299. BUS_ADDR_TRACK— Bus Address Tracker out which I/O was last being accessed.
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8.9 System Management TCO Registers
see LPC Device 31:Function 0 PCI Configuration registers.
8.9.1 TCO Register I/O Map
Table 300. BUS_CYC_TRACK— Bus Cycle Tracker Table 301. TCO I/O Register Map
8.9.2 TCO1_RLD—TCO Timer Reload and Current Value
8.9.3 TCO1_TMR—TCO Timer Initial Value
Table 302. TCO1_RLD—TCO Timer Reload and Current Value to prevent the timeout. Bits 7:6 will always be 0. Table 303. TCO1_TMR—TCO Timer Initial Value from 2.4 seconds to 38 seconds.
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8.9.4 TCO1_DAT_IN—TCO Data In Register
8.9.5 TCO1_DAT_OUT—TCO Data Out Register
Table 304. TCO1_DAT_IN—TCO Data In Register OS_TCO_SMI bit in the TCO_STS register. Table 305. TCO1_DAT_OUT—TCO Data Out Register selected by the TCO_INT_SEL bits.
8.9.6 TCO1_STS—TCO1 Status Register
Table 306. TCO1_STS—TCO1 Status Register (Sheet 1 of 2)
12 HUBSERR_STS
0 = Software clears this bit by writing a 1 to the bit position. generate a NMI (or SMI# when NMI routed to SMI#).
11 HUBNMI_STS
0 = Software clears this bit by writing a 1 to the bit position.
10 HUBSMI_STS
0 = Software clears this bit by writing a 1 to the bit position.
9 HUBSCI_STS
0 = Software clears this bit by writing a 1 to the bit position.
8 BIOSWR_STS
0 = Software clears this bit by writing a 1 to the bit position. SMI# to indicate an illegal attempt to write to the BIOS.
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This bit is in the RTC well. cause an SMI# (but not a wake event). the bit to be cleared after a “1” is written to the bit to clear it. handler until verifying that the bit has actually been cleared. This will ensure that the SMI is not re-entered. 0 = Software clears this bit by writing a 1 to the bit position. was caused by the TCO timer reaching 0. 0 = Software clears this bit by writing a 1 to the bit position. 0 = Software clears this bit by writing a 1 to the bit position.
0 NMI2SMI_STS
0 = Cleared by clearing the associated NMI status bit. caused an NMI (because NMI2SMI_EN is set). Table 306. TCO1_STS—TCO1 Status Register (Sheet 2 of 2)
8.9.7 TCO2_STS—TCO2 Status Register
Table 307. TCO2_STS—TCO2 Status Register
4 SMLINK_SLV_SMI_STS
into pre-determined sleep state. This avoids race conditions. Reset associated with exit from S3-S5 states.
2 BOOT_STS:
a 1 to clear the BOOT_STS bit. and the processor has not fetched the first instruction. timeout. The reboot is done by asserting PXPCIRST#.
0 INTRD_DET: Intruder
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8.9.8 TCO1_CNT—TCO1 Control Register
Table 308. TCO1_CNT—TCO1 Control Register
12 TCO_LOCK
change this bit from 1 to 0.
11 TCO_TMR_HLT: TCO
0 = The TCO Timer is enabled to count.
10 SEND_NOW
9 NMI2SMI_EN
0 = Normal NMI functionality. not be generated until the bit is cleared. BIOS or SMI handler to force an entry to the NMI handler.
8.9.9 TCO2_CNT—TCO2 Control Register
8.9.10 TCO_MESSAGE1 and TCO_MESSAGE2 Registers
Table 309. TCO2_CNT—TCO2 Control Register
3 GPIO11_ALERT_DISABL
01 = Interrupt (as selected by TCO_INT_SEL). Table 310. TCO_MESSAGE1 and TCO_MESSAGE2 Registers based on RSMRST# (but not PCI reset).
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8.9.11 Offset TCOBASE + OEh: TCO_WDSTATUS—TCO2
8.9.12 Offset TCOBASE + 10h: SW_IRQ_GEN—Software
Table 311. Offset TCOBASE + OEh: TCO_WDSTATUS—TCO2 Control Register based on RSMRST# (but not PCI reset). Table 312. Offset TCOBASE + 10h: SW_IRQ_GEN—Software IRQ Generation
1 IRQ12_CAUSE
expected to receive IRQ12 assertions from a SERIRQ device. expected to receive IRQ1 assertions from a SERIRQ device.
8.10 General Purpose I/O Registers (D31:F0)
I/O space. The base offset for this space is selected by the GPIO_BAR register.
8.10.1 GPIO Register I/O Address Map
Table 313. Registers to Control GPIO
2 GPIO Use Select 03000000h R/W
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8.10.2 Offset GPIOBASE + 00h: GPIO_USE_SEL—GPIO
8.10.3 Offset GPIOBASE + 04h: GP_IO_SEL—GPIO
Table 314. Offset GPIOBASE + 00h: GPIO_USE_SEL—GPIO Use Select Register GPIO, rather than for the native function.
- The following bits are not implemented because there is no
- The following bits are always 1 because they are
- When GPIO[n] does not exist, the bit in this register will
always read as 0 and writes will have no effect.
- After a full reset (RSMRST#) all multiplexed signals in the
Table 315. Offset GPIOBASE + 04h: GP_IO_SEL—GPIO Input/Output Select GPIO[n]_SEL 0 = Output. The corresponding GPIO signal is an output. 23 Always 0. The GPIOs are fixed as outputs.
8.10.4 Offset GPIOBASE + 0Ch: GP_LVL—GPIO Level for
6 Always 0. The GPIOs are fixed as outputs. 15:0 Always 1. These GPIOs are fixed as inputs. Table 316. Offset GPIOBASE + 0Ch: GP_LVL—GPIO Level for Input or Output values by RSMRST# and also by a write to the CF9h register.
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23 GP_LVL[n]
6 GP_LVL[n]
8.10.5 Offset GPIOBASE + 18h: GPO_BLINK—GPO Blink
Table 317. Offset GPIOBASE + 18h: GPO_BLINK—GPO Blink Enable Register 0 = The corresponding GPIO will function normally. not altered when this bit is set.
8 GP_BLINK[n]
to their default values by PXPCIRST#. 0 = The corresponding GPIO will function normally. not altered when this bit is set.
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8.10.6 Offset GPIOBASE + 2Ch: GPI_INV—GPIO Signal
Table 318. Offset GPIOBASE + 2Ch: GPI_INV—GPIO Signal Invert Register a write to the CF9h register.
8.10.7 Offset GPIOBASE + 30h:GPIO_USE_SEL2—GPIO
Table 319. Offset GPIOBASE + 30h:GPIO_USE_SEL2—GPIO Use Select 2 Register 6 Always 0. No corresponding GPIO. 4 Always 1. These pins are unmuxed. 2 Always 0. No corresponding GPIO. GPO mode must be glitch-free. 1 = Signal used as GPIO (or unmuxed). 0 = Signal used as native function. the core well are configured as GPIO. GPO mode must be glitch-free. 1 = Signal used as GPIO (or unmuxed). 0 = Signal used as native function. the core well are configured as GPIO. Implementation Note: Bits 26:31 may be in CORE Well.
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8.10.8 Offset GPIOBASE + 34h: GP_IO_SEL2—GPIO
8.10.9 Offset GPIOBASE + 38h: GP_LVL2—GPIO Level for
Table 320. Offset GPIOBASE + 34h: GP_IO_SEL2—GPIO Input/Output Select 2 6 Always 0. No corresponding GPIO. 2 Always 0. No corresponding GPIO. Implementation Note: Bits 26:31 may be in CORE Well. Table 321. Offset GPIOBASE + 38h: GP_LVL2—GPIO Level for Input or Output 2
4 GP_LVL[57:56]
high or low value on the output pin. 1 = high, 0 = low. cause a high value on the pin. these bits will be reset by RTCRST#.
drive a high or low value on the output pin. 1 = high, 0 = low. signal (1 = high, 0 = low). Writes will have no effect. these bits will be reset by PXPCIRST#. Implementation Note: Bits 26:31 may be in CORE Well.
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9.1 PCI Configuration Registers (IDE—D31:F1)
Table 322. PCI Configuration Map (IDE-D31:F1)
- See the Intel® 6300ESB ICH Specification Update for the most up-to-date value of the Revision ID Register.
- The Intel® 6300ESB ICH IDE controller is not arbitrated as a PCI device, therefore it does not need a master
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9.1.1 Offset 00 - 01h: VID—Vendor ID Register (LPC I/
9.1.2 Offset 02 - 03h: DID—Device ID Register (LPC I/
Table 323. Offset 00 - 01h: VID—Vendor ID Register (LPC I/F—D31:F1) 15:0 Vendor ID Value This is a 16-bit value assigned to Intel. Intel VID = 8086h. Table 324. Offset 02 - 03h: DID—Device ID Register (LPC I/F—D31:F1)
9.1.3 Offset 04h - 05h: CMD—Command Register (IDE—
Table 325. Offset 04h - 05h: CMD—Command Register (IDE—D31:F1)
10 Interrupt Disable (ID)
4 Postable Memory Write
NOTE: BIOS should set this bit to a 1.
0 IOSE - I/O Space Enable
This bit controls access to the I/O space registers. registers should be programmed before this bit is set.
- Separate bits are provided (IDE Decode Enable, in the IDE
- When this bit is 0 and the IDE controller is in Native Mode,
masking ends, the interrupt will be allowed to be asserted.
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9.1.4 Offset 06 - 07h: STS—Device Status Register
Table 326. Offset 06 - 07h: STS—Device Status Register (IDE—D31:F1)
13 Received Master-Abort
0 Cleared by writing a 1 to it.
11 Signaled Target-Abort
0 = Cleared by writing a 1 to it. terminates with a target abort.
8 Data Parity Error
7 Fast Back-to-Back
4 Capabilities List (CAP) Reserved as ‘0’ RO
3 Interrupt Status (IS)
the Interrupt Disable bit in the command register.
9.1.5 Offset 08h: RID—Revision ID Register (IDE—
9.1.6 Offset 09h: PI—Programming Interface (IDE—
Table 327. Offset 08h: RID—Revision ID Register (IDE—D31:F1) up-to-date value of the Revision ID Register. Table 328. Offset 09h: PI—Programming Interface (IDE—D31:F1)
7 This read-only bit is a 1 to indicate that the Intel ® 6300ESB
6:4 Reserved Reserved. Will always return 0. controller supports both legacy and native modes.
2 SOP_MODE_SEL
IDE channel is operating in. supports both legacy and native modes. IDE channel is operating in.
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9.1.7 Offset 0Ah: SCC—Sub Class Code (IDE—D31:F1)
Table 329. Offset 0Ah: SCC—Sub Class Code (IDE—D31:F1)
9.1.8 Offset 0Bh: BCC—Base Class Code (IDE—D31:F1)
9.1.9 Offset 0Dh: MLT—Master Latency Timer (IDE—
9.1.10 Offset 10h - 13h: PCMD_BAR—Primary Command
Table 330. Offset 0Bh: BCC—Base Class Code (IDE—D31:F1) Table 331. Offset 0Dh: MLT—Master Latency Timer (IDE—D31:F1) need a Master Latency Timer. These bits are fixed at 0. Table 332. Offset 10h - 13h: PCMD_BAR—Primary Command Block Base
0 Resource Type Indicator
NOTE: This 8-byte I/O space is used in native mode for the Primary Controller’s Command Block.
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9.1.11 Offset 14h - 17h: PCNL_BAR—Primary Control
9.1.12 Offset 18h - 1Bh: SCMD_BAR—Secondary
Table 333. Offset 14h - 17h: PCNL_BAR—Primary Control Block Base Address NOTE: This 4-byte I/O space is used in native mode for the Primary Controller’s Command Block. Table 334. Offset 18h - 1Bh: SCMD_BAR—Secondary Command Block Base NOTE: This 4-byte I/O space is used in native mode for the Secondary Controller’s Command Block.
9.1.13 Offset 1Ch - 1Fh: SCNL_BAR—Secondary Control
9.1.14 Offset 20h - 23h: BM_BASE—Bus Master Base
are used to decode the address. Table 335. Offset 1Ch - 1Fh: SCNL_BAR—Secondary Control Block Base NOTE: This 4-byte I/O space is used in native mode for the Secondary Controller’s Command Block. Table 336. Offset 20h - 23h: BM_BASE—Bus Master Base Address Register 15:4 Base Address Base address of the I/O space (16 consecutive I/O locations).
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9.1.15 Offset 24h - 27h: CPBA – IDE Command Posting
Intel® 6300ESB ICH to properly decode the accesses to this range. Table 337. Offset 24h - 27h: CPBA – IDE Command Posting Base Address
0 Base Address Base address of the IDE Command Posting memory space
0 RTE – Resource Type
9.1.16 Offset 2Ch - 2Dh: IDE_SVID—Subsystem Vendor
Table 338. Offset 2Ch - 2Dh: IDE_SVID—Subsystem Vendor ID (IDE—D31:F1) read, but subsequent writes to this register have no effect. UHCI #2, and SMBus functions.
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9.1.17 Offset 2Eh - 2Fh: IDE_SID—Subsystem ID (IDE—
Table 339. Offset 2Eh - 2Fh: IDE_SID—Subsystem ID (IDE—D31:F1) Table 340. Offset 3Ch: INTR_LN—Interrupt Line Register (IDE—D31:F1) interrupt pin is connected to.
9.1.19 Offset 3Dh: INTR_PN—Interrupt Pin Register
9.1.20 IDE_TIM—IDE Timing Register (IDE—D31:F1)
transfers. It also controls operation of the buffer for PIO transfers. Table 341. Offset 3Dh: INTR_PN—Interrupt Pin Register (IDE—D31:F1)
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Table 342. IDE_TIM—IDE Timing Register (IDE—D31:F1) (Sheet 1 of 3)
15 IDE Decode Enable
Individually enable/disable the Primary or Secondary decode.
14 Drive 1 Timing Register
0 = Use bits 13:12, 9:8 for both drive 0 and drive 1.
10 Fast Non-Data PIO
achievable on Hub Interface rather than the RCT timing. IOR#/IOW# strobe of the next cycle.
7 Drive 1 DMA Timing
6 Drive 1 Prefetch/Posting
5 Drive 1 IORDY Sample
0 = Disable IORDY sampling for this drive. Table 342. IDE_TIM—IDE Timing Register (IDE—D31:F1) (Sheet 2 of 3)
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4 Drive 1 Fast Timing Bank
3 Drive 0 DMA Timing
2 Drive 0 Prefetch/Posting
1 Drive 0 IORDY Sample
0 = Disable IORDY sampling is disabled for this drive.
0 Drive 0 Fast Timing Bank
Table 342. IDE_TIM—IDE Timing Register (IDE—D31:F1) (Sheet 3 of 3)
9.1.21 Offset 44H: SLV_IDETIM—Slave (Drive 1) IDE
Table 343. Offset 44H: SLV_IDETIM—Slave (Drive 1) IDE Timing Register register for secondary is set. of the IDE timing register for secondary is set. of the IDE timing register for primary is set.
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9.1.22 Offset 48h: SDMA_CNT—Synchronous DMA
Table 344. Offset 48h: SDMA_CNT—Synchronous DMA Control Register (IDE—
9.1.23 Offset 4A - 4Bh: SDMA_TIM—Synchronous DMA
Table 345. Offset 4A - 4Bh: SDMA_TIM—Synchronous DMA Timing Register
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9.2 Bus Master IDE I/O Registers (D31:F1)
master IDE I/O space registers may be accessed as byte, word, or DWORD quantities. registers is shown below in Table 347. Table 346. IDE_CONFIG—IDE I/O Configuration Register (IDE—D31:F1)
31 Enable Prefetch and
PIO posting and prefetching will not occur until this bit is set. Table 347. Bus Master IDE I/O Registers
00 BMICP Command Register Primary 00h R/W
01 Reserved 00h RO
02 BMISP Status Register Primary 00h R/WC
03 Reserved 00h RO
08 BMICS Command Register Secondary 00h R/W
09 Reserved 00h RO
9.2.1 BMIC[P,S]—Bus Master IDE Command
Table 348. BMIC[P,S]—Bus Master IDE Command Register 7:4 Reserved Reserved. Returns ‘0’.
3 Read / Write Control
must NOT be changed when the bus master function is active. 2:1 Reserved Reserved. Returns ’0’.
0 Start/Stop Bus Master
0 = All state information is lost when this bit is cleared. not clear this bit automatically.
9.2.2 BMIS[P,S]—Bus Master IDE Status Register
Table 349. BMIS[P,S]—Bus Master IDE Status Register
7 PRD_INT_STS
6 Drive 1 DMA Capable
do not attach BMIDE to the PCI bus.
5 Drive 0 DMA Capable
do not attach BMIDE to the PCI bus. 4:3 Reserved Reserved. Returns ’0’.
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assertion edge is detected on the interrupt line. abort or master abort when transferring data on PCI.
0 Bus Master IDE Active
bus master command was aborted. written to the Command register.
9.2.3 BMID[P,S]—Bus Master IDE Descriptor Table
Table 350. BMID[P,S]—Bus Master IDE Descriptor Table Pointer Register
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10.1 PCI Configuration Registers (D29:F0/F1)
Configuration Map” for details). Table 351. PCI Configuration Map (USB—D29:F0/F1) date value of the Revision ID Register.
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10.1.1 Offset 00 - 01h: VID—Vendor Identification
10.1.2 Offset 02 - 03h: DID—Device Identification
Table 352. Offset 00 - 01h: VID—Vendor Identification Register (USB—D29:F0/ Table 353. Offset 02 - 03h: DID—Device Identification Register (USB—D29:F0/
Table 354. Offset 04 - 05h: CMD—Command Register (USB—D29:F0/F1)
9 Fast Back-to-back
0 I/O Space Enable (IOSE)
This bit controls access to the I/O space registers.
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Table 355. Offset 06 - 07h: STA—Device Status Register (USB—D29:F0/F1) 0 = Software clears this bit by writing a ’1’ to the bit location. 0 = Software clears this bit by writing a ’1’ to the bit location. Intel® 6300ESB ICH terminates with a target abort. This 2-bit field defines the timing for DEVSEL# assertion. Table 356. Offset 08h: RID—Revision Identification Register (USB—D29:F0/F1)
10.1.6 Offset 09h: PI—Programming Interface (USB—
10.1.9 Offset 0Dh: MLT—Master Latency Timer
Interface, not PCI, it does not need a master latency timer. The bits are fixed at ‘0’. Table 357. Offset 09h: PI—Programming Interface (USB—D29:F0/F1) Table 358. Offset 0Ah: SCC—Sub Class Code Register (USB—D29:F0/F1) Table 359. Offset 0Bh: BCC—Base Class Code Register (USB—D29:F0/F1)
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10.1.10 Offset 0Eh: HTYPE—Header Type Register
the values in bits 15 and 9 of the function disable register (D31:F0:F2h). Table 360. Offset 0Dh: MLT—Master Latency Timer MLT These bits are fixed at ‘0’. Table 361. Offset 0Eh: HTYPE—Header Type Register (USB—D29:F0/F1)
7 Multi-Function Bit
10.1.11 Offset 20 - 23h: BASE—Base Address Register
10.1.12 Offset 2Ch - 2Dh: SVID—Subsystem Vendor ID
Table 362. Offset 20 - 23h: BASE—Base Address Register (USB—D29:F0/F1) Table 363. Offset 2Ch - 2Dh: SVID—Subsystem Vendor ID (USB—D29:F0/F1) by BIOS into the IDE_SVID register.
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10.1.13 Offset 2Eh-2Fh: SID—Subsystem ID (USB—
10.1.14 Offset 3Ch: INTR_LN—Interrupt Line Register
Table 364. Offset 2Eh-2Fh: SID—Subsystem ID (USB—D29:F0/F1) Table 365. Offset 3Ch: INTR_LN—Interrupt Line Register (USB—D29:F0/F1)
10.1.15 Offset 3Dh: INTR_PN—Interrupt Pin Register
10.1.16 Offset 60h: USB_RELNUM—USB Release Number
10.1.17 Offset C0 - C1h: USB_LEGKEY—USB Legacy
Table 366. Offset 3Dh: INTR_PN—Interrupt Pin Register (USB—D29:F0/F1) 6300ESB ICH PIRQ inputs. Function 0 will drive PIRQA. Table 367. Offset 60h: USB_RELNUM—USB Release Number Register (USB—
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Table 368. Offset C0 - C1h: USB_LEGKEY—USB Legacy Keyboard/ Mouse Control to determine the exact cause of the SMI#.
13 PCI Interrupt Enable
12 SMI Caused by USB
Indicates if an interrupt event occurred from this controller. enable bit to determine the exact cause of the SMI#. controllers. Writing a ’1’ to this bit will have no effect.
11 SMI Caused by Port 64
complete without setting this bit. NOTE: If bit 7 of the ETR1 (D31:F0, offset F4h ETR1) is set. external PCI agent will not set this bit.
10 SMI Caused by Port 64
to determine the exact cause of the SMI#. NOTE: If bit 7 of the ETR1 (D31:F0, offset F4h ETR1) is set. external PCI agent will not set this bit.
9 SMI Caused by Port 60
complete without setting this bit. NOTE: If bit 7 of the ETR1 (D31:F0, offset F4h ETR1) is set. external PCI agent will not set this bit.
8 SMI Caused by Port 60
to determine the exact cause of the SMI#. NOTE: If bit 7 of the ETR1 (D31:F0, offset F4h ETR1) is set. external PCI agent will not set this bit. through and needs to be serviced later.
6 Pass-Through State
in all of the host controllers to 0. A20GATE pass-through sequence.
5 A20Gate Pass-Through
64h does not result in the setting of the SMI status bits.
4 SMI on USB IRQ Enable
3 SMI on Port 64 Writes
1 = A ’1’ in bit 11 will cause an SMI event. NOTE: If bit 7 of the ETR1 (D31:F0, offset F4h ETR1) is set. external PCI agent will not set this bit.
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10.1.18 Offset C4h: USB_RES—USB Resume Enable
Note: This register is in the Resume Well.
2 SMI on Port 64 Reads
1 = A ’1’ in bit 10 will cause an SMI event. NOTE: If bit 7 of the ETR1 (D31:F0, offset F4h ETR1) is set. external PCI agent will not set this bit.
1 SMI on Port 60 Writes
1 = A ’1’ in bit 9 will cause an SMI event. NOTE: If bit 7 of the ETR1 (D31:F0, offset F4h ETR1) is set. external PCI agent will not set this bit.
0 SMI on Port 60 Reads
1 = A ’1’ in bit 8 will cause an SMI event. NOTE: If bit 7 of the ETR1 (D31:F0, offset F4h ETR1) is set. external PCI agent will not set this bit. Table 369. Offset C4h: USB_RES—USB Resume Enable Register (USB—D29:F0/ wakeup and connect/disconnect events.
10.2 USB I/O Registers
the PORTSC registers, bits [12,6,2]. See individual bit descriptions for more detail.
10.2.1 Offset 00 - 01h: USBCMD—USB Command Register
Table 370. USB I/O Registers
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Table 371. Offset 00 - 01h: USBCMD—USB Command Register (Sheet 1 of 3)
8 Loop Back Test Mode
0 = Disable loop back test mode.
7 Max Packet (MAXP)
for full-speed bandwidth reclamation at the end of a frame. error when executed during the critical window at frame end.
6 Configure Flag (CF)
semaphore service for software. of configuring the Host Controller.
5 Software Debug
the HCHalted bit in the USBSTS register. software sets the Run/Stop bit back to ‘1’.
4 Force Global Resume
transition causes the port to send a low speed EOP signal. This bit will remain a ’1’ until the EOP has completed.
3 Enter Global Suspend
(bit 0) is cleared prior to setting this bit. Table 371. Offset 00 - 01h: USBCMD—USB Command Register (Sheet 2 of 3)
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2 Global Reset (GRESET)
Controller does not send the Global Reset on USB.
1 Host Controller Reset
port. This virtual disconnect causes the port to be disabled. and bits 0 and 8 of the PORTSC will change accordingly. resets its internal timers, counters, state machines, etc. on USB is immediately terminated.
0 Run/Stop (RS)
consistency check failure, PCI Bus errors. prior to setting this bit again. Table 371. Offset 00 - 01h: USBCMD—USB Command Register (Sheet 3 of 3)
- HCD puts Host Controller in Stop state by setting the Run/Stop bit to ‘0’.
- HCD puts Host Controller in Debug Mode by setting the SWDBG bit to ‘1’.
- HCD sets up the correct command list and Start Of Frame value for starting point in
the Frame List Single Step Loop.
- HCD sets Run/Stop bit to ’1’.
- Host Controller executes next active TD, sets Run/Stop bit to ‘0’ and stops.
- HCD reads the USBCMD register to check if the single step execution is completed
- HCD checks results of TD execution. Go to step 4 to execute next TD or step 8 to
- HCD ends Software Debug mode by setting SWDBG bit to ‘0’.
- HCD sets up normal command list and Frame List table.
- HCD sets Run/Stop bit to ‘1’ to resume normal schedule execution.
In Software Debug mode, when the Run/Stop bit is set, the Host Controller starts. HCHalted bit in the USBSTS register (bit 5) is set. Table 372. Run/Stop, Debug Bit Interaction SWDBG (Bit 5), Run/Stop (Bit 0) Run/Stop = 0, the FRNUM register may be reprogrammed). frame list pointer selected by the current value in the FRNUM register.
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FRNUM Register description) rather than continuing where it stopped.
10.2.2 Offset 02 - 03h: USBSTA—USB Status Register
status resulting from a transaction on the serial bus is not indicated in this register. Software sets a bit to ‘0’ in this register by writing a ‘1’ to it. Table 373. Offset 02 - 03h: USBSTA—USB Status Register (Sheet 1 of 2)
4 Host Controller Process
hardware interrupt is generated to the system.
10.2.3 Offset Base + (04 - 05h): USBINTR—Interrupt
2 Resume Detect
1 USB Error Interrupt
set, both this bit and Bit ’0’ are set.
0 USB Interrupt (USBINT)
detection is enabled in that TD. Table 374. Offset Base + (04 - 05h): USBINTR—Interrupt Enable Register (Sheet
3 Short Packet Interrupt
Table 373. Offset 02 - 03h: USBSTA—USB Status Register (Sheet 2 of 2)
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2 Interrupt On Complete
1 Resume Interrupt
0 Timeout/CRC Interrupt
10.2.4 Offset Base + (06 - 07h): FRNUM—Frame Number
[9:0] are used to select a particular entry in the Frame List during scheduled execution. This register is updated at the end of each frame time. (USBCMD register) is ignored.
10.2.5 Offset Base + (08 - 0Bh): FRBASEADD—Frame List
for all list entries. This configuration supports 1024 Frame List entries. Table 375. Offset Base + (06 - 07h): FRNUM—Frame Number Register Table 376. Offset Base + (08 - 0Bh): FRBASEADD—Frame List Base Address
2 Base Address These bits correspond to memory address signals [31:12],
10.2.6 Offset Base + OCh: SOFMOD—Start of
Table 377. Offset Base + OCh: SOFMOD—Start of Frame Modify Register
- For a 12 MHz SOF counter clock input, this produces a
10.2.7 PORTSC[0,1]—Port Status and Control Register
1 this applies to the Intel® 6300ESB ICH USB ports 2 and 3. Table 378. PORTSC[0,1]—Port Status and Control Register (Sheet 1 of 2) currently in progress on the USB. 0 = Port not in suspend state.
11 Overcurrent Indicator
0 = Software clears this bit by writing a ‘1’ to the bit position.
10 Overcurrent Active
This bit is set and cleared by hardware. 0 = Indicates that the overcurrent pin is inactive (high). 1 = Indicates that the overcurrent pin is active (low).
8 Low Speed Device
0 = Full-speed device is attached. 1 = Low-speed device is attached to this port.
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6 Resume Detect
the port is still in the suspend state (bit 12, 2 are ‘11’). EOP. This bit will remain a ’1’ until the EOP has completed. 0 = No resume (K-state) detected/driven on port. 1 = Resume detected/driven on port. at EOF2 time (See Chapter 11 of the USB Specification).
3 Port Enable/Disable
1 = Port enabled/disabled status has changed. there is a transaction currently in progress on the USB.
1 Connect Status Change
determining state change history in such a case. 1 = Change in Current Connect Status.
0 Current Connect Status
Status Change bit (Bit 1) to be set. 1 = Device is present on port. Table 378. PORTSC[0,1]—Port Status and Control Register (Sheet 2 of 2)
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 485 11—Intel ® 6300ESB ICH USB EHCI Controller Registers (D29:F7) 11
11.1 USB EHCI Configuration Registers (D29:F7)
Note: Registers that are not shown should be treated as Reserved (see Section 6.2, “PCI Configuration Map” for details). Offset Reg. Name/Function Default Value Type 00-01h Vendor ID 8086h RO 02-03h Device ID 25ADh RO 04-05h Command Register 0000h RW 06-07h Device Status 0290h RW 08h Revision ID (RID) See NOTE: RO 09h Programming Interface 20h RO 0Ah Sub Class Code 03h RO 0Bh Base Class Code 0Ch RO 0Dh Master Latency Timer 00h RO 0Eh Header Type 00h RO 10-13h Memory Base Address Register 00000000h RW 2C-2Dh Subsystem Vendor ID XXXXh RW-Special 2E-2Fh Subsystem ID XXXXh RW-Special 34h Capabilities Pointer 50h RO 3Ch Interrupt Line 00h RW 3Dh Interrupt Pin 04h RO 50h Power Management Capability ID 01h RO 51h Next Item Ptr 58h RO 52-53h Power Management Capabilities C9C2h RO-Special 54-55h Power Management Control/ Status 0000h RW 57h Power Management Data 00h RO 58h Debug Port Capability ID 0Ah RO 59h Next Item Pointer #2 00h RO 5A-5Bh Debug Port Base Offset 2080h RO 60h USB Release Number 20h RO 61h Frame Length Adjustment 20h RW 62-63h Power Wake Capabilities 007Fh RW 64-65h Classic USB Override 0000 RO NOTE: Refer to the Intel® 6300ESB I/O Controller Hub Specification Update for the most up- to-date value of the Revision ID Register.
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11.1.1 Offset 04 - 05h: Command Register
Table 379. Offset 04 - 05h: Command Register capability to generate an SERR#. Interface (and subsequently on its internal interface). 0 = Disables this functionality. the PCI bus for USB transfers. 0 = Disables this functionality. to-date value of the Revision ID Register.
11.1.2 Offset 06 - 07h: Device Status
Table 380. Offset 06 - 07h: Device Status 0 = Software clears this bit by writing a ’1’ to this bit location. Command Register) must be ’1’ for this bit to be set. 0 = Software clears this bit by writing a ’1’ to this bit location. 0 = Software clears this bit by writing a ’1’ to this bit location. this to happen, so this bit will be hard-wired to ’0’. 0 = Software clears this bit by writing a ’1’ to this bit location.
6 UDF - User Definable
4 Capabilities List This bit is hardwired to ‘1’ indicating the presence of a valid
Intel® 6300ESB ICH—11 Intel® 6300ESB I/O Controller Hub DS November 2007
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11.1.3 Offset 08h: RID—Revision ID Register
11.1.4 Offset 09h: Programming Interface
11.1.5 Offset 0Ah: Sub Class Code
Table 381. Offset 08h: RID—Revision ID Register Table 382. Offset 09h: Programming Interface Table 383. Offset 0Ah: Sub Class Code
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11.1.6 Offset 0Bh: Base Class Code
11.1.7 Offset 0Dh: Master Latency Timer
11.1.8 Offset 10 - 13h: Memory Base Address
Table 384. Offset 0Bh: Base Class Code Table 385. Offset 0Dh: Master Latency Timer not need a master latency timer. These bits will be fixed to 0. Table 386. Offset 10 - 13h: Memory Base Address
0 Base Address
aligned to 1 Kbyte boundaries.
11.1.9 Offset 2C - 2Dh: USB EHCI Subsystem Vendor ID
11.1.10 Offset 2E - 2Fh: SID—USB EHCI Subsystem ID
11.1.11 Offset 34h: Capabilities Pointer
Table 387. Offset 2C - 2Dh: USB EHCI Subsystem Vendor ID (offset 80h, bit 0) is set to 1. Table 388. Offset 2E - 2Fh: SID—USB EHCI Subsystem ID (offset 80h, bit 0) is set to 1. Table 389. Offset 34h: Capabilities Pointer
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11.1.12 Offset 3Ch: Interrupt Line
11.1.13 Offset 3Dh: Interrupt Pin
11.1.14 Offset 50h: PCI Power Management Capability ID
Table 390. Offset 3Ch: Interrupt Line interrupt line that the interrupt pin is connected to. Table 391. Offset 3Dh: Interrupt Pin the fourth interrupt pin from the device–NTD# in PCI terms. Internally the USB EHCI controller uses PIRQ[H]#. Table 392. Offset 50h: PCI Power Management Capability ID
11.1.15 Offset 51h: Next Item Pointer #1
11.1.16 Offset 52 - 53h: Power Management Capabilities
Table 393. Offset 51h: Next Item Pointer #1 expected to be programmed in this register. Table 394. Offset 52 - 53h: Power Management Capabilities (Sheet 1 of 2)
1 PME_Support
Intel® 6300ESB ICH EHC is capable of generating PME#. Software should never need to modify this field.
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11.1.17 Offset 54 - 55h: Power Management Control/
- Normally, this register is read-only to report capabilities to the power management software. To report
register does not affect the hardware other than changing the value returned during a read.
- Reset: Core well, but not D3-to-D0 warm reset.
Table 395. Offset 54 - 55h: Power Management Control/Status
15 PME_Status
system each time the operating system is loaded.
3 Data_Scale The Intel® 6300ESB ICH hardwires these bits to 00b because
Table 394. Offset 52 - 53h: Power Management Capabilities (Sheet 2 of 2)
11.1.18 Offset 58h: Debug Port Capability ID
however, the data is discarded and no state change occurs. D0 state, the generation of the interrupt output is blocked. 6300ESB ICH when not in the D0 state. software must re-initialize the function. NOTE: Reset (bits 15, 8): suspend well, and not D3-to-D0 warm reset nor core well reset. Table 396. Offset 58h: Debug Port Capability ID
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11.1.19 Offset 59h: Next Item Pointer #2
11.1.20 Offset 5Ah - 5Bh: Debug Port Base Offset
11.1.21 Offset 60h: Serial Bus Release Number
11.1.22 Offset 61h: Frame Length Adjustment
Table 397. Offset 59h: Next Item Pointer #2 Table 398. Offset 5Ah - 5Bh: Debug Port Base Offset
3 BAR Number This field is hardwired to 20h to indicate the memory BAR
Table 399. Offset 60h: Serial Bus Release Number
11.1.23 Offset 62 - 63h: Port Wake Capability
Table 400. Offset 61h: Frame Length Adjustment decimal 32 (20h), which gives a SOF cycle time of 60000.
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11.1.24 Offset 64 - 65h: Classic USB Override
- The associated Port Owner bit does not reflect the value in this new Override register. This guarantees compatibility with EHCI drivers.
- The associated Port Owner bit does not reflect the value in this new Override register. This guarantees compatibility with EHCI drivers.
- BIOS must only write to this register during initialization (while the Configured Flag is ‘0’).
- The register is implemented in the Suspend well to maintain port-routing when the core power goes down
- When a ‘1’ is present in the Override register, the classic controller operates the port regardless of the EHCI port routing logic. The corresponding EHCI port will always appear disconnected in this mode. Note: EHCI test modes will not work on a port that has been overridden by this register.
Table 401. Offset 62 - 63h: Port Wake Capability
0 Port Wake Implemented A ’1’ in bit 0 indicates that this register is implemented to
Table 402. Offset 64-65h: CUO - Classic USB Override
11.1.25 Offset 68 - 6Bh: USB EHCI Legacy Support
Table 403. Offset 68 - 6Bh: USB EHCI Legacy Support Extended Capability 5 Reserved Reserved. Hardwired to 00h. ’1’ and the HC BIOS Owned Semaphore bit reads as clear.
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11.1.26 Offset 6C - 6Fh: USB EHCI Legacy Support
Table 404. Offset 6C - 6Fh: USB EHCI Legacy Support Extended Control/Status
31 SMI on BAR This bit is set to ‘1’ whenever the Base Address Register
30 SMI on PCI Command This bit is set to ‘1’ whenever the PCI Command Register is
29 SMI on OS Ownership
register transitions from ’1’ to a ’0’ or ’0’ to a ‘1’.
21 SMI on Async Advance
20 SMI on Host System
Error bit in the USB2STS register.
19 SMI on Frame List
Shadow bit of Frame List Rollover bit in the USB2STS register. List Rollover bit in the USB2STS register.
18 SMI on Port Change
Shadow bit of Port Change Detect bit in the USB2STS register. Change Detect bit in the USB2STS register.
17 SMI on USB Error
16 SMI on USB Complete
the USB Interrupt bit in the USB2STS register.
15 SMI on BAR Enable When this bit is ‘1’ and SMI on BAR is ‘1’, the host controller
14 SMI on PCI Command
13 SMI on OS Ownership
5 SMI on Async Advance
11.1.27 Offset 70 - 73h: Intel Specific USB EHCI SMI
4 SMI on Host System
3 SMI on Frame List
2 SMI on Port Change
1 SMI on USB Error Enable When this bit is a ’1’ and the SMI on USB Error bit is a ’1’, the
0 SMI on USB Complete
Table 405. Offset 70 - 73h: Intel Specific USB EHCI SMI (Sheet 1 of 2)
2 SMI on PortOwner
associated Port Owner bits transition from ‘0’->’1’ or ‘1’->’0’. Software clears these bits by writing a ’1’.
21 SMI on PMCSR
20 SMI on Async This bit is set to ‘1’ whenever the Async Schedule Enable bit
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19 SMI on Periodic This bit is set to ‘1’ whenever the Periodic Schedule Enable bit
18 SMI on CF This bit is set to ‘1’ whenever the Configure Flag (CF)
17 SMI on HCHalted This bit is set to ‘1’ whenever HCHalted transitions to ‘1’ as a
16 SMI on HCReset This bit is set to ‘1’ whenever HCRESET transitions to ‘1’ R/WC
PortOwner bits are ‘1’, the host controller will issue an SMI. Unused ports should have their corresponding bits cleared.
3 SMI on Periodic Enable When this bit is ‘1’ and SMI on Periodic is ‘1’, the host
2 SMI on CF Enable When this bit is ‘1’ and SMI on CF is ‘1’, then the host
1 SMI on HCHalted Enable When this bit is a ‘1’ and SMI on HCHalted is ‘1’, the host
Table 405. Offset 70 - 73h: Intel Specific USB EHCI SMI (Sheet 2 of 2)
11.1.28 Offset 80h: Access Control
11.1.29 HS_ Ref_V_USB HS Reference Voltage Register
11.2 Memory-Mapped I/O Registers
Capability Registers and Operational Registers. Table 406. Offset 80h: Access Control
- System-configured parameters
Table 407. HS_ Ref_V_USB HS Reference Voltage Register
2 Reserved Reserved RO
6 USB2 HS Ref Voltage
POST and resume from S3(STR)/S4(STD) states on ALL steppings of the Intel 6300ESB ICH.
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to any other targets that may be currently using that range.
11.2.1 Host Controller Capability Registers
11.2.1.1 Offset 00h: CAPLENGTH—Capability Registers Length
Table 408. Offset 00h: CAPLENGTH—Capability Registers Length Registers begin at offset 20h.
11.2.1.2 Offset 02 - 03h: HCIVERSION—Host Controller Interface
11.2.1.3 Offset 04 - 07h: HCSPARAMS—Host Controller Structural
Note: This register is reset by a suspend well reset and not a D3-to-D0 reset or HCRESET. Note: This register is writable when the WRT_RDONLY bit is set. Table 409. Offset 02 - 03h: HCIVERSION—Host Controller Interface Version Table 410. Offset 04 - 07h: HCSPARAMS—Host Controller Structural Parameters lowest numbered port on the Intel ® 6300ESB ICH. 16 Reserved Reserved. Hardwired to 0.
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associated with this USB ECHI host controller. are supported on the host controller root ports. 6300ESB ICH hardwires this field to 2h. 7:4 Reserved Reserved. These bits are reserved and default to ’0’.
11.2.1.4 Offset 08 - 0Bh: HCCPARAMS—Host Controller Capability
Table 411. Offset 08 - 0Bh: HCCPARAMS—Host Controller Capability Parameters information for scheduling isochronous transfers. This field is hardwired to 7h. 3 Reserved Reserved. These bits are reserved and should be set to ’0’.
2 Asynchronous Schedule
does not support this optional feature.
1 Programmable Frame
software should use the 32-bit or 64-bit data structures.
Intel® 6300ESB ICH—11 Intel® 6300ESB I/O Controller Hub DS November 2007
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11.2.2 Host Controller Operational Registers
This section defines the enhanced host controller operational registers. These registers are located after the capabilities registers. The operational register base must be DWORD-aligned and is calculated by adding the value in the first capabilities register (CAPLENGTH=20h) to the base address of the enhanced host controller register address space. All registers are 32 bits in length. Note: Software must read and write these registers using only DWORD accesses. These registers are divided into two sets. The first set at offsets 20h to 3Fh are implemented in the core power well. Unless otherwise noted, the core-well registers are reset by the assertion of any of the following:
- Core well hardware reset
- HCRESET
- D3-to-D0 reset The second set at offsets 60h to the end of the implemented register space are implemented in the Suspend power well. Unless otherwise noted, the suspend-well registers are reset by the assertion of either of the following:
- Suspend well hardware reset
- HCRESET Offset Register Default Special Notes Type 00-03h USB EHCI Command 00080000h R/W 04-07h USB EHCI Status 00001000h R/W 08-0Bh USB EHCI Interrupt Enable 00000000h R/W 0C-0Fh USB EHCI Frame Index 00000000h R/W 10-13h Control Data Structure Segment 00000000h R/W 14-17h Period Frame List Base Address 00000000h R/W 18-1Bh Next Asynchronous List Address 00000000h R/W 1C-3Fh Reserved 0h RO 40- 43h Configure Flag Register 00000000h Suspend R/W 44-47h Port 0 Status and Control 00003000h Suspend R/W 48-4Bh Port 1 Status and Control 00003000h Suspend R/W 4C-4Fh Port 2 Status and Control 00003000h Suspend R/W 50-53h Port 3 Status and Control 00003000h Suspend R/W 54-5Fh Reserved Undefined RO 60-73h Debug Port Registers. Undefined RO 74-3FFh Reserved Undefined RO
Table 412. Offset CAPLENGTH + 00 - 03h: USB EHCI CMD—USB EHCI Command 4 Reserved Reserved. These bits are reserved and should be set to ’0’. 15:8 Reserved Reserved. These bits are reserved and should be set to ’0’. does not support this optional feature.
7 Light Host Controller
6 Interrupt on Async
5 Asynchronous Schedule
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4 Periodic Schedule Enable
PWROK deassertion on the Intel® 6300ESB ICH). Capability Registers are not effected by this reset . process early by writing a ’0’ to this register. reset can be used to leave EHCI port test modes. finished the transaction and has entered the stopped state. to the register causes a command to be executed.
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11.2.2.2 Offset CAPLENGTH + 04 - 07h: USB EHCI STS—USB EHCI
status resulting from a transaction on the serial bus is not indicated in this register. USB EHCI interrupt conditions. Table 413. Offset CAPLENGTH + 04 - 07h: USB EHCI STS—USB EHCI Status (Sheet 6 Reserved Reserved. These bits are reserved and should be set to ’0’.
15 Asynchronous Schedule
Asynchronous Schedule Enable bit in the USBCMD register.
14 Periodic Schedule Status
Schedule is either enabled (1) or disabled (0).
13 Reclamation
12 HCHalted
5 Interrupt on Async
indicates the assertion of that interrupt source.
the Interrupt Enable Register).
3 Frame List Rollover
detected on a suspended port. provide a valid view of the Port Status registers. will result in this interrupt being asserted. Descriptor had its IOC bit set. than the expected number of bytes).
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11.2.2.4 Offset CAPLENGTH + 0C - 0Fh: FRINDEX—Frame Index
Table 414. Offset CAPLENGTH + 08 - 0Bh: USB EHCI INTR—USB EHCI Interrupt 31:6 Reserved Reserved.These bits are reserved and should be ’0’.
4 Host System Error
the Frame List Rollover bit.
2 Port Change Interrupt
- For all enable register bits, 1= Enabled, 0= Disabled.
- This register enables and disables reporting of the corresponding interrupt to the software. When a bit is set
Section 4 of the EHCI Specification), or not.
the SOF value. See Section 4 of the EHCI Specification for details. to increment SOFV each time the FRINDEX[2:0] increments from a ’0’ to a ’1’. FRINDEX value where the three least significant bits are 111b or 000b.
11.2.2.5 Offset CAPLENGTH + 10 - 13h: CTRLDSSEGMENT—Control
ASYNCLISTADDR, or any control data structure link field to construct a 64-bit address. same 4 Gbyte memory segment. Table 415. Offset CAPLENGTH + 0C - 0Fh: FRINDEX—Frame Index
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11.2.2.6 Offset CAPLENGTH + 14 - 17h: PERIODICLISTBASE—
Controller to step through the Periodic Frame List in sequence. this physical memory pointer is assumed to be 32-byte aligned. Table 416. Offset CAPLENGTH + 10 - 13h: CTRLDSSEGMENT—Control Data Table 417. Offset CAPLENGTH + 14 - 17h: PERIODICLISTBASE—Periodic Frame
2 Base Address (Low) These bits correspond to memory address signals [31:12],
of these bits are undefined.
11.2.2.8 Offset CAPLENGTH + 40 - 43h: CONFIGFLAG—Configure
11.2.2.9 PORTSC- Port N Status and Control
write to unreported Port Status and Control Registers.
- Port disabled. When a device is attached, the port state transitions to the attached
state and system software will process this as with any status change notification.
- When a port is being used as the Debug Port, the port may report device connected
and enabled when the Configured Flag is a ’0’. Table 418. Offset CAPLENGTH + 18 - 1Bh: ASYNCLISTADDR—Current Table 419. Offset CAPLENGTH + 40 - 43h: CONFIGFLAG—Configure Flag Register 31:1 Reserved Reserved. Read from this field will always return 0. Specification for operational details.
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Table 420. PORTSC- Port N Status and Control (Sheet 1 of 4) return a value of ’0’ when read.
22 Wake on Over-current
(bit 4 of this register) is set.
21 Wake on Disconnect
register changes from ’1’ to ‘0’).
20 Wake on Connect Enable
register changes from ’0’ to ‘1’). NOTE: This feature is not supported.
6 Port Test Control
4 Reserved Should be written to =00b; other values will result in
13 Port Owner
EHCI Specification for operational details.
0 Line Status
’0’ and the current connect status bit is set to a ’1’.
00 SE0 - Not Low-speed device, perform EHCI
10 J-state - Not Low-speed device, perform EHCI
01 K-state - Low speed device, release ownership
11 Undefined - Not Low-speed device, perform
9 Reserved Reserved. This bit will return a ’0’ when read. Specification Revision 2.0, completes. this bit from a ’1’ to a ’0’. HCHalted bit is a ’1’. This field is ’0’ if Port Power is ’0’. ’1’. Doing so will result in undefined behavior. Table 420. PORTSC- Port N Status and Control (Sheet 2 of 4)
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1 = Port in suspend state. 0 = Port not in suspend state.
10 Enable
11 Suspend
‘1’). A write of ’0’ to this bit is ignored by the host controller. state) detected/driven on port. Default = 0. must not set the Port Change Detect bit. switched to the high-speed idle.
5 Overcurrent Change
writing a ’1’ to this bit position. Table 420. PORTSC- Port N Status and Control (Sheet 3 of 4)
4 Overcurrent Active
over current condition is removed. the over-current active bit is ‘1’. 0 = No change in status. This is the default setting. 1 = Port enabled/disabled status has changed. Disabled-to-Enabled transition, nor due to a disconnect. Software clears this bit by writing a ’1’ to it. 1 = Change in Current Connect Status. 0 = No change. 1 = Device is present on port. 0 = No device is present. Connect Status Change bit (Bit 1) to be set. Table 420. PORTSC- Port N Status and Control (Sheet 4 of 4)
indicated by a 4-bit field (bits 20-23) in the HCSPARAMS register of the EHCI controller.
11.2.3.1 Offset 00h: Control/Status Register
- All of these registers are implemented in the core well and reset by PXPCIRST#, EHC
HCRESET, and a EHC D3-to-D0 transition.
- The hardware associated with this register provides no checks to ensure that software
Table 421. Offset 00h: Control/Status Register (Sheet 1 of 3)
30 OWNER_CNT
taken away from the companion Classic USB Host Controller).
28 ENABLED_CNT
This bit = ’1’ when the debug port is enabled for operation. enforced by the hardware). Reset default is ’0’.
16 DONE_STS
complete. Writing a ’1’ to this bit will clear it when it is set. Writing a ’0’ to this bit has no effect. Reset default is ’0’.
10 IN_USE_CNT
when the ERROR_GOOD#_STS bit is 0. checked when there is an error.
001 Transaction error: Indicates the USB EHCI
010 Hardware error: Request was attempted (or in
progress) when port was suspended or reset.
6 ERROR_GOOD#_STS
provided in the Exception field. Reset default = 0. 1 = Causes hardware to perform a read or write request. Table 421. Offset 00h: Control/Status Register (Sheet 2 of 3)
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transferred. Reset default = 0h. hardware behaves when used is undefined. defined. A value of 1-8 indicates 1-8 bytes were received. Hardware is not allowed to return values 9-Fh.
- Software should do Read-Modify-Write operations to this register to preserve the contents of bits not being
modified. This include Reserved bits.
- To preserve the usage of Reserved bits in the future, software should always write the same value read from
the bit until it is defined. Reserved bits will always return ’0’ when read. Table 421. Offset 00h: Control/Status Register (Sheet 3 of 3)
11.2.3.2 Offset 04h: USB PIDs Register
11.2.3.3 Offset 08h: Data Buffer Bytes 7:0
Table 422. Offset 04h: USB PIDs Register clears the GO_DONE#_CNT bit. sending data to USB (i.e., WRITE_READ#_CNT is asserted). to return PID information to the USB debug driver. Table 423. Offset 08h: Data Buffer Bytes 7:0 most significant byte (byte 7). number of bytes that are valid. NOTE: This register may be accessed as eight separate 8-bit registers or two separate 32-bit registers.
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11.2.3.4 Offset 10h: Config Register
Table 424. Offset 10h: Config Register
12.1 PCI Configuration Registers (SMBUS—
12.1.1 Offset 00 - 01h: VID—Vendor Identification
- Registers that are not shown should be treated as Reserved (See Section 6.2, “PCI
Configuration Map” on page 277 for details). Table 425. Offset 00 - 01h: VID—Vendor Identification Register (SMBUS—
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12.1.2 Offset 02 - 03h: DID—Device Identification
Table 426. Offset 02 - 03h: DID—Device Identification Register (SMBUS— Table 427. Offset 04 - 05h: CMD—Command Register (SMBUS—D31:F3)
7 Wait Cycle Control
5 VGA Palette Snoop
defined by the Base Address Register.
12.1.5 Offset 08h: RID—Revision ID Register (SMBUS—
Table 428. Offset 06 - 07h: STA—Device Status Register (SMBUS—D31:F3) Table 429. Offset 08h: RID—Revision ID Register (SMBUS—D31:F3)
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12.1.6 Offset 09h: PI—Programming Interface (SMBUS—
Table 430. Offset 09h: PI—Programming Interface (SMBUS—D31:F3) Table 431. Offset 0Ah: SCC—Sub Class Code Register (SMBUS—D31:F3) Table 432. Offset 0Bh: BCC—Base Class Code Register (SMBUS—D31:F3)
12.1.10 Offset 2Ch - 2Dh: SVID—Subsystem Vendor ID
Table 433. Offset 20 - 23h: SMB_BASE—SMBUS Base Address Register Table 434. Offset 2Ch - 2Dh: SVID—Subsystem Vendor ID (SMBUS—D31:F2/ written by BIOS into the IDE_SVID register.
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12.1.11 Offset 2Eh - 2Fh: SID—Subsystem ID (SMBUS—
12.1.12 Offset 3Ch: INTR_LN—Interrupt Line Register
12.1.13 Offset 3Dh: INTR_PN—Interrupt Pin Register
Table 435. Offset 2Eh - 2Fh: SID—Subsystem ID (SMBUS—D31:F2/F4) Table 436. Offset 3Ch: INTR_LN—Interrupt Line Register (SMBUS—D31:F3) Table 437. Offset 3Dh: INTR_PN—Interrupt Pin Register (SMBUS—D31:F3)
12.1.14 Offset 40h: HOSTC—Host Configuration Register
12.2 SMBUS I/O Registers
Table 438. Offset 40h: HOSTC—Host Configuration Register (SMBUS—D31:F3)
1 SMB_SMI_EN
0 = SMBus interrupts will not generate an SMI#. This bit needs to be set for SMBALERT# to be enabled.
0 HST_EN: SMBus Host
0 = Disable the SMBus Host Controller. all interrupt requests have been cleared. Table 439. SMB I/O Registers (Sheet 1 of 2)
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12.2.1 Offset 00h: HST_STS—Host Status Register
particular bit position. Writing a ‘0’ to any bit position has no effect. Table 439. SMB I/O Registers (Sheet 2 of 2)
Table 440. Offset 00h: HST_STS—Host Status Register (Sheet 1 of 2) immediately set the INTR bit (bit 1 in this register). to be implemented to handle these cases. ICH’s SMBus logic and has no other effect on hardware. 0 = After a full PCI reset, a read to this bit returns a ‘0’.
5 SMBALERT_STS
0 = Interrupt or SMI# was not generated by SMBALERT#. the bit position or by RSMRST# going low. 0 = Cleared by writing a ’1’ to the bit position. being set to terminate the host transaction. 0 = Cleared by writing a ’1’ to the bit position.
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0 = Software resets this bit by writing a ’1’ to this location. will be set, although the interrupt will not be generated. Software may poll the INTR bit in this non-interrupt case. completion of its last command. in order to check the BYTE_DONE_STS bit. Table 440. Offset 00h: HST_STS—Host Status Register (Sheet 2 of 2)
12.2.2 Offset 02h: HST_CNT—Host Control Register
Note: A read to this register will clear the byte pointer of the 32-byte buffer. Table 441. Offset 02h: HST_CNT—Host Control Register (Sheet 1 of 3) with the PEC phase appended. written prior to the write in which the START bit is set. writing a ‘1’ to this bit position.
5 LAST_BYTE
This bit is used for Block Read commands. after receiving the last byte.
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will not operate until DEV_ERR is cleared. are stored in the transmit slave address register. determines if this is a read or write command. the DATA0 and DATA1 registers will contain the read data. DATA1 registers will contain the read data. stored in the Block Data Byte register. data until the NAK is received. the Block Data Byte register. Table 441. Offset 02h: HST_CNT—Host Control Register (Sheet 2 of 3)
12.2.3 Offset 03h: HST_CMD—Host Command Register
12.2.4 Offset 04h: XMIT_SLVA—Transmit Slave Address
0 = Normal SMBus Host Controller functionality. allow the SMBus Host Controller to function normally. Table 442. Offset 03h: HST_CMD—Host Command Register Table 443. Offset 04h: XMIT_SLVA—Transmit Slave Address Register Direction of the host transfer. Table 441. Offset 02h: HST_CNT—Host Control Register (Sheet 3 of 3)
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12.2.5 Offset 05h: HST_D0—Data 0 Register
12.2.6 Offset 06h: HST_D1—Data 1 Register
Table 444. Offset 05h: HST_D0—Data 0 Register Table 445. Offset 06h: HST_D1—Data 1 Register
12.2.7 Offset 07h: Host_BLOCK_DB—Host Block Data
Table 446. Offset 07h: Host_BLOCK_DB—Host Block Data Byte Register write or read from on a block read. transaction always starts at index address 0. bit . See Section 12.2.1,HST_STS-Host Status Register, bit 7. pointed to by this register and clear the BYTE_DONE_STS bit. wait states on the interface.
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12.2.8 Offset 08h: PEC—Packet Error Check Register
12.2.9 Offset 09h: RCV_SLVA—Receive Slave Address
Table 447. Offset 08h: PEC—Packet Error Check Register following a read transaction. Table 448. Offset 09h: RCV_SLVA—Receive Slave Address Register is cleared by RSMRST#, but not by PXPCIRST#.
12.2.10 Offset 0Ah: SLV_DATA—Receive Slave Data
12.2.11 Offset 0Ch: AUX_STS—Auxiliary Status Register
Table 449. Offset 0Ah: SLV_DATA—Receive Slave Data Register Table 450. Offset 0Ch: AUX_STS—Auxiliary Status Register
1 SMBus TCO mode
that the Intel® 6300ESB ICH is in the advanced TCO mode.
0 CRC Error (CRCE)
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12.2.12 Offset 0Dh: AUX_CTL—Auxiliary Control Register
12.2.13 Offset 0Eh: SMLINK_PIN_CTL—SMLink Pin Control
Note: This register is in the resume well and is reset by RSMRST#. Table 451. Offset 0Dh: AUX_CTL—Auxiliary Control Register
1 Enable 32-byte Buffer
before the Intel® 6300ESB ICH generates an interrupt.
0 Automatically Append
Table 452. Offset 0Eh: SMLINK_PIN_CTL—SMLink Pin Control Register
2 SMLINK_CLK_CTL
This Read/Write bit has a default of 1. otherwise indicate for the SMLINK[0] pin. SMLINK logic controls the state of the pin.
1 SMLINK1_CUR_STS
low. This allows software to read the current state of the pin.
0 SMLINK0_CUR_STS
low. This allows software to read the current state of the pin.
12.2.14 Offset 0Fh: SMBUS_PIN_CTL—SMBUS Pin Control
Note: This register is in the resume well and is reset by RSMRST#.
12.2.15 Offset 10h: SLV_STS—Slave Status Register
Note: This register is in the resume well and is reset by RSMRST#. Table 453. Offset 0Fh: SMBUS_PIN_CTL—SMBUS Pin Control Register
2 SMBCLK_CTL
This Read/Write bit has a default of 1. logic controls the state of the pin. indicate for the SMBCLK pin.
1 SMBDATA_CUR_STS
SMBDATA pin. It will be ’1’ to indicate high, ’0’ to indicate low. This allows software to read the current state of the pin. SMBCLK pin. It will be ’1’ to indicate high, ’0’ to indicate low. This allows software to read the current state of the pin.
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12.2.16 Offset 11H: SLV_CMD—Slave Command Register
Note: This register is in the resume well and is reset by RSMRST#. Table 454. Offset 10h: SLV_STS—Slave Status Register
0 HOST_NOTIFY_STS
address) of any new “Host Notify” commands on the SMLink. Writing a ’0’ to this bit has no effect. Table 455. Offset 11H: SLV_CMD—Slave Command Register 0 = Allows the generation of the interrupt or SMI#.
1 HOST_NOTIFY_WKEN
0 HOST_NOTIFY_INTREN
does not affect the setting of the HOST_NOTIFY_STS bit. generated by ‘AND’ing the STS and INTREN bits.
12.2.17 Offset 14h: NOTIFY_DADDR—Notify Device
Note: This register is in the resume well and is reset by RSMRST#. Table 456. Offset 14h: NOTIFY_DADDR—Notify Device Address the Host Notify protocol of the SMBus 2.0 specification. HOST_NOTIFY_STS bit is set to ‘1’.
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12.2.18 Offset 16h: NOTIFY_DLOW—Notify Data Low Byte
Note: This register is in the resume well and is reset by RSMRST#.
12.2.19 Offset 17h: NOTIFY_DHIGH—Notify Data High
Note: This register is in the resume well and is reset by RSMRST#. Table 457. Offset 16h: NOTIFY_DLOW—Notify Data Low Byte Register the Host Notify protocol of the SMBus 2.0 specification. HOST_NOTIFY_STS bit is set to ‘1’. Table 458. Offset 17h: NOTIFY_DHIGH—Notify Data High Byte Register when the HOST_NOTIFY_STS bit is set to ‘1’.
13.1 AC’97 Audio PCI Configuration Space
Note: Registers that are not shown should be treated as Reserved. Table 459. PCI Configuration Map (Audio—D31:F5)
- Refer to the Intel® 6300ESB I/O Controller Hub Specification Update for the most up-to-date
value of the Revision ID Register.
Intel® 6300ESB ICH—13 Intel® 6300ESB I/O Controller Hub DS November 2007
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Note: Internal reset as a result of D3HOT to D0 transition will reset all the core well registers except the following BIOS programmed registers as BIOS may not be invoked following the D3-to-D0 transition. Resume well registers will not be reset by the D3 HOT to D0 transition.
- Offset 2Ch-2Dh – Subsystem Vendor ID (SVID)
- Offset 2Eh-2Fh – Subsystem ID (SID)
- Offset 40h – Programmable Codec ID (PCID)
- Offset 41h – Configuration (CFG) Resume Well registers will not be reset by the D3HOT to D0 transition:
- Offset 54h-55h – Power Management Control and Status (PCS)
- Bus Mastering Register: Global Status Register, bit[17:16]
- Bus Mastering Register: SDATA_IN MAP register , bit[7:3]
13.1.1 Offset 00 - 01h: VID—Vendor Identification
13.1.2 Offset 02 - 03h: DID—Device Identification
Table 460. Offset 00 - 01h: VID—Vendor Identification Register (Audio— Table 461. Offset 02 - 03h: DID—Device Identification Register (Audio—
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13.1.4 Offset 06 - 07h: PCISTS—PCI Device Status
Intel® 6300ESB ICH AC’97 controller for write requests. Table 462. Offset 04 - 05h: PCICMD—PCI Command Register (Audio—D31:F5) 0 Reserved Reserved. Read ‘0’. Enable (FBE) Not implemented. Hardwired to ‘0’. 8 SERR# Enable (SEN) Not implemented. Hardwired to ‘0’. (WCC) Not implemented. Hardwired to ‘0’. (PER) Not implemented. Hardwired to ‘0’. (VPS) Not implemented. Hardwired to ‘0’. Invalidate Enable (MWI) Not implemented. Hardwired to ‘0’. (SCE) Not implemented. Hardwired to ‘0’. Controls standard PCI bus mastering capabilities.
Table 463. Offset 06 - 07h: PCISTS—PCI Device Status Register (Audio— (DPE) Not implemented. Hardwired to ‘0’. 14 SERR# Status (SERRS) Not implemented. Hardwired to ‘0’.
13 Master-Abort Status
0 = Software clears this bit by writing a ‘1’ to the bit position. 12 Reserved Reserved. Will always read as ‘0’. Status (STA) Not implemented. Hardwired to ‘0’. timing when performing a positive decode.
8 Data Parity Detected
(DPD) Not implemented. Hardwired to ‘0’.
7 Fast Back to back
ICH as a target is capable of fast back-to-back transactions. 6 Reserved Reserved. Hardwired to ‘0’. 5 66 MHz Capable Hardwired to ‘0’.
4 Capabilities List Exists
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Table 464. Offset 08h: RID—Revision Identification Register (Audio—D31:F5) Table 465. Offset 09h: PI—Programming Interface Register (Audio—D31:F5) Table 466. Offset 0Ah: SCC—Sub Class Code Register (Audio—D31:F5) a multimedia device (Base Class Code = 04h).
13.1.9 Offset 0Eh: HEDT—Header Type Register (Audio—
13.1.10 Offset 10 - 13h: NAMBAR—Native Audio
and address offsets 80h - FEh for the secondary codec. and only becomes writeable when the IOSE bit in offset 41h is set. For descriptions of these I/O registers, refer to the AC’97 specification. Table 467. Offset 0Bh: BCC—Base Class Code Register (Audio—D31:F5) Table 468. Offset 0Eh: HEDT—Header Type Register (Audio—D31:F5) 7:0 Header Type Value Hardwired to 00h.
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13.1.11 Offset 14 - 17h: NABMBAR—Native Audio Bus
address space. These DMA functions are only available from the new MBBAR register. Table 469. Offset 10 - 13h: NAMBAR—Native Audio Mixer Base Address 6 Reserved Reserved. All bits are hardwired to ‘0’. block size of 256 bytes for this base address. 7:1 Reserved Reserved. Read as ‘0’s.
13.1.12 Offset 18 - 1Bh: MMBAR—Mixer Base Address
- 128 bytes for the primary codec (offsets 00 – 7Fh)
- 128 bytes for the secondary codec (offsets 80h – FFh)
- 128 bytes for the tertiary codec (offsets 100h – 17Fh).
- 128 bytes of reserved space (offsets 180h – 1FFh), returning all ‘0’.
Table 470. Offset 14 - 17h: NABMBAR—Native Audio Bus Mastering Base 6 Reserved Reserved. Hardwired to ‘0’. I/O block size of 64 bytes for this base address. 5:1 Reserved Reserved. Read as ‘0’s. Table 471. Offset 18 - 1Bh: MMBAR—Mixer Base Address Register (Audio—
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13.1.13 Offset 1C - 1Fh: MBBAR—Bus Master Base Address
to the same registers as the NABMBAR. Table 472. Offset 1C - 1Fh: MBBAR—Bus Master Base Address Register
13.1.14 Offset 2D - 2Ch: SVID—Subsystem Vendor ID
environment to distinguish one audio subsystem from the other(s). value may be read back. Any subsequent writes will have no effect. This register is not affected by the D3 HOT to D0 transition.
13.1.15 Offset 2E - 2Fh: SID—Subsystem ID Register
value may be read back. Any subsequent writes will have no effect. Table 473. Offset 2D - 2Ch: SVID—Subsystem Vendor ID Register (Audio— Table 474. Offset 2E - 2Fh: SID—Subsystem ID Register (Audio—D31:F5)
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13.1.16 Offset 34h: CAP_PTR—Capabilities Pointer
Note: This register indicates the offset for the capability pointer.
13.1.17 Offset 3Ch: INTR_LN—Interrupt Line Register
Note: This register indicates which PCI interrupt line is used for the AC’97 module interrupt. Table 475. Offset 34h: CAP_PTR—Capabilities Pointer (Audio—D31:F5) Table 476. Offset 3Ch: INTR_LN—Interrupt Line Register (Audio—D31:F5)
13.1.18 Offset 3Dh: INTR_PN—Interrupt Pin Register
Note: This register indicates which PCI interrupt pin is used for the AC’97 module interrupt. The AC’97 interrupt is internally OR’d to the interrupt controller with the PIRQB# signal.
13.1.19 Offset 40h: PCID—Programmable Codec ID
accesses. This register is not affected by the D3 HOT to D0 transition. Note: The value in this register must only be modified prior to any AC’97 codec accesses. Table 477. Offset 3Dh: INTR_PN—Interrupt Pin Register (Audio—D31:F5) Table 478. Offset 40h: PCID—Programmable Codec ID Register (Audio— is the second bit sent on AC_SDATA_OUT during slot 0. the second bit sent on AC_SDATA_OUT during slot 0.
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13.1.20 Offset 41h: CFG—Configuration Register (Audio—
accesses. This register is not affected by the D3 HOT to D0 transition.
13.1.21 Offset 50h: PID—PCI Power Management
Table 479. Offset 41h: CFG—Configuration Register (Audio—D31:F5) this bit to allow a legacy driver to work. Table 480. Offset 50h: PID—PCI Power Management Capability ID Register
13.1.22 Offset 52h: PC—Power Management Capabilities
Note: This register is not affected by the D3 HOT to D0 transition.
13.1.23 Offset 54h: PCS—Power Management Control and
Table 481. Offset 52h: PC—Power Management Capabilities Register (Audio—
5 Device Specific Initial-
Table 482. Offset 54h: PCS—Power Management Control and Status Register
15 PME Status (PMES)
PME_En bit. This bit resides in the resume well.
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13.2 AC’97 Audio I/O Space (D31:F5)
bits[1:0] of the TAG field (codec ID). the first word of the qWord that contains the address of this request.
8 Power Management
space is available, but the I/O and memory spaces are not. Additionally, interrupts are blocked. this field, the write operation must complete normally. However, the data is discarded and no state change occurs.
Table 483. Intel ® 6300ESB I/O Controller Hub Audio Mixer Register
- Software should not try to access reserved registers.
- Primary Codec ID cannot be changed. Secondary codec ID may be changed through bits 1:0
- The tertiary offset is only available through the memory space defined by the MMBAR
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dWord quantities, but reads must not cross dWord boundaries. 17Fh for the tertiary codec. these registers in either audio or modem I/O space affects the same physical register.
- Software should not try to access reserved registers.
- Primary Codec ID cannot be changed. Secondary codec ID may be changed through bits 1:0
- The tertiary offset is only available through the memory space defined by the MMBAR
Table 484. Native Audio Bus Master Control Registers (Sheet 1 of 3)
Table 484. Native Audio Bus Master Control Registers (Sheet 2 of 3)
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registers will not be reset by the D3 HOT to D0 transition.
- Offset 2Ch-2Fh – bits[15,6:0] Global Control (GLOB_CNT)
- Offset 30h-33h – bits[29,15,11:10,0] Global Status (GLOB_STA)
- Offset 34h – Codec Access Semaphore Register (CAS) Resume Well registers and bits will NOT be reset by the D3 HOT to D0 transition:
- Offset 30h-33h – bits[17:16] Global Status (GLOB_STA) 13.2.1 x_BDBAR—Buffer Descriptor Base Address Register Note: Software may read the register at offset 00h by performing a single 32-bit read from address offset 00h. Reads across dWord boundaries are not supported. 13.2.2 x_CIV—Current Index Value Register Note: Software may read the registers at offsets 04h, 05h and 06h simultaneously by performing a single 32-bit read from address offset 04h. Software may also read this register individually by doing a single 8-bit read to offset 04h. Reads across dWord boundaries are not supported. 68-69h SP_PICB S/PDIF Position In Current Buffer 0000h RO 6Ah SP_PIV S/PDIF Prefetched Index Value 00h RO 6Bh SP_CR S/PDIF Control Register 00h R/W 80h SDM SData_IN Map 00h R/W
Table 484. Native Audio Bus Master Control Registers (Sheet 3 of 3) Table 485. x_BDBAR—Buffer Descriptor Base Address Register
boundaries are not supported. Table 486. x_CIV—Current Index Value Register rolls over after it reaches 31. Table 487. x_LVI—Last Valid Index Register buffer and adds it to the list.
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Table 488. x_SR—Status Register
4 FIFO Error (FIFOE)
0 = Cleared by writing a “1” to this bit position. written into the FIFO, thus is lost.
3 Buffer Completion
0 = Cleared by writing a “1” to this bit position. descriptor. It remains active until cleared by software. 0 = Cleared by writing a “1” to this bit position. cleared when the software clears this bit.
1 Current Equals Last
controller exits this state.
0 DMA Controller Halted
a single 8-bit read to offset 0Ah. Reads across dWord boundaries are not supported. Table 489. x_PICB—Position In Current Buffer Register been transmitted/received across AC-link. Table 490. x_PIV—Prefetched Index Value Register and roll over after they reach 31.
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a single 8-bit read to offset 0Bh. Reads across dWord boundaries are not supported.
13.2.8 GLOB_CNT—Global Control Register
Note: Reads across dWord boundaries are not supported. Table 491. x_CR—Control Register
4 Interrupt On Completion
buffer completes with the IOC bit set in its descriptor. 0 = Disable. Interrupt will not occur.
3 FIFO Error Interrupt
1 = Enable. Interrupt will occur.
2 Last Valid Buffer
buffer will cause an interrupt or not. the interrupt will not occur.
1 Reset Registers (RR)
0 = Removes reset condition. the Run bit is set will cause undefined consequences.
0 Run/Pause Bus master
may be stopped and then resumed). 1 = Run. Bus master operation starts.
Table 492. GLOB_CNT—Global Control Register (Sheet 1 of 2)
0 S/PDIF Slot Map (SSM)
will result; the hardware will not check for a conflict.
2 PCM Out Mode (POM)
PCM out. This does not affect the microphone of S/PDIF DMA. 10 = Reserved. When set, indeterminate behavior will result. 11 = Reserved. When set, indeterminate behavior will result.
0 PCM 4/6 Enable
Configures PCM Output for 2, 4 or 6 channel mode.
6 AC_SDIN2 Interrupt
AC_SDIN[2] causes a resume event on the AC-link.
5 AC_SDIN1 Resume
AC_SDIN[1] causes a resume event on the AC-link.
4 AC_SDIN0 Resume
AC_SDIN[0] causes a resume event on the AC-link.
3 ACLINK Shut Off (LSO)
internal pull down resistors.
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13.2.9 GLOB_STA—Global Status Register
Note: Reads across dWord boundaries are not supported.
1 AC’97 Cold Reset#
sooner than the minimum number of ms have elapsed. automatically upon resuming. NOTE: This bit is in the Core well.
0 GPI Interrupt Enable
sets bit ’0’ of the Global Status Register. Table 492. GLOB_CNT—Global Control Register (Sheet 2 of 2)
Table 493. GLOB_STA—Global Status Register (Sheet 1 of 3)
29 AC_SDIN2 Resume
0 = Cleared by writing a ’1’ to this bit position. This bit is not affected by D3HOT to D0 Reset.
28 AC_SDIN2 Codec Ready
software must check this bit before starting the bus masters.
27 Bit Clock Stopped (BCS)
cleared when a transition is found on BIT_CLK.
26 S/PDIF Interrupt
25 PCM In 2 Interrupt
24 Microphone 2 In
2 Sample Capabilities
Indicates the capability to support greater than 16-bit audio.
0 Multichannel Capabilities Indicates the capability to support more 4 and 6 channels on
17 MD3
entry of the two codecs into D3 state.
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16 AD3
entry of the two codecs into D3 state. This bit is not affected by D3HOT to D0 Reset.
15 Read Completion Status
This bit indicates the status of codec read completions. 0 = A codec read completes normally. This bit is not affected by D3HOT to D0 Reset.
11 AC_SDIN1 Resume
0 = Cleared by writing a ’1’ to this bit position. This bit is not affected by D3HOT to D0 Reset.
10 AC_SDIN0 Resume
0 = Cleared by writing a ’1’ to this bit position. This bit is not affected by D3HOT to D0 Reset.
9 AC_SDIN1 Codec Ready
software must check this bit before starting the bus masters.
8 AC_SDIN0 Codec Ready
software must check this bit before starting the bus masters.
7 Mic In Interrupt (MINT)
cleared, this bit will be cleared. Table 493. GLOB_STA—Global Status Register (Sheet 2 of 3)
6 PCM Out Interrupt
cleared, this bit will be cleared.
5 PCM In Interrupt (PIINT)
cleared, this bit will be cleared.
2 Modem Out Interrupt
bit is cleared, this bit will be cleared.
1 Modem In Interrupt
0 GPI Status Change
This bit is not affected by D3HOT to D0 Reset. Table 493. GLOB_STA—Global Status Register (Sheet 3 of 3)
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13.2.10 CAS—Codec Access Semaphore Register
Note: Reads across dWord boundaries are not supported.
13.2.11 SDM—SDATA_IN Map Register
Note: Reads across dWord boundaries are not supported. Table 494. CAS—Codec Access Semaphore Register
0 Codec Access
driver that read this bit may then perform an I/O access. Table 495. SDM—SDATA_IN Map Register (Sheet 1 of 2)
2 Data In Line (DI2L)
and Mic In 2 DMA engines are not available.
00 AC_SDIN0
01 AC_SDIN1
10 AC_SDIN2
11 Reserved
1 Data In Line (DI1L)
and Mic In 1 engines use the OR’d AC_SDIN lines.
3 Steer Enable (SE)
Microphone In 2 and PCM In 2 DMA engines are not available. Table 495. SDM—SDATA_IN Map Register (Sheet 2 of 2)
Intel® 6300ESB ICH—13 Intel® 6300ESB I/O Controller Hub DS November 2007
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14.1 AC’97 Modem PCI Configuration Space
Note: Registers that are not shown should be treated as Reserved.
- Offset 2Ch-2Dh – Subsystem Vendor ID (SVID)
- Offset 2Eh-2Fh – Subsystem ID (SID)
Table 496. PCI Configuration Map (Modem—D31:F6)
- Refer to the Intel® 6300ESB I/O Controller Hub Specification Update for the most up-to-date
value of the Revision ID Register.
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- Offset 54h-55h – Power Management Control and Status (PCS)
14.1.1 Offset 00 - 01h: VID—Vendor Identification
14.1.2 Offset 02 - 03h: DID—Device Identification
Table 497. Offset 00 - 01h: VID—Vendor Identification Register (Modem— Table 498. Offset 02 - 03h: DID—Device Identification Register (Modem—D31:F6)
14.1.3 Offset 04 - 05h: PCICMD—PCI Command Register
details on each bit.PCISTA—Device Status Register (Modem—D31:F6). Table 499. Offset 04 - 05h: PCICMD—PCI Command Register (Modem—D31:F6) 0 Reserved Reserved. Read 0. Enable (FBE) Not implemented. Hardwired to ‘0’. 8 SERR# Enable (SEN) Not implemented. Hardwired to ‘0’. (WCC) Not implemented. Hardwired to ‘0’. (PER) Not implemented. Hardwired to ‘0’. (VPS) Not implemented. Hardwired to ‘0’. Invalidate Enable (MWI) Not implemented. Hardwired to ‘0’. (SCE) Not implemented. Hardwired to ‘0’. Controls standard PCI bus mastering capabilities.
1 Memory Space (MS) Hardwired to ‘0’; AC ‘97 does not respond to memory
0 I/O Space (IOS)
This bit controls access to the I/O space registers. 0 = Disable access (default = 0).
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Table 500. Offset 06 - 07h: PCISTA—Device Status Register (Modem—D31:F6)
15 DPE (Detected Parity
13 MAS (Master-Abort
0 = Software clears this bit by writing a ‘1’ to the bit position.
11 STA (Signaled Target-
8 DPD (Data Parity
7 FBC (Fast Back to back
Table 501. Offset 08h: RID—Revision Identification Register (Modem—D31:F6) Table 502. Offset 09h: PI—Programming Interface Register (Modem—D31:F6) Table 503. Offset 0Ah: SCC—Sub Class Code Register (Modem—D31:F6)
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14.1.9 Offset 0Eh: HEDT—Header Type Register
14.1.10 Offset 10 - 13h: MMBAR—Modem Mixer Base
link to the codec where the registers reside. and address offsets 80h - FEh for the secondary codec. Table 504. Offset 0Bh: BCC—Base Class Code Register (Modem—D31:F6) Table 505. Offset 0Eh: HEDT—Header Type Register (Modem—D31:F6)
14.1.11 Offset 14 - 17h: MBAR—Modem Base Address
the controller; therefore cycles are not forwarded over the AC-link to the codec. Table 506. Offset 10 - 13h: MMBAR—Modem Mixer Base Address Register 6 Reserved Hardwired to ‘0’. block size of 256 bytes for this base address. Table 507. Offset 14 - 17h: MBAR—Modem Base Address Register (Modem— 6 Reserved Hardwired to ‘0’. block size of 128 bytes for this base address. 6:1 Reserved Reserved. Read as ‘0’.
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14.1.12 Offset 2C - 2Dh: SVID—Subsystem Vendor ID
affected by D3HOT to D0 reset.
14.1.13 Offset 2E - 2Fh: SID—Subsystem ID (Modem—
environment to distinguish one audio subsystem from the other(s). affected by D3HOT to D0 reset. Table 508. Offset 2C - 2Dh: SVID—Subsystem Vendor ID (Modem—D31:F6) 6 Reserved Hardwired to ‘0’s. block size of 128 bytes for this base address.
14.1.14 Offset 34h: CAP_PTR—Capabilities Pointer
Note: This register indicates the offset for the capability pointer.
14.1.15 Offset 3Ch: INTR_LN—Interrupt Line Register
Note: This register indicates which PCI interrupt line is used for the AC’97 module interrupt. Table 509. Offset 2E - 2Fh: SID—Subsystem ID (Modem—D31:F6) Table 510. Offset 34h: CAP_PTR—Capabilities Pointer (Modem—D31:F6) Table 511. Offset 3Ch: INTR_LN—Interrupt Line Register (Modem—D31:F6)
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14.1.16 Offset 3Dh: INT_PIN—Interrupt Pin (Modem—
Note: This register indicates which PCI interrupt pin is used for the AC’97 modem interrupt. The AC’97 interrupt is internally OR’d to the interrupt controller with the PIRQB# signal.
14.1.17 Offset 50h: PID—PCI Power Management
Table 512. Offset 3Dh: INT_PIN—Interrupt Pin (Modem—D31:F6) Table 513. Offset 50h: PID—PCI Power Management Capability ID Register
14.1.18 Offset 52h: PC—Power Management Capabilities
14.1.19 Offset 54h: PCS—Power Management Control and
Note: This register is not affected by the D3 HOT to D0 transition. Table 514. Offset 52h: PC—Power Management Capabilities Register (Modem— Table 515. Offset 54h: PCS—Power Management Control and Status Register PME_En bit. This bit resides in the resume well.
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space is available, but the I/O and memory spaces are not. Additionally, interrupts are blocked. the data is discarded and no state change occurs.
14.2 AC’97 Modem I/O Space (D31:F6)
shows the register addresses for the modem mixer registers. these registers in either audio or modem I/O space affects the same physical register. Table 516. Intel ® 6300ESB I/O Controller Hub Modem Mixer Register
- Registers in italics are for functions not supported by the Intel ® 6300ESB ICH.
- Software should not try to access reserved registers.
- The Intel® 6300ESB ICH supports a modem codec connected to AC_SDIN[2:0] as long as the
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Table 517 presents the modem registers. except the registers shared with the AC’97 Audio Controller (GCR, GSR, CASR). Resume well registers will not be reset by the D3 HOT to D0 transition.
- Offset 3Ch-3Fh – bits[6:0] Global Control (GLOB_CNT)
- Offset 40h-43h – bits[29,15,11:10] Global Status (GLOB_STA)
- Offset 44h – Codec Access Semaphore Register (CAS) Resume Well registers and bits will not be reset by the D3HOT to D0 transition:
- Offset 40h-43h – bits[17:16] Global Status (GLOB_STA)
Table 517. Modem Registers
address offset 00h. Reads across dWord boundaries are not supported. boundaries are not supported. Table 518. x_BDBAR—Buffer Descriptor List Base Address Register Table 519. x_CIV—Current Index Value Register descriptor is processed, this value is incremented.
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boundaries are not supported. boundaries are not supported. Table 520. x_LVI—Last Valid Index Register 7:5 Hardwired to 0 Hardwired to 0. Table 521. x_SR—Status Register (Sheet 1 of 2) 0 = Cleared by writing a ‘1’ to this bit position. into the FIFO, thereby being lost. 0 = Cleared by writing a ‘1’ to this bit position. descriptor. Remains active until software clears bit.
processed. It remains active until cleared by software. interrupt if the enable bit in the Control Register is set. The interrupt is cleared when the software clears this bit. new value is written to the LVI register). controller exits this state. Table 522. x_PICB—Position in Current Buffer Register Table 521. x_SR—Status Register (Sheet 2 of 2)
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a single 8-bit read to offset 0Ah. Reads across dWord boundaries are not supported. a single 8-bit read to offset 0Bh. Reads across dWord boundaries are not supported. Table 523. x_PIV—Prefetch Index Value Register Table 524. x_CR—Control Register (Sheet 1 of 2) buffer completes with the IOC bit set in its descriptor. 1 = Enable. Interrupt will occur.
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14.2.8 GLOB_CNT—Global Control Register
Note: Reads across dWord boundaries are not supported. buffer will cause an interrupt or not. the interrupt will not occur.
1 Reset Registers(RR)
0 = Removes reset condition. (software needs not clear it). may be stopped and then resumed). 1 = Run. Bus master operation starts. Table 525. GLOB_CNT—Global Control Register (Sheet 1 of 2) AC_SDIN[2] causes a resume event on the AC-link. AC_SDIN[1] causes a resume event on the AC-link. AC_SDIN[0] causes a resume event on the AC-link. internal pull down resistors. Table 524. x_CR—Control Register (Sheet 2 of 2)
14.2.9 GLOB_STA—Global Status Register
in the Global Status Register. Reads across dWord boundaries are not supported.
2 AC’97 Warm Reset
sooner than the minimum number of ms have elapsed. automatically upon resuming. NOTE: This bit is in the Core well. sets bit ’0’ of the Global Status Register. Table 525. GLOB_CNT—Global Control Register (Sheet 2 of 2)
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Table 526. GLOB_STA—Global Status Register (Sheet 1 of 3) 0 = Cleared by writing a ’1’ to this bit position. This bit is not affected by D3HOT to D0 Reset. software must check this bit before starting the bus masters. cleared when a transition is found on BIT_CLK.
entry of the two codecs into D3 state. This bit is not affected by D3HOT to D0 Reset. entry of the two codecs into D3 state. This bit indicates the status of codec read completions. 0 = A codec read completes normally. This bit is not affected by D3HOT to D0 Reset. 0 = Cleared by writing a ’1’ to this bit position. This bit is not affected by D3HOT to D0 Reset. 0 = Cleared by writing a ’1’ to this bit position. This bit is not affected by D3HOT to D0 Reset. software must check this bit before starting the bus masters. software must check this bit before starting the bus masters. Table 526. GLOB_STA—Global Status Register (Sheet 2 of 3)
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14.2.10 CAS—Codec Access Semaphore Register
Note: Reads across dWord boundaries are not supported. cleared, this bit will be cleared. cleared, this bit will be cleared. cleared, this bit will be cleared. bit is cleared, this bit will be cleared. cleared, this bit will be cleared. Table 527. CAS—Codec Access Semaphore Register driver that read this bit may then perform an I/O access. Table 526. GLOB_STA—Global Status Register (Sheet 3 of 3)
15.1 Memory Mapped Registers
D0h) in Device 31, Function 0.
15.1.1 Behavioral Rules
- Software must not attempt to read or write across register boundaries. For
accesses may only be to x0h and must not cross 64-bit boundaries.
- Software should not write to read-only registers.
- Reads or writes to unimplemented timers should not be attempted. Timers 3:31
- All registers are implemented in the Core Well, and all bits are reset by PXPCIRST#.
- Reads to reserved registers or bits will return a value of ‘0’.
- Software must not attempt locks to the memory mapped I/O ranges for Multimedia
Table 528. Memory-Mapped Registers (Sheet 1 of 2)
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15.1.2 Offset 000-007h: General Capabilities and ID
Table 529. Offset 000-007h: General Capabilities and ID Register
15 LEG_RT_CAP Legacy Rout Capable: This bit will return a ’1’ when read,
14 Reserved Reserved. This bit will return ’0’ when read.
13 COUNT_SIZE_CAP Counter Size: This bit will return a ’1’ when read, indicating
7:0 REV_ID This indicates which revision of the function is implemented. Table 528. Memory-Mapped Registers (Sheet 2 of 2)
15.1.3 Offset 010-017h: General Config Register
Table 530. Offset 010-017h: General Config Register 63:2 Reserved Reserved. These bits will return ’0’ when read.
- Timer 0 will be routed to IRQ0 in 8259 or IRQ2 in the I/O APIC.
- Timer 1 will be routed to IRQ8 in 8259 or IRQ8 in the I/O APIC.
- Timer 2-n will be routed as per the routing in the timer n config registers.
- When the Legacy Rout bit is set, the individual routing bits for Timers 0 and 1 (APIC) will have no impact.
- When the Legacy Rout bit is not set, the individual routing bits for each of the timers are used.
- This bit will default to ‘0’. BIOS may set it to ’1’ to enable the legacy routing or ’0’ to disable the legacy routing. R/W
0 ENABLE_CNF: Overall
Txx_INT_STS bits to clear the interrupts. NOTE: This bit will default to ‘0’. BIOS may set it to ’1’ or ‘0’.
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15.1.4 Offset 020-027h: General Interrupt Status
Table 531. Offset 020-027h: General Interrupt Status Register 63:3 Reserved Reserved. These bits will return ’0’ when read.
2 T02_INT_STS: Timer 2
1 T01_INT_STS: Timer 1
0 T00_INT_STS: Timer 0
When set to level-triggered mode: This bit defaults to ‘0’. set, a write of ’0’ will not clear the bit. always read as ’0’ and writes will have no effect.
15.1.5 Offset 0F0 - 0f7h: Main Counter Value
15.1.6 Timer n Config and Capabilities
Note: The letter n may be 0, 1, or 2, referring to Timer 0, 1 or 2. Table 532. Offset 0F0 - 0f7h: Main Counter Value
- Software can access the various bytes in this register
- Writes to this register should only be done while the
- Reads to this register return the current value of the main
- 32-bit counters will always return ’0’ for the upper 32 bits
- If 32-bit software attempts to read a 64-bit counter, it
- Reads to this register are monotonic. No two consecutive
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Table 533. Timer n Config and Capabilities (Sheet 1 of 3) 6 Reserved Reserved. These bits will return ’0’ when read. used in conjunction with the TIMERn_INT_ROUT_CNF field. this field will be set to ‘1’. All other bits will be ‘0’. ‘0’. Writes will have no effect. other devices to ensure the proper operation of MMT#2. 6 Reserved Reserved. These bits will return ’0’ when read. processor side bus delivery of this timer’s interrupt. not support the direct FSB interrupt delivery.
14 TIMERn_FSB_EN_CNF
(where n is the timer number: 00 to 31). TIMERn_INT_ROUT_CNF field in this register will be ignored. The TIMERn_FSB_ROUT register will be used instead.
written. The software must only write valid values.
- When the Legacy Rout bit is set, Timers 0 and 1 will have
- Timer 0,1 Specific: Software is responsible to make sure it
programs a valid value (20, 21, 22, or 23) for this field.
- Timer 2 Specific: Software is responsible to make sure it
validity of the value written.
8 TIMERn_32MODE_CNF
these two timers are 32 bits. 7 Reserved Reserved. This bit will return ’0’ when read.
6 TIMERn_VAL_SET_CNF
’0’; it automatically clears. timer is set to non-periodic mode. an effect for Timer 0 when it is set to periodic mode. Writes will have no effect for Timers 1 and 2.
5 TIMERn_SIZE_CAP
4 TIMERn_PER_INT_CAP
hardware supports a periodic mode for this timer’s interrupt. interrupts, so the bit will always read as ‘0’. Table 533. Timer n Config and Capabilities (Sheet 2 of 3)
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and writes will have no impact. bit enables the timer to generate a periodic interrupt.
2 TIMERn_INT_ENB_CNF
but will not cause an interrupt. Default value is ‘0’.
1 TIMERn_INT_TYPE_CNF
occurs, another edge will be generated. interrupt will remain active. 0 Reserved Reserved. These bits will return ’0’ when read. Table 533. Timer n Config and Capabilities (Sheet 3 of 3)
15.1.7 Timer n Comparator Value
Table 534. Timer n Comparator Value
- Reads to this register return the current value of the
- When Timers 0,1, or 2 are configured to non-periodic
main counter will be compared for this timer.
- When Timer 0 is configured to periodic mode:
- An interrupt will be generated when the main counter
- The value in this register will be adjusted by the
- Another interrupt will be generated when the main
- The value in this register will be adjusted by the
- Default value for each timer is all ones for the bits that are
have a default value of FFFFFFFFFFFFFFFFh.
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Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 615 16—Intel ® 6300ESB ICH Watchdog Timer (WDT) (D29:F4)16
16.1 Product Features
The Watchdog Timer (WDT) supports the following features and functions:
- Selectable prescaler – approximately 1 MHz and approximately 1 KHz
- 33 MHz clock (30 ns clock ticks)
- Multiple modes: WDT and free-running — Free-running mode: One stage timer. Toggles WDT_OUT# after programmable time. —W D T M o d e : Two stage timer: 1. First stage generates IRQ and SMI interrupt after programmable time. 2. Second stage drives WDT_OUT# low or inverts the previous value. *Used only after first timeout occurs. *Status bit preserved in RTC well for possible error detection and correction. *Drives WDT_TOUT# when OUTPUT is enabled. Timer may be disabled (default state) or locked (hard reset required to disable WDT) WDT automatic reload of preload value when WDT reload sequence is performed Note: The WDT device (Dev 29:F4) cannot be hidden by using bit 12 of the D31:F0 FUNC_DIS Register. The WDT will always be present as a PCI device in PCI Config Space.
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16.2 Product Overview
second Preload register into the WDT’s 35-bit down-counter and starts counting down.
- Write 80 to offset BAR + 0Ch.
- Write 86 to offset BAR + 0Ch.
- Write 1 to WDT_RELOAD in Reload Register.
counter until the next time the WDT enters the second stage. Figure 29. WDT Block Diagram
16.3 Signal Descriptions
The following signals are driven from the WDT.
16.4 Device 29: Function 4 Configuration
16.4.1 Configuration Registers
Table 535. WDT Interface This signal is muxed with GPIO[32]. signal is an active low interrupt. Table 536. Configuration Registers (Sheet 1 of 2) date value of the Revision ID register.
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16.4.2 Memory Mapped Registers
16.4.3 Offset 00h: VID—Vendor Identification Register
Table 537. Memory Mapped Registers Table 538. Offset 00h: VID—Vendor Identification Register Table 536. Configuration Registers (Sheet 2 of 2) date value of the Revision ID register.
16.4.4 Offset 02h: DID—Device Identification Register
16.4.5 Offset 04 - 05h: COM—Command Register
Table 539. Offset 02h: DID—Device Identification Register Table 540. Offset 04 - 05h: COM—Command Register
4 PMWE - Postable
3 SCE - Special Cycle
1 MSE - Memory Space
WDT should be programmed before this bit is set.
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16.4.6 Offset 06h - 07h: DS—Device Status Register
Table 541. Offset 06h - 07h: DS—Device Status Register
15 DPE - Detected Parity
14 SSE - Signaled System
13 RMA - Received Master
12 RTA - Received Target
11 STA - Signaled Target-
that the Intel® 6300ESB ICH terminates with a target abort. Software resets STA to ’0’ by writing a ’1’ to this bit location. This 2-bit field defines the timing for DEVSEL# assertion. timing when performing a positive decode.
16.4.7 Offset 08h: RID—Revision Identification Register
to-date value of the Revision ID. Table 542. Offset 08h: RID—Revision Identification Register that Intel® 6300ESB ICH terminates with a target abort. Software resets STA to ’0’ by writing a ’1’ to this bit location. This two-bit field defines the timing for DEVSEL# assertion. DEVSEL# timing when performing a positive decode.
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16.4.8 Offset 09h: PI—Programming Interface Register
16.4.9 Offset 0Ah: SCC—Sub Class Code Register
16.4.10 Offset 0Bh: BCC—Base Code Class Register
16.4.11 Offset 0Eh: HEDT—Header Type Register
Watchdog Timer. It decodes the smallest possible region of 16 Bytes. Table 543. Offset 09h: PI—Programming Interface Register Table 544. Offset 0Ah: SCC—Sub Class Code Register Table 545. Offset 0Bh: BCC—Base Code Class Register
16.4.12 Offset 10h: BAR—Base Address Register
16.4.13 Offset 2Dh - 2Ch: SVID—Subsystem Vendor ID
combined with the write to the SID to create one 32-bit write. Table 546. Offset 0Eh: HEDT—Header Type Register Table 547. Offset 10h: BAR—Base Address Register
0 RTE - Resource Type
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16.4.14 Offset 2Eh - 2Fh: SID—Subsystem ID
combined with the write to the SVID to create one 32-bit write. Table 548. Offset 2Dh - 2Ch: SVID—Subsystem Vendor ID Table 549. Offset 2Eh - 2Fh: SID—Subsystem ID
16.4.15 Offset 60 - 61h: WDT Configuration Register
16.4.16 Offset 68h: WDT Lock Register
Table 550. Offset 60 - 61h: WDT Configuration Register
5 WDT_OUTPUT: Output
external WDT_TOUT# pin when the WDT times out. This signal is muxed with GPIO32.
2 WDT_PRE_SEL:
point of the 35-bit down counter. multiplied by the clock period. The WDT timer supports programmable routing of interrupts.
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Table 551. Offset 68h: WDT Lock Register
- In this mode the timer is restarted whenever
The following bit enables or disables the WDT. of writes (see Register Unlocking Sequence). reset occurs or power is cycled. power is cycled or a hard reset occurs.
16.4.17 Offset F8 - FBh: Manufacturer’s ID
16.4.18 Offset Base + 00h: Preload Value 1 Register
Table 552. Offset F8 - FBh: Manufacturer’s ID Table 553. Offset Base + 00h: Preload Value 1 Register Use this register to hold the preload value for the WDT Timer. for details on how to change the value of this register.
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16.4.19 Offset Base + 04h: Preload Value 2 Register
16.4.20 Offset Base + 08h: General Interrupt Status
Table 554. Offset Base + 04h: Preload Value 2 Register Use this register to hold the preload value for the WDT Timer. for details on how to change the value of this register. Table 555. Offset Base + 08h: General Interrupt Status Register
0 Watchdog Timer
This is a sticky bit and is only cleared by writing a 1. NOTE: This bit is not set in free-running mode.
16.4.21 Offset Base + 0Ch: Reload Register
16.5 Theory Of Operation
16.5.1 RTC Well and WDT_TOUT# Functionality
low until the system is reset or power is cycled.
16.5.2 Register Unlocking Sequence
Table 556. Offset Base + 0Ch: Reload Register Register Unlocking Sequence followed by a '1' to this bit. 1 = System has become unstable.
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The following is an example of how to prevent a timeout: 1. Write 80 to offset BAR + 0Ch. 2. Write 86 to offset BAR + 0Ch. 3. Write a ‘1’ to RELOAD [8] (WDT_RELOAD) of the Reload Register. Note: Any subsequent writes require that this sequence be performed again.
16.5.3 Reload Sequence
To keep the timer from causing an interrupt or driving WDT TOUT#, the timer must be updated periodically. Other timers refer to updating the timer as “kicking” the timer . The frequency of updates required is dependent on the value of the Preload values. To update the timer, the Register Unlocking Sequence must be performed followed by writing a ‘1’ to bit 8 at offset BAR+ 0Ch within the watchdog timer memory mapped space. This sequence of events is referred to as the “Reload Sequence”.
16.5.4 Low Power State
The Watchdog Timer does not operate when PCICLK is stopped.
PCI segment can access only APIC0 registers. passed to both APIC0 and APIC1 internally. CPU/MCU’s access to address FEC0xxxxH other than the EOI cycle stated above. APIC extension to the I/O APIC. For APIC1, this extension is always enabled.
17.1 APIC1 Configuration Registers (D29:F5)
Map” on page 277 for details. Table 557. APIC1 Configuration Map (D29:F5) (Sheet 1 of 2)
- Refer to the Intel® 6300ESB I/O Controller Hub Specification Update for the most up-to-date
value of the Revision ID Register.
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17.1.2 Offset 04 - 05h: APIC1CMD—APIC1 COMMAND
Table 558. Offset 00 - 03h: VID_DID—Vendor/ID Register (APIC1—D29:F5) Table 559. Offset 04 - 05h: APIC1CMD—APIC1 COMMAND Register (APIC1— Table 557. APIC1 Configuration Map (D29:F5) (Sheet 2 of 2)
- Refer to the Intel® 6300ESB I/O Controller Hub Specification Update for the most up-to-date
value of the Revision ID Register.
6 PERE: Parity Error
0 = No action is taken when detecting a parity error. for PERE to have any effect.
2 BME: Bus Master Enable
Table 560. Offset 06 - 07h: APIC1STA—APIC1 Device Status (APIC1—D29:F5) device select does not exist, so they have no effect.
4 Capabilities List This bit is hardwired to ‘1’, indicating the presence of a valid
capabilities pointer at offset 34h.
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17.1.4 Offset 08h: RID—Revision ID Register (APIC1—
17.1.5 Offset 09 - 0Bh: CC—Class Code Register (APIC1—
Table 561. Offset 08h: RID—Revision ID Register (APIC1—D29:F5) Table 562. Offset 09 - 0Bh: CC—Class Code Register (APIC1—D29:F5)
6 BCC: Base Class Code The value of 08h indicates that this is a generic system
be written only once after PXPCIRST# deassertion. Table 563. Offset 0C - 0Fh: HEADTYP—Header Type Register (APIC1—D29:F5)
6 Header Type This indicates that it is a type ‘00’ header (normal PCI device)
Table 564. Offset 2C - 2Fh: SS—APIC1 Subsystem Identifiers (APIC1—D29:F5)
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17.1.9 Offset 3Ch: ILINE—Interrupt Line (APIC1—
17.1.10 Offset 3Dh: IPIN—Interrupt Pin (APIC1—D29:F5)
Table 565. Offset 34h: CAP_PTR—APIC1 Capabilities Pointer (APIC1—D29:F5) Table 566. Offset 3Ch: ILINE—Interrupt Line (APIC1—D29:F5) interrupt line that the interrupt pin is connected to. Table 567. Offset 3Dh: IPIN—Interrupt Pin (APIC1—D29:F5)
17.1.11 Offset 40 - 41h: ABAR—APIC1 Alternate Base
only ABAR + offset 20h are claimed.
17.1.12 Offset 44 - 47h: MBAR—APIC1 Memory Base
Note: This register contains the APIC1 Base Address for the memory space. Table 568. Offset 40 - 41h: ABAR—APIC1 Alternate Base Address Register
15 EN: Enable
14 BIE: Boot Interrupt
0 = Boot interrupt is enabled. 1 = Boot interrupt is disabled.
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Table 569. Offset 44 - 47h: MBAR—APIC1 Memory Base Register (APIC1—
17.1.13 Offset 50 - 51h: XID—PCI-X Identifiers Register
17.1.14 Offset 52h: XSR—PCI-X Status Register (APIC1—
Table 570. Offset 50 - 51h: XID—PCI-X Identifiers Register (APIC1—D29:F5) Table 571. Offset 52h: XSR—PCI-X Status Register (APIC1—D29:F5)
19 Unexpected Split
18 Split Completion
Indicates the bus number of the bus segment for this device.
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17.2 Advanced Interrupt Controller (APIC)
(either FEC0_0020H or FEC1_0020H) to generate interrupt from APIC1. APIC extension to the I/O APIC. For APIC1, this extension is always enabled.
17.2.1 APIC1 Direct Register Map
into memory space. The registers are shown in Table 572. Register. When accessing these registers, accesses must be done a DWORD at a time. programming model in this case.
17.2.2 IND—Index Register
will program this register to select the desired APIC internal register. Table 572. APIC1 Direct Registers Table 573. APIC Indirect Registers
17.2.3 DAT—Data Register
to by the Index register. This register may only be accessed in DWORD quantities.
17.2.4 IRQPA—IRQ Pin Assertion Register
(e.g., a PCI segment on a P64H) are not supported. Table 574. IND—Index Register Table 575. DAT—Data Register
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17.2.5 EOIR—EOI Register
semantics for level-triggered interrupts issued on the parallel bus. later time. Only bits 7:0 are actually used. Bits 31:8 are ignored. Table 576. IRQPA—IRQ Pin Assertion Register should always write a value of ’0’ to Bits 31:5. Table 577. EOIR—EOI Register should always write a value of ’0’ to Bits 31:8.
17.2.6 Offset 00h: ID—Identification Register
17.2.7 Offset 01h: VER—Version Register
Table 578. Offset 00h: ID—Identification Register Table 579. Offset 01h: VER—Version Register hardwired to 17h to indicate 24 interrupts. devices to write to it to cause interrupts. ICH for the I/O (x) APIC is 20h.
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17.2.8 Offset 03h: BOOT_CONFIG—Boot Configuration
Note: This register is used to control the interrupt delivery mechanism for the APIC.
17.2.9 Redirection Table
the corresponding interrupt pin into an APIC message. Table 580. Offset 03h: BOOT_CONFIG—Boot Configuration Register Table 581. Redirection Table (Sheet 1 of 3) System Bus mode. They become bits [11:4] of the address. 8 Reserved Reserved. Software should program these bits to 0.
17 Disable Flushing
regardless of the setting of this bit. Default Value: Bit 16-1, Bits[15:12]=0.
in the delivery of the interrupt to the destination. 1 = Masked: Interrupts are not delivered nor held pending. but before the interrupt is dispensed to the processor. connected to the interrupt pins. interrupt. Writes to this bit have no effect. 0 = Idle. No activity for this interrupt. receiving APIC unit to accept the interrupt at this time. 0 = Physical. Destination APIC ID is identified by bits [59:56]. Table 581. Redirection Table (Sheet 2 of 3) Default Value: Bit 16-1, Bits[15:12]=0.
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7:0 Vector This field contains the interrupt vector for this interrupt. priority among all the processors listed in the specified destination. Trigger Mode can be edge or level. 010 = SMI. This delivery mode is not supported. 100 = NMI. This delivery mode is not supported. 101 = INIT. This delivery mode is not supported. generated as long as the INTR input is asserted. Table 581. Redirection Table (Sheet 3 of 3) Default Value: Bit 16-1, Bits[15:12]=0.
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 647 18—Intel ® 6300ESB ICH PCI-X Overview (D28:F0) 18 Note: Since the Intel® 6300ESB ICH supports a PCI interface and a PCI-X interface, the notation PCI-X will be used to refer to the PCI-X interface. Since the PCI-X interface can support the PCI-X protocol as well as the PCI protocol, the PCI-X terminology is intended to refer to the interface being described and not to the protocol.
18.1 I/O Window Addressing
This section describes the I/O window that may be set up in the bridge. Refer to Section 18.3, “VGA Addressing” to see how I/O cycles in the VGA range are handled. The register bits listed below also modify the response by the Intel ® 6300ESB ICH to I/ O transactions:
- I/O Base and Limit Registers
- I/O Enable bit in the Command Register
- Master enable bit in the Command Register
- Enable 1K granularity in the Intel® 6300ESB ICH Configuration Register To enable outbound I/O transactions, the I/O enable bit must be set in the command register in the Intel® 6300ESB ICH configuration space (bit ’0’ at offset 04-05h). When the I/O enable bit is not set, all I/O transactions initiated on the Hub Interface receive a master abort completion. No inbound I/O transactions may cross the bridge and are therefore master aborted. The Intel ® 6300ESB ICH implements one set of I/O base and limit address registers in configuration space that define an I/O address range for the bridge. Hub interface I/O transactions with addresses that fall inside the range defined by the I/O base and limit registers are forwarded to PCI-X, and PCI-X I/O transactions with addresses that fall outside this range are master aborted. Setting the base address to a value greater than that of the limit address turns off the I/O range. When the I/O range is turned off, no I/O transactions are forwarded to PCI even when the I/O enable bit is set. The I/O range has a minimum granularity of 4 Kbytes and is aligned on a 4 Kbyte boundary. The maximum I/O range is 64 Kbytes. This range may be lowered to 1K granularity by setting the EN1K bit in the Intel 6300ESB ICH Configuration register at offset 40h. The base register consists of an 8-bit field at configuration address 1Ch, and a 16-bit field at address 30h. The top four bits of the 8-bit field define bits [15:12] of the I/O base address. The bottom four bits read only as 0h to indicate that the Intel® 6300ESB ICH supports 16-bit I/O addressing. Bits [11:0] of the base address are assumed to be ’0’, which naturally aligns the base address to a 4 Kbyte boundary. The I/O base upper 16 bits register at offset 30h is reserved. After chip reset, the value of the I/O base address is initialized to 0000h. The I/O limit register consists of an 8-bit field at offset 1Dh and a 16-bit field at offset 32h. The top four bits of the 8-bit field define bits [15:12] of the I/O limit address. The bottom four bits read only as 0h to indicate that 16-bit I/O addressing is supported. Bits [11:0] of the limit address are assumed to be FFFh, which naturally aligns the limit address to the top of a 4 Kbyte I/O address block. The 16 bits contained in the I/O limit upper 16 bits register at offset 32h are reserved. After chip reset, the value of the I/O limit address is reset to 0FFFh.
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Note: When the EN1K bit is set in the Intel ® 6300ESB ICH Configuration register, the base and limit registers are changed so that the top six bits of the 8-bit field define bits [15:10] of the I/O base/limit address, and the bottom two bits read only as 0h to indicate support for 16-bit I/O addressing. Bits [9:0] are assumed to be ‘0’ for the base register and ‘1’ for the limit register, which naturally aligns the address to a 1 Kbyte boundary.
18.2 Memory Window Addressing
This section describes the memory windows that may be set up in the bridge. Refer to Section 18.2.2, “Prefetchable Memory Base and Limit Address Registers, Upper 32-Bit Registers” to see how memory cycles in the VGA range are handled.
- Memory-mapped I/O Base and Limit registers
- Prefetchable Memory Base and Limit registers
- Prefetchable Memory Base and Limit upper 32 bits register
- Memory Enable bit in the Command register
- Master Enable bit in the Command register To enable outbound memory transactions, the memory space enable bit in the command register must be set (bit 1 of offset 04-05h). To enable inbound memory transactions, the master enable bit in the command register must be set (bit 2 of offset 04-05h). The Intel ® 6300ESB ICH does not prefetch data from PCI devices. The Intel® 6300ESB ICH supports 64 bits of addressing (DAC cycles) on both interfaces.
18.2.1 Memory Base and Limit Address Registers
The memory base address and memory limit address registers define an address range that the Intel® 6300ESB ICH uses to determine when to forward memory commands. The Intel® 6300ESB ICH forwards a memory transaction from the Hub Interface to PCI- X when the address falls within the range, and forwards it from PCI-X to the Hub Interface when the address is outside the range, provided that they do not fall into the prefetchable memory range (see Section 18.2.2, “Prefetchable Memory Base and Limit Address Registers, Upper 32-Bit Registers”). This memory range supports 32-bit addressing only (addresses 4 Gbytes). It has a granularity and alignment of 1 Mbyte. This range is defined by a 16-bit base address register at offset 20h in configuration space and a 16-bit limit address register at offset 22h. The top 12 bits of each of these registers correspond to bits [31:20] of the memory address. The low four bits are hardwired to ‘0’. The low 20 bits of the base address are assumed to be all ‘0’, which results in a natural alignment to a 1 Mbyte boundary. The low 20 bits of the limit address are assumed to be all ‘1’s, which results in an alignment to the top of a 1 Mbyte block. Setting the base to a value greater than that of the limit turns off the memory range.
18.2.2 Prefetchable Memory Base and Limit Address
Registers, Upper 32-Bit Registers The prefetchable memory base and address registers, along with their upper 32-bit counterparts, define an additional address range that the Intel ® 6300ESB ICH uses to forward accesses. The Intel® 6300ESB ICH forwards a memory transaction from the Hub Interface to PCI-X when the address falls within the range, and forwards
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 649 18—Intel ® 6300ESB ICH transactions from PCI-X to the Hub Interface when the address is outside the range and do not fall into the regular memory range (see Section 18.2.1, “Memory Base and Limit Address Registers”). This memory range supports 64-bit addressing and has a granularity and alignment of 1 Mbyte. This lower 32 bits of the range are defined by a 16-bit base register at offset 24h in configuration space and a 16-bit limit register at offset 26h. The top 12 bits of each of these registers correspond to bits [31:20] of the memory address. The low four bits are hardwired to 1h, indicating 64-bit address support. The low 20 bits of the base address are assumed to be all ‘0’s, which results in a natural alignment to a 1 Mbyte boundary. The low 20 bits of the limit address are assumed to be all ‘1’s, which results in an alignment to the top of a 1 Mbyte block. The upper 32 bits of the range are defined by a 32-bit base register at offset 28h in configuration space and a 32-bit limit register at offset 2Ch. Setting the entire base (with upper 32 bits) to a value greater than that of the limit turns off the memory range.
18.3 VGA Addressing
When a VGA-compatible device exists behind an Intel ® 6300ESB ICH bridge, the VGA enable bit in the bridge control register is set (offset 3 at 3E-3Fh). When set, the Intel® 6300ESB ICH forwards all transactions addressing the VGA frame buffer memory and VGA I/O registers from the Hub Interface to PCI-X, regardless of the values of the Intel ® 6300ESB ICH base and limit address registers. When set, the Intel ® 6300ESB ICH does not forward VGA frame buffer memory accesses to the Hub Interface regardless of the values of the memory address ranges. However, the I/O enable and memory enable bit in the command register must still be set. When cleared, the Intel ® 6300ESB ICH forwards transactions addressing the VGA frame buffer memory and VGA I/O registers from the Hub Interface to PCI-X when the defined memory address ranges enable forwarding. When cleared, accesses to the VGA frame buffer memory are forwarded from PCI-X to the Hub Interface when the defined memory address ranges enable forwarding. However, the master enable bit must still be set. The VGA I/ O addresses are never forwarded to the Hub Interface. The VGA frame buffer consists of the following memory address range: 000A 0000h– 00B FFFFh. The VGA I/O addresses consist of the I/O addresses 3B0h–3BBh and 3C0h–3DFh. These I/O addresses are aliased every 1 Kbyte throughout the first 64 Kbyte of I/O space. This means that address bits [9:0] (3B0h-3BBh and 3C0h-3DFh) are decoded, [15:10] are not decoded and may be any value, and address bits [31:16] must be all ‘0’s.
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18.4 Configuration Addressing
Figure 30 shows how the Intel® 6300ESB ICH appears to configuration software. does not have a space visible to software. number, device number, function number and register number present in the address. Refer to the Hub Interface specification for details of the address.
18.4.1 Type 0 Accesses to the Intel ® 6300ESB ICH
- The bus command is a configuration read or configuration write transaction.
- Low 2 address bits AD[1:0] must be 00b.
- The device number matches one of the Intel ® 6300ESB ICH devices (28).
18.4.2 Type 1 to Type 0 Translation
Figure 30. Intel ® 6300ESB I/O Controller Hub Appearance to Software Table 582. Configuration Addressing
translation is done for cycles that originate on the Hub Interface and target PCI/PCI-X.
- The bus command is a Configuration read or write transaction.
- The low 2 address bits on AD [1:0] are 01b.
- The bus number in address field AD [23:16] is equal to the value in the secondary bus number register in the Intel ® 6300ESB ICH configuration space. The resulting Type 0 address to be driven on PCI-X is shown in Figure 31. Device numbers are decoded to generate a single ‘1’ in address bits 31:16. When the device number is greater than 16, then all bits are ‘0’.
18.4.3 Type 1 to Type 1 Forwarding
bus under the following conditions.
- The bus command is a configuration read or write transaction.
- The low two address bits are equal to 01b.
- The bus number falls in the range defined by the lower limit (exclusive) in the secondary bus number register and the upper limit (inclusive) in the subordinate bus number register. Type 1 to type 1 forwarding is only done for cycles from the Hub Interface to PCI-X.
18.4.4 Type 1 to Special Cycle Forwarding
- The low two address bits on AD[1:0] are equal to 01b.
- The device number in address bits AD[15:11] is equal to 11111b.
- The function number in address bits AD[10:8] is equal to 111b.
- The register number in address bits AD[7:2] is equal to 000000b.
- The bus number is equal to the value in the secondary bus number register in configuration space.
- The bus command is a Configuration Write command. The address and data are forwarded unchanged. Devices ignore the address and decode only the bus command. The data phase contains the special cycle message. The transaction does a master abort but results in a normal completion on the opposite bus
Figure 31. Type ‘1’ to Type ‘0’ Translation
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disconnect operation during the first data phase.
18.5 Transaction Ordering
18.5.2 Other Notes
- The Intel® 6300ESB ICH does not combine separate write transactions into a single write transaction.
- The Intel® 6300ESB ICH does not merge bytes on separate write transactions to the same dWord address.
- The Intel® 6300ESB ICH does not collapse sequential write transactions to the same address into a single write transaction – the PCI Local Bus Specification does not permit this.
Table 583. Comparison of Rules vs. A PCI – PCI Bridge
- Subsequent requests only (prefetches). All inbound initial requests are in order.
- In a bridge, these are allowed to be yes/no.
- In a bridge, these are allowed to be yes/no. These particular entries are “No” because the
18.6 Device 28 – Hub Interface to PCI-X Bridge
18.6.1 Configuration Space Registers
18.6.1.1 Register Summary
Table 584. Configuration Space Register Summary (Sheet 1 of 2) date value of the Revision ID register.
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18.6.1.2 Offset 00: ID—Identifiers
Note: Contains the vendor and device identifiers for software. Table 585. Offset 00: ID—Identifiers Table 584. Configuration Space Register Summary (Sheet 2 of 2) date value of the Revision ID register.
18.6.1.3 Offset 04: CMD—Command
Control” located at offset 3E. Table 586. Offset 04: CMD—Command (Sheet 1 of 2) Section 5.1.4 for more details on this bit. error is detected on the Hub Interface. Interface and sets the DPD bit in the status register. have a corresponding transfer type.
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18.6.1.4 Offset 06: PSTS—Primary Status
Note: RASERR# will be asserted based on activity of bits 15:11, 8. address a device behind the Intel® 6300ESB ICH. address a device that resides behind the Intel® 6300ESB ICH. Table 586. Offset 04: CMD—Command (Sheet 2 of 2)
Table 587. Offset 06: PSTS—Primary Status that each bridge sets this bit, regardless of address. packet with master abort status. packet with target abort status. offset for the first entry in the linked list of capabilities.
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18.6.1.5 Offset 08: RID—Revision ID
Table 588. Offset 08: RID—Revision ID
18.6.1.6 Offset 09: CC—Class Code
Note: This contains the class code, sub class code, and programming interface for the device.
18.6.1.7 Offset 0C: CLS—Cache Line Size
Note: This indicates the cache line size of the system. Table 589. Offset 09: CC—Class Code Table 590. Offset 0C: CLS—Cache Line Size line, and a value of ‘20h’ represents a 128-byte line. avoided in the memory subsystem.
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18.6.1.8 Offset 0D: PLT—Primary Latency Timer
18.6.1.9 Offset 0E: HTYPE—Header Type
Note: This register determines how the rest of the configuration space is laid out. Table 591. Offset 0D: PLT—Primary Latency Timer Table 592. Offset 0E: HTYPE—Header Type
Note: This contains the primary, secondary, and maximum subordinate bus number registers. should be 64 in PCI-X mode (Section 8.6.1 of the PCI-X 1.0 Specification). Table 593. Offset 18: BNUM—Bus Numbers one configuration cycle on the PCI bus. configuration cycle and run on the PCI bus. (i.e., it still may match the other bridge). Table 594. Offset 1B: SLT—Secondary Latency Timer
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Note: Defines the base and limit, aligned to a 4 Kbyte boundary, of the I/O area of the bridge. sent to PCI-X when the I/O space enable bit is set. Note: Accesses from PCI-X that are outside the ranges specified result in a master abort. Table 595. Offset 1C: IOBL—I/O Base and Limit Kbyte alignment. Bits 11:0 are assumed to be FFFh.
00 R/W
4 Kbyte alignment. Bits 11:0 are assumed to be 000h. I/O address bits 11:10 to determine the 1K base address. When the EN1K bit is cleared, this field becomes Read Only.
Note: RASERR# will be asserted based on activity of bits 15:11, 8. Table 596. Offset 1E: SSTS—Secondary Status (Sheet 1 of 2) an initiator on the PCI-X bus and the cycle is master-aborted. an initiator on PCI-X and a cycle is target-aborted on PCI-X.
- T h e I n t e l® 6300ESB ICH is the initiator on PCI-X.
- PERR# is detected asserted or a parity error is detected internally.
- The Parity Error Response Enable bit in the Bridge Control Register (bit 0, offset 3Eh) is set. 0R / W C Fast Back- to-Back Capable (FBC) Indicates that the secondary interface of the Intel ® 6300ESB ICH may receive fast back-to-back cycles. 1R O 6 Reserved Reserved. 0 RO Device 28 Function 0 Offset 1E Attribute: Read/Write Clear Size: 16-bit
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register are sent to PCI-X when the memory space enable bit is set. Interface when the bus master enable bit is set. an internal SERR# and be a source for the NMI logic. Table 597. Offset 20: MBL—Memory Base and Limit than or equal to this value. greater than or equal to this value. Table 596. Offset 1E: SSTS—Secondary Status (Sheet 2 of 2)
in this register are sent to PCI-X when the memory space enable bit is set. Interface when the bus master enable bit is set. Note: This defines the upper 32 bits of the prefetchable address base register. Table 598. Offset 24: PMBL—Prefetchable Memory Base and Limit Indicates that 32-bit addressing is supported for the limit. greater than or equal to this value. Indicates that 32-bit addressing is supported for the limit. Table 599. Offset 28: PMBU32—Prefetchable Memory Base Upper 32 Bits
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Note: This defines the upper 32 bits of the prefetchable address limit register. Note: Since I/O is limited to 64 Kbytes, this register is reserved and not used. Table 600. Offset 2C: PMLU32—Prefetchable Memory Limit Upper 32 Bits within the Intel® 6300ESB ICH. Table 601. Offset 30: IOBLU16—I/O Base and Limit Upper 16 Bits
Note: Contains the pointer for the first entry in the capabilities list. Note: This register contains information on interrupts on the bridge. Note: This register provides extensions to the Command register that are specific to a bridge. bits affect operation of both interfaces of the bridge. Table 602. Offset 34: CAPP—Capabilities List Pointer Table 603. Offset 3C: INTR—Interrupt Information
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Table 604. Offset 3E: BCTRL—Bridge Control (Sheet 1 of 3) assertion. The SERR# can be a s source on NMI. response to a timer discard on the secondary interface. transaction from its queues.
Compensation Register” for SBRE details. software must keep asserted for at least 100 µsecs. abort occurs on either interface. drives all '1's for reads and discards data on writes.
04 VGA 16-bit
03 VGA Enable
enable and I/O enable in the command register. [15:10] of the address are ignored (i.e., aliased). ranges are forwarded to the Hub Interface. Table 604. Offset 3E: BCTRL—Bridge Control (Sheet 2 of 3)
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02 ISA Enable
Modifies the response by the bridge to ISA I/O addresses. forward I/O transactions across the bridge.
01 PXSERR#
Table 604. Offset 3E: BCTRL—Bridge Control (Sheet 3 of 3)
Table 605. Offset 40: CNF—Intel® 6300ESB I/O Controller Hub Configuration Disables a PCI-X clock output that is not used in the system. disabled, the PCLKOUT pin is tri-stated.
08 PCI-X Mode
1 N/A PCI-X 66 MHz 1
of M66EN and PCIXCAP pins as per the table above. the value will not affect the PCI-X Mode.
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1 N/A PCI-X 66 MHz
0 33 Only valid when PMODE is 0. of M66EN and PCIXCAP pins as per the table above. the value will not affect the PCI-X Mode.
00: Allow prefetching on MRM, MRL, and MR. 1x: Disable all prefetching. frequency read from bits 8:6 of this register. Table 606. Offset 42: MTT—Multi-Transaction Timer
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Note: This register indicates the states of various straps for this PCI-X interface. Table 607. Offset 44: STRP—PCI Strap Status Table 608. Offset 50: PX_CAPID—PCI-X Capabilities Identifier Table 609. Offset 51: PX_NXTP—Next Item Pointer
Note: This is the PCI-X command register which controls various modes of the bridge. Table 610. Offset 52: PX_SSTS—PCI-X Secondary Status (Sheet 1 of 2)
000 PCI Mode N/A
Transaction Control register. NOTE: The Intel® 6300ESB ICH does not set this bit. because its buffers are full. NOTE: The Intel® 6300ESB ICH does not set this bit.
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Note: Identifies PCI-X capabilities and current operating mode of the bridge.
133 MHz
interface is capable of 133 MHz operation in PCI-X mode. Table 611. Offset 54: PX_BSTS - PCI-X Bridge Status Table 610. Offset 52: PX_SSTS—PCI-X Secondary Status (Sheet 2 of 2)
An alias to the PBN field of the BNUM register at offset 18h.
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forwarding Split Transactions from the secondary bus to the Hub Interface. forwarding Split Transactions from the Hub Interface to the secondary bus. Table 612. Offset 58: PX_USTC - PCI-X Upstream Split Transaction Control R/W field available for use by diagnostic software. algorithms keep buffers from being overallocated.
Table 613. Offset 5C: PX_DSTC - PCI-X Downstream Split Transaction Control R/W field available for use by diagnostic software.
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Table 614. Offset E0: ACNF – Additional Intel® 6300ESB ICH Configuration When 1, bunit bypasses it’s read pending queue when empty.
Table 615. Offset E4: PCR - PCI Compensation Register
09 SBR Enable
BCTRL—Bridge Control” , bit 6, for SBR details. the secondary bus reset for the PCI-X bus.
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transaction is established when the master wished the burst to continue. Table 616. Offset F0: HCCR - Hub Interface Command/Control Register
000 R/W
Table 617. Offset F8h: PC33 - Prefetch Control – 33 MHz Table 618. Offset FAh: PC66 - Prefetch Control – 66 MHz
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18.7 PCI Mode in the PCI-X Interface
18.7.1 Summary of Changes
the PCI interface for the P64H2.
- Full 64 bit addressing inbound
- Inbound packet size based upon cache line size of the platform.
- I/O space may be programmed to 1K granularity through the EN1K bit of the CNF register.
- When inbound reads are retried, they are moved to the side so posted writes and completion packets may pass. I/O reads and writes on PCI are no longer be forwarded to the Hub Interface.
18.7.2 Transaction Types
disconnects the transaction after the first data transfer. Table 619. Intel ® 6300ESB I/O Controller Hub PCI Transactions
0000 Interrupt
0001 Special cycle Yes No 1001 Reserved † No No
0010 I/O read Yes No 1010 Configuration Read Yes No
0011 I/O write Yes No 1011 Configuration Write Yes No
0100 Reserved † No No 1100 Memory Read
0101 Reserved † No No 1101 Dual Address Cycle Yes Yes
0110 Memory read Yes Yes 1110 Memory Read Line No Yes
0111 Memory write Yes Yes 1111 Memory Write and
reserved command codes as a target.
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18.7.3 Detection of 64-Bit Environment
The Intel® 6300ESB ICH drives REQ64# low during PXPCIRST# on each PCI-X interface to signal that the bus is a 64-bit bus .
18.7.4 Data Bus
For supplying data, the Intel® 6300ESB ICH drives the following in the data phase:
- The low 32 bits of data on PXAD[31:0]
- The low four byte enable bits on PXC/BE#[3:0]
- The high 32 bits of data on PXAD[63:32] (64-bit data phases only)
- The high four byte enable bits on PXC/BE#[7:4] (64-bit data phases only) As a PCI master, when the Intel® 6300ESB ICH drives PXREQ64# and detects PXACK64# asserted in the same clock that it detects PXDEVSEL# asserted, every data phase then consists of 64 bits and eight byte enable bits. On write transactions, when the Intel ® 6300ESB ICH does not detect PXACK64# asserted in the same clock that it detects PXDEVSEL# asserted, it redirects all data to AD[31:0] and byte enables to C/BE#[3:0]. For 64-bit memory-write transactions that end at an odd dWord boundary, the Intel® 6300ESB ICH drives the byte enable bits to ’1’, and drives random but stable data on PXAD[63:32]. On read transactions, the Intel® 6300ESB ICH drives eight bits of byte enables on PXC/ BE#[7:0]. It generates byte enables from the Hub Interface byte enables, with the upper dWord driven on PXC/BE#[7:4]. When ACK64# is not sampled active with PXDEVSEL# active, then the Intel ® 6300ESB ICH downshifts the all byte enables PXC/ BE#[3:0]. The Intel® 6300ESB ICH does not assert REQ64# when initiating a transfer under the following conditions:
- The Intel® 6300ESB ICH is initiating an I/O transaction.
- The Intel® 6300ESB ICH is initiating a configuration transaction.
- The Intel® 6300ESB ICH is initiating a special cycle transaction.
- A 1-dWord or 2-dWord transaction is being performed.
- When the address of the Hub Interface initiated transaction is not quad word aligned. As a PCI target, the Intel® 6300ESB ICH does not assert PXACK64# when PXREQ64# was not asserted by the initiator.
18.7.5 Write Transactions
18.7.5.1 Posted
Posted write forwarding is used for memory write and for memory write and invalidate transactions. When the Intel® 6300ESB ICH decodes a memory write transaction for the Hub Interface, it asserts PXDEVSEL# and PXTRDY# in the same clock, provided that enough buffer space is available in the posted data queue. The Intel ® 6300ESB ICH adds no target wait states.
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The Intel® 6300ESB ICH disconnects a write transaction when:
- The initiator terminates the transaction by de-asserting PXFRAME# and PXIRDY#.
- A 4 Kbyte page boundary is reached.
- The posted write data buffer fills up.
18.7.5.2 Non-Posted
Delayed write forwarding is not used. It is only for I/O write transactions. Since the Intel® 6300ESB ICH does not support I/O write transactions across a bridge, these cycles all result in a master abort. Note: Configuration cycles are not allowed to cross a bridge per the PCI bridge specification.
18.7.5.3 Fast Back-to-Back
The Intel® 6300ESB ICH allows fast back-to-back write transactions on PCI.
18.7.6 Read Transactions
18.7.6.1 Prefetchable
Any memory read multiple command on PCI that is decoded by the Intel ® 6300ESB ICH is prefetched on the Hub Interface. Prefetching may be optionally disabled when bit 4 of the Intel ® 6300ESB ICH Configuration Register (offset 40-41h) is set. The Intel ® 6300ESB ICH does not prefetch past a 4 Kbyte page boundary.
18.7.6.2 Delayed
All memory read transactions are delayed read transactions. When the Intel® 6300ESB ICH accepts a delayed read request, it samples the address, command, and address parity. This information is entered into the delayed transaction queue and all I/O transactions then master abort.
18.7.7 Transaction Termination
18.7.7.1 Normal Master Termination
As a PCI master , the Intel® 6300ESB ICH uses normal termination when DEVSEL# is returned by the target within five clock cycles of PXFRAME# assertion. It terminates a transaction when the following conditions are met:
- All write data for the transaction is transferred from the Intel ® 6300ESB ICH data buffers to the target.
- The master latency timer expires and the Intel ® 6300ESB ICH’s bus grant is de- asserted.
18.7.7.2 Master Abort Termination
When an Intel® 6300ESB ICH initiated transaction is not responded to with DEVSEL# within five clocks of PXFRAME# assertion, the Intel ® 6300ESB ICH terminates the transaction with a master abort. The Intel ® 6300ESB ICH sets the received master abort bit in the status register corresponding to the target bus.
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18.7.7.3 Target Termination Received by the Intel ® 6300ESB ICH
When the Intel® 6300ESB ICH receives a retry or disconnect response from a target, it re-initiates the transfer with the remaining length. When the Intel ® 6300ESB ICH receives a target abort, and the cycle requires completion on the Hub Interface, the Intel ® 6300ESB ICH returns the target abort code to the Hub Interface as the completion status.
18.7.7.4 Target Termination Initiated by the Intel ® 6300ESB ICH
The Intel® 6300ESB ICH returns a target retry to an initiator for memory read transactions when any of the following conditions are met:
- A new transaction for delayed transaction queue.
- The request has already been queued, but has not completed on the Hub Interface.
- The delayed transaction queue is full, and the transaction cannot be queued. — A LOCK transaction has been established from the Hub Interface to PCI. The Intel® 6300ESB ICH disconnects an initiator when one of the following conditions is met:
- The Intel® 6300ESB ICH cannot accept any more write data
- The Intel® 6300ESB ICH has no more read data to deliver
- When the memory address is non-linear The Intel® 6300ESB ICH returns a target abort to PCI when the cycle master aborted or target aborted on the Hub Interface.
18.7.8 LOCK Cycles
A lock is established when a memory read from the Hub Interface that targets PCI with the lock bit set, and at least one byte enable active, is responded to with a TRDY# by a PCI target. The Intel® 6300ESB ICH does not support a split-lock request with no byte enables are asserted on the initial locked read request. The bus is unlocked when the Unlock Special Cycle is sent on the Hub Interface. When the bus is locked, the cycle is retried when a memory cycle originates on PCI that is outside the range of the memory windows. No I/O cycles that are destined across the bridge are accepted, whether the bus is locked or not, and then master abort. Once the bus is locked, any Hub Interface cycle to PCI is driven with the LOCK# pin, even when that particular cycle is not locked.
18.7.9 Error Handling
The Intel® 6300ESB ICH checks and generates parity on the Hub Interface and parity on the PCI interfaces. Parity errors must always be reported to some system level software, typically the device driver or the OS. This section describes how a standard PCI bridge handles these errors. For enhanced error detection, see the RAS section located section.
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The Intel® 6300ESB ICH requires that the “Hub Interface Parity Unsupported” bit (D30:F0:40h:bit 20) is cleared in order to perform any parity checking as described below. Good Hub Interface parity is presented to all logic in the Intel ® 6300ESB ICH when the bit is set. To support error reporting on the PCI bus, the Intel ® 6300ESB ICH implements the following:
- PERR# and SERR# signals on PCI
- Primary status (offset 06-07h) and secondary status registers (offset 1E-1Fh) The Intel® 6300ESB ICH does not have the PERR# or SERR# pins on the Hub Interface. The Intel® 6300ESB ICH is capable of generating NMI, and SMI Address Parity Errors Address parity errors are very serious and may abort further data transfers, depending upon the direction of the transfer and the setting of the Parity Error Response Enable bit, as described in the following paragraphs. The Intel ® 6300ESB ICH checks address parity for all transactions on both the Hub Interface and PCI buses, for all address and all bus commands. When the Intel® 6300ESB ICH detects an parity error in the header section of a Hub Interface packet, it:
- Sets the Detected Parity Error bit in the Primary status register (bit 15 of offset 06- 07h) when the address is targeting the device. The bridge devices log address parity errors independent of the target address.
- Generates NMI/SMI (as enabled) and sets the signaled system error bit in the primary status register (bit 14 of offset 06-07h), when the parity error response bit in the command register (bit 6 of offset 04-05h) is set and SERR# is enabled.
- Attempts to interpret the cycle as best it can, and forwards the cycle with an address parity error tag to the internal logic, where it aborts internally. When a device is not enabled to respond to parity errors, it ignores the address parity error (except for setting the Detected Parity Error bit). When the address targets that device, the device accepts the cycle and responds as though there was no address parity error. The cycle is forwarded to PCI with good address parity when the cycle targets a bridge and it is not enabled to respond to parity errors. When the Intel ® 6300ESB ICH detects an address parity error on the PCI interface, the following events occur: The Intel® 6300ESB ICH sets the detected parity error bit in the secondary status register (bit 15 of offset 1E-1F).
- When the parity error response bit is ’0’ in the bridge control register (bit ’0’ of offset 3E-3F), the address parity errors are ignored. The cycles would be treated as though no error was observed.
- When the parity error response bit is set and the address parity error is observed on memory cycles, the cycle is accepted as though the address was correct. Delayed Transactions are established for memory reads and data are posted for memory writes. The cycles are forwarded to the Hub Interface with correct address parity. The Intel ® 6300ESB ICH generates NMI/SMI (as enabled) sets the signaled system error bit in the Primary Status Register, when all of the following conditions are met:
- The SERR# enable bit is set in the primary command register.
- The parity error response bit is set in the bridge control register.
- The SERR# enable bit is set in the bridge control register. The Intel® 6300ESB ICH generates NMI, if the following conditions are met:
- Port70.7 (I/O register at offset 70h, bit 7) is enabled.
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- The parity errors response bit is set in the bridge control register (D28:3Eh,0)
18.7.9.1 Data Parity Errors
Unlike address parity errors, data parity errors are not considered as severe and transactions are aborted. The following sections describe the sequence of events when a data parity error is detected for the following transactions:
- Configuration Write Transactions
- Read Transactions (inbound and outbound)
- Posted Write Transaction
18.7.9.1.1 Hub Interface Configuration Write Transactions
When the Intel® 6300ESB ICH detects a data parity error during a Type 0 configuration write transaction to one of the Intel ® 6300ESB ICH configuration spaces, the Intel ® 6300ESB ICH:
- Does not write the data to the configuration register when parity error response is enabled.
- Sets the Detected Parity Error bit in the Primary status register (bit 15 of offset 06- 07h).
- Generates NMI/SMI (depending on which is enabled) and sets the signaled system error bit (bit 14) in the Primary status register, when the Parity Error Response Enable bit in the command register (bit 6 of offset 04-05h) is set.
18.7.9.1.2 Read Transactions from Hub Interface Targeting PCI on the PCI-X
When the Intel® 6300ESB ICH detects a read data parity error on the PCI bus from a Hub Interface initiated read, it:
- Sets the detected parity error bit in the secondary status register (bit 15 of offset 1E-1Fh).
- Sets the Data parity detected bit in the secondary status register (bit 8 of offset 1E- 1Fh), when the secondary interface parity error response bit is set in the bridge control register (bit ’0’ of offset 3E-3Fh).
- Forces bad parity error with the data back to the initiator on the Hub Interface.
18.7.9.1.3 Read Transactions from PCI Targeting Hub Interface
When the Intel® 6300ESB ICH detects a data parity error on a Hub Interface completion packet from a previous memory read request on PCI, the Intel ® 6300ESB ICH:
- Sets the detected parity error bit in the primary status register (bit 15 of offset 06- 07h).
- Sets the data parity detected bit in the primary status register (bit 8 of offset 06- 07h) and generates the NMI/SMI (depending on which is enabled), when the primary interface parity error response bit is set in the command register (bit 6 of offset 04-05h).
- Forwards the bad parity with the data back to PCI.
18.7.9.1.4 Write Transactions on Hub Interface – Intel ® 6300ESB ICH as a Hub
When the Intel® 6300ESB ICH detects a data parity error on a Hub Interface write request, it:
- Sets the data parity error detected bit in the status register (bit 15 of offset 06- 07h) of the target interface (PCI bridge primary).
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- Forwards the bad parity with the data to PCI when decoded by the bridge.
- Generates NMI/SMI (depending on which is enabled) and sets the signaled system error bit (bit 14) in the Primary status register, when the parity error response bit (bit 6) is set in the command register.
18.7.9.1.5 Write Transactions on Hub Interface – Intel ® 6300ESB ICH as a Hub
There is no way of detecting that a northern device detected a parity error from a Hub Interface posted write from PCI. Therefore, no action is taken by the Intel ® 6300ESB ICH.
18.7.9.1.6 Write Transactions on PCI – Intel ® 6300ESB ICH as PCI Target
When the Intel® 6300ESB ICH detects a data parity error on a PCI write, it:
- Asserts PERR# two cycles after the data transfer, when the secondary interface parity error response bit is set in the bridge control register.
- Sets the secondary interface parity error detected bit in the secondary status register.
- Forces bad parity error condition to the primary bus.
18.7.9.1.7 Write Transactions on PCI – Intel ® 6300ESB ICH as PCI Master
When a data parity error is reported on the PCI bus from a Hub Interface or PCI peer initiated write request by the target’s assertion of PERR#, the Intel® 6300ESB ICH:
- Sets the Detected Parity Detected bit in the secondary status register (bit 8 of offset 1E-1Fh), when the secondary interface parity error response bit is set in the bridge control register.
- Generates NMI/SMI (depending on which is enabled) and sets the signaled system error bit in the status register, when all of the following conditions are met: — The SERR# enable bit is set in the command register. — The secondary interface parity error response bit is set in the bridge control register. — The primary interface parity error response bit is set in the command register. —T h e I n t e l ® 6300ESB ICH did not detect the parity error on the Hub Interface (i.e., the parity error was not forwarded from the Hub Interface).
18.7.9.2 System Errors
18.7.9.2.1 PCI SERR# Pin Assertion
When SERR# is sampled asserted, the Intel ® 6300ESB ICH sets the received system error bit in the secondary status register . The Intel® 6300ESB ICH generates NMI/SMI (depending on which is enabled) when:
- The SERR# forward enable bit is set in the bridge control register, and
- The primary SERR# enable bit is set in the Primary command register.
18.7.9.2.2 Other System Errors
The Intel® 6300ESB ICH also conditionally NMI or SMI as enabled for any of the following reasons:
- Master timeout on delayed transaction when the primary SERR# enable bit is set and SERR# due to timeout enable bit (bit 11 of offset 3E-3Fh) is set.
- The MAM bit (Master Abort Mode) is set in the bridge control register and a posted write from the Hub Interface results in a master abort on PCI, or a posted write from one PCI interface results in a master abort on the other PCI interface. (No
Hub Interface – the north Hub Interface agent must handle this condition).
18.8 PCI-X Interface
all details related to PCI-X operation.
18.8.1 Command Encoding
18.8.2 Attributes
PCI-X specification leaves some implementation leeway. Table 620. PCI-X Interface Command Encoding
1 Special cycle No No 100
0 I/O read Yes No 101
0 Configuration Read Yes No
1 I/O write Yes No 101
1 Configuration Write Yes No
0 Reserved No No 110
0 Split Completion Yes Yes
1 Reserved No No 110
1 Dual Address Cycle Yes Yes
0 Memory Read dWord Yes Yes 111
0 Memory Read Block Yes Yes
1 Memory Write Yes Yes 111
1 Memory Write Block No Yes
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18.8.3 Special Notes for Burst Transactions
6300ESB ICH allows a burst past a 4K page boundary. initiator. When it does not have this space available, it does not issue the transaction.
18.8.4 Device Select Timing
Table 622. The Intel® 6300ESB ICH responds as a type A target.
18.8.5 Wait States
Table 621. Intel ® 6300ESB ICH Implementation of Requester Attribute Fields is never generated on PCI-X from a Hub Interface packet. time, this field is be set to 0. Interface, which is dWord based. Table 622. DEVSEL# Timing
18.8.6 Split Transactions
18.8.6.1 Completer Attributes
18.8.6.2 Requirements for Accepting Split Completions
from this device, or when the byte count exceeds that of the Split Request. Interface, but only one is pending on any PCI/PCI-X interface at a time.
18.8.6.3 Split Completion Messages
18.8.6.4 Arbitration Among Multiple Split Completions
MLT has not expired for that transaction. Table 623. Intel ® 6300ESB ICH Implementation Completer Attribute Fields (SCM) This bit shadows the SCE bit. Table 624. Split Completion Messages
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18.8.7 Transaction Termination as a PCI-X Target
18.8.7.1 Retry
The Intel® 6300ESB ICH retries a cycle when the Split Request queue is full (i.e., we already have four current and four pending Split Transactions). It has room to accept a split completion as it has a dedicated buffer for split completions. It also retries a cycle when the bus is locked. The Intel ® 6300ESB ICH stores no state from the transaction on a retry.
18.8.7.2 Split Response
All cycles that cross the bridge receive this termination, when they are not retried.
18.8.7.3 Master-Abort
Any I/O transaction that would cross from PCI-X to either the Hub Interface or the peer bridge are not decoded and results in a master abort to the PCI-X initiator.
18.8.8 Arbitration
The Intel® 6300ESB ICH parks on the last agent to use PCI. This allows PCI devices operating as a single stream to stay on PCI bus for the duration of their transfer.
18.8.9 Bridge Buffer Requirements
The Intel® 6300ESB ICH has 128 bytes (one ADQ) available for accepting memory write, split completion, and immediate read data. The Intel ® 6300ESB ICH contains 1.5K of data total for inbound transactions. The Intel® 6300ESB ICH PCI-X interface terminates all memory transactions (Memory Read DWORD, Memory Read Block, and Alias to Memory Read Block) that address a device north of the bridge with a Split Response. Other split transaction commands are not decoded by the Intel ® 6300ESB ICH. The Intel® 6300ESB ICH does not implement any split completion buffer allocation algorithm as listed in the PCI-X specification. This is overhead that is not necessary. The Intel® 6300ESB ICH does not request on the Hub Interface more than it has buffer space for on returns, and does not initiate a cycle from the Hub Interface that it cannot accept as a return. The bridge rules of the specification already allow the PCI-X interface to retry split completions when the bridge is temporarily full. Therefore, the split transaction control registers are not used by the Intel ® 6300ESB ICH.
18.8.10 Locked Transactions
The Intel® 6300ESB ICH is not locked until the target has completed at least the first data phase as an Immediate Transaction or a Split Transaction (target signals Split Response).
18.8.11 Error Support
it generates NMI/SMI (depending on which is enabled).
18.9 Transaction Termination Translation
PCI-X bridge that supports a secondary bus configured as either PCI or PCI-X. occurred on the secondary bus without any translation. a specific termination, see the specific sections on the interface above.
18.9.1 Behavior of Hub Interface Initiated Cycles to PCI/
completion that terminates in either Master Abort or Target Abort. Table 625. Immediate Terminations of Completion Required Cycles to PCI/PCI-X † The Master Data Parity Error bit is set only when a data parity error is encountered on the PCI/PCI-X bus.
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18.9.2 Behavior of Hub Interface Initiated Cycles to PCI-
explicitly master or target aborts on the PCI-X interface. Table 626. Immediate Terminations of Posted Write Cycles to PCI/PCI-X † The Master Data Parity Error bit is set only when a data parity error is encountered on the PCI/PCI-X bus. Table 627. Split Terminations of Completion Required Cycles to PCI-X (Sheet 1 of
18.9.3 Hub Interface Action on Immediate Responses to
immediate response indicating some kind of error. Table 627. Split Terminations of Completion Required Cycles to PCI-X (Sheet 2 of Table 628. Hub Interface Response to PCI-X Split Completion Terminations of SERR# Enabled in the primary command register is set.
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18.9.4 Behavior of PCI/PCI-X Initiated Cycles to Hub
18.10 Delayed/Split Transactions
18.10.1 Number Supported
and one delayed/split transaction outbound. Table 629. Terminations of Completion Required Cycles to Hub Interface
- The Intel® 6300ESB ICH only signals Target Abort when the error has been logged from the
- The Intel® 6300ESB ICH issues a Split Completion Error Message with either Master Abort or
Split Completion Error Message.
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18.10.2 Prefetch Algorithm
Since outbound cycles are not prefetched, there is no algorithm. The algorithm for inbound cycles is below. Note that the algorithm changes depending upon whether only one device is requesting or multiple devices are requesting. 18.10.2.1Parameters Parameters based upon the Prefetch Parameter Registers at offset F8h – FFh Ri Initial request size (bits[03:00]) Ti Initial threshold (bits[07:04]) Rs Subsequent request (bits [11:08]) Ts Subsequent threshold (bits[15:12]) D Delay to wait between next Ts (calculated). The value is “Rs:111” clocks. Other Algorithm Parameters Sb Buffer size (either 1K or 2K, depending upon the delayed transaction bit (offset 40h, bit 2)) N Data in buffer + data in flight (requested to SiBUS but not returned) B Data in buffer 18.10.2.2Algorithm (Single Device Only) 1. Establish DT , launch request of size Ri. The actual amount fetched is such that the transfer ends on a naturally aligned 128-byte line. When the initial address is less than 64-bytes into the 128-byte line, the Ri value is rounded down (i.e., eight 64- byte lines become seven 64-byte lines + remainder). When the initial address is more than 64-bytes into the 128-byte line, the Ri value is rounded up (i.e., eight 64-byte lines become nine 64-byte lines + remainder). Example 1: Address starts at 32 bytes into a 128-byte line, and the fetch length is 4*64 byte lines (256 bytes). The amount fetched is 256 - 32 = 224 bytes (56 dWords). Example 2: Address starts at 96 bytes into a 128-byte line, and the fetch length is 4*64-byte lines (256 bytes). The amount fetched is 256 + (128 - 96) = 288 bytes (72 dWords). 2. Wait until at least some data has returned and master has reconnected. In PCI mode, this is when the first qWord becomes available. In PCI-X, when not running in 133 MHz mode, or running in 133 MHz mode but the request size is less than or equal to 256 bytes, this is when the first ADB becomes available. 3. When N < Ti, launch a request of size Rs (truncated by Sb, when necessary). Start Timer when there are not more active delayed transactions. When there are other active delayed transactions, go to step 5. 4. Check for size B vs. Ts When B < Ts, wait for timer to expire before launch of size Rs. Restart timer. Go to Step 4. When B > Ts before timer expires, reset timer . Go to Step 5.
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- Wait for B < Ts; launch request of size Rs (truncated by Sb, when necessary). Restart timer . Go to step 4.
18.10.3 Algorithm (Multiple PCI-X Devices Requesting)
When multiple agents are requesting in PCI-X mode, the definition of T S changes. Instead of just indicating data in buffer , it becomes like TI, and represents data in buffer plus data in flight. When multiple agents are requesting in PCI-X mode, the Intel ® 6300ESB ICH needs to switch between these agents for completions. It does this by utilizing its MLT parameter. When the MLT expires, it stops this stream and switches to another stream. Differences from P64H algorithm:
- No connect threshold: as soon as the first data is available in the DT buffer, a PCI device is allowed to connect.
- Allows multiple outstanding reads per DT buffer, (so long as restrict size of all outstanding reads for a DT buffer to remaining capacity in DT buffer), yielding smaller prefetch overshoot
- Periodic subsequent fetch: smaller, more frequent requests reduce prefetch overshoot
- TI and TS as a low watermark takes into account data in flight; not just data remaining in the DT buffer
- Delayed subsequent launch for multi-stream operation to reduce prefetch overshoot
- First subsequent launch threshold
18.10.4 Accesses From Multiple Agents to Same 4K Page
In order to avoid the need to track the status of the buffers when multiple agents are asking for data from the same 4K page, the Intel ® 6300ESB ICH retries a PCI master when the same PCI master has already established another delayed transaction to that 4K page.
18.11 Internal Bus/Device Communication
Internally, all devices that reside on the “logical PCI bus” are connected to an internal bus called “SiBus” (silicon bus). This is a bus architecture developed within PCG that allows for high code reuse and the ability to connect multiple units together in a standard manner. It is split transaction based. By choosing this micro-architecture, cycles may originate from any agent and be decoded by any other agent. This allows peer-to-peer communication to effectively be free. For this reason, the SM Bus controller is also connected to this bus, allowing PCI configuration cycles that originate either from the Hub Interface or SM Bus to use the same data and control paths to access internal registers. However, this must be monitored carefully by the micro-architecture. Configuration cycles from SM Bus must be allowed to reach their destination, even when the Hub Interface communication to one of the PCI busses is blocked due to a deadlock condition. Therefore, the micro-architecture must ensure the following:
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- All units that have a configuration space that could be accessed by SM Bus have a “1 command only” depth. This helps ensure that multiple requests are not outstanding, minimizing any possibility of SM Bus accesses being stuck.
- The Intel® 6300ESB ICH does not launch successive requests that have the same hub ID/pipe ID on the internal bus, ensuring that no space has to be reserved to re-order the completion data. Only cycles that have a unique hub ID/pipe ID may be launched simultaneously, and their completions may return in any order.
- Any request from SM Bus (or the Hub Interface) that targets the I/OxAPIC must be able to complete, even when the I/OxAPIC has an interrupt to deliver to the Hub Interface. Otherwise, the completion for the SM Bus/Hub Interface access is blocked behind the I/OxAPIC request to the Hub Interface, and it does not finish. System management software must ensure that the SM Bus does not generate accesses PCI. When this occurs and PCI is blocked, the SM Bus is blocked.
18.12 Data Return Behavior of Hub Interface
For all Hub Interface initiated memory read cycles targeting PCI/PCI-X, the Intel ® 6300ESB ICH ensures a return length of a naturally aligned 128-bytes. When a request is less than 128 bytes and within a single 128-byte line, the Intel ® 6300ESB ICH generates one completion. When the request crosses a line, the Intel ® 6300ESB ICH returns multiple completions, broken on 128-byte line boundaries, until the request is fulfilled. The Intel ® 6300ESB ICH does not return a dWord completion on a memory read command that is longer than a dWord and is qWord aligned. The Intel® 6300ESB ICH only generates qWord aligned reads whose length is a multiple number of qWords. The Intel® 6300ESB ICH requires that the completions for these requests be returned as qWords and never dwords. For read streaming to work, the Intel ® 6300ESB ICH requires that the driving agent only disconnect read completions on a cache line boundary (64 or 128 bytes).
18.13 Performance Targets
18.13.1 Introduction
This information is organized into three sections. The first section specifies general bus timings. The second specifies single active master throughputs. The third specifies concurrent performance when multiple agents are generating requests from both busses.
18.13.2 Definitions and Assumptions
Bandwidth tests are sustained throughput tests. The system may be run until it reaches steady state and then run longer with the bandwidth measured. The system under test uses 4x, 8 bit, HL 1.5. Memory bandwidth in the system under test is sufficient to service the requirements of the PCI-X so that contention for memory and other system resources is not a performance bottleneck.
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References to signal timings are stated from the point of view of the bus itself. Internal register timings of the individual devices are not considered. One Megabyte =106 Bytes rather than 220 Bytes.
18.13.3 Active Master Clock Counts
This section specifies clock counts for general bus timings and first word latencies for read requests. Bus timings should be consistent regardless of other system activity. First word latency specifications only apply in situations where contention for system resources does not present a performance bottleneck. First word latency is measured as the number of clocks from the initial assertion of PXFRAME# (this is clock 0) to the first clock on which valid data is returned in response to the request.
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 703 19—Intel ® 6300ESB ICH Serial I/O Unit 19 The SIU is similar to currently available Super I/O controllers. It is specifically designed for integration into the Intel® 6300ESB ICH. It is connected externally through the LPC bus and consists of two UARTS, a Serial Interrupt Controller, Port 60/64 Emulation and the LPC interface.
19.1 Features
- Multiplexed command, address and data bus
- 8-Bit I/O transfers
- 16-Bit address qualification for I/O transactions
- Serial IRQ interface compatible with serialized IRQ support for PCI systems Note: Each SIU port must use a dedicated interrupt. SIU interrupts cannot be shared with each other or with other devices. Serial Port
- Two serial ports Note: The serial ports of the Intel® 6300ESB ICH are not completely compatible with other 16550 standard devices. A system or software designer must follow the specifications laid out in this document above standard 16550 specifications.
- Configurable I/O addresses and interrupts
- 16-Byte FIFOs
- Supports up to 115 Kbps
- Programmable baud rate generator
- Modem control circuitry Port 60/64 Emulation
- Configurable unit disable
- Positive decode for I/O cycles to 60h and 64h
- Read/Write scratchpad registers only (sticky bits)
- Configurable interrupt generation on writes to either register
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19.2 Pin Description
19.2.1 Universal Asynchronous Receive And Transmit
Figure 32. SIU Block Diagram Table 630. Universal Asynchronous Receive And Transmit (UART0, UART1) generation logic of each UART in the SIU. device pin to the receive port. pins will be set to MARKING condition (logic ‘1’ state).
exchanged between the Intel® 6300ESB ICH and external interface. These pins have no effect on the transmitter. Status Interrupt is enabled. input has changed state since the previous reading of the MSR. Status Interrupt is enabled. ‘1’). LOOP mode operation holds this signal in its inactive state. ‘1’). LOOP mode operation holds this signal in its inactive state.
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19.3 Functional Description
19.3.1 Host Processor Interface (LPC)
a series of read/write registers and accomplished through I/O cycles or DMA transfers. Configuration Register 07H (SCR7). See Table 631.
19.4 LPC Interface
Interface Specification, Rev 1.0.
19.4.1 LPC Cycles
The following cycle types are supported by the LPC protocol. The SIU ignores cycles that it does not support.
19.4.1.1 I/O Read and Write Cycles
FIFO accesses and will generally have minimal Sync times. 32-bit transfer, the host must break it up into 8-bit transfers. Table 631. Address Map Table 632. Supported LPC Cycle Types
19.4.2 Reset Policy
- The SIU reset (active low) is internally tied to the PCI bus reset.
- When the SIU reset goes active (low): — The host drives the LFRAME# signal high, tristates the LAD[3:0] signals, and ignores the LDRQ# signal. — The SIU ignores LFRAME#, tristates the LAD[3:0] pins and drives the SIU’s LDRQ# signal inactive (high). Note: LPC bus signals from SIU are tied to primary LPC interface external to the Intel ® 6300ESB ICH device. Host LPC and SIU LPC names are used interchangeably throughout.
19.4.3 LPC Transfers
19.4.3.1 I/O Transfers
larger data transfers into 8 bit cycles.
19.5 Logical Device 4 and 5: Serial Ports (UARTs)
with the only difference being the Logical Device Number assigned to each.
19.5.1 Overview
UART including hardware flow control interface. error conditions (parity, overrun, framing, or break interrupt). Table 633. I/O Sync Bits Description 0000 Sync Achieved with no error. 0101 Indicates that Sync not Achieved yet, but the part is driving the bus.
0110 Indicates that Sync not Achieved yet, but the part is driving the bus, and expect
1010 Special Case: Peripheral indicating errors.
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16-byte Receive FIFO buffers data from the serial link until read by the processor. of the baud rate generator is 16 times the baud rate.
19.5.1.1 UART Feature List
- Adds or deletes standard asynchronous communications bits (start, stop, and parity) to or from the serial data
- Independently controlled transmit, receive, line status and data set interrupts
- Programmable baud rate generator allows division of clock by 1 to (2 16 -1) and generates an internal 16X clock
- Modem control functions (CTS#, RTS#, DSR#, DTR#, RI#, and DCD#)
- Fully programmable serial-interface characteristics:
Table 634. UART Clock Divider Support frequency. An option will be to use the 48.0 MHz clock. Table 635. Baud Rate Examples
- 5, 6, 7 or 8-bit characters
- Even, odd, or no parity detection
- 1, 1-1/2, or 2 stop bit generation
- Baud rate generation (up to 115kbps)
- False start bit detection
- 16-byte Receive FIFO
- Complete status reporting capability
- Line break generation and detection
- Internal diagnostic capabilities include:
- Loopback controls for communications link fault isolation — Break, parity, overrun, and framing error simulation — Fully prioritized interrupt system controls
19.5.1.2 UART Operational Description
The format of a UART data frame is shown in Figure 33. data byte, or if odd parity is enabled and the data byte contains an even number of ’1’s. user, which is represented by one or two successive bit periods of a logic ’1’. receiving a byte and stops transmitting/receiving more data. Figure 33. Example UART Data Frame Receive data sample counter frequency = 16x bit frequency, each bit is sampled three times in the middle. Shaded bits are optional and may be programmed by users.
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19.5.1.3 Internal Register Descriptions
Baud Rate Generator Divisor Latches. Table 636. SIU Signal Reset States Interrupt Enable Register RESET All bits are low. low. Bits 4-5 are permanently low. Line Control Register RESET All bits are forced low. Table 637. Internal Register Descriptions
19.5.1.3.1 Receive Buffer Register (RBR)
19.5.1.3.2 Transmit Holding Register (THR)
of the FIFO is loaded to the shift register when it is empty.
19.5.1.3.3 Interrupt Enable Register (IER)
receive FIFO at the same time. Note: The use of bit 4 and 5 is different from the register definition of standard 16550. Table 638. Receive Buffer Register (RBR) 7:0 RB[7:0] Data byte received, least significant bit first. Table 639. Transmit Holding Register (THR) 7:0 TB[7:0] Data byte transmitted, least significant bit first.
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19.5.1.3.4 Interrupt Identification Register (IIR)
Table 640. Interrupt Enable Register (IER) 0 = Bit 0 of this register also controls RTOIE and bit 4 is RSVD. 1 = Bit 4 of this register controls RTOIE. of the 16550. The 16550 has this bit always set to 0. 0 = Receiver data Time out interrupt disabled. 1 = Receiver data Time out interrupt enabled. of the 16550. The 16550 has this bit always set to 0. 0 = Modem Status interrupt disabled. 1 = Modem Status interrupt enabled. 0 = Receiver Line Status interrupt disabled. 1 = Receiver Line Status interrupt enabled. 0 = Transmit FIFO Data Request interrupt disabled. 1 = Transmit FIFO Data Request interrupt enabled. When BIT 5 = ’0’ the following additional functionality is used. 0 = Receiver data Time Out Interrupt also disabled. 1 = Receiver data Time Out Interrupt enabled.
Table 641. Interrupt Conditions 1 (highest) Receiver Line Status: One or more error bits were set. the receive FIFO but no activity for a time period. half empty; in non-FIFO mode, THR is read already. 4 Modem Status: One or more of the modem input signals has changed state. Table 642. Interrupt Identification Register (IIR) 00 = Non-FIFO mode is selected. 11 = FIFO mode is selected (TRFIFOE = 1).
3 TOD
0 = No time out interrupt is pending. 01 = Transmit FIFO requests data. 1 = No interrupt is pending.
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19.5.1.3.5 FIFO Control Register (FCR)
transmitter/receiver FIFOs, and sets the receiver FIFO trigger level. Note: The use of bit 6 and 7 is different from the register definition of standard 16550. Table 643. Interrupt Identification Register Decode Framing Error, Break Interrupt. Reading the Line Status Register. setting RESETRF bit in FCR register. the Transmit Holding Register. Table 644. FIFO Control Register (FCR) (Sheet 1 of 2) 00 = 1 byte or more in FIFO causes interrupt (same as 16550).
19.5.1.3.6 Line Control Register (LCR)
2 RESETTF
RESETTF is automatically reset to 0. 0 = Writing ’0’ has no effect. clearing, bit is automatically reset to 0.
1 RESETRF
0 = Writing ’0’ has no effect. clearing, bit is automatically reset to 0. written or the other bits are not programmed. Table 644. FIFO Control Register (FCR) (Sheet 2 of 2)
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Table 645. Line Control Register (LCR) (Sheet 1 of 2) Transmit Holding Register, or the Interrupt Enable Register. Register (RBR) and Interrupt Enable Register.
- Load 00H in the Transmit Holding register in response to a TDRQ interrupt
- After TDRQ goes high (indicating that 00H is being shifted out), set the break bit before the parity or stop bits reach the TXD pin
- Wait for the transmitter to be idle (TEMT = 1) and clear the break bit when normal transmission has to be restored During the break, the transmitter may be used as a character timer to accurately establish the break duration. In FIFO mode, wait for the transmitter to be idle (TEMT=1) to set and clear the break bit. 0 = No effect on TXD output. 1 = Forces TXD output to ’0’ (space). 5S T K Y P Sticky Parity: This bit is the “sticky parity” bit, which may be used in multiprocessor communications. When PEN and STKYP are logic 1, the bit that is transmitted in the parity bit location (the bit just before the stop bit) is the complement of the EPS bit. If EPS is 0, the bit at the parity bit location will be transmitted as a 1. In the receiver, if STKYP and PEN are 1, the receiver compares the bit that is received in the parity bit location with the complement of the EPS bit. If the values being compared are not equal, the receiver sets the Parity Error bit in LSR and causes an error interrupt if line status interrupts were enabled. For example, if EPS is 0, the receiver expects the bit received at the parity bit location to be 1. If it is not, then the parity error bit is set. By forcing the bit value at the parity bit location, rather than calculating a parity value, a system with a master transmitter and multiple receivers may identify some transmitted characters as receiver addresses and the rest of the characters as data. If PEN = 0, STKYP is ignored. 0 = No effect on parity bit. 1 = Forces parity bit to be opposite of EPS bit value.
19.5.1.3.7 Line Status Register (LSR)
bits contain information about the receiver . mode, these three bits of status are stored with each received character in the FIFO. when any of the corresponding conditions are detected and the interrupt is enabled. is transmitted or checked in the data word bits and the parity bit. parity bit. If PEN = 0, EPS is ignored. 0 = Sends or checks for odd parity. 1 = Sends or checks for even parity. 1 = Allows parity generation and checking. regardless of the number of stop bits selected. Table 645. Line Control Register (LCR) (Sheet 2 of 2)
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previous bytes are read and the erroneous byte is moved to the top of the FIFO. Table 646. Line Status Register (LSR) (Sheet 1 of 2) read from the FIFO. FIFOE set to ’1’ does not generate interrupt. 0 = No FIFO or no errors in receiver FIFO. 1 = At least one character in receiver FIFO has errors. register or the transmitter shift register contains a data character. the Transmit Shift register are both empty. the FIFO, the excess characters are lost. 0 = Processor has loaded the Transmit Holding Register. 0 = No break signal has been received.
19.5.1.3.8 Modem Control Register (MCR)
1 = Invalid stop bit has been detected. 1 = Parity error has occurred. when the processor reads the Line Status register. 1 = Received data has been lost. RBR) or the RESETRF bit is set in FCR. 0 = No data has been received. 1 = Data is available in RBR or the FIFO. Table 646. Line Status Register (LSR) (Sheet 2 of 2)
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Table 647. Modem Control Register (MCR) (Sheet 1 of 2)
- Coming out of the loopback test mode may result in unpredictable activation of the delta bits (bits 3:0) in the Modem Status Register (MSR). It is recommended that MSR be read once to clear the delta bits in the MSR. The lower four bits of the Modem Control register are connected to the upper four Modem Status register bits:
- DTR = ’1’ forces DSR to a '1'
- RTS = ’1’ forces CTS to a '1'
- OUT1 = ’1’ forces RI to a '1'
- OUT2 = ’1’ forces DCD to a '1' In the diagnostic mode, data that is transmitted is immediately received. This feature allows the processor to verify the transmit and receive data paths of the UART. The transmit, receive and modem control interrupts are operational, except the modem control interrupts are activated by Control register bits, not the modem control inputs. A break signal may also be transferred from the transmitter section to the receiver section in loopback mode. 0 = Normal UART operation 1 = Test mode UART operation 3O U T 2 Out2# Signal Control: This bit controls the OUT2# output. When the OUT2 bit is set, OUT2# is asserted low. When the OUT2 bit is cleared, OUT2# is deasserted (set high). Outside of the UART module, the OUT2# signal is used to connect the UART's interrupt output to the Interrupt Controller unit. 0 = OUT2# signal is '1' , which disables the UART interrupt. 1 = OUT2# signal is ‘0’. 2O U T 1 Test Bit: This bit is used only in Loopback test mode. See (LOOP) Above. 1R T S Request To Send: This bit controls the Request to Send (RTS#) output pin. Bit ’1’ affects the RTS# output in a manner identical to that described below for the DTR bit. 0 = RTS# pin is 1 1 = RTS# pin is 0
19.5.1.3.9 Modem Status Register (MSR)
of the Interrupt Enable Register is set. output pin is forced to a logic ‘1’.
- The DTR# output of the UART may be applied to an EIA inverting line driver (such as the DS1488) to obtain the proper polarity input at the succeeding modem or data set. 0 = DTR# pin is 1 1 = DTR# pin is 0
Table 647. Modem Control Register (MCR) (Sheet 2 of 2) Table 648. Modem Status Register (MSR) (Sheet 1 of 2) of the Modem Control register if LOOP in the MCR is set to 1. Modem Control register if LOOP in the MCR is set to 1. Modem Control register if LOOP in the MCR is set to 1. Modem Control register if LOOP in the MCR is set to 1. 0 = No change in DCD# pin since last read of MSR. 1 = DCD# pin has changed state.
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register for use by the programmer. on initial load. Access to the Divisor latch may be done with a word write. For example, if UART_CLK is 14.7456MHz and the divisor is 96, the baud rate is 9600. 1 = RI# pin has changed from ’0’ to 1. 0 = No change in DSR# pin since last read of MSR. 1 = DSR# pin has changed state. 0 = No change in CTS# pin since last read of MSR. 1 = CTS# pin has changed state. Table 648. Modem Status Register (MSR) (Sheet 2 of 2) Table 649. Scratch Pad Register (SCR) Table 650. Divisor Latch Register Low (DLL)
19.5.1.4 FIFO Operation
19.5.1.4.1 FIFO Interrupt Mode Operation
- The receive data available interrupt is invoked when the FIFO has reached its programmed trigger level. The interrupt is cleared when the FIFO drops below the programmed trigger level.
- The IIR receive data available indication also occurs when the FIFO trigger level is reached, and like the interrupt, the bits are cleared when the FIFO drops below the trigger level.
- The receiver line status interrupt (IIR = C6H), as before, has the highest priority. The receiver data available interrupt (IIR=C4H) is lower. The line status interrupt occurs only when the character at the top of the FIFO has errors.
- The data ready bit (DR in LSR register) is set to ’1’ as soon as a character is transferred from the shift register to the Receive FIFO. This bit is reset to ’0’ when the FIFO is empty. Character Timeout Interrupt When the receiver FIFO and receiver time out interrupt are enabled, a character timeout interrupt occurs when all of the following conditions exist:
- At least one character is in the FIFO.
- The last received character was longer than four continuous character times ago (if 2 stop bits are programmed the second one is included in this time delay).
- The most recent processor read of the FIFO was longer than four continuous character times ago.
- The receiver FIFO trigger level is greater than one. The maximum time between a received character and a timeout interrupt is 160 ms at 300 baud with a 12-bit receive character (i.e., 1 start, 8 data, 1 parity, and 2 stop bits). When a time out interrupt occurs, it is cleared and the timer is reset when the processor reads one character from the receiver FIFO. If a timeout interrupt has not occurred, the timeout timer is reset after a new character is received or after the processor reads the receiver FIFO. Transmit Interrupt When the transmitter FIFO and transmitter interrupt are enabled (FCR[0]=1, IER[1]=1), transmit interrupts occur as follows:
- The Transmit Data Request interrupt occurs when the transmit FIFO is half empty or more than half empty. The interrupt is cleared as soon as the Transmit Holding
Table 651. Divisor Latch Register High (DLH)
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Register is written (1 to 16 characters may be written to the transmit FIFO while servicing the interrupt) or the IIR is read.
19.5.1.4.2 FIFO Polled Mode Operation
With the FIFOs enabled (TRFIFOE bit of FCR set to 1), setting IER[3:0] to all zeros puts the serial port in the FIFO polled mode of operation. Since the receiver and the transmitter are controlled separately, either one or both may be in the polled mode of operation. In this mode, software checks receiver and transmitter status through the LSR. As stated in the register description:
- LSR[0] is set as long as there is one byte in the receiver FIFO.
- LSR[1] through LSR[4] specify which error(s) has occurred for the character at the top of the FIFO. Character error status is handled the same way as interrupt mode. The IIR is not affected since IER[2] = 0.
- LSR[5] indicates when the transmitter FIFO needs data.
- LSR[6] indicates that both the transmitter FIFO and shift register are empty.
- LSR[7] indicates whether there are any errors in the receiver FIFO.
19.6 Logical Device 7 (07H): Port 60/64
This section describes the Port 60/64 Emulation integrated into the SIU.
19.6.1 Feature List
- Configurable unit disable
- Positive decode for I/O cycles to 60h and 64h
- Read/Write Scratchpad Registers Only (sticky bits)
- Interrupt on write and self-interrupt clearing
19.6.2 Overview
The Port 60/64 Emulation Unit consists of two 8-bit I/O registers intended to preserve values written to Port 60 and 64 thus emulating a legacy 8042 device formerly at this legacy I/O address space. These registers may be enabled by BIOS typically in a pre- OS environment and may be disabled during run time. These registers may be used for 8042 keyboard controller emulation but in no way support any controller or functionality beyond a scratchpad register and interrupt generation on writes. When enabled, this Device will positively decode 8-bit I/O accesses to address 60h and 64h. Writes to these addresses may generate an interrupt as configured in the Logical Device 07 Primary Interrupt Register (70h). The interrupt generated from this unit will drive active (drives a logical 0) for one SIRQ frame. It does not require any further action (i.e., no EOI required or status bit to clear).
19.6.2.1 Port 60H Emulation (SCR60)
19.6.2.2 Port 64H Emulation (SCR64)
19.7 SERIAL IRQ
system. The serial interrupt scheme adheres to the Serial IRQ Specification.
19.7.1 Timing Diagrams For SIU_SERIRQ Cycle
Table 652. Scratch Pad Register P60 (SCR60) Table 653. Scratch Pad Register P64 (SCR64) Figure 34. Start Frame Timing with Source Sampled a Low Pulse on IRQ1
- H=Host Control; R=Recovery; T=Turn-Around; SL=Slave Control; S=Sample
- Start Frame pulse may be 4-8 clocks wide depending on the location of the device in the PCI
bridge hierarchy in a synchronous bridge design.
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19.7.1.1 SIU_SERIRQ Cycle Control
There are two modes of operation for the SIU_SERIRQ Start Frame.
- Quiet (Active) Mode: Any device may initiate a Start Frame by driving the
be Idle when there are no IRQ/Data transitions which should be most of the time.
- Continuous (Idle) Mode: Only the Host controller may initiate a Start Frame to
continuous mode by initiating a Start Frame at the end of every Stop Frame. An SIU_SERIRQ mode transition may only occur during the Stop Frame. Frames pulse width to determine the next SIU_SERIRQ Cycle’s mode. each other or with other devices. Figure 35. Stop Frame Timing with Host Using 17 SIU_SERIRQ Sampling Period
- H=Host Control; R=Recovery; T=Turn-Around; S=Sample; I=Idle
- Stop pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous mode.
- There may be none, one or more Idle states during the Stop Frame.
- The next SIU_SERIRQ cycle’s Start Frame pulse may or may not start immediately after the
turn-around clock of the Stop Frame.
19.7.1.2 SIU_SERIRQ Data Frame
regardless of which device initiated the Start Frame. after the rising edge of the Start Pulse). SIU_SERIRQ Period 13 is used to transfer IRQ12.
19.7.1.3 Stop Cycle Control
second clock or more after the rising edge of the Stop Frame’s pulse. Table 654. SIU_SERIRQ Sampling Periods
13 IRQ12 38
14 IRQ13 41
15 IRQ14 44
16 IRQ15 47
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19.7.1.4 Latency
Latency for IRQ/Data updates over the SIU_SERIRQ bus in bridge-less systems with the minimum Host supported IRQ/Data Frames of seventeen, will range up to 96 clocks (2.88 µs with a 33MHz PCI Bus). If one or more PCI to PCI Bridge is added to a system, the latency for IRQ/Data updates from the secondary or tertiary buses will be a few clocks longer for synchronous buses, and approximately double for asynchronous buses.
19.7.1.5 EOI/ISR Read Latency
Any serialized IRQ scheme has a potential implementation issue related to IRQ latency. IRQ latency could cause an EOI or ISR Read to precede an IRQ transition that it should have followed. This could cause a system fault. The host interrupt controller is responsible for ensuring that these latency issues are mitigated. The recommended solution is to delay EOIs and ISR Reads to the interrupt controller by the same amount as the SIU_SERIRQ Cycle latency in order to ensure that these events do not occur out of order.
19.7.1.6 Reset and Initialization
The SIU_SERIRQ bus uses SIU_LRESET# as its reset signal. The SIU_SERIRQ pin is tri- stated by all agents while SIU_LRESET# is active. With reset, SIU_SERIRQ Slaves are put into the (continuous) IDLE mode. The Host Controller is responsible for starting the initial SIU_SERIRQ Cycle to collect system’s IRQ/Data default values. The system then follows with the Continuous/Quiet mode protocol (Stop Frame pulse width) for subsequent SIU_SERIRQ Cycles. It is Host Controller’s responsibility to provide the default values to the Interrupt controller and other system logic before the first SIU_SERIRQ Cycle is performed. For SIU_SERIRQ system suspend, insertion, or removal application, the Host controller should be programmed into Continuous (IDLE) mode first. This is to ensure that the SIU_SERIRQ bus is in IDLE state before the system configuration changes.
19.8 Configuration
The Configuration of the SIU is very flexible and is based on the configuration architecture implemented in typical Plug-and-Play components. The SIU is designed for motherboard applications in which the resources required by their components are known. With its flexible resource allocation architecture, the SIU allows the BIOS to assign resources at POST.
19.8.1 Configuration Port Address Selection
The SIU configuration port addresses for INDEX and DATA are fixed at 4Eh/4Fh. See also Section 8.1.31, “Offset E6h - E7h: LPC_EN—LPC I/F Enables (LPC I/F— D31:F0)” on page 337.
19.8.2 Primary Configuration Address Decoder
After a PCI Reset (SIU_LRESET# pin asserted) or Power On Reset the SIU is in the Run Mode with the two UARTs disabled. They may be configured through two standard Configuration I/O Ports (INDEX and DATA) by placing the SIU into Configuration Mode.
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 729 19—Intel ® 6300ESB ICH The BIOS uses these configuration ports to initialize the logical devices at POST. The INDEX and DATA ports are only valid when the SIU is in Configuration Mode. The INDEX and DATA ports are effective only when the chip is in the Configuration State. When the SIU is not in the Configuration State, reads return FFh and write data is ignored.
19.8.2.1 Entering the Configuration State
The device enters the Configuration State by the following contiguous sequence: Write 80H to Configuration Port. Write 86H to Configuration Port.
19.8.2.2 Exiting the Configuration State
The device exits the Configuration State by the following contiguous sequence: Write 68H to Configuration Port. Write 08H to Configuration Port.
19.8.2.3 Configuration Sequence
To program the configuration registers, the following sequence must be followed: 1. Enter Configuration Mode. 2. Configure the Configuration Registers. 3. Exit Configuration Mode.
19.8.2.4 Configuration Mode
The system sets the logical device information and activates desired logical devices through the INDEX and DATA ports. In configuration mode, the INDEX PORT is located at the CONFIG PORT address and the DATA PORT is at INDEX PORT address + 1. The desired configuration registers are accessed in two steps: 1. Write the index of the Logical Device Number Configuration Register (i.e., 07) to the INDEX PORT and then write the number of the desired logical device to the DATA PORT. 2. Write the address of the desired configuration register within the logical device to the INDEX PORT and then write or read the configuration register through the DATA PORT. Note: If accessing the Global Configuration Registers, step (a) is not required. 3. The chip returns to the RUN State. Note: Only two states are defined: Run and Configuration. In the Run State, the chip will always be ready to enter the Configuration State.
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19.8.3 SIU Configuration Registers Summary
Table 655. Configuration Registers Summary
19.8.3.1 Global Control/Configuration Registers [00h — 2Fh]
and bits ignore writes and return ’0’ when read.
19.8.3.2 Logical Device Configuration Registers [30h — FFh]
for each logical device and is selected with the Logical Device # Register . then accessed through the DATA PORT. State. The logical register addresses are shown in Table 657 through Table 659. Table 656. Global Control Registers configuration registers for each logical device.
00 Divide by 1
01 Divide by 8
10 Divide by 26
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Table 657. Logical Device 4 (Serial Port 0) Bits[7:1] Reserved, set to ’0’. the Logical Device # register. NOTE: Each SIU port must use a dedicated interrupt.
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Table 658. Logical Device 5 (Serial Port 1) Bits[7:1] Reserved, set to ’0’. the Logical Device # register. NOTE: Decode is on 8 Byte boundaries. NOTE: Each SIU port must use a dedicated interrupt.
Table 659. Logical Device 7 (Port Emulation)
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Bits[7:1] Reserved, set to ’0’. the Logical Device # register. 0 = Logical device currently selected is inactive. captured by the single value of 60h in this space.
20.1 PCI Configuration Registers (SATA–D31:F2)
Note: Registers that are not shown should be treated as reserved. All of the SATA registers are in the core well. They can never be locked. Table 660. PCI Configuration Map (SATA–D31:F2) (Sheet 1 of 2)
- The Intel® 6300ESB ICH SATA Controller is not arbitrated as a PCI device, therefore it does not need a
- Refer to the Intel® 6300ESB I/O Controller Hub Specification Update for the most up-to-date value of the
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20.1.1 Offset 00 - 01h: VID—Vendor ID Register (SATA—
Table 661. Offset 00 - 01h: VID—Vendor ID Register (SATA—D31:F2) Table 660. PCI Configuration Map (SATA–D31:F2) (Sheet 2 of 2)
- The Intel® 6300ESB ICH SATA Controller is not arbitrated as a PCI device, therefore it does not need a
- Refer to the Intel® 6300ESB I/O Controller Hub Specification Update for the most up-to-date value of the
20.1.2 Offset 02 - 03h: DID—Device ID Register (SATA—
20.1.3 Offset 04h - 05h: CMD—Command Register
Table 662. Offset 02 - 03h: DID—Device ID Register (SATA—D31:F2) Indicates what device number was assigned by the PCI SIG. Table 663. Offset 04h - 05h: CMD—Command Register (SATA–D31:F2) (Sheet
10 Interrupt Disable
a data parity error is detected. data parity error is detected.
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the generation of completions for split transaction commands. This bit controls access to the I/O space registers.
Table 664. Offset 06 - 07h: STS—Device Status Register (SATA–D31:F2) 0 = No Parity error detected by SATA controller. and bit 6 of the Command register is set to 1. Software clears this bit by writing a ‘1’ to this bit location. 0 = 0 Cleared by writing a ’1’ to it.
12 Received Target-Abort
read completions when there is a parity error.
4 Capabilities List (CL)
capabilities pointer at offset 34h.
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20.1.5 Offset 09h: PI—Programming Interface (SATA–
20.1.6 Offset 0Ah: SCC—Sub Class Code (SATA–D31:F2)
Table 665. Offset 09h: PI—Programming Interface (SATA–D31:F2)
7 This read-only bit is a ’1’ to indicate that the SATA Controller
6:4 Reserved Reserved. Will always return 0. IDE channel is operating in.
1 POP_MODE_CAP This read-only bit is a ’1’ to indicate that the primary
0 POP_MODE_SEL
IDE channel is operating in. Table 666. Offset 0Ah: SCC—Sub Class Code (SATA–D31:F2)
20.1.7 Offset 0Bh: BCC—Base Class Code (SATA–D31:F2)
20.1.8 Offset 0Dh: MLT—Master Latency Timer (SATA–
Table 667. Offset 0Bh: BCC—Base Class Code (SATA–D31:F2) Table 668. Offset 0Dh: MLT—Master Latency Timer (SATA–D31:F2) need a Master Latency Timer.
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20.1.9 Offset 10h - 13h: PCMD_BAR—Primary Command
20.1.10 Offset 14h - 17h: PCNL_BAR—Primary Control
Note: This 4-byte I/O space is used in native mode for the Primary Controller’s Control Block. Table 669. Offset 10h - 13h: PCMD_BAR—Primary Command Block Base Table 670. Offset 14h - 17h: PCNL_BAR—Primary Control Block Base Address
20.1.11 Offset 18h - 1Bh: SCMD_BAR—Secondary
20.1.12 Offset 14h - 17h: SCNL_BAR—Secondary Control
Table 671. Offset 18h - 1Bh: SCMD_BAR—Secondary Command Block Base Table 672. Offset 14h - 17h: SCNL_BAR—Secondary Control Block Base
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20.1.13 Offset 20h - 23h: BAR—Legacy Bus Master Base
are used to decode the address.
20.1.14 Offset 2Ch - 2Dh: SVID—Subsystem Vendor ID
Table 673. Offset 20h - 23h: BAR—Legacy Bus Master Base Address Register Table 674. Offset 2Ch - 2Dh: SVID—Subsystem Vendor ID (SATA–D31:F2) read, but subsequent writes to this register have no effect.
20.1.15 Offset 2Eh - 2Fh: SID—Subsystem ID (SATA–
20.1.16 Offset 34h: CAP—Capabilities Pointer Register
20.1.17 Offset 3Ch: INTR_LN—Interrupt Line Register
Table 675. Offset 2Eh - 2Fh: SID—Subsystem ID (SATA–D31:F2) registers for the USB#1, USB#2 and SMBus functions. Table 676. Offset 34h: CAP—Capabilities Pointer Register (SATA–D31:F2) Table 677. Offset 3Ch: INTR_LN—Interrupt Line Register (SATA–D31:F2)
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20.1.18 Offset 3Dh: INTR_PN—Interrupt Pin Register
20.1.19 Offset 40 - 41h: IDE_TIMP—Primary IDE Timing
transfers. It also controls operation of the buffer for PIO transfers. Table 678. Offset 3Dh: INTR_PN—Interrupt Pin Register (SATA–D31:F2) Table 679. Offset 40 - 41h: IDE_TIMP—Primary IDE Timing Register (SATA– Individually enable/disable the Primary or Secondary decode. 0 = Use bits 13:12, 9:8 for both drive 0 and drive 1.
IOR#/IOW# strobe of the next cycle. 0 = Disable IORDY sampling for this drive. 0 = Disable IORDY sampling is disabled for this drive. IORDY sample point, and bits 9:8 for the recovery time.
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20.1.20 IDE_TIMS—Secondary IDE Timing Register
20.1.21 Offset 44h: SIDETIM—Slave IDE Timing Register
Table 680. Offset 44h: SIDETIM—Slave IDE Timing Register (SATA–D31:F2) register for secondary is set. of the IDE timing register for secondary is set. of the IDE timing register for primary is set.
20.1.22 Offset 48h: SDMA_CNT—Synchronous DMA
Table 681. Offset 48h: SDMA_CNT—Synchronous DMA Control Register (SATA–
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20.1.23 Offset 4A - 4Bh: SDMA_TIM—Synchronous DMA
Table 682. Offset 4A - 4Bh: SDMA_TIM—Synchronous DMA Timing Register
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20.1.24 Offset 54h: IDE_CONFIG—IDE I/O Configuration
Table 683. Offset 54h: IDE_CONFIG—IDE I/O Configuration Register (SATA–
0 Scratchpad (SP2) The Intel® 6300ESB ICH does not perform any actions on
disable Ultra ATA/100 timings for the Secondary Slave drive. drive (overrides bit 3 in this register). disable Ultra ATA/100 timings for the Secondary Master drive. drive (overrides bit 2 in this register). disable Ultra ATA/100 timings for the Primary Slave drive. 0 = Disable Ultra ATA/100 timing for the Primary Slave drive. (overrides bit ’1’ in this register). disable Ultra ATA/100 timings for the Primary Master drive. (overrides bit ’0’ in this register).
3 SCB1: Secondary Drive
1 Base Clock
0 = 33 MHz base clock for Ultra ATA timings.
20.1.25 Offset 70 - 71h: PID—PCI Power Management
20.1.26 Offset 72 - 73h: PC—PCI Power Management
2 SCBO: Secondary Drive
0 Base Clock
0 = 33 MHz base clock for Ultra ATA timings.
1 PCB1: Primary Drive 1
0 = 33 MHz base clock for Ultra ATA timings.
0 PCB0: Primary Drive 0
0 = 33 MHz base clock for Ultra ATA timings. Table 684. Offset 70 - 71h: PID—PCI Power Management Capability ID (SATA– 7:0 Cap ID (CID) Indicates that this pointer is a PCI power management. Table 685. Offset 72 - 73h: PC—PCI Power Management Capabilities (SATA–
10 D2_Support The D2 state is not supported
9 D1_Support The D1 state is not supported
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20.1.27 Offset 74 - 75h: PMCS—PCI Power Management
ization (DSI) Indicates that no device-specific initialization is required. 3 PME Clock (PMEC) Indicates that PCI clock is not required to generate PME#. Table 686. Offset 74 - 75h: PMCS—PCI Power Management Control and Status 15 PME Status (PMES) Reserved as ‘0’. 8 PME Enable (PMEE). Reserved as ‘0’. is available, but the I/O and memory spaces are not. Additionally, interrupts are blocked.
20.1.28 Offset 80 - 81h: MID—Message Signaled Interrupt
20.1.29 Offset 82 - 83h: MC—Message Signaled Interrupt
Table 687. Offset 80 - 81h: MID—Message Signaled Interrupt Identifiers 7:0 Capability ID (CID) Capability ID indicates MSI. Table 688. Offset 82 - 83h: MC—Message Signaled Interrupt Message Control
0 MSI Enable (MSIE)
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20.1.30 Offset 84 - 87h: MA—Message Signaled Interrupt
Table 689. Offset 84 - 87h: MA—Message Signaled Interrupt Message Address
20.1.31 Offset 88 - 89h: MD—Message Signaled Interrupt
20.1.32 Offset 90h: MAP—Address Map (SATA–D31:F2)
Table 690. Offset 88 - 89h: MD—Message Signaled Interrupt Message Data Table 691. Offset 90h: MAP—Address Map (SATA–D31:F2) 100 = Combined. P0 is primary master. P1 is primary slave. 101 = Combined. P0 is primary slave. P1 is primary master. 110 = Combined. P-ATA is primary. P0 is secondary master.
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20.1.33 Offset 92h: PCS—Port Status and Control (SATA–
20.1.34 Offset A0h: SRI—SATA Registers Index (SATA–
Table 692. Offset 92h: PCS—Port Status and Control (SATA–D31:F2) on, partial, and slumber states and may detect devices. on, partial, and slumber states and may detect devices. Table 693. Offset A0h: SRI—SATA Registers Index (SATA–D31:F2)
20.1.35 Offset A4h - A7h: SRD—SATA Registers Data
Table 694. Offset A4h - A7h: SRD—SATA Registers Data (SATA–D31:F2)
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20.1.36 STTT—SATA TX Termination Test Register A
20.1.37 STOT — SATA TX Output Test Register (SATA–
Table 695. STTT—SATA TX Termination Test Register A (SATA–D31:F2)
1 Port 1 TX Termination
0 Port 0 TX Termination
Table 696. STOT — SATA TX Output Test Register (SATA–D31:F2) used for system board testing.
20.1.38 Offset Index 54h - 57h: SER0—SATA SError
20.1.39 Offset Index 64h - 67h: SER1—SATA SError
20.1.40 Offset E0h - E3h: BFCS—BIST FIS Control/Status
Table 697. Offset Index 54h - 57h: SER0—SATA SError Register Port 0 (SATA– Table 698. Offset Index 64h - 67h: SER1—SATA SError Register Port 1 (SATA– Table 699. Offset E0h - E3h: BFCS—BIST FIS Control/Status Register (SATA–
764 Order Number: 300641-004US
11 BIST FIS Successful
0 = Software clears this bit by writing a ’1’ to it.
10 BIST FIS Failed (BFF)
0 = Software clears this bit by writing a ’1’ to it.
9 Port 1 BIST FIS Initiate
8 Port 0 BIST FIS Initiate
20.1.41 Offset E4h - E7h: BFTD1—BIST FIS Transmit
Table 700. Offset E4h - E7h: BFTD1—BIST FIS Transmit Data1 Register (SATA– will be used for BIST FIS initiated on port 0 or port 1. not the ‘T’ bit is indicated in the BFCS register.
20.1.42 Offset E8h - EBh: BFTD2—BIST FIS
20.2 Bus Master IDE I/O Registers (D31:F2)
master IDE I/O space registers may be accessed as byte, word, or DWORD quantities. registers is shown below in Table 702. Table 701. Offset E8h - EBh: BFTD2—BIST FIS Transmit Data2 Register (SATA– will be used for BIST FIS initiated on port 0 or port 1. not the ‘T’ bit is indicated in the BFCS register. Table 702. Bus Master IDE I/O Registers
01 Reserved RO
03 Reserved RO
09 Reserved RO
20.2.1 BMIC[P,S]—Bus Master IDE Command Register
Table 703. BMIC[P,S]—Bus Master IDE Command Register (D31:F2) 7:4 Reserved Reserved. Returns ’0’. must NOT be changed when the bus master function is active. 2:1 Reserved Reserved. Returns ’0’. 0 = All state information is lost when this bit is cleared. not clear this bit automatically.
768 Order Number: 300641-004US
20.2.2 BMIS[P,S]—Bus Master IDE Status Register
Table 704. BMIS[P,S]—Bus Master IDE Status Register (D31:F2)
7 PRD Interrupt Status
that has its PRD_INT bit set. do not attach BMIDE to the PCI bus. do not attach BMIDE to the PCI bus. 4:3 Reserved Reserved. Returns ’0’. assertion edge is detected on the interrupt line. abort or master abort when transferring data on PCI. bus master command was aborted. written to the Command register.
20.2.3 BMID[P,S]—Bus Master IDE Descriptor Table
Table 705. BMID[P,S]—Bus Master IDE Descriptor Table Pointer Register
Intel® 6300ESB ICH—20 Intel® 6300ESB I/O Controller Hub DS November 2007
770 Order Number: 300641-004US
21.1 Ball Location
Figure 36. Ball Diagram (Top View - Left Side)
772 Order Number: 300641-004US
Figure 37. Ball Diagram (Top View - Right Side)
Figure 38. Mechanical Drawing
Package Information
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 774 Table 706. Signal List (Alphabetical
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 775 GPIO[43] K24 GPIO[56] C22 GPIO[57] D22 HI_STB#/HI_STBF T29 HI_STB/HI_STBS T28 HIREF P24 HIHIHIHI0 P29 HI1 P28 HI2 R29 HI3 R28 HI4 U29 HI5 U28 HI6 T26 HI7 R24 HI8 N29 HI9 N25 HI10 N28 HI11 M28 HICLK T24 HICOMP T27 IGNNE# U24 INIT# W28 INTR Y28 INTRUDER# AG23 IRDY# E3 IRQ[14] AC23 IRQ[15] V23 LAD[0] C15 LAD[1] B15 LAD[2] A15 LAD[3] A14 LDRQ[0]# F14 LDRQ[1]# G14 LFRAME# B14 NC B20 NC B21 NC B13 NC B12 NC A11 NC A12 NC A13 NC A21 NC A22 NC AD13 NC AJ14 NC AJ15 NC D19 NC E13 NC F13 NC F27 NC F28
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 776 PIORDY (/PDRSTB /PWDMARDY#) AF26 PIRQ[A]# E12 PIRQ[B]# A6 PIRQ[C]# A9 PIRQ[D]# B8 PLOCK# J6 PME# AJ8 PWRBTN# AJ10 PWROK AF22 PXACK64# AF4 PXAD[0] AF2 PXAD[1] W7 PXAD[2] V7 PXAD[3] Y4 PXAD[4] AA2 PXAD[5] W8 PXAD[6] Y2 PXAD[7] AA6 PXAD[8] W1 PXAD[9] W2 PXAD[10] AA4 PXAD[11] V2 PXAD[12] V1 PXAD[13] V4 PXAD[14] Y1 PXAD[15] T7 PXAD[16] R1 PXAD[17] P1 PXAD[18] P2 PXAD[19] P5 PXAD[20] N2 PXAD[21] P7 PXAD[22] N1 PXAD[23] N3 PXAD[24] N4 PXAD[25] M1 PXAD[26] M2 PXAD[27] L1 PXAD[28] L3 PXAD[29] M7 PXAD[30] M5 PXAD[31] K2 PXAD[32] AF1 PXAD[33] AE4 PXAD[34] AE3 PXAD[35] AE2 PXAD[36] AD7 PXAD[37] AD6 PXAD[38] AD4 PXAD[39] AC6
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 777 PXRCOMP AC12 PXREQ[0]# L2 PXREQ[1]# L6 PXREQ64# AE5 PXSERR# U1 PXSTOP# T2 PXTRDY# T5 RASERR# AE1 RCIN# V26 REQ[0]# D8 REQ[1]# G12 REQ[2]# B11 REQ[3]# D12 RI# AH10 RSMRST# AJ24 RTCRST# AG22 RTCX1 AE21 RTCX2 AD20 SATA[0]RXN AJ19 SATA[0]RXP AH19 SATA[0]TXN AG18 SATA[0]TXP AF18 SATA[1]RXN AJ21 SATA[1]RXP AH21 SATA[1]TXN AG20 SATA[1]TXP AF20 SATACLKN AJ17 SATACLKP AH17 SATALED# J28 SATARBIASN AJ23 SATARBIASP AH23 SDA[0] V24 SDA[1] AD29 SDA[2] AC29 SDCS1# AB28 SDCS3# AA27 SDD[0] AA26 SDD[1] AE29 SDD[2] AB27 SDD[3] AD26 SDD[4] AA24 SDD[5] AF29 SDD[6] W22 SDD[7] AF28 SDD[8] Y23 SDD[9] AE26 SDD[10] AB24 SDD[11] AC26 SDD[12] AE28 SDD[13] AB25 SDD[14] AD27
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 778 USBP2P A26 USBP3N B24 USBP3P A24 USBRBIASN D29 USBRBIASP E28 V_CPU_IO U25 V_CPU_IO U27 V_CPU_IO W26 V5REF AB19 V5REF E11 V5REF_Sus G22 VBIAS AD19 Vcc1_5 AB10 Vcc1_5 AB8 Vcc1_5 AC13 Vcc1_5 AC16 Vcc1_5 AC17 Vcc1_5 AD18 Vcc1_5 AE17 Vcc1_5 AE18 Vcc1_5 AE20 Vcc1_5 AF16 Vcc1_5 AG16 Vcc1_5 AH18 Vcc1_5 F12 Vcc1_5 G20 Vcc1_5 H19 Vcc1_5 H21 Vcc1_5 J8 Vcc1_5 N23 Vcc1_5 N7 Vcc1_5 T23 Vcc1_5 V8 Vcc3_3 AA3 Vcc3_3 AA5 Vcc3_3 AB11 Vcc3_3 AB26 Vcc3_3 AB6 Vcc3_3 AC21 Vcc3_3 AC25 Vcc3_3 AC9 Vcc3_3 AD24 Vcc3_3 AD3 Vcc3_3 AE11 Vcc3_3 AE22 Vcc3_3 AE8 Vcc3_3 AF21 Vcc3_3 AF5 Vcc3_3 AG3 Vcc3_3 AG7 Vcc3_3 C13
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 779 VccSus1_5 J25 VccSus1_5 N24 VccSus1_5 U23 VccSus3_3 B23 VccSus3_3 A23 VccSus3_3 AF13 VccSus3_3 AG12 VccSus3_3 C23 VccSus3_3 D23 VccSus3_3 D24 VccSus3_3 G21 VccSus3_3 H20 VRMPWRGD Y26 VSS B2 VSS B25 VSS B27 VSS B28 VSS B9 VSS A25 VSS A27 VSS A3 VSS A7 VSS AA25 VSS AB12 VSS AB18 VSS AB4 VSS AC11 VSS AC15 VSS AC18 VSS AC24 VSS AC27 VSS AC3 VSS AC7 VSS AD11 VSS AD12 VSS AD17 VSS AD23 VSS AD5 VSS AD9 VSS AE13 VSS AE19 VSS AE25 VSS AE27 VSS AE6 VSS AF10 VSS AF12 VSS AF14 VSS AF17 VSS AF19 VSS AF3 VSS AF8
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 780 VSS F11 VSS F15 VSS F17 VSS F18 VSS F19 VSS F25 VSS F26 VSS F3 VSS F7 VSS F8 VSS G26 VSS G4 VSS H10 VSS H18 VSS H27 VSS H6 VSS J24 VSS J4 VSS K22 VSS K26 VSS L23 VSS L25 VSS L27 VSS L4 VSS L7 VSS M12 VSS M13 VSS M14 VSS M15 VSS M16 VSS M17 VSS M18 VSS M22 VSS M26 VSS M3 VSS M6 VSS N12 VSS N13 VSS N14 VSS N15 VSS N16 VSS N17 VSS N18 VSS N26 VSS P12 VSS P13 VSS P14 VSS P15 VSS P16 VSS P17 VSS P18
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 781 Table 707. Signal List (by Location)
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 782 AD6 PXAD[37] AD7 PXAD[36] AD8 PXPAR64 AD9 VSS AD10 PXAD[48] AD11 VSS AD12 VSS AD13 NC AD14 SLP_S4# AD15 SUS_STAT# AD16 VCCPLL1 AD17 VSS AD18 Vcc1_5 AD19 VBIAS AD20 RTCX2 AD21 PDD[5] AD22 PDD[3] AD23 VSS AD24 Vcc3_3 AD25 PDCS3# AD26 SDD[3] AD27 SDD[14] AD28 SDDREQ AD29 SDA[1] AE1 RASERR# AE2 PXAD[35] AE3 PXAD[34] AE4 PXAD[33] AE5 PXREQ64# AE6 VSS AE7 PXC/BE[4]# AE8 Vcc3_3 AE9 PXAD[51] AE10 PXAD[49] AE11 Vcc3_3 AE12 GPIO[8] AE13 VSS AE14 GPIO[24] AE15 VccSus1_5 AE16 VCCPLL2 AE17 Vcc1_5 AE18 Vcc1_5 AE19 VSS AE20 Vcc1_5 AE21 RTCX1 AE22 Vcc3_3 AE23 PDD[12] AE24 PDD[14] AE25 VSS AE26 SDD[9] AE27 VSS AE28 SDD[12]
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 783 AG20 SATA[1]TXN AG21 VSS AG22 RTCRST# AG23 INTRUDER# AG24 VSS AG25 PDD[1] AG26 VSS AG27 PDA[1] AG28 PDA[0] AG29 VSS AH2 VSS AH3 PXAD[63] AH4 PXAD[62] AH5 PXAD[59] AH6 PXAD[57] AH7 PXAD[55] AH8 PXPCIRST# AH9 GPIO[25] AH10 RI# AH11 SYSRESET# AH12 SMLINK[1] AH13 SMLINK[0] AH14 SMBCLK AH15 VSS AH16 VSS AH17 SATACLKP AH18 Vcc1_5 AH19 SATA[0]RXP AH20 VSS AH21 SATA[1]RXP AH22 VSS AH23 SATARBIASP AH24 PDD[6] AH25 PDD[11] AH26 PDD[2] AH27 PDD[15] AH28 VSS AJ3 VSS AJ4 PXAD[61] AJ5 PXAD[58] AJ6 PXAD[56] AJ7 PXAD[52] AJ8 PME# AJ9 GPIO[28] AJ10 PWRBTN# AJ11 SLP_S5# AJ12 SUSCLK AJ13 SMBDATA AJ14 NC AJ15 NC AJ16 VSS AJ17 SATACLKN
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 784 C15 LAD[0] C16 VSS C17 Vcc3_3 C18 VSS C19 SIU1_TXD C20 VSS C21 GPIO[6] C22 GPIO[56] C23 VccSus3_3 C24 VSS C25 USBP1N C26 VSS C27 USBP0P C28 VSS C29 VSS D1 AD[14] D2 PERR# D3 Vcc3_3 D4 AD[5] D5 AD[9] D6 AD[6] D7 VSS D8 REQ[0]# D9 GNT[1]# D10 GPIO[4] / PIRQ[G]# D11 VSS D12 REQ[3]# D13 VSS D14 THRM# D15 Vcc3_3 D16 SIU0_CTS# D17 SIU1_RI# D18 SIU1_RXD D19 NC D20 GPIO[37] D21 VccSus1_5 D22 GPIO[57] D23 VccSus3_3 D24 VccSus3_3 D25 USBP1P D26 VSS D27 USBP0N D28 VSS D29 USBRBIASN E1 AD[17] E2 AD[10] E3 IRDY# E4 SERR# E5 VSS E6 Vcc3_3 E7 AD[26]
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 785 G1 GPIO[33] / PXIRQ[0]# G2 AD[31] G3 Vcc3_3 G4 VSS G5 DEVSEL# G6 AD[12] G7 C/BE[1]# G8 AD[1] G9 PAR G10 FRAME# G11 AD[30] G12 REQ[1]# G13 GNT[3]# G14 LDRQ[1]# G15 Vcc3_3 G16 SIU1_RTS# G17 SERIRQ G18 NC G19 AC_BIT_CLK G20 Vcc1_5 G21 VccSus3_3 G22 V5REF_Sus G23 OC[2]# G24 VccSus1_5 G25 NC G26 VSS G27 NC G28 NC G29 GPIO[42] H1 GPIO[34] / PXIRQ[1]# H2 GPIO[35] / PXIRQ[2]# H3 Vcc3_3 H4 AD[29] H5 C/BE[3]# H6 VSS H7 AD[23] H8 AD[8] H9 Vcc3_3 H10 VSS H11 AD[0] H12 AD[28] H18 VSS H19 Vcc1_5 H20 VccSus3_3 H21 Vcc1_5 H22 VccSus1_5 H23 VccSus1_5 H24 NC H25 NC
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 786 L28 NC L29 NC M1 PXAD[25] M2 PXAD[26] M3 VSS M4 Vcc3_3 M5 PXAD[30] M6 VSS M7 PXAD[29] M8 Vcc3_3 M12 VSS M13 VSS M14 VSS M15 VSS M16 VSS M17 VSS M18 VSS M22 VSS M23 Vcc3_3 M24 GPIO[32] / WDT _TOUT# M25 NC M26 VSS M27 Vcc3_3 M28 HI11 M29 NC N1 PXAD[22] N2 PXAD[20] N3 PXAD[23] N4 PXAD[24] N5 Vcc3_3 N6 PXC/BE[3]# N7 Vcc1_5 N12 VSS N13 VSS N14 VSS N15 VSS N16 VSS N17 VSS N18 VSS N23 Vcc1_5 N24 VccSus1_5 N25 HI9 N26 VSS N27 VccHI N28 HI10 N29 HI8 P1 PXAD[17] P2 PXAD[18] P3 VSS P4 Vcc3_3 P5 PXAD[19]
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 787 T24 HICLK T25 VSS T26 HI6 T27 HICOMP T28 HI_STB/ HI_STBS T29 HI_STB#/ HI_STBF U1 PXSERR# U2 PXC/BE[1]# U3 VSS U4 PXPAR U5 Vcc3_3 U6 PXPERR# U7 Vcc3_3 U12 VSS U13 VSS U14 VSS U15 VSS U16 VSS U17 VSS U18 VSS U23 VccSus1_5 U24 IGNNE# U25 V_CPU_IO U26 VSS U27 V_CPU_IO U28 HI5 U29 HI4 V1 PXAD[12] V2 PXAD[11] V3 VSS V4 PXAD[13] V5 VSS V6 VCCREF V7 PXAD[2] V8 Vcc1_5 V12 VSS V13 VSS V14 VSS V15 VSS V16 VSS V17 VSS V18 VSS V22 VSS V23 IRQ[15] V24 SDA[0] V25 VSS V26 RCIN# V27 VSS V28 CPUSLP# V29 SMI#
21— Intel® 6300ESB ICH Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 788
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 789 22—Intel ® 6300ESB ICH Electrical Characteristics 22 This chapter provides the absolute maximum ratings, DC characteristics, AC characteristics and AC timing diagrams for the Intel ® 6300ESB ICH component.
22.1 Absolute Maximum Ratings
Voltage on any 3.3 V pin with respect to Ground = –0.5 to Vcc3_3 +0.5 V Voltage on any 5 V tolerant pin with respect to Ground (V5REF = 5 V) = –0.5 to V5REF + 0.5 V 1.5 V supply voltage with respect to Vss = –0.5 to +2.1 V 3.3 V supply voltage with respect to Vss = –0.5 to +4.6 V 5.0 V supply voltage (V5REF) with respect to Vss = –0.5 to +5.5 V Warning:Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. See Section 22.2, “Functional Operating Range” for the Functional Operating Range of the Intel® 6300ESB ICH.
22.2 Functional Operating Range
All of the AC and DC Characteristics specified in this document assume that the Intel ® 6300ESB ICH component is operating within the Functional Operating Range given in this section. Operation outside of the Functional Operating Range is not recommended, and extended exposure outside of the Functional Operating Range may affect component reliability.
- 1.5 V supply voltage (Vcc1_5, VccHI, VccSus1_5) with respect to Vss = 1.425 V to 1.575 V
- 3.3 V supply voltage (Vcc3_3, VccSus3_3) with respect to Vss = 3.135 V to 3.465 V
- 5 V supply voltage (V5REF, V5REF_Sus) with respect to Vss = 4.75 V to 5.25 V
- V_CPU_IO voltage with respect to Vss = 0.8 V—1.75 V
- VCCRTC voltage with respect to Vss = 2.0 V to 3.6 V
- Case temperature under Bias = 0 o C to +105o C Note: A non-condensing environment is required to maintain RTC accuracy.
790 Order Number: 300641-004US
22.3 DC Characteristics
Table 708. DC Current Characteristics (Preliminary)
- Icc(RTC) data is taken with Vcc(RTC) at 3.0 V while the system is in a mechanical off
(G3) state at room temperature (25o C). Table 709. DC Characteristic Input Signal Association (Sheet 1 of 2)
Table 710. DC Input Characteristics (Sheet 1 of 2)
- Applies to Ultra DMA Modes greater than Ultra DMA Mode 4.
- This is an AC Characteristic that represents transient values for these signals.
- VDI = | USBPx[P] - USBPx[N].
- Applies to High-speed USB 2.0.
- SATA Vdiff,rx is measured at the SATA connector on the receive side.
- When probed at the receiver pin of the ICH for data/strobe, the waveform may show a “knee” due to package
ICH ball input due to internal receiver termination. Table 709. DC Characteristic Input Signal Association (Sheet 2 of 2)
792 Order Number: 300641-004US
Table 710. DC Input Characteristics (Sheet 2 of 2)
- Applies to Ultra DMA Modes greater than Ultra DMA Mode 4.
- This is an AC Characteristic that represents transient values for these signals.
- VDI = | USBPx[P] - USBPx[N].
- Applies to High-speed USB 2.0.
- SATA Vdiff,rx is measured at the SATA connector on the receive side.
- When probed at the receiver pin of the ICH for data/strobe, the waveform may show a “knee” due to package
ICH ball input due to internal receiver termination.
Table 711. DC Characteristic Output Signal Association
- These signals are open drain.
794 Order Number: 300641-004US
Table 712. DC Output Characteristics
- The CPUPWRGD, SERR#, PIRQ[A:H], SATALED#, SMBDATA, SMBCLK, and SMLINK[1:0], RASERR#,
signal must have external pull up resistor .
- SATA Vdiff,tx is measured at the SATA connector on the transmit side.
Table 713. Other DC Characteristics (Sheet 1 of 2)
- Includes CLK14, CLK48, HICLK, PCICLK and PXPCICLK.
Table 713. Other DC Characteristics (Sheet 2 of 2)
- Includes CLK14, CLK48, HICLK, PCICLK and PXPCICLK.
796 Order Number: 300641-004US
22.4 AC Characteristics
Table 714. Clock Timings (Sheet 1 of 3)
Table 714. Clock Timings (Sheet 2 of 3)
798 Order Number: 300641-004US
- CLK48 is a 48 MHz clock that expects a 40/60% duty cycle.
- CLK48 is a pass-thru clock that is not altered by the Intel® 6300ESB ICH. This frequency tolerance
generator and the system board.
- The maximum high time (t18 Max) provide a simple ensured method for devices to detect bus idle
- BITCLK Rise and Fall times are measured from 10%VDD and 90%VDD.
- This specification includes pin-to-pin skew from the clock generator as well as board skew.
- SUSCLK duty cycle can range from 30% minimum to 70% maximum.
- For clock frequencies above 33 MHz, the clock frequency may not change beyond the spread-spectrum limits
except while RST# is asserted.
- This slew rate must be met across the minimum peak-to-peak portion of the clock waveform as shown in
- The minimum clock period must not be violated for any single clock cycle, i.e., accounting for all system
Table 714. Clock Timings (Sheet 3 of 3)
Table 715. PCI-X Interface Timings
- Refer to Figure 41. For timing and measurement condition details, refer to the PCI-X Addendum to the PCI
Local BUS Specification document.
- Minimum times are measured at the package pin (not a test point).
- Setup time for point-to-point signals applies to PXREQ[3:0] and PXGNT[3:0] only. All other signals are bused.
- See timing measurement conditions in Figure 42.
- PXPCIRST# is asserted and deasserted asynchronously with respect to PXCLKO[4:0].
- All output drivers must be floated when RSTIN# is active.
- For purposes of Active/Float timing measurements, the Hi-Z or “off” state is defined to be when the total
- Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at
- Maximum value is also limited by delay to the first transaction (Trhfa). The PCI-X initialization pattern control
FRAME# and must be floated no later than one clock before FRAME# is asserted. 10.A PCI-X device is permitted to have the minimum values shown for Tval, Tval(ptp), and Ton only in PCI-X mode. Revision 2.2, for the appropriate clock frequency. 11.Device must meet this specification independent of how many outputs switch simultaneously.
800 Order Number: 300641-004US
Table 716. PCI Interface Timing
802 Order Number: 300641-004US
Table 718. Ultra ATA Timing (Mode 0, Mode 1, Mode 2) (Sheet 1 of 2)
- The specification symbols in parentheses correspond to the AT Attachment - 6 with Packet Interface (ATA/
ATAPI - 6) specification name.
- See the AT Attachment - 6 with Packet Interface (ATA/ATAPI - 6) specification for further details on
measuring these timing parameters.
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Table 719. Ultra ATA Timing (Mode 3, Mode 4, Mode 5) (Sheet 1 of 2)
- The specification symbols in parentheses correspond to the AT Attachment - 6 with Packet Interface (ATA/
ATAPI - 6) specification name.
- See the AT Attachment - 6 with Packet Interface (ATA/ATAPI - 6) specification for further details on
measuring these timing parameters.
806 Order Number: 300641-004US
Table 720. Universal Serial Bus Timing
0 USBPx+, USBPx- Driver Rise Time 4 20 ns 1, CL = 50 pF Figure 56
1 USBPx+, USBPx- Driver Fall Time 4 20 ns 1, CL = 50 pF Figure 56
3 Source SE0 interval of EOP 160 175 ns 4F i g u r e 5 8
6 EOP Width: Must accept as EOP 82 ns 4F i g u r e 5 8
7 Width of SE0 interval during differential transition 14 ns
8 USBPx+, USBPx- Driver Rise Time 75 300 ns
9 USBPx+, USBPx- Driver Fall Time 75 300 ns
- Driver output resistance under steady state drive is spec’d at 28 ohms at minimum and 43 ohms at
- Timing difference between the differential data signals.
- Measured at crossover point of differential data signals.
- Measured at 50% swing point of data signals.
- Measured from last crossover point to 50% swing point of data line at leading edge of EOP.
- Measured from 10% to 90% of the data signal.
- Full Speed Data Rate has minimum of 11.97 Mbps and maximum of 12.03 Mbps.
- Low Speed Data Rate has a minimum of 1.48 Mbps and a maximum of 1.52 Mbps.
- Refer to the latest revision of the Universal Serial Bus Specification for High speed source timings
4 EOP Width: Must accept as EOP 670 ns 4F i g u r e 5 8
5 Width of SE0 interval during differential transition 210 ns
- Driver output resistance under steady state drive is spec’d at 28 ohms at minimum and 43 ohms at
- Timing difference between the differential data signals.
- Measured at crossover point of differential data signals.
- Measured at 50% swing point of data signals.
- Measured from last crossover point to 50% swing point of data line at leading edge of EOP.
- Measured from 10% to 90% of the data signal.
- Full Speed Data Rate has minimum of 11.97 Mbps and maximum of 12.03 Mbps.
- Low Speed Data Rate has a minimum of 1.48 Mbps and a maximum of 1.52 Mbps.
- Refer to the latest revision of the Universal Serial Bus Specification for High speed source timings
808 Order Number: 300641-004US
Table 721. SATA Interface Timings
- As measured from 100 mV differential crosspoints of last and first edges of burst.
- Operating data period during Out-Of-Band burst transmissions.
Table 722. SMBus Timing
4 Data Hold Time 0 ns 4F i g u r e 5 9
5 Data Setup Time 250 ns Figure 59
6 Device Time Out 25 35 ms 1
7 Cumulative Clock Low Extend Time (slave device) 25 ms 2F i g u r e 6 0
8 Cumulative Clock Low Extend Time (master device) 10 ms 3F i g u r e 6 0
- A device will timeout when any clock low exceeds this value.
- t137 is the cumulative time a slave device is allowed to extend the clock cycles in one message from the
- t138 is the cumulative time a master device is allowed to extend its clock cycles within each byte of a
message as defined from start-to-ack, ack-to-ack or ack-to-stop.
- t134 has a minimum timing for I2C of 0 ns, while the minimum timing for SMBus is 300 ns.
Table 723. AC’97 Timing Table 724. LPC Timing
0 LAD[3:0] Valid Delay from PCICLK Rising 2 11 ns Figure 45
1 LAD[3:0] Output Enable Delay from PCICLK Rising 2 ns Figure 49
2 LAD[3:0] Float Delay from PCICLK Rising 28 ns Figure 47
3 LAD[3:0] Setup Time to PCICLK Rising 7 ns Figure 46
4 LAD[3:0] Hold Time from PCICLK Rising 0 ns Figure 46
5 LDRQ[1:0]# Setup Time to PCICLK Rising 12 ns Figure 46
6 LDRQ[1:0]# Hold Time from PCICLK Rising 0 ns Figure 46
7 LFRAME# Valid Delay from PCICLK Rising 2 12 ns Figure 45
Table 725. Miscellaneous Timings
0 SERIRQ Setup Time to PCICLK Rising 7 ns Figure 46
1 SERIRQ Hold Time from PCICLK Rising 0 ns Figure 46
2 RI# Pulse Width 2 RTCCLK Figure 48
3 SPKR Valid Delay from CLK14 Rising 200 ns Figure 45
4 SERR# Active to NMI Active 200 ns
5 IGNNE# Inactive from FERR# Inactive 230 ns
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Table 726. UART Timings
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Table 728. Power Management Timings
- These transitions are clocked off the internal RTC. 1 RTC clock is approximately 32 µs.
- The Intel® 6300ESB ICH STPCLK# assertion will trigger the processor to send a stop grant acknowledge
- These transitions are clocked off the 33 MHz PCICLK. 1 PCICLK is approximately 30ns.
- The Intel® 6300ESB ICH has no maximum timing requirement for this transition. It is up to the system
designer to determine if the SLP_S3#, SLP_S4# and SLP_S5# signals are used to control the power planes.
- If the transition to S5 is due to Power Button Override, SLP_S3#, SLP_S4# and SLP_S5# are asserted
together similar to timing t194 (PXPCIRST# active to SLP_S3# active).
- If there is no RTC battery in the system, so VccRTC and the VccSus supplies come up together, the delay from
RTCRST# and RSMRST# inactive to SUSCLK toggling may be as much as 2.5 s.
22.5 Timing Diagrams and Test Conditions
22.5.1 PCI-X
Figure 39. PCI-X 3.3V Clock Figure 40. Clock Uncertainty (PXPCLK[0:4]) Table 729. Clock Uncertainty Parameters
0.6 Vcc
0.2 Vcc
0.5 Vcc
0.4 Vcc
0.3 Vcc
0.4 Vcc, p-to-p
814 Order Number: 300641-004US
Figure 41. PCI-X Output Timing Figure 42. PCI-X Input Timing
22.5.2 System Clocks and General Timing
Table 730. PCI-X Measurement Condition Parameters
- The test for the 3.3V environment is done with 0.1*Vcc of overdrive. Vmax specifies the
- Vtrise and Vtfall are reference voltages for timing measurements only.
- Input signal slew rate in PCI-X mode is measured between Vil and Vih.
Figure 43. PCI-X RST# Timing for switching to PCI-X Mode Pull-ups Figure 44. Clock Timing
816 Order Number: 300641-004US
Figure 45. Valid Delay from Rising Clock Edge Figure 46. Setup and Hold Times Figure 47. Float Delay Figure 48. Pulse Width
22.5.3 IDE and Ultra ATA Timing
Figure 49. Output Enable Delay Figure 50. IDE PIO Mode
818 Order Number: 300641-004US
Figure 51. IDE Multiword DMA Figure 52. Ultra ATA Mode (Drive Initiating a Burst Read)
820 Order Number: 300641-004US
22.5.4 USB
Figure 55. Ultra ATA Mode (Terminating a DMA Burst) Figure 56. USB Rise and Fall Times
22.5.5 SMBus
Figure 57. USB Jitter Figure 58. USB EOP Width Figure 59. SMBus Transaction
822 Order Number: 300641-004US
22.5.6 Power and Reset
Figure 60. SMBus Timeout Figure 61. Power Sequencing and Reset Signal Timings
824 Order Number: 300641-004US
22.5.7 AC’97 and Miscellaneous
Figure 64. S0 to S5 to S0 Timings Figure 65. AC’97 Data Input and Output Timings
23.1 Test Mode Description
PWROK is high will activate a particular test mode as described in Table 731. Note: RTCRST# can be driven low any time after PXPCIRST# is inactive. Table 731. Test Mode Selection
43 X O R C h a i n 1
53 X O R C h a i n 2
63 X O R C h a i n 3
73 X O R C h a i n 4
826 Order Number: 300641-004US
23.2 Tri-State Mode
23.3 XOR Chain Mode
23.3.1 XOR Chain Testability Algorithm Example
Figure 66. Test Mode Entry (XOR Chain Example) Figure 67. Example XOR Chain Circuitry
“1” at the XOR output on a good board. to “1” is odd, expect “0” at the output. toggling sequence (e.g., “1011”) will identify the location of the short or open. Table 732. XOR Test Pattern Example Table 733. XOR Chain #1
Table 734. XOR Chain #2
Table 735. XOR Chain #3
Table 736. XOR Chain #4 Table 737. XOR Chain #5
Table 738. XOR Chain #6 (RTCRST# asserted for 52 PCI clocks while Table 739. XOR Chain #7 (RTCRST# asserted for 60 PCI clocks while
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 835 —Intel ® 6300ESB ICH Index GP_LVL 432, 433
6 Channel Capability 575, 602
64-bit Addressing Capability 507 A A20Gate Pass-Through Enable (A20PASSEN) 471 AC ‘97 Cold Reset# 574, 601 AC ‘97 Interrupt Routing 590 AC’97 Warm Reset 574, 601 AC97_EN 404 AC97_STS 403 ACLINK Shut Off 573, 600 AD3 576, 603 ADDRESS 539 Address Increment/Decrement Select 352 Address of Descriptor Table (ADDR) 459, 769 ADLIB_ACT_STS 412 ADLIB_LPC_EN 337 ADLIB_TRP_EN 414 AF Alarm Flag 380 AFTERG3_EN 387 AIE Alarm Interrupt Enable 378 ALT_A20_GATE 382 ALTACC_EN Alternate Access Mode Enable 328 APIC Data 370, 641 APIC ID 371, 643 APIC Index 369, 641 APIC_EN 328 APM_STS 409 APMC_EN 406 Asynchronous Schedule Enable 509 Asynchronous Schedule Status 512 AUDIO_ACT_STS 412 AUDIO_TRP_EN 414 Autoinitialize Enable 353 Automatic End of Interrupt (AEOI) 364 Automatically Append CRC (AAC) 544 Aux_Current 493 B BAR Number 496 Base Address 441, 442, 443, 556, 557, 587, 588, 744, 745, 746 Base and Current Address 348 Base and Current Count 349 Base Class Code 441, 743 Binary/BCD Countdown Select 356 BIOS_EN 407 BIOS_RLS BIOS Release 406 BIOS_STS 409 BIOSWR_STS 419 BIST FIS Failed 764
Intel® 6300ESB ICH— Intel® 6300ESB I/O Controller Hub DS November 2007
836 Order Number: 300641-004US
BIST FIS Transmit Data 1 765 BIST FIS Transmit Data 2 766 Bit 1 of slot 12 576, 603 Bit 2 of slot 12 576, 603 Bit 3 of slot 12 576, 603 Bit Clock Stopped (BCS) 575, 602 Block Data (BDTA) 541 BOOT_STS 421 Buffer Completion Interrupt Status (BCIS) 570, 596 Buffer Descriptor Base Address 568 Buffer Descriptor List Base Address 595 Buffered Mode (BUF) 364 Bus Master Enable (BME) 437, 463, 552, 583, 740 Bus Master IDE Active (ACT) 458, 768 BUS_ERR 535 BYTE_DONE_STS 535 C Cap ID (CAP) 562 Capability ID 499 Cascaded Interrupt Controller IRQ Connection 363 Channel 1 Select 327 Channel 2 Select 327 Channel 3 Select 326 Channel 5 Select 326 Channel 6 Select 326 Channel 7 Select 326 Channel Mask Bits 355 Channel Mask Select 352 Channel Request Status 351 Channel Terminal Count Status 351 Clear Byte Pointer 353 Clear Mask Register 354 CNF1_LPC_EN 337 CNF2_LPC_EN 337 Codec Access Semaphore (CAS) 604 Codec Write In Progress (CWIP) 578 COMA Decode Range 332 COMA_LPC_EN 338 COMB Decode Range 332 COMB_LPC_EN 338 Configure Flag (CF) 474 Connect Status Change 484, 521 COPR_ERR_EN Coprocessor Error Enable 328 COPROC_ERR 383 Count Register Status 359 COUNT_SIZE_CAP 606 Countdown Type Status 359 Counter 0 Select 357 Counter 1 Select 357 Counter 2 Select 357 Counter Latch Command 358 Counter OUT Pin State 359 Counter Port 360 Counter Select 356 Counter Selection 358 COUNTER_CLK_PER_CAP 606
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 837 —Intel ® 6300ESB ICH COUNTER_VAL 609 CPU Thermal Trip Status (CTS 386 CPU_BIST_EN Enables CPU BIST 330 CPUPWR_FLR CPU Power Failure 386 CPUSLP_EN 385 Current Connect Status 484, 521 Current Equals Last Valid (CELV) 570, 597 Current Index Value 569, 595 D D1_Support 493 D2_Support 493 D29_F0_Disable 343 D29_F1_Disable 343 D29_F7_Disable 343 D31_F1_Disable 344 D31_F3_Disable 344 D31_F5_Disable 343 D31_F6_Disable 343 Data 761 DATA_HIGH_BYTE 548 DATA_LEN_CNT 524 DATA_LOW_BYTE 548 DATA_MSG0 Data Message Byte 0 543 DATA_MSG1 Data Message Byte 1 543 DATA0/COUNT 540 DATA1 540 Date Alarm 380 DCB_EN DMA Collection Buffer Enable 329 Debug Port Number (DP_N) 505 Debug Port Offset 496 Delivery Mode 374 Delivery Status 374, 645 Destination 373, 644 Destination Mode 374, 645 DEV_ERR 536 DEV_TRAP_EN 411 DEV_TRAP_STS 411 Device Connects 231 Device ID value 528 DEVICE_ADDRESS 547 DEVMON_STS Device Monitor Status 408 DEVSEL# Timing Status (DEVT) 464, 529, 553 DM Data Mode 379 DMA Channel Group Enable 350 DMA Channel Select 352, 353 DMA Controller Halted (DCH) 570, 597 DMA Group Arbitration Priority 345, 350 DMA Low Page 350 DMA Transfer Mode 352 DMA Transfer Type 353 DONE_STS 523 Drive 0 DMA Capable 457, 768 Drive 0 DMA Timing Enable (DTE0) 450, 749 Drive 0 Fast Timing Bank (TIME0) 450, 749 Drive 0 IORDY Sample Point Enable (IE0) 450, 749 Drive 0 Prefetch/Posting Enable (PPE0) 450, 749 Drive 1 DMA Capable 457, 768
Intel® 6300ESB ICH— Intel® 6300ESB I/O Controller Hub DS November 2007
838 Order Number: 300641-004US
Drive 1 DMA Timing Enable (DTE1) 449, 749 Drive 1 Fast Timing Bank (TIME1) 450, 749 Drive 1 IORDY Sample Point Enable (IE1) 449, 749 Drive 1 Prefetch/Posting Enable (PPE1) 449, 749 Drive 1 Timing Register Enable (SITRE) 448, 748 DSE Daylight Savings Enable 379 DSI 493 DT Delivery Type 373, 644 DTE Delayed Transaction Enable 329 DV Division Chain Select 377 E Edge/Level Bank Select (LTIM) 361 EHC Initialization 221 EHC Resets 222 EHCI Extended Capabilities Pointer (EECP) 507 Enable 32-byte Buffer (E32B) 544 Enable Special Mask Mode (ESMM) 366 ENABLE_CNF Overall Enable 607 ENABLED_CNT 522 Enter Global Suspend Mode (EGSM) 475 EOS End of SMI 407 Error 458, 768 ERROR_GOOD#_STS 523 EXCEPTION_STS 523 Extended Destination ID (EDID) 373, 644, 646 F FAILED 535 Fast Non-Data PIO (FNDPIO) 449 FAST_PCB0 Fast Primary Drive 0 Base Clock 754 FAST_PCB1 Fast Primary Drive 1 Base Clock 754 FAST_SCB0 Fast Secondary Drive 0 Base Clock 754 FAST_SCB1 Fast Secondary Drive 1 Base Clock 754 FDD Decode Range 333 FDD_LPC_EN 338 FIFO error (FIFOE) 570, 596 FIFO Error Interrupt Enable (FEIE) 572, 599 Force Global Resume (FGR) 474 Force Port Resume 520 FORCE_THTL 398 Frame Length Timing Value 497 Frame List Current Index/Frame Number 481, 515 Frame List Rollover 513 Frame List Rollover Enable 514 Frame List Size 510 FREQ_STRAP 330 FULL_RST 383 FWH_C0_EN 336, 342 FWH_C0_IDSEL 339 FWH_C8_EN 336, 342 FWH_C8_IDSEL 339 FWH_D0_EN 336, 342 FWH_D0_IDSEL 339 FWH_D8_EN 335, 342 FWH_D8_IDSEL 339, 341
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 839 —Intel ® 6300ESB ICH FWH_E0_EN 335 FWH_E0_IDSEL 339, 341 FWH_E8_EN 335 FWH_E8_IDSEL 339, 341 FWH_F0_EN 335 FWH_F0_IDSEL 339, 341 FWH_F8_EN 335 FWH_F8_IDSEL 339 G GAMEH_LPC_EN 337 GAMEL_LPC_EN 337 GBL _STS 395 GBL_EN 396 GBL_RLS Global Release 397 GBL_SMI_EN 407 GEN1_BASE Generic I/O Decode Range 1 Base 336 GEN1_EN Generic Decode Range 1 Enable 336 GEN2_BASE Generic I/O Decode Range 2 Base 340 GEN2_EN Generic I/O Decode Range 2 Enable 340 Global Reset (GRESET) 476 GO_CNT 523 GP_IO_SEL2 432 GP_LVL2 433 GPE0_STS 409 GPE1_STS 409 GPI Interrupt Enable (GIE) 574, 601 GPI Status Change Interrupt (GSCI) 577, 604 GPI0 Route 389 GPI15 Route 389 GPIn_EN 404 GPIn_STS 401 GPIO_SEL 426 GPIO11_ALERT_DISABLE 423 H HC BIOS Owned Semaphore 499 HC OS Owned Semaphore 499 HCHalted 478, 512 HCRESE 223 HIDE_ISA Hide ISA Bridge 327 Host Controller Process Error 478 Host Controller Reset 511 Host Controller Reset (HCRESET) 476 Host System Error 478, 513 Host System Error Enable. 514 HOST_BUSY 536 HOST_NOTIFY_INTREN 546 HOST_NOTIFY_STS 546 HOST_NOTIFY_WKEN 546 HOURFORM Hour Format 379 HST_EN SMBus Host Enable 533 HUBNMI_STS 419 HUBSCI_STS 419 HUBSERR_STS 419 HUBSMI_STS 419
Intel® 6300ESB ICH— Intel® 6300ESB I/O Controller Hub DS November 2007
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I I/O APIC Identification 372 I/O Space (IOS) 583 I/O Space Enable (IOSE) 463, 528, 562 I2C 246, 249 I2C_EN 533 ICW/OCW select 361 ICW4 Write Required (IC4) 361 IDE Decode Enable (IDE) 448, 748 IDEP0_ACT_STS 413 IDEP0_TRP_EN 415 IDEP1_ACT_STS 413 IDEP1_TRP_EN 415 IDES0_ACT_STS 413 IDES0_TRP_EN 415 IDES1_ACT_STS 413 IDES1_TRP_EN 414 IN_USE_CNT 523 Index 760 INIT_NOW 382 INTEL_USB2_EN 405 INTEL_USB2_STS 408 Interrupt 458, 768 Interrupt Input Pin Polarity 374, 645 Interrupt Level Select (L2, L1, L0) 365 Interrupt Line 446, 747 Interrupt on Async Advance 512 Interrupt on Async Advance Doorbell 509 Interrupt on Async Advance Enable 514 Interrupt On Complete (IOC) Enable 480 Interrupt On Completion Enable (IOCE) 572, 599 Interrupt Pin 447, 748 Interrupt Request Level 362 Interrupt Request Mask 364 Interrupt Threshold Control 509 Interrupt Vector Base Address 362 INTR 536 INTRD_DET Intruder Detect 421 INTRD_SEL 423 INTREN 539 INUSE_STS 535 IOCHK_NMI_EN 381 IOCHK_NMI_STS IOCHK# NMI Source Status 381 IORDY Sample Point (ISP) 448, 748 IOSE I/O Space Enable (IOSE) 437, 740 IRQ Number 370, 642 IRQ Routing 324 IRQ1_CAUSE 424 IRQ10 ECL 368 IRQ11 ECL 368 IRQ12 ECL 367 IRQ12_CAUSE 424 IRQ12LEN Mouse IRQ12 Latch Enable 328 IRQ14 ECL 367 IRQ15 ECL 367 IRQ1LEN Keyboard IRQ1 Latch Enable 328 IRQ3 ECL 367 IRQ4 ECL 367 IRQ5 ECL 367
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 841 —Intel ® 6300ESB ICH IRQ6 ECL 367 IRQ7 ECL 367 IRQ9 ECL 368 IRQEN 324 IRQF Interrupt Request Flag 380 Isochronous Scheduling Threshold 507 K KBC_ACT_STS 412 KBC_LPC_EN 337 KBC_TRP_EN 414 KILL 539 L L128LOCK Lower 128-byte Lock 331 Last Codec Read Data Input (LDI) 579 Last Valid Buffer Completion Interrupt (LVBCI) 570, 597 Last Valid Buffer Interrupt Enable (LVBIE) 572, 600 Last Valid Index 569, 596 Latch Count of Selected Counters 357 Latch Status of Selected Counters 357 latency 728 LEG_ACT_STS 413 LEG_IO_TRP_EN 414 LEG_RT_CAP 606 LEG_RT_CNF 607 LEGACY_USB_EN 406 LEGACY_USB_STS 409 LEGACY_USB2_EN 405 LEGACY_USB2_STS 408 Light Host Controller Reset 509 Line Status 484, 519 Link Pointer Low 517 LINK_ID_STS 523 Loop Back Test Mode 474 Low Speed Device Attached (LS) 483 LPT Decode Range 333 LPT_LPC_EN 338 M MAS (Master-Abort Status) 584 Mask 374, 645 Master Clear 354 Master/Slave in Buffered Mode 364 Master-Abort Status (MAS) 553 Max Packet (MAXP) 474 Maximum Redirection Entries 372, 643 MC_LPC_EN 337 MCSMI_EN Microcontroller SMI Enable 406 MCSMI_STS Microcontroller SMI# Status 409 MD3 575, 603 Memory Space (MS) 552 Memory Space Enable (MSE) 437, 740 Mic In Interrupt (MINT) 576, 604 Microphone 2 In Interrupt (M2INT) 575, 602 Microprocessor Mode 364
— Intel® 6300ESB ICH Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 842 MIDI Decode Range 334 MIDI_ACT_STS 412 MIDI_LPC_EN 337 MIDI_TRP_EN 414 MMT_ADDR_EN 328 MMT_ADDR_SEL 328 Mode Selection Status 359 Modem In Interrupt (MIINT) 577, 604 Modem Out Interrupt (MOINT) 577, 604 MON_TRAP_BASE 391 MON4_FWD_EN 390 MON4_MASK 391 MON5_FWD_EN 390 MON5_MASK 391 MON6_FWD_EN 390 MON6_MASK 391 MON7_FWD_EN 390 MON7_MASK 391 MSS Decode Range 334 MSS_LPC_EN 337 Multi-Function Bit 466 N GP_BLINK 429 GP_INV 430 GP_LVL 427 N_PORTS 506 NEWCENTURY_STS 420 Next Capability (NEXT) 562 Next EHCI Capability Pointer 499 NMI_EN 382 NMI_NOW 422 NMI2SMI_EN 420, 422 NO_REBOOT 329 NUM_TIM_CAP 606 Number of Companion Controllers (N_CC) 506 Number of Ports per Companion Controller (N_PCC) 506 O OCW2 Select 365 OCW3 Select 366 Over-current Active 521 Overcurrent Active 483 Over-current Change 520 Overcurrent Indicator 483 OWNER_CNT 522 P Pass Through State (PSTATE) 471 PCB0 755 PCB1 755 PCI Interrupt Enable (USBPIRQEN) 470 PCI_SERR_EN 381 PCM 4/6 Enable 573 PCM In 1, Microphone In 1 Data In Line (DI1L) 578 PCM In 2 Interrupt (P2INT) 575, 602 PCM In 2, Microphone In 2 Data In Line (DI2L) 578 PCM In Interrupt (PIINT) 577, 604 PCM Out Interrupt (POINT) 577, 604 PCM Out Mode (POM) 573 PEC_DATA 542 PEC_EN 537 PER_SMI_SEL 385 Periodic List Execution 224 Periodic Schedule Enable 510 Periodic Schedule Status 512 PERIODIC_EN 406 PERIODIC_STS 408 PF Periodic Interrupt Flag 380 PIE Periodic Interrupt Enable 378 PIRQAE_ACT_STS 413 PIRQBF_ACT_STS 413 PIRQCG_ACT_STS 413 PIRQDH_ACT_STS 412 PM1_STS_REG 409 PME Clock 494 PME Status (PMES) 563, 591 PME_B0_EN 404 PME_B0_STS 401 PME_EN 404, 494 PME_Status 494 PME_STS 402 PME_Support 493 Poll Mode Command 366 POP_MODE_CAP 439, 742 POP_MODE_SEL 439, 742 Port 0 BIST FIS Initiate 764 Port 1 BIST FIS Initiate 764 Port Change Detect 513 Port Change Interrupt Enable 514 Port Enable/Disable Change 484, 521 Port Enabled/Disabled 521 Port Enabled/Disabled (PORT_EN) 484 Port Owner 518 Port Power (PP) 518 Port Reset 483, 519 Port Test Control 518 Port Wake Implemented 498 Port Wake Up Capability Mask 498 PORT0EN 472 PORT1EN 472 Port-Routing Logic 230 Position In Current Buffer 571, 597, 599 Power Management Event Enable (PMEE) 564, 592 Power Sequencing 811 Power State (PS) 564, 592 PowerState 495 PRBTNOR_STS Power Button Override Status 394 Prefetched Index Value 571 Primany Resume Interrupt Enable 573, 600 Primary Codec Ready (PCR) 576, 603 Primary Drive 0 Cycle Time (PCT0) 454, 753 Primary Drive 0 Synchronous DMA Mode Enable (PSDE0) 452, 751 Primary Drive 1 Cycle Time (PCT1) 454, 753
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 843 —Intel ® 6300ESB ICH Primary Drive 1 IORDY Sample Point (PISP1) 451, 750 Primary Drive 1 Recovery Time (PRCT1) 451, 750 Primary Drive 1 Synchronous DMA Mode Enable (PSDE1) 452, 751 Primary Resume Interrupt 576, 603 programmable baud rate generator 722 Programmable Frame List Flag 507 PRQ 372, 643 PWR_FLR Power Failure 387 PWRBTN__STS 395 PWRBTN_EN 396 PWRBTN_LVL 385 PWROK_FLR PWROK Failure 386 R Read / Write Control (RWC) 456, 767 Read Back Command 357 Read Completion Status 576, 603 Read Policies for Periodic DMA 224 Read/Write Select 356 Read/Write Selection Status 359 Received Master-Abort Status (RMA 464 Received Master-Abort Status (RMA) 438, 741 RECEIVED_PID_STS 525 receiver interrupts 723 Reclamation 512 Recovery Time (RCT) 449, 749 Redirection Entry Clear 371, 642 REF_TOGGLE Refresh Cycle Toggle 381 Register Read Command 366 Remote IRR 374, 645 Reset Registers(RR) 600 Reset Registers(RR). 572 Resource Type Indicator (RTE) 441, 442, 443, 556, 557, 558, 587, 588, 744, 745, 746 Resume Detect (RSM_DET 484 Resume Detect (RSM_DET) 479 Resume Interrupt Enable 480 RI_EN 404 RI_STS 402 Rotate and EOI Codes (R, SL, EOI) 365 RS Rate Select 377 RST_CPU 383 RTC_EN RTC Event Enable 396 RTC_INDX Real Time Clock Index Address 382 RTC_PWR_STS 387 RTC_STS 395 Run/Pause Bus master (RPBM) 572, 600 Run/Stop (RS) 476, 511 RW 539 S S/PDIF Interrupt (SPINT) 575, 602 SAFE_MODE 329 Sample Capabilities 575, 602 SATA Setup Data A 762 SATA Setup Data B 762 SB16 Decode Range 334 SB16_LPC_EN 338
Intel® 6300ESB ICH— Intel® 6300ESB I/O Controller Hub DS November 2007
844 Order Number: 300641-004US
SCI_EN 397 SECOND_TO_STS 421 Secondary Codec ID (SCID) 561 Secondary Codec Ready (SCR) 576, 603 Secondary Drive 0 Cycle Time (SCT0) 453, 752 Secondary Drive 0 Synchronous DMA Mode Enable (SSDE0) 452, 751 Secondary Drive 1 Cycle Time (SCT1) 453, 752 Secondary Drive 1 IORDY Sample Point (SISP1) 451, 750 Secondary Drive 1 Recovery Time (SRCT1) 451, 750 Secondary Drive 1 Synchronous DMA Mode Enable (SSDE1) 452, 751 Secondary Resume Interrupt 576, 603 Secondary Resume Interrupt Enable 573, 600 Secondary Slave Channel Cable Reporting 754 SEND_PID_CNT 525 SENDNOW 422 SERIRQ_SMI_STS 408 SERR#_NMI_STS SERR# NMI Source Status 381 SET Update Cycle Inhibit 378 Short Packet Interrupt Enable 479 Signaled Target-Abort Status 529 Signaled Target-Abort Status (STA) 438, 464, 741 Single or Cascade (SNGL) 361 Slave Identification Code 363 SLAVE_ADDR 542 SLP_EN 397 SLP_SMI_EN 406 SLP_SMI_STS 409 SLP_TYP 397 SMB_CMD 538 SMB_FOR_BIOS 344 SMB_SMI_EN 533 SMB_WAK_STS SMBus Wake Status 402 SMBALERT_DIS 546 SMBALERT_STS 535 SMBCLK_CTL 545 SMBCLK_CUR_STS 545 SMBDATA_CUR_STS 545 SMBus SMI Status (SMBUS_SMI_STS) 408 SMI at End of Pass-through Enable (SMIATENDPS) 471 SMI Caused by End of Pass-through (SMIBYENDPS) 470 SMI Caused by Port 60 Read (TRAPBY60R) 471 SMI Caused by Port 60 Write (TRAPBY60W) 471 SMI Caused by Port 64 Read (TRAPBY64R) 470 SMI Caused by Port 64 Write (TRAPBY64W) 470 SMI Caused by USB Interrupt (SMIBYUSB) 470 SMI on Async 501 SMI on Async Advance 500 SMI on Async Advance Enable 500 SMI on Async Enable 502 SMI on BAR 500 SMI on BAR Enable 500 SMI on CF 502 SMI on CF Enable 502 SMI on Frame List Rollover 500 SMI on Frame List Rollover Enable 501 SMI on HCHalted 502 SMI on HCHalted Enable 502 SMI on HCReset 502
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 845 —Intel ® 6300ESB ICH SMI on HCReset Enable 502 SMI on Host System Error 500 SMI on Host System Error Enable 501 SMI on OS Ownership Change 500 SMI on OS Ownership Enable 500 SMI on PCI Command 500 SMI on PCI Command Enable 500 SMI on Periodic 502 SMI on Periodic Enable 502 SMI on PMCSR 501 SMI on PMSCR Enable 502 SMI on Port 60 Reads Enable (60REN) 472 SMI on Port 60 Writes Enable (60WEN) 472 SMI on Port 64 Reads Enable (64REN) 472 SMI on Port 64 Writes Enable (64WEN) 471 SMI on Port Change Detect 500 SMI on Port Change Enable 501 SMI on PortOwner 501 SMI on PortOwner Enable 502 SMI on USB Complete 500 SMI on USB Complete Enable 501 SMI on USB Error 500 SMI on USB Error Enable 501 SMI on USB IRQ Enable (USBSMIEN) 471 SMLINK_CLK_CTL 544 SMLINK_SLV_SMI_STS—R/W. SMLink Slave SMI Status 421 SMLINK0_CUR_STS 544 SMLINK1_CUR_STS 544 SOF Timing Value 482 Software Debug (SWDBG) 474 SOP_MODE_CAP 439, 742 SOP_MODE_SEL 439, 742 Special Fully Nested Mode (SFNM) 364 Special Mask Mode (SMM) 366 SPKR_DAT_EN 381 SQWE Square Wave Enable 378 START 537 Start/Stop Bus Master (START) 456, 767 Steer Enable (SE) 579 STPCLK_DE 388 Sub Class Code 440, 742 Subsystem ID (SID) 446, 747 Subsystem Vendor ID (SVID) 445, 746 Suspend 483 SW_TCO_SMI 420 SWSMI_RATE_SEL 387 SWSMI_TMR_EN Software SMI# Timer Enable 406 SWSMI_TMR_STS 409 SYS_RST 383 System Reset Status (SRS) 386 T T00_INT_STS 608 T01_INT_STS 608 T02_INT_STS 608 TCO_EN 406 TCO_INT_STS 420 TCO_MESSAGE 423 TCO_STS 408
Intel® 6300ESB ICH— Intel® 6300ESB I/O Controller Hub DS November 2007
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TCO_TMR_HLT TCO Timer Halt 422 TCOSCI_EN 404 TCOSCI_STS 402 Tertiary Codec ID (TID 561 Tertiary Codec Ready (TCR) 575, 602 Tertiary Resume Interrupt (TRI) 575, 602 Tertiary Resume Interrupt Enable (TRE) 573, 600 THRM#_POL 405 THRM_DTY 399 THRM_EN 405 THRM_STS Thermal Interrupt Status 403 THRMOR_STS Thermal Interrupt Override Status 403 THT_EN 399 THTL_DTY 399 THTL_STS Throttle Status 398 TIM_CNT2_EN Timer Counter 2 Enable 381 TIMEOUT 420 Timeout/CRC Interrupt Enable 480 TIMERn_32MODE_CNF 611 TIMERn_INT_ENB_CNF 612 TIMERn_INT_ROUT_CAP 610 TIMERn_INT_ROUT_CNF 611 TIMERn_INT_TYPE_CN 612 TIMERn_PER_INT_CAP 611 TIMERn_SIZE_CAP 611 TIMERn_TYPE_CNF 612 TIMERn_VAL_SET_CNF 611 TMR_VAL 398 TMR2_OUT_STS Timer Counter 2 OUT Status 381 TMROF_EN Timer Overflow Interrupt Enable 396 TMROF_STS Timer Overflow Status 395 TOKEN_PID_CNT 525 TOP_SWAP 330 Trigger Mode 374, 645 U U128E Upper 128-byte Enable 331 U128LOCK Upper 128-byte Lock 331 UF Update-ended Flag 380 UHCI v/s EHCI 221 UIE Update-ended Interrupt Enable 378 UIP Update In Progress 377 USB Error Interrupt 479, 513 USB Error Interrupt Enable 514 USB Interrupt 513 USB Interrupt (USBINT) 479 USB Interrupt Enable 514 USB_ADDRESS_CNF 526 USB_ENDPOINT_CNF 526 USB1_EN 405 USB1_STS 403 USB2.0 Controller (D29 F7) 221 USB2_EN 405 USB2_STS 403
Intel® 6300ESB I/O Controller Hub November 2007 DS Order Number: 300641-004US 847 —Intel ® 6300ESB ICH V Vector 374 Vendor ID Value 527 VENDOR_ID_CAP 606 VRT Valid RAM and Time Bit 380 W WAK_STS 394 WDSTATUS Watchdog Status 424 Write Policies for Periodic DMA 225 WRITE_READ#_CNT 524 WRT_RDONLY 503
Intel® 6300ESB ICH— Intel® 6300ESB I/O Controller Hub DS November 2007